JP2008112335A - MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Abstract

Even if the capacity of one page of a flash memory is increased, storage data is moved through the buffer without increasing the processing time and the capacity of the buffer.
When storage data is moved between physical blocks belonging to the same physical zone, the data is read and read from the data register in the first flash memory including the first physical block constituting the physical zone. The stored data is stored in the data storage means, and the stored data is transferred to the data register in the second flash memory including the second physical block belonging to the same physical zone as the first physical block. In this process, data reading from the data register in the first flash memory and data transfer to the data register in the second flash memory are performed alternately or in parallel. Data is moved from the first physical block to a second physical block that is a physical block in the flash memory different from the first physical block without accumulating data for one page.
[Selection] Figure 8

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. A NAND flash memory is composed of a data register and a memory cell array, and data is written or read in units of pages between the data register and the memory cell array. A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. One gate is called a control gate and the other gate is called a floating gate. Data is written or erased by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Further, when the memory cell is changed from the logical value “1” corresponding to the erased state to the logical value “0” corresponding to the written state, the memory cell can be changed in units of memory cells. When changing, it can be changed only in units of blocks (for example, a data area of 64 pages). Hereinafter, a block which is a unit of erasure processing in the NAND flash memory is referred to as a physical block.

  Therefore, when a part of data stored in a plurality of pages in a physical block is rewritten, one empty block in which no data is written (one erased block in which all memory cells are in an erased state) is stored. It is necessary to select and write the rewritten data in this empty block, and copy the data not to be rewritten stored in the same block as the data before rewriting to this empty block. In this data movement process, data is read from the flash memory and accumulated in a buffer in the memory controller, and the data accumulated in the buffer in the controller is written to the flash memory (hereinafter referred to as data transfer process) or in the flash memory. Is performed by a copy back process (a process of writing data read from the memory cell array to the data register to another memory cell array).

  In NAND flash memory, errors may occur in stored data due to overprogramming or disturb phenomenon. For this reason, in Patent Document 1, an error correction code corresponding to data stored in the user area is stored in a redundant area of the same page, and the error correction code corresponding to the data is read when data is read. Based on this, an error included in the read data is detected and corrected, and the data in which the error is corrected is written in an empty block. That is, in this correction process, the read data is stored in a buffer in the memory controller, corrected for errors, and then transferred to an empty block.

[Description of data transfer process]
FIG. 9 is a diagram showing an outline of the data transfer process. The data transfer process is a data movement process via a buffer in the memory controller, and is performed by repeating the following steps.
(S91) Based on the information given from the memory controller, the memory cell of the transfer source page is selected, and data is copied from the selected memory cell to the data register.
(S92) One page of data is sequentially read from the data register and stored in a buffer in the controller.
(S93) One page of data stored in the buffer in the controller is transferred to the data register.
(S94) Based on the information given from the memory controller during the transfer in S93, the memory cell of the transfer destination page is selected, and the data in the data register is copied to the selected memory cell. In this way, data transfer is performed in units of one page.

  On the other hand, when one page is composed of an area of a plurality of sectors (one sector is 512 bytes), a data transfer method that is not in units of one page is also known. In this method, for example, data for one page is copied from a memory cell to a data register, and data held in the data register is read out in units of one sector and stored in a buffer in the memory controller. The data of one sector stored in the buffer is transferred to the data register and copied from the data register to the memory cell. By repeating this process for the number of sectors included in one page, the data transfer process for one page is completed. In this case, since the data stored in the buffer is in units of one sector, the buffer capacity can be reduced. However, in this data transfer method, the same data register is accessed during reading and writing, and when data is transferred to the data register, the data held in the data register is cleared. Each time a copy from the memory cell to the data register must be made. Therefore, in this data transfer method, the number of copying processes between the memory cell and the data register in the flash memory increases, and the processing time of the data transfer process becomes longer.

JP 2004-272476 A

  The data stored in the flash memory can be moved by either the data transfer process or the copy back process. In the copy back process, errors contained in the data can be corrected during the move. Can not. Therefore, when correcting an error included in data at the time of movement, data transfer processing having a longer processing time than copy back processing must be performed.

  Further, as the capacity of the flash memory increases, the capacity of one page increases. For example, in the small block configuration, one page was 512 (user area) + 16 (redundant area) bytes, but in the large block structure, one page increased to 2048 (user area) + 64 (redundant area) bytes. did. Furthermore, the shipment of flash memory in which one page is 4096 (user area) +128 bytes (redundant area) has been announced. Therefore, in order to perform data transfer processing for storing data for one page in a buffer in the memory controller, the capacity of the buffer must be increased. On the other hand, the processing time becomes long in the data transfer processing in which the transfer in units of one sector is repeated.

  Therefore, the present invention provides a memory controller capable of performing data transfer processing without increasing the processing time and buffer capacity of the data transfer processing, a flash memory system including the memory controller, and a flash memory control method. The purpose is to do.

  To achieve the above object, a memory controller according to the present invention is a memory controller that controls access to a physical zone composed of physical blocks in a plurality of flash memories, and is a first physical controller belonging to the physical zone. Read means for reading data from a data register in a first flash memory including a block, storage means for storing data read by the read means, and data stored in the storage means Transfer means for transferring to a data register in a second flash memory including a second physical block belonging to the same physical zone as the physical block, and a flash memory in which the first physical block and the second physical block are different Selecting means for selecting the second physical block to be included, By performing the reading by the reading unit and the transfer by the transfer unit alternately or in parallel, the storage unit does not store one page of data from the first physical block to the second physical block. It is characterized by moving data.

  Further, it is preferable that the selection unit includes a free block search unit capable of searching for a free block belonging to the physical zone for each flash memory.

  To achieve the above object, a flash memory system according to the present invention includes any one of the memory controllers and a multi-chip flash memory.

  To achieve the above object, a flash memory control method according to the present invention is a flash memory control method for controlling access to a physical zone composed of physical blocks in a plurality of flash memories, wherein the physical zone A read step for reading data from a data register in the first flash memory including the first physical block belonging to the storage step, an accumulation step for accumulating data read in the read step, and data accumulated in the accumulation step Transferring to a data register in a second flash memory including a second physical block belonging to the same physical zone as the first physical block, and reading by the reading step and the transferring step By performing the transfer according to the above alternately or in parallel, Characterized in that for moving data from the first physical block without storing the data of one page in the second physical block in different flash memory with the first physical block by the product step.

  According to the present invention, when a zone is constituted by a plurality of (multiple chips) physical blocks in a flash memory and storage data is moved between physical blocks included in the zone, the movement source physical block and the movement destination are moved. Since the physical blocks are different flash memories (flash memories of different chips), a buffer that can store storage data for one page is not provided in the memory controller, and the data register and the memory cell The stored data can be moved through the buffer in the memory controller without increasing the number of times of copying.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing the flash memory system 1. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

[Description of flash memory 2]
FIG. 2 is an explanatory diagram showing the relationship between a NAND flash memory block (hereinafter, a block in the flash memory is referred to as a physical block) and a page. The physical block and page configurations differ depending on the specifications of the flash memory, but general flash memories include a flash memory having a small block configuration and a flash memory having a large block configuration. In the small block configuration, as shown in FIG. 2A, one block includes 32 pages (P0 to P31), and each page includes a 512-byte user area and a 16-byte redundant area. In the large block configuration, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. Yes. In the present embodiment, the flash memory 2 is described as having a large block configuration.

  In the case of a large block configuration, data for 4 sectors (512 bytes for one sector) is stored in the user area of each page. Therefore, if the area for 1 sector is a subpage, each page has 4 Each physical block is composed of 256 subpages. On the other hand, in the case of the small block configuration, since data for one sector is stored in the user area of each page, the subpage is the same as the page, and each physical block is configured by 32 subpages.

  Here, the user area is mainly an area in which data supplied from the host system 4 is stored, and the redundant area is an area in which additional data such as error correction code, logical address information and block status is stored. is there. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block 11 described later.

  The logical address information is written when data is stored in the physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the logical address information is not written. Therefore, whether the block is an empty block (erased block) depending on whether the logical address information is written. Can be judged. That is, if logical address information is not written, it is determined that the block is an empty block (erased block).

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written), and when the physical block is determined to be a bad block. Is set with a flag indicating that it is a bad block.

[Description of controller 3]
As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12.

  The host interface block 7 exchanges data, address information, status information, external commands (commands given from the host system 4 to the flash memory system 3) and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 is a block that controls writing processing from the buffer 9 to the flash memory 2 and reading processing from the flash memory 2 to the buffer 9. A series of control operations when executing the writing process and the reading process are executed based on information instructing a series of control operations stored in the ROM 12.

  The ECC block 11 generates an error correcting code (ECC) to be added to data to be written to the flash memory 2, and based on the error correcting code (ECC) added to the data read from the flash memory 2. Then, an error included in the read data is detected and corrected.

  The ROM 12 is a non-volatile storage element that stores a program or the like that defines the procedure of processing executed by the microprocessor 6. Specifically, the ROM 12 stores, for example, a program that defines a processing procedure such as creation of an address conversion table described below.

[Description of zone configuration]
As the storage capacity of flash memory has been increasing, in order to smoothly manage the storage area of the flash memory whose capacity has been increased, a method of managing this storage area by dividing it into a plurality of zones has been used. Yes.

  FIG. 3 is a diagram schematically showing the address space on the host system side and the address space of the flash memory. First, the configuration of the conventional zone will be specifically described with reference to FIG. The address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes) as shown in FIG. A group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. Further, as shown in FIG. 3B, the serial numbers assigned to the logical blocks are called logical block numbers (LBN), and the serial numbers assigned to the logical zones are called logical zone numbers (LZN). In addition, a serial number in each logical zone of a logical block included in each logical zone is called a logical zone block number (LZIBN). On the other hand, as shown in FIG. 3C, each physical block is assigned a unique physical block address (PBA). Further, a physical zone is constituted by a plurality of physical blocks, and a physical zone number (PZN) is assigned to each physical zone. A serial number in each physical zone of a physical block included in each physical zone is called an intra-physical zone block number (PZIBN).

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Therefore, the number of sectors included in one logical block is set according to the number of sector areas included in one physical block.

  In the example shown in FIG. 3, a flash memory in which one physical block is composed of 256 subpages is assumed, so 256 sectors correspond to one logical block. Therefore, the logical zone of LZN # 0 configured by 1000 logical blocks of LBN # 0 to # 999 corresponds to the area of 256000 sectors of LBA # 0 to # 255999. Similarly, the logical zone of LZN # 1 corresponds to the area of 256000 sectors of LBA # 256000 to # 511999, the logical zone of LZN # 2 corresponds to the area of 256000 sectors of LBA # 512000 to # 767999, The logical zone of LZN # 3 corresponds to an area of 256000 sectors of LBA # 768000 to # 1023999.

  In addition, the logical zone of LZN # 0 configured with 1000 logical blocks of LBN # 0 to # 999 is allocated to the physical zone of PZN # 0 configured with 1024 physical blocks of PBA # 0 to # 1023. It has been. Similarly, the logical zone of LZN # 1 is assigned to the physical zone of PZN # 1, the logical zone of LZN # 2 is assigned to the physical zone of PZN # 2, and the logical zone of LZN # 3 is assigned to PZN #. Assigned to three physical zones. Here, the reason why the number of physical blocks included in the physical zone is larger than the number of logical blocks included in the logical zone is that new data and old data corresponding to the same logical block coexist in different physical blocks. This is a case in which a case where a defective block in which data cannot be normally written is generated.

  Conventionally, as described above, the physical zone is composed of physical blocks in the same flash memory (the same chip). However, in the flash memory system 1 according to the present invention, a plurality of flash memories 2 (a plurality of chips) are used. The physical zone is composed of physical blocks in (). The configuration of this physical zone will be described with reference to the example shown in FIG. FIG. 4 shows an example in which a physical zone is configured with physical blocks in the two-chip flash memory 2. In FIG. 4, each physical zone is composed of 512 physical blocks in chip 0 and 512 physical blocks in chip 1. Here, the 512 physical blocks from the head of the physical block address (PBA) in the chip 0 and the 512 physical blocks from the head of the physical block address (PBA) in the chip 1 are assigned to the physical zone of the LZN # 0. Assigned to. For subsequent physical zones (physical zones of LZN # 1 to #N), 512 physical blocks in each chip are sequentially assigned to each physical zone in the order of physical block addresses in each chip.

  In the flash memory system 1 according to the present invention, an address conversion table and a free block search table, which will be described later, are created for the physical zone as described above. FIG. 5 shows the relationship between the address conversion table 21 created for each physical zone and the free block search tables 22 and 23. As shown in FIG. 5, one address conversion table 21 is created for each physical zone, and the free block search tables 22 and 23 are created for each chip to which the physical blocks constituting the physical zone belong. That is, when each physical zone is composed of a physical block in chip 0 and a physical block in chip 1, a free block search table 22 for chip 0 and a free block for chip 1 are assigned to each physical zone. A search table 23 is created.

[Description of logical address and physical address]
When data is rewritten, the rewritten data is written in a physical block different from the physical block in which the data before rewriting is stored. Further, when rewriting the error-corrected data, the data after the error correction is written into a physical block different from the physical block in which the data before the error correction is stored. Each time such processing is performed, the correspondence between the logical address supplied from the host system 4 side and the physical address in the flash memory 2 dynamically changes. For this reason, an address conversion table showing the correspondence between logical addresses and physical addresses is required. This address conversion table is created based on the logical address information written in the redundant area of the flash memory 2. After the creation, the address translation table changes each time the correspondence between the logical address and the physical address changes. The correspondence is updated for the part.

[Description of address translation table]
Next, the address conversion table will be described with reference to the drawings. In this embodiment, the logical zone of LZN # 0 and the physical zone of PZN # 0, the logical zone of LZN # 1 and the physical zone of PZN # 1, and so on are the physical zone of LZN # N and the physical zone of PZN # N. The correspondence relationship between the logical zone and the physical zone is set in advance so that the zones correspond to each other.
FIG. 6 shows an example of an address conversion table for a set of logical zones and physical zones in correspondence with each other, and data corresponding to each logical block of LZIBN # 0 to # 999 included in the logical zone is stored. The physical block is indicated by a chip number and PZIBN (# 0 to # 511) for each chip. PZIBN is a serial number in each physical zone of a physical block included in each physical zone. PZIBN for each chip means a serial number for each chip in each physical zone. Therefore, in the configuration of the physical zone shown in FIG. 4, # 0 to # 511 are assigned as PZIBN for each chip to 512 physical blocks in the chip 0 included in each physical zone, and the chip included in each physical zone. # 0 to # 511 are assigned to 512 physical blocks in 1 as PZIBN for each chip.

  In this embodiment, since the correspondence relationship between the logical zone and the physical zone is set in advance, if the LZN of the logical zone is known, the PZN of the physical zone in the correspondence relationship can be obtained. Also, PZIBN can be converted to PBA based on the value of PZN. When converting PZIBN to PBA, an offset corresponding to PZN is added to PZIBN. For example, when PZIBN is converted to PBA in the configuration of the physical zone shown in FIG. 4, if the physical zone PZN is # 1, 512 is added as an offset, and if the physical zone PZN is # 2, 1024 is added as an offset. The

  In the configuration of the physical zone shown in FIG. 4, the PZIBN range for each physical block in the chip 0 constituting each physical zone is the same as the PZIBN range for each physical block in the chip 1. Since the chip number is described in the address conversion table, the data storage destination corresponding to each logical block is uniquely identified. For a logical block in which the corresponding data is not stored, a flag (hereinafter referred to as “no corresponding chip number” or “PZIBN”) is stored in the portion corresponding to the logical block in the address conversion table. , A flag indicating that the corresponding data is not stored is referred to as an unstored flag).

  If PZIBN # 0 to # 511 are allocated to the physical block in the flash memory of chip 0 and PZIBN # 512 to # 1023 are allocated to the physical block in the flash memory of chip 1, the chip number is added to the address conversion table. Need not be described. In addition, when PZIBN # 5122 to # 1023 are allocated to physical blocks in the flash memory of chip 1, when this PZIBN # 512 to # 1023 is converted to PBA in chip 1, 512 is subtracted from PZIBN. What is necessary is just to add an offset.

  When creating this address conversion table, for example, an area where a chip number for 1000 blocks and a PZIBN for each chip can be described is secured on the work area 8, and one of the areas describing the chip number and the PZIBN for each chip is allocated. , Or both, an unstored flag is set as an initial setting. After that, the physical block (redundant area) in the chip 0 assigned to the physical zone for creating the address conversion table is sequentially read. If LZIBN is described as the logical address information in the redundant area, the address conversion is performed. The PZIBN for each chip of the physical block in which the LZIBN is described is described in the portion corresponding to the LZIBN in the table. At this time, the chip number is also described together with the PZIBN for each chip. The same processing is also performed for chip 1, and when this processing is completed for 512 blocks in chip 0 and 512 blocks in chip 1 assigned to the physical zone for creating the address conversion table, the address conversion table is completed. To do. It should be noted that the unstored flag described in the initial setting remains as it is for the part where the chip-specific PZIBN and the chip number are not described in the address conversion table creation process. When the chip number is not described in the address conversion table, for example, PZIBN # 0 to # 511 are assigned to the physical block in the flash memory of chip 0, and PZIBN # 512 to # 1023 are assigned to the physical block in the flash memory of chip 1. When the PZIBN of the physical block in the chip 1 is described in the address conversion table, 512 may be added to the serial number (# 0 to # 511) of each physical block included in each physical zone. .

[Description of free block search table]
Next, the empty block search table will be described with reference to the drawings. FIG. 7 shows an example of this empty block search table. The empty block search table includes a table for chip 0 and a table for chip 1. Since the configuration of the empty block search table for 512 blocks in chip 0 and the empty block search table for 512 blocks in chip 1 is the same, the empty block search for 512 blocks in chip 0 is configured. The table for use will be described.

  When creating this empty block search table, work area 8 includes a 512-bit area corresponding to 512 blocks in chip 0 constituting the physical zone, an area describing the number of empty blocks, and an area describing the search end position. To ensure. In the 512-bit area corresponding to 512 blocks, physical blocks are allocated in the order of PZIBN # 0 to # 7 and PZIBN # 8 to # 15 from the top row. For the bits included in each row, physical blocks are assigned in the order of PZIBN (the order in which the lower PZIBN is lower) from the lower side (right side) to the upper side (left side). Therefore, the least significant bit of the top row corresponds to PZIBN # 0, and the most significant bit of the bottom row corresponds to PZIBN # 511.

Next, when physical blocks (redundant areas) in the chip 0 are sequentially read and LZIBN is described as logical address information in the redundant areas, or a flag indicating a bad block is set as the block status , “0” is set to the bit corresponding to the physical block. On the other hand, if the flag indicating the bad block is not set as the block status and the logical address information is not described in the redundant area, “1” is set to the bit corresponding to the physical block.
In the area describing the number of empty blocks, “0” is set when the creation of the empty block search table is started, and when the bit corresponding to the physical block is set to “1”, the value is set. Is incremented. In addition, a value set in advance or a value acquired by a random number generator or the like is set in the area describing the search end position.

  This empty block search table is preferably created together with the address conversion table. If data is written to an empty block after creation, the bit corresponding to the physical block is rewritten from “1” to “0”, the number of empty blocks is decremented, and the physical block to which data is written When the erase process is performed, the bit corresponding to the physical block is rewritten from “0” to “1”, and the number of empty blocks is incremented.

[Explanation of free block search processing]
Next, the empty block search process using the empty block search table will be described. Since there are a table for chip 0 and a table for chip 1, it is necessary to first determine which table to search. When it is necessary to search for an empty block, the address conversion table is searched and there is no PZIBN for each chip corresponding to LZIBN, and there is a PZIBN for each chip corresponding to LZIBN (when data is rewritten, or Correction process). In the former case, a free block search table on the chip side having a large number of free blocks is used so that the number of free blocks is not biased between chip 0 and chip 1. In the latter case, the reason will be described in [Data Transfer Processing and Copyback Selection], which will be described later. However, there is a method for selecting the free block search table to be used when performing the data transfer processing and when performing the copyback processing. Different. First, when data transfer processing is performed, a free block search table on a chip side different from a chip including a physical block in which data to be rewritten or data to be corrected is written is used. That is, the chip number of the physical block in which the data to be rewritten or the data to be corrected is written is obtained from the address conversion table, and when the chip number is 0, the table for chip 1 is used, If the chip number is 1, the table for chip 0 is used. Next, when the copy back process is performed, the empty block search table on the chip side including the physical block in which the target data of the copy back process is written is used. In other words, the chip number of the physical block in which the data to be copied back is written is obtained from the address conversion table. If the chip number is 0, the chip 0 table is used and the chip number is 1 If so, a table for chip 1 is used.

  The empty block search method is the same for the 512 blocks in the chip 0 constituting the physical zone and for the 512 blocks in the chip 1, so the empty blocks for the 512 blocks in the chip 0 constituting the physical zone are used. A search method will be described.

  In this search for an empty block using the empty block search table, the bits included in each row are searched from the lower row to the upper row, and the bit having the logical value “1” is searched from the upper row to the lower row. . When the search proceeds to the most significant bit of the bottom row, the search returns to the least significant bit of the top row. The bit for starting the search is determined based on the value set in the area describing the search end position. When the value set in the area describing the search end position is n, the search is started from the bit next to the bit corresponding to PZIBN # n for each chip. For example, if the value set in the area describing the search end position is 128, the search is started from the bit corresponding to PZIBN # 129 for each chip, and the value set in the area describing the search end position Is 511, the search is started from the bit corresponding to PZIBN # 0 for each chip.

  This search ends when a bit having a logical value of “1” is detected, and the value of PZIBN for each chip corresponding to the detected bit is set in an area describing the search end position. Accordingly, in the next search, the search is started from the bit next to the logical value “1” detected in the current search.

  For example, when the search is started from the bit corresponding to PZIBN # 0 for each chip in the empty block search table shown in FIG. 7, the bit corresponding to PZIBN # 27 for each chip (the lower order of the fourth row from the top) Since the fourth bit from the side) is “1”, the search ends here, and “27” is set in the area describing the search end position. The next search starts from the bit corresponding to PZIBN # 28 for each chip (the fifth bit from the lower side of the fourth row from the top).

[Description of data transfer process]
The outline of the data transfer process according to the present invention will be described with reference to FIG. The data transfer process means a data movement process in which data is read from the flash memory and accumulated in a buffer in the controller, and then the data accumulated in the buffer in the controller is written to the flash memory. On the other hand, data movement processing of data in the flash memory (processing for reading data from the memory cell array to the data register and then writing the data read to the data register in the flash memory in the flash memory) is called copy back processing.

The data transfer process according to the present invention is performed by repeating the following steps.
(S81) Based on the information given from the memory controller 3, the memory cell of the page to be read from the physical block in the chip 0 is selected, and the data is copied from the selected memory cell to the data register.
(S 82) Data for one subpage (one sector) is read from the data register in the chip 0 and stored in the buffer 9 in the memory controller 3. An error correction code corresponding to the read data is also read, and an error contained in the read data is detected and corrected by the ECC block 11.
(S83) Data for one subpage (one sector) stored in the buffer 9 in the memory controller is transferred to the data register in the chip 1. In addition, an error correction code corresponding to the transferred data is generated by the ECC block 11, and the generated error correction code is also transferred to the data register in the chip 1.
Here, when data for one page is transferred, the data for one page is transferred from the data register in the chip 0 to the data register in the chip 1 through the buffer 9 in the memory controller until the data is transferred to S82. The process of S83 is repeated. In this embodiment, since one page corresponds to four subpages (4 sectors), when transferring data for one page, the processes of S82 to S83 are repeated four times.
(S84) When data corresponding to the first subpage (sector) is transferred to the data register in the chip 1, the memory cell of the write destination page is selected based on the information given from the memory controller 3, Data in the data register is copied to the selected memory cell.

  As described above, in the data transfer process according to the present invention, data is transferred between two chips, so that one page of data is not accumulated in the buffer 9 in the memory controller 3, but in units of subpages (sectors). Data can be transferred from the data register in the chip 0 to the data register in the chip 1 in units. That is, processing for reading data for one subpage (for one sector) from the data register in chip 0 and processing for transferring data for one subpage (for one sector) to the data register in chip 1 are alternately performed. By repeating, it is possible to transfer data from the data register in the chip 0 to the data register in the chip 1 without accumulating data for one page in the buffer 9 in the memory controller 3. Therefore, it is not necessary to change the capacity of the buffer 9 in the memory controller in accordance with the capacity of one page, and if the capacity of the buffer 9 is at least one subpage (one sector), data transfer processing can be performed. it can. If the capacity of the buffer 9 is 2 subpages (2 sectors), the data is read from the data register in one chip and stored in the buffer 9, and the data stored in the buffer 9 is stored in the other chip. The process of transferring to the internal data register can be performed in parallel. When the process of accumulating in the buffer 9 and the process of transferring to the data register are performed in parallel, the internal bus 14 connected to the chip 0 and the internal bus 14 connected to the chip 1 are independent. Although it is preferable, the shared internal bus 14 may be used in a time division manner.

  In this description, the data transfer process from the flash memory of the chip 0 to the flash memory of the chip 1 has been described. However, the data transfer process from the flash memory of the chip 1 to the flash memory of the chip 0 can be similarly performed. it can.

[Select data transfer and copyback]
In the data transfer process, the data read from the flash memory is stored in the buffer in the controller and then written to the flash memory. If the read data contains an error, the error can be corrected. . On the other hand, in the copyback process, data is read from the memory cell array to the data register in the flash memory and then written to the memory cell array, so that the data can be moved in a short time. In order to be executed, the page before and after movement must belong to the same chip.

  In the access process to the flash memory, it is preferable to use the data transfer process and the copy back process properly depending on the situation in consideration of the characteristics of the data transfer process and the copy back process as described above. That is, when it is desired to correct an error included in the stored data when moving the stored data, the stored data is moved by the data transfer process, and there is no need to correct the error included in the stored data when moving the stored data. In some cases, the stored data is moved by copy back processing.

  The zone configuration of the flash memory system according to the present invention is not particularly limited. For example, the number of blocks and the number of chips constituting the zone can be appropriately set according to the application.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 is a block diagram schematically showing a flash memory system in an embodiment of the present invention. FIG. It is explanatory drawing which shows the relationship between a block and a page. It is a figure which shows roughly the structure of the address space of flash memory. It is a figure which shows the example which comprised the zone with the flash memory of 2 chips | tips. It is a figure which shows the relationship between the address conversion table produced for every zone, and the empty block search table. It is the figure which showed the example of the address conversion table. It is the figure which showed the example of the table for empty block searches. It is a figure which shows the outline | summary of the data transfer process by this invention. It is a figure which shows the outline | summary of the data transfer process by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 21 Address conversion table 22, 23 Empty block search table

Claims (4)

A memory controller that controls access to a physical zone composed of physical blocks in a plurality of flash memories,
Reading means for reading data from a data register in a first flash memory including a first physical block belonging to the physical zone;
Accumulating means for accumulating data read by the reading means;
Transfer means for transferring data stored in the storage means to a data register in a second flash memory including a second physical block belonging to the same physical zone as the first physical block;
Selecting means for selecting the second physical block so that the first physical block and the second physical block are included in different flash memories, wherein reading by the reading means and transfer by the transfer means are alternately performed Or a memory controller for transferring data from the first physical block to the second physical block without storing data for one page in the storage means.   The memory controller according to claim 1, wherein the selection unit includes a free block search unit capable of searching for a free block belonging to the physical zone for each flash memory.   A flash memory system comprising the memory controller according to claim 1 and a plurality of flash memories. A flash memory control method for controlling access to a physical zone composed of physical blocks in a plurality of flash memories,
A step of reading data from a data register in a first flash memory including a first physical block belonging to the physical zone;
An accumulation step for accumulating the data read in the reading step;
A transfer step of transferring the data accumulated in the accumulation step to a data register in a second flash memory including a second physical block belonging to the same physical zone as the first physical block;
By performing the reading in the reading step and the transferring in the transfer step alternately or in parallel, the first physical block to the first physical block without accumulating data for one page in the accumulation step. A method for controlling a flash memory, comprising: moving data to the second physical block in a different flash memory.

Images