JP2008262623A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A nonvolatile semiconductor memory device that performs efficient write voltage setting is provided.
A test circuit related to a write test sequence includes a first counter for counting the number of loops for each page write, a second counter for counting the number of accumulated loops required for all selected page writes, and a cumulative counter. Divider the number of loops by the total number of pages selected, a divider that calculates the average number of loops, an adder that calculates the difference between the average number of loops and its expected value, and the initial value of the write voltage set based on the difference A determination circuit for determining whether or not the device is appropriate.
[Selection] Figure 5

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a method for setting an initial value of a write voltage.

  In the EEPROM flash memory, the setting of the write voltage (specifically, the write voltage Vpgm applied to the selected word line) for writing data to the cell is important for both the writing speed performance and the data reliability.

  As shown in FIG. 4, the normal data write uses step-up write in which the write voltage Vpgm is stepped up by ΔVpgm every write cycle. With this method, a desired data threshold distribution is realized by controlling so that the subsequent writing is performed only for the cells that are determined to be unwritten by the verify reading for one page on which simultaneous writing is performed.

  If the initial value of the write voltage is too low, a large number of write cycles (number of write loops) are required until the writing of one page is completed. On the other hand, if the initial value of the write voltage is too high, cell threshold fluctuations in one write increase, the threshold distribution between cells spreads, and further, an unexpected threshold level is written. Arise. Particularly in the case of multi-value data storage, it is necessary to realize a narrow data threshold distribution with high accuracy, and the importance of setting the write voltage becomes high.

  Therefore, it is necessary to perform a write test as a wafer test and set a preferable initial value of the write voltage. Specifically, it is necessary to set the write voltage initial value so that the number of write loops falls within a predetermined value, and the write voltage initial value obtained as a result of the test is, for example, an initial setting data area ( ROM fuse area), which is automatically read out to the adjustment data register when the power is turned on, and used for subsequent writing control (see, for example, Patent Document 1).

  The write test performed in the conventional NAND flash memory uses an external tester, and will be briefly described as follows. First, block erase (Erase) is performed on a block to be measured. Then, the writing voltage initial value is normally set to a minimum value, and writing is performed. Specifically, write voltage application and verify read are repeated in a step-up manner.

  This writing is performed up to a preset number of loops for each page, and pass / fail judgment is performed at that time. If it passes, the address transitions to the next page. In the case of failure, block erasure is performed again at that time, the initial value of the write voltage is increased again, and a similar write test is performed.

When a write test is performed with the specified number of loops set in this way, whether the cause of failure is due to the cell (in this case, any write voltage is not passed) or whether the write voltage is set Cannot be determined. In order to know this, it is necessary to conduct a test for searching for a block in advance before measurement. Furthermore, when the write test of a certain page is failed, the block erase is performed again and the write test is performed, so that an enormous test time is required.
JP 2002-117699 A

  An object of the present invention is to provide a non-volatile semiconductor memory device that enables an efficient write voltage setting.

A nonvolatile semiconductor memory device according to an aspect of the present invention is executed by a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, a control circuit that performs a write sequence control of the memory cell array, and the control circuit And a test circuit for writing test,
The initial value of the write voltage is set, a write test is performed until each page write passes for a plurality of pages of the memory cell array, and the average number of loops for page write is obtained from the cumulative number of loops required for all page write, and this is expected A write test sequence for determining the suitability of the initial value of the write voltage compared with the value,
As the test circuit related to the write test sequence,
A first counter that counts the number of loops for each page write;
A second counter that counts the cumulative number of loops required to write all selected pages;
A divider for dividing the cumulative number of loops by the total number of pages selected to determine an average number of loops;
An adder for obtaining a difference between the average number of loops and an expected value thereof;
And a determination circuit that determines whether the initial value of the write voltage set based on the difference is appropriate.

A nonvolatile semiconductor memory device according to another aspect of the present invention is executed by a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, a control circuit that performs a write sequence control of the memory cell array, and the control circuit. And a test circuit related to the write test.
Set the initial value of the write voltage, perform a write test until each page write passes for multiple pages of the memory cell array, compare the number of loops for each page write with the expected value, find the difference, and add / subtract the difference sequentially A write test sequence for determining suitability of the write voltage initial value based on an average difference required for writing all pages,
As the test circuit related to the write test sequence,
A first counter that counts the number of loops for each page write;
A comparator for obtaining a difference between a count value obtained by the first counter and an expected value thereof;
A second counter that counts the difference obtained in each loop in both directions according to polarity;
And a determination circuit that determines the suitability of the set initial value of the write voltage based on an average value of the difference count values obtained by the second counter.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device that enables efficient write voltage setting.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a functional block configuration of a NAND flash memory according to an embodiment, and FIG. 2 shows a configuration of the memory cell array 1. As shown in FIG. 2, the memory cell array 1 is configured by arranging NAND cell units (NAND strings) NU.

  Each NAND cell unit has a plurality of (32 in the illustrated example) memory cells M0 to M31 connected in series. One end of the NAND cell unit is connected to the bit line BLe (or BLo) via the selection gate transistor S1, and the other end is connected to the cell source line CELSRC via the selection gate transistor S2.

  Control gates of memory cells M0-M31 are connected to different word lines WL0-WL31, respectively, and gates of select gate transistors S1, S2 are connected to select gate lines SGD, SGS, respectively.

  A sense amplifier / data latch circuit 2 is arranged at one end of the bit line. In the example of FIG. 2, the even-numbered bit line BLe and the odd-numbered bit line BLo adjacent to each other share one sense amplifier SA and are selectively connected to the sense amplifier SA by the selection circuit 4a. In this case, a set of memory cells selected by one word line and all even-numbered bit lines (or all odd-numbered bit lines) constitutes one page on which simultaneous writing / reading is performed.

  A set of NAND cell units arranged in the word line direction constitutes a block serving as a basic unit of data erasing, and a plurality of blocks BLK (BLK0, BLK1,..., BLKn-1) are arranged in the bit line direction. The A row decoder 3 is arranged for selectively driving the word line and the selection gate line.

  At the time of reading, one page of read data read to the sense amplifier circuit 2 is selected in units of columns by the column decoder 4 and output to the outside via the data line 7 and the I / O buffer 5.

  At the time of writing, write data supplied from the I / O port is loaded into the sense amplifier circuit 2 via the I / O buffer 5 and the data line 7. Writing is performed in a state where write data for one page is loaded.

  The address Add supplied from the outside is supplied to the row decoder 3 and the column decoder 4 via the address register 6. The command CMD supplied from the outside is decoded by the state control circuit 8 and instructed control is performed.

  The control circuit 8 performs sequence control for writing and erasing in accordance with the command CMD and external timing control signals (chip enable signal CEn, write enable signal WEn, read enable signal REn, address latch enable signal ALE, command latch enable signal CLE, etc.) Read control is performed.

  An internal voltage generation circuit 11 is provided in order to generate a necessary high voltage according to the operation mode. The internal voltage generation circuit 11 generates a necessary voltage under the control of the control circuit 8.

  Further, a self-test circuit necessary for performing a writing test at the wafer stage, that is, a so-called BIST (Build-in Self Test) circuit 9 is prepared in the chip. As will be described in detail later, in the writing test, writing to a plurality of pages of the block is performed, and an initial value of the writing voltage is set. The set write voltage is temporarily held in the parameter register 10 and written to the ROM fuse area 1a in the memory cell array 1 after the write test.

  The ROM fuse area 1a is set as an area for storing various voltage and timing adjustment data (initial setting data) obtained by the wafer test in addition to the initial value of the write voltage. These adjustment data are automatically read and set in the parameter register 10 under the control of the control circuit 8 as a power-on reset operation set based on the power-on detection circuit 12 when the power is turned on. It is used for each operation control.

  The data write operation will be briefly described as follows. Writing is performed in units of pages after the selected blocks are erased collectively. A write voltage Vpgm (for example, 20 V) is applied to the selected word line, and a write pass voltage Vpass (for example, 10 V) is applied to the non-selected word line. Prior to the application of these word line voltages, Vss is applied to the selected bit line when “0” is written, and Vdd is applied when “1” is written (write prohibited).

  As a result, the NAND cell channel for writing “0” is set to Vss, and when the write voltage Vpgm is applied to the selected word line, electron injection occurs in the floating gate due to the FN tunnel current, and the threshold value rises. . As a result of the select gate transistor being turned off, the NAND cell channel for writing “1” becomes floating, the channel potential is boosted by capacitive coupling, and electron injection does not occur.

  Binary storage is performed with the negative threshold value of the erase state being data “1” and the positive write threshold state being data “0”. Multi-value data storage is performed by setting the positive write threshold state to multiple levels. For example, if positive write threshold states A, B, and C (A <B <C) are prepared for the erase threshold state E, quaternary data storage in which one memory cell stores 2 bits is possible. it can.

  Data writing based on such a principle is actually performed by an operation of repeating a write cycle by applying a write voltage and subsequent verify read. At that time, a desired data threshold distribution is obtained by stepping up the write voltage every write cycle.

  In this embodiment, a write test for trimming the initial value of the write voltage is written to, for example, all pages in a block without providing a prescribed number of loops (number of write cycles) in the one-page write test as in the prior art. The initial value of the write voltage is set using the average number of loops obtained by testing or the average value of the difference between the expected number of loops of each page. When such a write test method is used, the number of block erases in the write test sequence can be reduced, and the time for the write test can be shortened.

  Hereinafter, a specific example of a write test sequence and a necessary self test circuit will be described.

[First writing test method]
FIG. 3 shows a first write test sequence. Here, a case will be described in which attention is paid to a certain selected block, a write test is performed on a plurality of pages, and a required write voltage initial value is set. The plurality of pages to be tested may be, for example, all pages of the block, or all even pages and all odd pages can be selected.

  Here, a single block write test will be described, but a similar test may be performed for a plurality of blocks to obtain a preferable initial write voltage value for each block or a preferable initial write voltage value of the chip as an average value thereof. .

  First, the selected block is collectively erased (step S1). Next, the initial value of the write voltage Vpgm is set (step S2). Here, the Vpgm initial value is set so that, for example, the number of loops up to the write pass becomes an expected value.

  Then, the plurality of pages selected in the selected block are sequentially written (step S3). More specifically, for each page, while the number of loops is counted, the write voltage application and the write verify read are performed in a step-up manner until the write passes.

  The number of loops required for writing each page is accumulated and stored, and the average number of loops per page is obtained, and the difference ΔL between the average number of loops and the expected value (= [average number of loops] − [expected value] ) Is obtained (step S4). Then, it is determined whether or not the absolute value ABS (ΔL) of the difference ΔL is a predetermined value, for example, 0.5 or less (step S5). If the determination result is YES, the write test is terminated. The obtained write voltage initial value is written in the parameter register 10 as described above, and this is written in the ROM fuse area 1a of the memory cell array 1 after the wafer test.

  When ABS (ΔL) is out of the predetermined value range, it is determined whether or not the difference ΔL is greater than 0 (ie, positive / negative) (step S6). Since the determination in step S5 has already been received, if the determination in step S6 is YES, ΔL is positive (specifically, ΔL> 0.5). Therefore, it is determined that the setting value of the initial value of the write voltage is too low, the initial value of the write voltage is increased by the predetermined value ΔVpgm (step S7), and if NO (that is, ΔL <−0.5), It is determined that the initial value is set too high, and the write voltage initial value is lowered by a predetermined value ΔVpgm (step S8). At the same time, the number of write test routines is counted up, the selected block is erased again (step S9), and the write test is performed again (step S3).

  According to such a writing test method, the total number of times of writing can be reduced as compared with the conventional method in which pass / fail judgment is performed for each page. In addition, the number of block erases can be reduced because writing is performed until each page write passes without limiting the number of page write loops. Normal erasing requires a longer time than writing, and when erasing many times, the entire writing test time becomes longer. However, the writing test time can be shortened by the first writing test method.

  In the first write test method, since it is assumed that the block is not defective, that is, until each page write is passed, it is necessary to select a block having no unwritable cells.

  However, even if there is a defective page, it can be dealt with by the following countermeasures. That is, in the write step S3, the maximum number of loops and the minimum number of loops for page writing are set, and when the maximum number of loops is exceeded or when writing is completed at the minimum number of loops or less, it is determined that there is a cell defect and the number of loops. Skip the page without accumulating. As a result, even a partially defective block can be measured.

  FIG. 5 shows the configuration of the self-test circuit 9 when the first write test method is applied. That is, the test circuit 9 includes a loop counter 21 that counts the number of loops during page writing, a cumulative loop counter 22 that calculates a cumulative value of the number of loops over a plurality of page writes, and an average loop obtained by dividing the obtained cumulative loop number by the selected page number. The divider 23 for obtaining the number, the full adder 24 for obtaining the difference ΔL between the obtained average loop number and its expected value, and the absolute value ABS (ΔL) of the obtained difference Δ are below a predetermined value. A determination circuit 25 for determining whether or not there is provided.

  FIG. 6 shows an operation example of loop number counting and cumulative loop number counting. Here, one word line is one page, all word lines in one block are WL0 to WL15, the number of loops for each page writing until all 16 pages are written, and the cumulative number of loops accumulated for each page are specific numerical values. An example is shown.

  In the example shown in the figure, the number of accumulated loops is 167, assuming that the number of expected loops is 10 between WL2 and WL14. At this time, the average number of loops is 167/16 = 10.7, and the difference from the expected value is ΔL = 10.7−10 = 0.7. Therefore, if the pass / fail judgment in step S5 in FIG. 3 is performed with ABS (ΔL) ≦ 0.5, the result is a fail. On the other hand, the determination in step S6 means YES, that is, it means that the initial value of the write voltage is low. Therefore, the initial write voltage is increased and the next write test is performed.

  FIG. 3 shows the case where the initial set value of the write voltage initial value is set to the expected value, and accordingly, the case where the correction of the write voltage initial value is + ΔVpgm (step S7) and the case where −ΔVpgm is set ( It is assumed that there is a step S8). However, if the initial write voltage value to be initially set is set to be somewhat lower than the expected value, the initial write voltage value can be corrected only to + ΔVpgm.

[Second writing test method]
FIG. 7 shows a write test sequence corresponding to FIG. 3 in the case where the expected value is changed according to the write test times as the second write test method to obtain the accuracy and time saving.

  The difference from the first writing test method is a determination step S5 'corresponding to the determination step S5 in FIG. Other than that, it is the same as FIG. In this determination step S5 ′, for example, in the first writing test (N = 1), it is determined that the allowable range of ABS (ΔL) is m = 0.5, and in the second and subsequent times (N ≧ 2), m = 1. .0 is a determination condition that facilitates passing.

  As described above, by appropriately switching the determination conditions in the plurality of write test routines, it is possible to shorten the test time while ensuring the accuracy of setting the write voltage initial value.

[Third writing test method]
FIG. 8 shows a third write test sequence. In this write test, the same test as the previous write test example is performed using a bidirectional counter without counting the cumulative loop number.

  First, the selected block is erased (step S11), and then the initial value of the write voltage is set so that the target number of loops is reached (step S12). Up to this point, there is no difference from the case of the first and second write test methods.

  Next, page writing is performed with a loop count (step S13). If the writing of one page passes, a difference ΔL (= [number of loops] − [expected value]) between the number of loops at that time and the expected value is obtained (step S14). And it is determined whether (DELTA) L is larger than 0 (namely, positive / negative) (step S15).

  If the determination result is YES (when the initial value of the write voltage should be increased), the bidirectional counter (difference counter) is counted up (step S16). On the other hand, in the case of NO (when the initial value of the write voltage is to be reduced), the bidirectional counter is counted down (step S17).

  Note that the initial value of the bidirectional counter needs to be sufficiently large. For example, when a 10-bit bidirectional counter is used, the most significant bit is set to 1 and the others are set to 0 as the initial value.

  It is determined whether or not the number of pages to be written has reached a prescribed maximum value Pmax (step S18). If NO, the pages are switched (step S19), and the same writing test is repeated.

  When the above writing is repeated up to a prescribed maximum number of pages, the bidirectional counter can obtain the total of the above-described difference ΔL. When the total difference is divided by the number of measurement pages, an average error per page is obtained (step S20).

  For example, as in the first writing test method, whether or not the absolute value ABS (ΔL) of the average error to be obtained is equal to or less than a predetermined value (for example, 0.5) is set as the test end determination condition (step S21). If YES, the test is completed, and if NO, the write voltage initial value is corrected, the number of routines is counted up (step S22), the block is erased again (step S23), and the next write test Is performed (step S13).

  In step S22, the correction of the write voltage is indicated by ± ΔVpgm. Specifically, as in the first and second write test methods, the write voltage is corrected upward according to the positive / negative of ΔL. A downward correction may be performed.

  FIG. 9 shows a circuit configuration of the self-test circuit 9 applied to the third write test method. The self-test circuit 9 includes a loop counter 31 that counts the number of loops for one page write, a comparator 32 that obtains a difference between the loop number count value and an expected value for each page write, and the obtained difference as the difference. A bidirectional counter 33 that counts according to the polarity, a divider 34 that obtains an average error by dividing the total difference obtained by writing all selected pages by the number of pages, and a write test based on the obtained average error And a determination circuit 35 for determining termination.

  FIG. 10 shows the operation of the loop counter and bidirectional counter in this self-test circuit in the case of a total of 16 pages, corresponding to FIG. The bidirectional counter indicates the count value on the assumption that the initial value is 10, the expected number of loops for one page is 10, and WL2-WL14 are all expected values. In this example, after all the pages are written, the total difference by the bidirectional counter 33 is 36, and the average error obtained by the divider 34 is 36/16 = 2.25.

  In this case, the determination result in step S21 of FIG. 8 is NO, and the write voltage initial value is stepped up and the write test is performed again.

  As described above, the write test is repeated until the average error falls within the specified value, and the optimum write voltage initial value can be obtained. In any of the first to third writing test methods, the number of pages to be measured is not limited. For example, when this is raised to a power of 2, a shift register can be used as the divider used in FIG. 5 or FIG. This simplifies the circuit.

  In addition, the first write test method and the third write test method can actually be a mixed type including both of them. That is, the cumulative loop number counter used in the first write test method can be configured to accumulate the difference from the expected value of each page write.

It is a figure which shows the functional block structure of the flash memory by embodiment of this invention. It is a figure which shows the structure of the memory cell array of the flash memory. It is a figure which shows the write sequence by the 1st write test method of the flash memory. It is a figure which shows the write voltage waveform of the step-up write of the same flash memory. It is a figure which shows the structure of the self test circuit by a 1st write test method. It is a figure for demonstrating operation | movement of the self-test circuit. It is a figure which shows the write sequence by the 2nd write test method. It is a figure which shows the write-in sequence by the 3rd write-in test method. It is a figure which shows the structure of the self test circuit by the 3rd write-in test method. It is a figure for demonstrating operation | movement of the self-test circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 1a ... ROM fuse area, 2 ... Sense amplifier circuit system data latch circuit, 3 ... Row decoder, 4 ... Column decoder, 5 ... I / O buffer, 6 ... Address register, 7 ... Data line, 8 ... State control circuit, 9 ... Self test circuit, 10 ... Parameter register, 11 ... Internal voltage generation circuit, 12 ... Power-on detection circuit, 21 ... Loop counter, 22 ... Cumulative loop loop counter, 23 ... Divider, 24 ... Full addition 25, determination circuit, 31 ... loop counter, 32 ... comparator, 33 ... bidirectional counter, 34 ... divider, 35 ... determination circuit.

Claims (5)

Nonvolatile semiconductor memory comprising a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, a control circuit for controlling a write sequence of the memory cell array, and a test circuit for a write test executed by the control circuit In the device
The initial value of the write voltage is set, a write test is performed until each page write passes for a plurality of pages of the memory cell array, and the average number of loops for page write is obtained from the cumulative number of loops required for all page write, and this is expected A write test sequence for determining the suitability of the initial value of the write voltage compared with the value,
As the test circuit related to the write test sequence,
A first counter that counts the number of loops for each page write;
A second counter that counts the cumulative number of loops required to write all selected pages;
A divider for dividing the cumulative number of loops by the total number of pages selected to determine an average number of loops;
An adder for obtaining a difference between the average number of loops and an expected value thereof;
A non-volatile semiconductor memory device, comprising: a determination circuit that determines whether the initial value of the write voltage set based on the difference is appropriate. The nonvolatile semiconductor memory device according to claim 1, wherein the determination circuit has a determination reference value that is switched according to a loop. Nonvolatile semiconductor memory comprising a memory cell array in which electrically rewritable nonvolatile memory cells are arranged, a control circuit for controlling a write sequence of the memory cell array, and a test circuit for a write test executed by the control circuit In the device
Set the initial value of the write voltage, perform a write test until each page write passes for multiple pages of the memory cell array, compare the number of loops for each page write with the expected value, find the difference, and add / subtract the difference sequentially A write test sequence for determining suitability of the write voltage initial value based on an average difference required for writing all pages,
As the test circuit related to the write test sequence,
A first counter that counts the number of loops for each page write;
A comparator for obtaining a difference between a count value obtained by the first counter and an expected value thereof;
A second counter that counts the difference obtained in each loop in both directions according to polarity;
A non-volatile semiconductor memory device comprising: a determination circuit that determines the suitability of the set initial value of the write voltage based on an average value of the difference count values obtained by the second counter. A parameter register that holds a write voltage initial value obtained in the write test sequence;
The initial value of the write voltage of the parameter register is written in the ROM fuse area of the memory cell array after the write test, and then automatically read out every time the power is turned on, transferred and held in the parameter register, and used for write control. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array is configured by arranging NAND cell units having a plurality of memory cells connected in series.

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