JP2008277923A - Clock error detection circuit - Google Patents

Abstract

A clock abnormality detection circuit capable of accurately detecting an abnormality in a clock signal is provided.
A pulse generation circuit 11 that detects a clock signal CK and generates a pulse, a charging circuit 13 that charges a current output from a current source 18, and a pulse from the pulse generation circuit 11 causes the charging circuit 13 to A discharge circuit 12 that discharges the charged voltage, a first voltage level detection circuit 15 that detects a voltage charged in the charging circuit 13 and outputs a signal corresponding to the voltage, and a first voltage level detection circuit 15, a peak hold circuit 17 that outputs a control voltage controlled according to the output of 15, a voltage shift circuit 14 that steps down the voltage charged in the charging circuit 13 and generates a step-down voltage, and a voltage that is stepped down by the voltage shift circuit 14. And a second voltage level detection circuit 16 for detecting the stepped down voltage. The current source 18 outputs current to the charging circuit 13 in accordance with the control voltage output from the peak hold circuit 17.
[Selection] Figure 1

Description

  The present invention relates to a clock anomaly detection circuit that detects an anomaly of a clock signal, and is used, for example, in an RF tag or an IC card manufactured by a CMOS process.

  In RF tags and non-contact IC cards (hereinafter collectively referred to as tags), it is difficult to obtain a clock with a high frequency using a crystal oscillator or the like due to the lack of a power supply and restrictions on the housing. For this reason, a method of extracting a reception carrier and using it as an operation clock may be used, but there are the following problems.

  This is because the voltage amplitude induced in the antenna varies greatly depending on the communication distance and becomes considerably small at a distance, and the load switching, which is a means for the tag to transmit (reply) data, reduces the antenna end voltage amplitude of the tag itself. To make it smaller. The load switching is a method of transmitting the amplitude at the antenna end on the reader / writer (R / W) side that supplies power by changing the impedance on the tag side. In general, since the tag performs by short-circuiting its antenna using a resistor or a transistor, the induced voltage amplitude is reduced. In this way, it is difficult to extract a carrier when the tag itself transmits at a distance, and the case where the carrier cannot be completely extracted or one to several carriers are lost.

  As means for detecting such a state, a circuit including a trigger pulse generation circuit, an integration circuit, a discharge circuit, and a comparator has been used. The trigger pulse generation circuit is a circuit that outputs a short high pulse in synchronization with the edge of the input clock CK. The integrating circuit is reset by the discharging circuit in synchronization with the clock. Here, the integrated voltage value and the reference voltage at this time are compared by the comparator, but the integrated voltage is set to exceed the reference voltage when the clock has a desired frequency. As a result, when the clock is slower than the desired frequency, the comparator is inverted, and an abnormality of the clock can be detected.

  However, the constants and reference voltages of circuit elements constituting the integrating circuit vary in absolute values in the case of an LSI manufactured by a general CMOS process. In addition, since the first stage of the comparator is composed of a differential amplifier, the response speed tends to be slow when the comparison voltage difference is small. However, the moment of detection is when the two input voltages intersect, and the voltage difference is small, and the output cannot be inverted at the moment of detection. This delay in response speed depends on the mutual conductance of the MOS transistors constituting the comparator and causes a detection error. As described above, the conventional circuit has a problem that the abnormality of the clock signal cannot be accurately detected.

Further, as a conventional technique related to the present invention, for example, Patent Document 1 proposes an abnormality detection circuit for an oscillation circuit.
JP 2002-43907 A

  An object of the present invention is to provide a clock abnormality detection circuit capable of accurately detecting an abnormality of a clock signal.

  A clock abnormality detection circuit according to an embodiment of the present invention includes a pulse generation circuit that detects a clock signal to generate a pulse, a charging circuit that charges a current output from a current source, and the pulse from the pulse generation circuit The discharge circuit for discharging the voltage charged in the charging circuit, the first voltage level detection circuit for detecting the voltage charged in the charging circuit and outputting a signal corresponding to the voltage, and the first A peak hold circuit that outputs a control voltage controlled according to the output of the voltage level detection circuit, a voltage shift circuit that steps down the voltage charged in the charging circuit and generates a step-down voltage, and the voltage shift circuit A second voltage level detection circuit for detecting the stepped down voltage, and the current source is controlled in accordance with the control voltage output from the peak hold circuit. And outputs the current to the charging circuit.

  According to the present invention, it is possible to provide a clock abnormality detection circuit that can accurately detect abnormality of a clock signal.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  FIG. 1 is a block diagram showing a configuration of a clock abnormality detection circuit according to an embodiment of the present invention. The clock abnormality detection circuit includes a trigger pulse generation circuit 11, a discharge circuit 12, a charging circuit 13, a voltage shift circuit 14, a first voltage level detection circuit 15, a second voltage level detection circuit 16, a peak hold circuit 17, and a voltage control. A current source 18 is provided.

  The clock signal CK is input to the trigger pulse generation circuit 11. The output of the trigger pulse generation circuit 11 is input to the discharge circuit 12, and the output of the discharge circuit 12 is input to the charging circuit 13. The output of the charging circuit 13 is input to the voltage shift circuit 14 and the first voltage level detection circuit 15, respectively. The output of the first voltage level detection circuit 15 is input to the peak hold circuit 17, and the output of the peak hold circuit 17 is input to the voltage controlled current source 18. The output of the voltage controlled current source 18 is input to the charging circuit 13. The output of the voltage shift circuit 14 is input to the second voltage level detection circuit 16, and the abnormality detection signal DET is output from the second voltage level detection circuit 16.

  A clock signal CK extracted from a reception carrier or the like is input to the trigger pulse generation circuit 11. The trigger pulse generation circuit 11 detects a rising edge or a falling edge of the clock signal CK, generates a trigger pulse, and outputs it to the discharge circuit 12. A current is output from the voltage controlled current source 18 to the charging circuit 13, and the charging circuit 13 charges the current output from the voltage controlled current source 18. The discharge circuit 12 discharges the charge charged in the charging circuit 13 by the trigger pulse from the trigger pulse generation circuit 11. The first voltage level detection circuit 15 detects the voltage charged in the charging circuit 13 and outputs a signal corresponding to the voltage. The peak hold circuit 17 outputs a controlled control voltage according to the output of the first voltage level detection circuit 15. The control voltage output from the peak hold circuit 17 is supplied to the voltage controlled current source 18, and the voltage controlled current source 18 outputs a current to the charging circuit 13 according to the control voltage. The voltage shift circuit 14 steps down the voltage charged in the charging circuit 13 to generate a stepped down voltage. The second voltage level detection circuit 16 detects the step-down voltage stepped down by the voltage shift circuit 14. Then, the second voltage level detection circuit 16 outputs an abnormality detection signal DET assuming that the clock signal CK is abnormal when the step-down voltage is higher than a predetermined voltage.

  Next, the configuration and operation of the clock abnormality detection circuit shown in FIG. 1 will be described in detail with reference to FIGS. FIG. 2 is a circuit diagram showing a configuration of the clock abnormality detection circuit of the embodiment, and FIG. 3 is a circuit diagram of the trigger pulse generation circuit 11 in the clock abnormality detection circuit.

  For example, as shown in FIG. 3, the trigger pulse generation circuit 11 includes an AND circuit AD and a delay circuit DLY. The trigger pulse generation circuit 11 generates a trigger pulse TRG synchronized with the rising edge or falling edge of the extracted clock signal CK. The trigger pulse TRG is input to the gate of an n-channel MOS transistor (hereinafter referred to as nMOS transistor) N1, and turns on the nMOS transistor N1. Thereby, the electric charge accumulated in the capacitor C1 is discharged in a short time. The nMOS transistor N1 forms a discharge circuit 12, and the capacitor C1 forms a charging circuit 13. As will be described later, a p-channel MOS transistor (hereinafter referred to as a pMOS transistor) P2 constituting the voltage-controlled current source 18 can be regarded as a constant current source in the operation equilibrium state, and the pMOS transistor P2 and the capacitor C1 are combined together to form the first Configure an integration circuit. The first integration circuit generates an integration voltage INT. The time constant at this time needs to exceed the threshold voltage of the inverter IV1 at the clock frequency in the steady state. The inverter IV1 constitutes a first voltage level detection circuit 15.

  The integrated voltage (first voltage) INT is input to the inverter IV1, and the inverter IV1 controls the operating state of the p-channel MOS transistor (hereinafter referred to as pMOS transistor) P1 depending on whether or not the integrated voltage INT exceeds the threshold voltage. To do. A capacitor C2 and a resistor R1 are connected to the drain of the pMOS transistor P1. The capacitor C2 and the resistor R1 constitute a second integration circuit, which generates a control voltage CTL for the pMOS transistor P2. The time constant at this time is set to such an extent that the pMOS transistor P2 can be regarded as a constant current source at the clock frequency in the steady state and the voltage INT_TRG is generated every time the trigger pulse TRG is generated. The pMOS transistor P1 and the second integration circuit constitute a peak hold circuit 17.

  On the other hand, the integrated voltage INT is stepped down by resistance division using the resistors R2 and R3 to generate the voltage INTS. The voltage INTS is input to an inverter IV2 made with the same size as the inverter IV1. When the threshold voltage of the inverter IV1 is VTH1 and the threshold voltage of the inverter IV2 is VTH2, the relationship is VTH1 = VTH2 × (1+ (R2 / R3)). Since the threshold voltages of the inverters formed in the same size and close to each other on the same chip have the same value, the apparent threshold voltage of the inverter IV2 is lower than that of the inverter IV1 depending on the ratio of the resistors R2 and R3. Set to any voltage. Here, in the inverters IV1 and IV2 used for detection, a large current flows as a through current in the vicinity of the threshold voltage. However, when the voltage deviates from the threshold voltage, the current hardly flows, and the power efficiency is higher than that of the comparator. Is good.

  The operation of the clock abnormality detection circuit of the embodiment will be described below.

  As an initial state, it is assumed that the potential of the control voltage CTL is 0V. In this case, since a large gate-source voltage is applied to the pMOS transistor P2, a relatively large current is supplied to the capacitor C1 to charge the capacitor C1 rapidly. When the integration voltage INT exceeds the threshold voltage of the inverter IV1, the pMOS transistor P1 is turned on and charges are stored in the capacitor C2. As described above, the time constant at this time is set to be long so that the pMOS transistor P2 can be regarded as a constant current source. Therefore, the capacitor C2 cannot be sufficiently charged only by turning on the pMOS transistor P1 once.

  However, the charging of the capacitor C2 raises the control voltage CTL to a voltage higher than the initial 0V. Even in this state, the gate-source voltage of the pMOS transistor P2 is still large, and the operation continues to increase the control voltage CTL. However, the current flowing from the pMOS transistor P2 to the capacitor C1 gradually increases as the control voltage CTL increases. It will become less.

  When the current of the pMOS transistor P2 becomes too small by the above-described operation, the integrated voltage INT does not exceed the threshold voltage of the inverter IV1, and the pMOS transistor P1 does not turn on. Then, the capacitor C2 is not charged by the pMOS transistor P1, and the charge of the capacitor C2 is discharged by the resistor R1, and the control voltage CTL decreases. As described above, when the control voltage CTL decreases, the current from the pMOS transistor P2 to the capacitor C1 again increases.

  As described above, when the frequency of the clock signal CK is constant, the pMOS transistor is such that the peak value of the integrated voltage INT reaches the threshold voltage of the inverter IV1 by the control voltage CTL supplied to the gate of the pMOS transistor P2. The current flowing from P2 to the capacitor C1 is adjusted. Thus, the feedback of the control voltage CTL controlled according to the integration voltage INT corrects the variation in the capacitance value of the capacitor C1 and the threshold voltage of the pMOS transistor P2, and the clock signal CK is continuously extracted. In the equilibrium state, the voltage INTS does not reach the threshold voltage of the inverter IV2. Therefore, the abnormality detection signal DET is not inverted.

  Next, it is assumed that the continuous clock signal CK is lost. As described above, in the equilibrium state, the peak value of the integral voltage INT reaches the threshold voltage of the inverter IV1. However, when the clock signal CK is lost, the trigger pulse TRG is not generated at a predetermined time, and the capacitor C1 is not discharged. Then, the capacitor C1 continues to be charged by the current of the pMOS transistor P2, and rises so as to greatly exceed the threshold voltage of the inverter IV1. At this time, the pMOS transistor P1 is turned on to try to increase the control voltage CTL. However, since the time constant is long, the control voltage CTL can only increase slowly, and the current of the pMOS transistor P2 hardly changes from the equilibrium state. . As a result, the voltage INTS also increases following the increase of the integrated voltage INT, and the abnormality detection signal DET is inverted when the voltage INTS exceeds the threshold voltage of the inverter IV2. By inverting the abnormality detection signal DET, it can be detected that the clock signal CK is abnormal.

  As described above, according to the embodiment of the present invention, the feedback circuit is used to control the integration voltage INT, thereby correcting the variation of the elements, and the configuration using the inverter having a high response speed for the detection of the integration voltage INT. The abnormality of the clock signal can be detected with high accuracy.

  The embodiment described above is not the only embodiment, and various embodiments can be formed by changing the configuration or adding various configurations.

It is a block diagram which shows the structure of the clock abnormality detection circuit of embodiment of this invention. It is a circuit diagram which shows the structure of the clock abnormality detection circuit of the said embodiment. It is a circuit diagram of a trigger pulse generation circuit in the clock abnormality detection circuit of the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Trigger pulse generation circuit, 12 ... Discharge circuit, 13 ... Charging circuit, 14 ... Voltage shift circuit, 15 ... 1st voltage level detection circuit, 16 ... 2nd voltage level detection circuit, 17 ... Peak hold circuit, 18 ... Voltage Control current source.

Claims (5)

A pulse generation circuit that detects a clock signal and generates a pulse;
A charging circuit for charging a current output from a current source;
A discharge circuit for discharging a voltage charged in the charging circuit by the pulse from the pulse generating circuit;
A first voltage level detection circuit that detects a voltage charged in the charging circuit and outputs a signal corresponding to the voltage;
A peak hold circuit that outputs a control voltage controlled in accordance with an output of the first voltage level detection circuit;
A voltage shift circuit that steps down a voltage charged in the charging circuit and generates a step-down voltage;
A second voltage level detection circuit for detecting the step-down voltage stepped down by the voltage shift circuit;
A clock abnormality detection circuit, wherein the current source outputs a current to the charging circuit in accordance with the control voltage output from the peak hold circuit.   2. The clock abnormality detection circuit according to claim 1, wherein the voltage charged in the charging circuit is fed back through the first voltage level detection circuit, the peak hold circuit, and the current source.   3. The clock abnormality detection circuit according to claim 1, wherein each of the first and second voltage level detection circuits includes an inverter.   4. The second voltage level detection circuit according to claim 1, wherein when the step-down voltage is higher than a predetermined voltage, the clock signal is abnormal and outputs an abnormality detection signal. Clock error detection circuit.   5. The clock abnormality detection circuit according to claim 1, wherein the current source and the charging circuit constitute an integration circuit including a p-channel MOS transistor and a capacitor, respectively.

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