JP2008292611A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To securely prevent crosstalk and a deficiency in writing of video data to pixels in a precharge type display device by securing a sufficient precharge time. <P>SOLUTION: When a pixel transistor GT(R) of a pixel GS(R) is turned on and pixel transistors GT(G) and GT(B) are turned off (namely, in a writing period of the pixel GS(R)), source lines SL(G) and SL(B) are precharged through precharge transistors PT(G) and PT(B). When the pixel transistors GT(G) and GT(B) of pixels GS(G) and GS(B) are turned on and a pixel transistor GT(R) is turned off (namely, in a writing period of the pixels GS(G) and GS(B)), on the other hand, a source line SL(R) is precharged through a precharge transistor PT(R). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device that precharges a source line.

  In order to prevent crosstalk and insufficient writing of a source signal (video signal) to a pixel, a liquid crystal display device employing a precharge method for precharging a source line is known. In this type of liquid crystal display device, a source line is set to a predetermined precharge potential during a precharge period, and a plurality of pixels connected to one gate line are simultaneously opened during a subsequent write period, and the corresponding source line The source signal is written to a plurality of pixels.

A liquid crystal display device using a precharge method is described in Patent Documents 1 and 2, for example.
JP 2006-154088 A JP 2004-12891 A

  Incidentally, in a high-definition liquid crystal display device that has been developed in recent years, it is necessary to ensure a sufficient precharge period. However, in the conventional precharge method, a source line is precharged, and thereafter, a plurality of pixels connected to one gate line are simultaneously opened, and source signals are written to the plurality of pixels through corresponding source lines. There was a problem that a sufficient precharge period could not be secured.

  The display device of the present invention includes a plurality of source lines, a precharge switch connected to each of the plurality of source lines, a plurality of pixels each connected to the plurality of source lines and including a pixel switch, and the plurality of the plurality of source lines. When a pixel switch of a pixel is turned on among the pixels, a precharge switch of a source line connected to another pixel of which the pixel switch is turned off is turned on so that the source line is precharged And a control circuit for performing control.

  According to the present invention, a sufficient precharge time can be secured in a precharge display device. As a result, crosstalk and insufficient writing of video data to the pixels can be reliably prevented.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a liquid crystal display device.

  A plurality of pixels GS (R), GS (G), GS (B),... Are arranged in a matrix on the glass substrate 100. The pixel GS (R) is a pixel corresponding to red (R) (an example of the first pixel of the present invention), and the pixel GS (G) is a pixel corresponding to green (G) (an example of the second pixel of the present invention). ), And the pixel GS (B) is a pixel corresponding to blue (B). These three types of pixels GS (R), GS (G), and GS (B) are arranged in a row and repeatedly in the row direction (X direction). In FIG. 1, for convenience of explanation, only pixels of 1 row × 3 columns are shown.

  The pixel GS (R), the pixel GS (G), and the pixel GS (B) include pixel transistors GT (R), GT (G), and GT (B) each including an N-channel thin film transistor (the pixel switch of the present invention). The pixel electrodes 10R, 10G, and 10B are connected to the drains of the pixel transistors GT (R), GT (G), and GT (B), respectively. A common electrode 11 is provided to face the pixel electrodes 10R, 10G, and 10B, and a liquid crystal 12 is provided between the pixel electrodes 10R, 10G, and 10B and the common electrode 11. A common electrode signal VCOM (for example, an AC signal) is applied to the common electrode 11.

  On the glass substrate 100, a source line SL (R) (an example of a first source line of the present invention), a source line SL (G) (an example of a second source line of the present invention), a source SL ( B) extends in the column direction (Y direction) at regular intervals. The source lines SL (R), SL (G), and SL (B) are connected to the pixel transistors GT (R), GT (G), and GT (B) of the corresponding pixels GS (R), GS (G), and GS (B). B) connected to the source.

  Further, on the glass substrate 100, the source lines SL (R), SL (G), SL (B) corresponding to the R enable signal RENB, the G enable signal GENB, and the B enable signal BENB are selected, A source selection circuit 13 having a source switch SW for supplying source signals corresponding to each color of RGB is provided. Further, a precharge transistor PT (R), PT that selects a source line to be precharged and supplies a precharge signal DSD (same as the common electrode signal VCOM in this embodiment) to the selected source line. A precharge selection circuit 14 including (G) and PT (B) (an example of the precharge switch of the present invention) is provided.

  A precharge signal DSD is applied to the common source of the precharge transistors PT (R), PT (G), and PT (B), and their drains correspond to the corresponding source lines SL (R), SL (G), SL ( B). The outputs of the AND circuits 15 (R), 15 (G), and 15 (B) are applied to the gates of the precharge transistors PT (R), PT (G), and PT (B), respectively. The vertical enable signal VENB is commonly input to the AND circuits 15 (R), 15 (G), and 15 (B). Further, the precharge control signal DSG is input to the AND circuits 15 (G) and 15 (B), and the inverted signal of the precharge control signal DSG is input to the AND circuit 15 (R).

  On the glass substrate 100, the gate lines GL1-1 and GL1-2 extend in the row direction (X direction) at regular intervals. The gate line GL1-1 is connected to the gate of the pixel transistor GT (R) of the pixel GS (R), and the gate line GL1-2 is connected to the pixel transistor GT (G) of the two pixels GS (G) and GS (B). ) And GT (B). Further, a pixel write line selection circuit 17 including AND circuits 16 (R) and 16 (GB) for outputting a pixel selection signal to the gate lines GL1-1 and GL1-2 is provided. The vertical enable signal VENB is commonly input to the AND circuits 16 (R) and 16 (GB). Further, a precharge control signal DSG is input to the AND circuit 16 (R), and an inverted signal of the precharge control signal DSG is input to the AND circuit 16 (GB).

  According to the configuration described above, when the pixel transistor GT (R) of the pixel GS (R) is on and the pixel transistors GT (G) and GT (B) are off (that is, writing to the pixel GS (R)). The source lines SL (G) and SL (B) can be precharged through the precharge transistors PT (G) and PT (B). Conversely, when the pixel transistors GT (G) and GT (B) of the pixels GS (G) and GS (B) are on and the pixel transistor GT (R) is off (that is, the pixels GS (G) and GS (B) can be written), and the source line SL (R) can be precharged through the precharge transistor PT (R).

  Hereinafter, the operation of the liquid crystal display device will be described with reference to FIGS. The vertical enable signal VENB becomes H level in a predetermined period of the first half and the second half of one horizontal period (hereinafter referred to as 1H period) defined by the horizontal synchronization signal Hsync. The precharge control signal DSG is at the H level in the first half of the 1H period and at the L level in the latter half. Accordingly, in the first half of the 1H period, the output of the AND circuit 16 (R) of the pixel write line selection circuit 17 becomes H level, and thereby the potential of the gate line GL1-1 becomes H level, and the pixel of the pixel GS (R) The transistor GT (R) is turned on. Further, the output of the AND circuit 16 (GB) becomes L level, whereby the potential of the gate line GL1-2 becomes L level, and the pixel transistors GT (G), GT of the pixels GS (G), GS (B). (B) is off.

  At this time, when the source line SL (R) is selected according to the R enable signal RENB, the source signal S (R) corresponding to red (R) is output to the source line SL (R) through the source switch SW. . The source signal S (R) is written into the pixel GS (R) through the pixel transistor GT (R).

  On the other hand, since the outputs of the AND circuits 15 (G) and 15 (B) of the precharge selection circuit 14 are at the H level, the precharge switches PT (G) and PT (B) are turned on, and the source lines SL (G) and SL (B) is precharged. At this time, since the output of the AND circuit 15 (R) of the precharge selection circuit 14 is at the L level, the precharge switch PT (R) is turned off so that the source line SL (R) is not precharged. It has become.

  Next, in the second half of the 1H period, the output of the AND circuit 16 (R) of the pixel write line selection circuit 17 falls to the L level, and in response to this, the potential of the gate line GL1-1 falls to the L level, and the pixel GS. The pixel transistor GT (R) of (R) is turned off. Further, the output of the AND circuit 16 (GB) rises to H level, and in response to this, the potential of the gate line GL1-2 becomes H level, and the pixel transistors GT (G) of the pixels GS (G) and GS (B). , GT (B) is turned on.

  At this time, when the source line SL (G) is selected according to the G enable signal GENB, the source signal S (G) corresponding to green (G) is output to the source line SL (G) through the source switch SW. . The source signal S (G) is written to the pixel GS (G) through the pixel transistor GT (G). Subsequently, when the source line SL (B) is selected according to the B enable signal BENB, the source signal S (B) corresponding to blue (B) is output to the source line SL (B) through the source switch SW. Is done. Then, the source signal S (B) is written into the pixel GS (B) through the pixel transistor GT (B).

  On the other hand, since the output of the AND circuit 15 (R) of the precharge selection circuit 14 rises to the H level, the precharge switch PT (R) is turned on and the source line SL (R) is precharged. At this time, since the outputs of the AND circuits 15 (G) and 15 (B) of the precharge selection circuit 14 are at the L level, the precharge switches PT (G) and PT (B) are off and the source line SL (G ), SL (B) is not precharged.

  FIG. 3 is a diagram illustrating a change in potential of the source line SL (R) to which the red (R) pixel GS (R) is connected. Conventionally, the source line SL (R) has been precharged before writing. However, according to the present invention, the source line SL (R) can be used while the pixel GS (G) and the pixel GS (B) are open. Is precharged.

  As described above, according to the present invention, during the period in which the pixel transistor of a certain pixel is on, the source line corresponding to the other pixel in which the pixel transistor is off is precharged. A long precharge period for each source line can be secured. As a result, crosstalk and insufficient writing of video data to the pixels can be reliably prevented.

  Needless to say, the present invention is not limited to the above-described embodiment and can be changed without departing from the scope of the invention. In the embodiment, the 1H period is divided into two periods, the first half and the second half. In the first half, the pixel transistor GT (R) of the pixel GS (R) is turned on to perform writing, and the source lines SL (G) and SL (B ), The pixel transistors GT (G) and GT (B) of the pixels GS (G) and GS (B) are turned on in the latter half to perform writing, and the source line SL (R) is precharged. However, if the source line connected to the other pixel transistor is turned off during the period in which the pixel transistor of a certain pixel is turned on, other modes may be used. May be.

  For example, in the first half of the 1H period, the pixel transistors GT (R) and GT (G) of the pixels GS (R) and GS (G) are turned on to perform writing, and the source line SL (B) is precharged. In the latter half, the pixel transistor GT (B) of the pixel GS (B) may be turned on to perform writing, and the source lines SL (R) and SL (G) may be precharged.

  In addition, the 1H period is divided into three periods. In the first period, the pixel transistor GT (R) of the pixel GS (R) is turned on to perform writing, and the source line SL (G) is precharged. In the second period following the period 1, the pixel transistor GT (G) of the pixel GS (G) is turned on to perform writing, and the source line SL (B) is precharged, and the second period continues. During the period 3, the pixel transistor GT (B) of the pixel GS (B) may be turned on to perform writing, and the source line SL (R) may be precharged.

  The present invention is also applicable to a display device other than a liquid crystal display device, such as an organic EL display device, as long as the display device includes a plurality of pixels including pixel transistors and precharges a source line to which each pixel is connected. Can be applied.

1 is a circuit diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 6 is an operation timing chart of the liquid crystal display device according to the embodiment of the present invention. It is a figure which shows the mode of the change of the electric potential of the source line of the liquid crystal display device by embodiment of this invention.

Explanation of symbols

10R, 10G, 10B Pixel electrode 11 Common electrode 12 Liquid crystal 13 Source selection circuit 14 Precharge selection circuit 15 (R), 15 (G), 15 (B) AND circuit 16 (R), 16 (GB) AND circuit 17 Pixel Write line selection circuit 100 Glass substrate GL1-1, GL1-2 Gate lines GT (R), GT (G), GT (B) Pixel transistors GS (R), GS (G), GS (B) Pixel PT (R ), PT (G), PT (B) Precharge switch SL (R), SL (G), SL (B) Source line SW Source switch

Claims (3)

Multiple source lines,
A precharge switch connected to each of the plurality of source lines;
A plurality of pixels each connected to the plurality of source lines and including a pixel switch;
Among the plurality of pixels, when a pixel switch of a certain pixel is turned on, a precharge switch of a source line connected to another pixel for which the pixel switch is turned off is turned on to precharge the source line. A display circuit comprising: a control circuit that performs control so as to perform. A first precharge switch connected to the first source line;
A first pixel including a first pixel switch connected to the first source line;
A second precharge switch connected to the second source line;
A second pixel including a second pixel switch connected to the second source line;
When the first pixel switch is on and the second pixel switch is off,
Turning off the first precharge switch, turning on the second precharge switch, and precharging the second source line;
When the first pixel switch is off and the second pixel switch is on,
A display device comprising: a control circuit that controls to turn off the second precharge switch and turn on the first precharge switch to perform precharge of the first source line. When the first pixel switch is on, a first source signal is output to the first source line, and when the second pixel switch is on, the first source signal is output to the second source line. The display device according to claim 2, further comprising a source selection circuit that outputs two source signals.

Images