JP2008205399A - Semiconductor integrated circuit design method - Google Patents

Abstract

Provided is a semiconductor integrated circuit design method capable of optimizing the size of a semiconductor chip and shortening the design time while enhancing power supply in layout design.
The present invention relates to a layout design of a semiconductor integrated circuit. First, after arranging a cell on a semiconductor chip, power wiring for the cell is performed (S1, S2). Next, a voltage drop generated on the power supply wiring is measured, and IR drop analysis is performed based on the measurement result (S3). Further, based on the IR drop analysis result, the arrangement position of the cells already arranged on the semiconductor chip is changed (S4, S5). After the completion, signal wiring between cells on the semiconductor chip is performed (S6).
[Selection] Figure 1

Description

  The present invention relates to a method for designing a semiconductor integrated circuit (LSI).

In recent years, the operation power supply voltage of semiconductor integrated circuits has been lowered with the miniaturization of processes and the reduction of power consumption, and the voltage drop due to the wiring pattern has become a problem due to the increase of the wiring resistance.
That is, the voltage supplied from the outside to the semiconductor integrated circuit is reduced in the voltage level at the center of the internal integrated circuit due to power consumption and power supply wiring resistance due to the operation of the internal integrated circuit. It is necessary to strengthen the power supply.

In order to strengthen this power supply, in the conventional layout design, for example, after the cells are automatically arranged on the semiconductor chip, automatic wiring is performed, and thereafter the IR drop is measured to reinforce the power supply.
Also, in the internal integrated circuit, it is difficult to increase the number of power supply lines or to reinforce the power supply after the automatic placement and routing, so measures such as increasing the number of initial power supply lines are adopted. Yes.

Furthermore, in order to strengthen the power supply of the semiconductor integrated circuit, the inventions described in Patent Document 1 and Patent Document 2 below are known.
In Patent Document 1, the amount of current flowing in each feeder line area is calculated based on the type and number of basic circuit cells arranged in each feeder line area, and the wiring width of the branch power supply wiring is determined based on the amount of current. The invention made is disclosed.

In Patent Document 2, after automatic placement and routing, the current consumption is calculated from the operating frequency of the functional cell and the actual output capacity of the functional cell, and the voltage drop value of each functional cell is used as a reference for each cell column. An invention for optimizing the wiring width and the cell row width is disclosed.
JP-A-8-23029 JP 2000-20576 A

However, the above prior art has the following problems.
(1) When there is no space for power supply reinforcement, it was necessary to redo the placement and routing.
(2) When the number of power supply wirings in the internal integrated circuit is increased, the size of the semiconductor chip increases because cells cannot be arranged in the region used as the power supply wiring.
(3) When the number of power supply wirings is increased, the size of the semiconductor chip is increased, and the remaining number cannot be automatically deleted, which is useless for the deletion. Time will occur.

(4) In the invention of Patent Document 1, the width of the power supply wiring can be optimized in each power supply area. However, in the power supply area where the width of the power supply wiring is increased, there is a situation where the area needs to be increased. As a result, the size of the semiconductor chip is increased.
(5) In the invention of Patent Document 2, the wiring width of the power supply and the width of the cell row can be optimized. However, when the wiring width of the power supply is increased, the size of the semiconductor chip is increased as a result.
SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor integrated circuit design method capable of optimizing the size of a semiconductor chip and shortening the design time while enhancing the power supply in layout design. It is to provide.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
A first invention is a method for designing a semiconductor integrated circuit, in which a cell is arranged on a semiconductor chip, and then a power supply wiring for the cell is measured, and a voltage drop generated on the power supply wiring is measured. A second step of performing IR drop analysis based on the measurement result, a third step of changing the arrangement position of the cells already arranged on the semiconductor chip based on the IR drop analysis result, and the third step. And a fourth step of performing signal wiring between cells on the semiconductor chip after the step is completed.

  In a second aspect based on the first aspect, in the second step, in the second step, an area on the semiconductor chip is divided according to the measured value of the voltage drop, and in the third step, out of the divided areas In order to obtain the use efficiency of any of the areas, and to change the density of the arrangement of the cells in the area based on the obtained use efficiency, the arrangement position of the cells already arranged in the area is changed.

  A third invention is a method for designing a semiconductor integrated circuit, in which a cell having a predetermined capacity is arranged on a semiconductor chip, and then a power supply wiring for the cell is performed, and a voltage drop generated on the power supply wiring A second step of performing IR drop analysis based on the measurement result, and changing a cell already arranged on the semiconductor chip to a cell having a different capability based on the IR drop analysis result A third step and a fourth step for performing signal wiring between cells on the semiconductor chip after the completion of the third step.

  In a fourth aspect based on the third aspect, in the second step, in the second step, an area on the semiconductor chip is divided according to the measured value of the voltage drop, and in the third step, among the divided areas A region having a large voltage drop changes a cell already arranged to a cell having a higher capacity, and a region having a small voltage drop changes a cell already arranged to a cell having a smaller capacity.

  A fifth invention is a method for designing a semiconductor integrated circuit, wherein after a cell is arranged on a semiconductor chip, a first step of performing power supply wiring for the cell, and a voltage drop generated on the power supply wiring are measured, A second step of performing IR drop analysis based on the measurement result, a third step of changing the wiring density of the power supply wiring already wired on the semiconductor chip based on the IR drop analysis result, And a fourth step of performing signal wiring between cells temporarily arranged on the semiconductor chip after the completion of the three steps.

In a sixth aspect based on the fifth aspect, in the second step, the region on the semiconductor chip is divided in accordance with the measured value of the voltage drop in the second step, and among the divided regions in the third step, In the area where the voltage drop is large, the power wiring already wired is changed so that the wiring density is lower than that. In the area where the voltage drop is low, the power wiring already wired is higher than that. Change as follows.
According to the present invention, it is possible to optimize the size of the semiconductor chip and shorten the design time while enhancing the power supply in the layout design.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
A first embodiment of a semiconductor integrated circuit design method of the present invention will be described with reference to FIGS.
The design method according to the first embodiment relates to the layout design of a semiconductor integrated circuit, and is performed by the procedure shown in FIG. 1 using an automatic placement and routing system based on the assistance of a computer. .

First, the cells registered in the computer are temporarily (temporarily) arranged on the semiconductor chip (step S1). Thereby, a plurality of cells are arranged at each desired position on the semiconductor chip.
Next, power supply wiring is performed for each of the plurality of cells (step S2). Thereby, each of the plurality of cells is connected to a predetermined power supply wiring.
Further, a voltage drop (IR drop) generated on the power supply wiring wired on the semiconductor chip is measured, and IR drop analysis is performed based on the measurement result (step S3). As an example of this IR drop analysis, a diagram as shown in FIG. 2 is displayed on the display screen of the computer.

FIG. 2 represents the distribution of IR drop on the semiconductor chip with contour lines, and the semiconductor chip is divided into regions A to G. The area A has the largest IR drop, the area B, the area C, the area D, the area E, and the area F decrease in the order, and the area G has the smallest IR drop.
Next, the cell use efficiency is calculated for an arbitrary area among the areas A to G divided according to the IR drop value (step S4), and the calculation result is displayed on the display screen of the computer. Here, the reason why the usage efficiency is obtained for an arbitrary area is that there is an area in which the cell arrangement position described later cannot be changed depending on the area. The arbitrary area is designated by the designer with reference to the display screen.
An example of the cell usage efficiency calculated as described above is shown in FIG. As shown in FIG. 3, the usage efficiency in the regions A to G is 20 to 50%.
In addition, the use efficiency of said cell is calculated | required by following (1) Formula.

  Cell usage efficiency = (total number of cells arranged in the area) / (total number of basic cells that can be arranged in the area) (1)

According to FIG. 3, it can be seen that the larger the IR drop region, the smaller the cell use efficiency.
Next, in order to change the density of the cell arrangement according to the IR drop value, the arrangement position of the already arranged cell is changed (corrected) (step S5). That is, the area where the IR drop value is large (the area where the cell usage efficiency is low) is relatively high, and the area where the IR drop value is low (the area where the cell usage efficiency is high) is the cell usage efficiency. The cells are rearranged so that the efficiency is relatively low.

By such cell rearrangement, the IR drop value can be made almost uniform (uniform) regardless of the region, and the power supply can be strengthened.
Next, when the rearrangement of cells is completed, wiring (signal wiring) between the cells is performed (step S6). As a result, the plurality of cells are connected to each other by signal wiring.
According to the first embodiment described above, the design time can be shortened while reinforcing the power supply during the layout design of the semiconductor integrated circuit.

Also, according to the first embodiment, the IR drop value can be made almost uniform everywhere on the semiconductor chip, so that the accuracy of the delay library is improved. That is, the yield is not improved and the signal timing is not excessively adjusted, and the size of the semiconductor chip can be optimized.
Furthermore, according to the first embodiment, since it is not necessary to wire a large number of power supply wires in advance, the chip size can be optimized and the wiring efficiency can be improved, so that the convergence in timing analysis can be improved. Will improve.

(Second Embodiment)
A second embodiment of the semiconductor integrated circuit design method of the present invention will be described with reference to FIG.
In the second embodiment, when the arrangement of cells is changed in the first embodiment, there is a case where the arrangement and wiring cannot be performed in accordance with the change, and this is dealt with.
Therefore, in the second embodiment, as shown in FIG. 4, the processes from step S1 to S6 are the same as the processes from step S1 to S6 in the first embodiment, and the processes in steps S7 and S8 are performed. Is added.

In the second embodiment, signal wiring between cells is performed in step S6. At this time, signal wiring cannot be performed, and it is determined by the computer whether or not an increase in the wiring layer is necessary (step). S7). As a result of this determination, when the signal wiring is completed and the wiring layer does not need to be increased, the processing is terminated.
On the other hand, if the signal wiring cannot be performed and the wiring layer needs to be increased, the process proceeds to step S8. In step S8, the number of wiring layers is increased, necessary wiring is performed using the wiring layers, and the process ends.
According to 2nd Embodiment described above, the effect similar to 1st Embodiment is realizable.

(Third embodiment)
A third embodiment of the semiconductor integrated circuit design method of the present invention will be described with reference to FIG.
The design method according to the third embodiment relates to the layout design of a semiconductor integrated circuit, and is performed by the procedure shown in FIG. 5 using an automatic placement and routing system based on the assistance of a computer. .
First, the cells registered in the computer are temporarily (temporarily) arranged on the semiconductor chip (step S11). Thereby, a plurality of cells are arranged at each desired position on the semiconductor chip.

  Here, as for the plurality of cells to be arranged, a plurality of cells having different capabilities are prepared in advance for each logic circuit (logic function). That is, each cell has the same function, and for example, three cells having different driving speeds (driving capabilities) from large, medium, and small are prepared. Then, when the plurality of cells are arranged, each cell has a medium driving speed.

Next, power supply wiring is performed for each of the plurality of cells (step S12). Thereby, each of the plurality of cells is connected to a predetermined power supply wiring.
Further, a voltage drop generated on the power supply wiring after the above wiring is measured, and IR drop analysis is performed based on the measurement result (step S13). An example of this IR drop analysis is shown in FIG. Thereby, the semiconductor chip is divided into a plurality of parts according to the IR drop.

Next, based on the IR drop analysis result, the cell already arranged on the semiconductor chip is changed to a cell having a different capability in accordance with the IR drop value (step S14). That is, among the divided areas, the area where the voltage drop is large is changed (replaced) to a cell having a higher driving speed than that of the already arranged area, and the area where the voltage drop is already arranged. Change the cell to a cell with a lower driving speed.
By such cell rearrangement, the cell driving speed can be made uniform regardless of the difference in the IR drop value. This is equivalent to strengthening the power supply.
Next, when the rearrangement of the cells is completed, wiring (signal wiring) between the cells is performed (step S15). As a result, the plurality of cells are connected to each other by signal wiring.

According to the third embodiment described above, the design time can be shortened while reinforcing the power supply when designing the layout of the semiconductor integrated circuit.
Further, according to the third embodiment, the driving speed can be made uniform regardless of the cells arranged on the semiconductor chip, so that the accuracy of the delay library is improved. That is, the yield is not improved and the timing is not adjusted excessively, and the size of the semiconductor chip can be optimized.
Furthermore, according to the third embodiment, since it is not necessary to wire a large number of power supply wires in advance, the chip size can be optimized and the wiring efficiency can be improved so that the convergence in timing analysis can be improved. Will improve.

(Fourth embodiment)
A fourth embodiment of the semiconductor integrated circuit design method of the present invention will be described with reference to FIGS.
The design method according to the fourth embodiment relates to the layout design of a semiconductor integrated circuit, and is performed by the procedure shown in FIG. 6 using an automatic placement and routing system based on the assistance of a computer. .
First, the cells registered in the computer are temporarily (temporarily) arranged on the semiconductor chip (step S21). Thereby, a plurality of cells are arranged at each desired position on the semiconductor chip.

Next, power supply wiring is performed for each of the plurality of cells (step S22). Thereby, each of the plurality of cells is connected to a predetermined power supply wiring. Here, an example of the arrangement of the cells and the power supply wiring on the semiconductor chip is as shown in FIG.
In FIG. 7, power supply wires are arranged in the vertical and horizontal directions. Of these, the thin power supply wires 11 arranged in the horizontal direction are arranged, for example, in the first metal layer, and the thick power supply wires are arranged in the vertical direction. For example, 12 is disposed in the metal first layer.

Of the power supply wirings 11 and 12, those indicated by hatching are connected by through holes at the intersections and used for the power supply voltage VDD. In addition, the parts other than the shaded part are connected by a through hole at the intersection and used for the power supply voltage VSS. Further, in FIG. 7, the square block represents the cell 13.
Next, a voltage drop (IR drop) generated on the power supply wiring wired on the semiconductor chip is measured, and IR drop analysis is performed based on the measurement result (step S23). An example of this IR drop analysis is shown in FIG. Thereby, the semiconductor chip is divided into regions A to C according to the size of the IR drop.

Next, according to the IR drop value, the wiring density of the power wiring already wired on the semiconductor chip is changed, and the power wiring is re-executed (rearranged) (step S24).
That is, among the divided areas A to C, in the area A where the IR drop (voltage drop) is large, the power supply wiring already wired is changed so that the wiring density is lower than that. Specifically, in the area A, the arrangement interval of the power supply wirings is widened (equivalent to reducing the number of power supply wirings), or the width of the power supply wiring itself is narrowed.

On the other hand, in the region C where the IR drop is small, the power wiring already wired is changed so that the wiring density is higher than that. Specifically, in the region C, the arrangement interval of the power supply wiring is narrowed (equivalent to increasing the number of power supply wirings), or the width of the power supply wiring itself is widened.
FIG. 9 shows an example of power supply wiring reimplemented based on this concept. This example is prepared in correspondence with the IR drop of FIG. 8, and among the semiconductor chips, the density of the power supply wiring is higher on the outer peripheral side where the IR drop is smaller, and the power supply wiring is higher on the center side where the IR drop is larger. Density is sparse. The density adjustment of the power supply wiring is realized by adjusting the arrangement interval with the width of the power supply wiring being constant.

Here, in FIG. 9, the power supply wirings arranged in the horizontal direction are arranged in the first metal layer, for example, and the power supply wiring arranged in the vertical direction is arranged in the first metal layer, for example.
By changing the power supply wiring as described above, the IR drop value can be made substantially uniform (uniform) regardless of the region, and the power supply can be strengthened.
Next, when the change of the power supply wiring is completed, the cell arrangement is corrected along with the change, and when the change is completed, wiring between the cells (signal wiring) is performed (step S25). As a result, the plurality of cells are connected to each other by signal wiring.

According to the fourth embodiment described above, the design time can be shortened while reinforcing the power supply when designing the layout of the semiconductor integrated circuit.
Further, according to the fourth embodiment, the IR drop value can be made almost uniform everywhere on the semiconductor chip, so that the accuracy of the delay library is improved. That is, the yield is not improved and the timing is not adjusted excessively, and the size of the semiconductor chip can be optimized.
Furthermore, according to the fourth embodiment, since it is not necessary to wire a large number of power supply wires in advance, the chip size can be optimized and the wiring efficiency can be improved, so that the convergence in timing analysis can be improved. Will improve.

It is a flowchart which shows the design procedure of 1st Embodiment of this invention. It is a figure which shows an example of IR drop analysis of 1st Embodiment. It is a figure which shows an example of the utilization efficiency of each area calculated | required based on the IR drop analysis. It is a flowchart which shows the design procedure of 2nd Embodiment of this invention. It is a flowchart which shows the design procedure of 3rd Embodiment of this invention. It is a flowchart which shows the design procedure of 4th Embodiment of this invention. It is a figure which shows an example of the arrangement | positioning wiring of 4th Embodiment. It is a figure which shows an example of IR drop analysis of 4th Embodiment. It is a figure which shows an example of the power supply wiring rearranged based on the result of the IR drop analysis.

Explanation of symbols

  11, 12 ... power supply wiring, 13 ... cell

Claims (6)

A method for designing a semiconductor integrated circuit, comprising:
A first step of arranging a cell on a semiconductor chip and then performing power supply wiring for the cell;
A second step of measuring a voltage drop generated on the power supply wiring and performing an IR drop analysis based on the measurement result;
A third step of changing an arrangement position of a cell already arranged on the semiconductor chip based on the analysis result of the IR drop;
A fourth step of performing signal wiring between cells on the semiconductor chip after completion of the third step;
A method for designing a semiconductor integrated circuit, comprising: In the second step, a region on the semiconductor chip is divided according to the measured value of the voltage drop,
In the third step, in order to obtain the use efficiency of an arbitrary area among the divided areas, and to change the density of the arrangement of cells in the area based on the obtained use efficiency, 2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the arrangement position of the arranged cell is changed. A method for designing a semiconductor integrated circuit, comprising:
A first step of arranging a cell having a predetermined capacity on a semiconductor chip and then performing power supply wiring for the cell;
A second step of measuring a voltage drop generated on the power supply wiring and performing an IR drop analysis based on the measurement result;
A third step of changing a cell already arranged on the semiconductor chip to a cell having a different capability based on the analysis result of the IR drop;
A fourth step of performing signal wiring between cells on the semiconductor chip after completion of the third step;
A method for designing a semiconductor integrated circuit, comprising: In the second step, a region on the semiconductor chip is divided according to the measured value of the voltage drop,
In the third step, among the divided areas, a cell having a large voltage drop is changed from a cell already arranged to a cell having a larger capacity, and a cell having a small voltage drop is already arranged. 4. The method of designing a semiconductor integrated circuit according to claim 3, wherein the cell is changed to a cell having a smaller capacity. A method for designing a semiconductor integrated circuit, comprising:
A first step of arranging a cell on a semiconductor chip and then performing power supply wiring for the cell;
A second step of measuring a voltage drop generated on the power supply wiring and performing an IR drop analysis based on the measurement result;
A third step of changing the wiring density of the power supply wiring already wired on the semiconductor chip based on the analysis result of the IR drop;
A fourth step of performing signal wiring between cells temporarily arranged on the semiconductor chip after the completion of the third step;
A method for designing a semiconductor integrated circuit, comprising: In the second step, a region on the semiconductor chip is divided according to the measured value of the voltage drop,
In the third step, among the divided areas, the power supply wiring which has already been wired is changed so that the wiring density is lower in the area where the voltage drop is large, and the area where the voltage drop is already wired. 6. The method of designing a semiconductor integrated circuit according to claim 5, wherein the power supply wiring is changed so that the wiring density is higher than that.

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