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JP2008306134A - Semiconductor module - Google Patents

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JP2008306134A
JP2008306134A JP2007154317A JP2007154317A JP2008306134A JP 2008306134 A JP2008306134 A JP 2008306134A JP 2007154317 A JP2007154317 A JP 2007154317A JP 2007154317 A JP2007154317 A JP 2007154317A JP 2008306134 A JP2008306134 A JP 2008306134A
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insulating substrate
layer
thermal expansion
conductor layer
constituent
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Eisuke Yagi
英介 八木
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

【課題】絶縁基板と導体層との間で発生する熱応力を緩和することが可能な半導体モジュールを提供する。
【解決手段】半導体モジュール１０は、第１熱膨張率を有する絶縁基板１５と、絶縁基板上に形成され、第２熱膨張率を有する導体層１３，１７と、導体層上に固定された半導体素子と、絶縁基板と導体層とを接合する接合層であって、熱膨張率の異なる複数の構成層を積層して構成されており、導体層側の構成層の熱膨張率は第１熱膨張率に近く、絶縁基板側の構成層の熱膨張率は第２熱膨張率に近い接合層１４，１６と、を備える。
【選択図】図２A semiconductor module capable of relieving thermal stress generated between an insulating substrate and a conductor layer is provided.
A semiconductor module includes an insulating substrate having a first coefficient of thermal expansion, conductor layers formed on the insulating substrate and having a second coefficient of thermal expansion, and a semiconductor fixed on the conductor layer. A joining layer that joins the element, the insulating substrate, and the conductor layer, and is formed by laminating a plurality of constituent layers having different thermal expansion coefficients. The thermal expansion coefficient of the constituent layer on the conductor layer side is the first heat The thermal expansion coefficient of the constituent layer on the insulating substrate side is close to the expansion coefficient, and the bonding layers 14 and 16 are close to the second thermal expansion coefficient.
[Selection] Figure 2

Description

本発明は、半導体素子を一部に備える半導体モジュールに関する。   The present invention relates to a semiconductor module partially including a semiconductor element.

従来文献（特開２００６−２６９７１３号公報）には、半導体モジュールの一例が示されている。この従来文献の半導体モジュールは、ヒートシンクに形成された有底穴に半導体チップを埋設するものであり、半導体チップは有底穴の底面にロウ付けされて接合される。
特開２００６−２６９７１３号公報 An example of a semiconductor module is shown in a conventional document (Japanese Patent Laid-Open No. 2006-269713). The semiconductor module of this prior art is a semiconductor chip embedded in a bottomed hole formed in a heat sink, and the semiconductor chip is brazed and joined to the bottom surface of the bottomed hole.
JP 2006-269713 A

半導体モジュールには、絶縁基板上に導体層を形成し、導体層上に半導体素子を配置したものがある。絶縁基板と導体層とでは熱膨張率に違いがあるため、絶縁基板および導体層が熱膨張または熱収縮した際に、絶縁基板と導体層との接合部位に大きな熱応力が発生し、クラックが発生することがある。   Some semiconductor modules have a conductor layer formed on an insulating substrate and a semiconductor element placed on the conductor layer. Because there is a difference in the thermal expansion coefficient between the insulating substrate and the conductor layer, when the insulating substrate and the conductor layer are thermally expanded or contracted, a large thermal stress is generated at the joint portion between the insulating substrate and the conductor layer, and cracks are generated. May occur.

本発明は、上記の課題を解決するためになされたもので、絶縁基板と導体層との間で発生する熱応力を緩和することが可能な半導体モジュールを提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor module capable of relieving thermal stress generated between an insulating substrate and a conductor layer.

上述した目的を達成するために、本発明に係る半導体モジュールは、第１熱膨張率を有する絶縁基板と、絶縁基板上に形成され、第２熱膨張率を有する導体層と、導体層上に固定された半導体素子と、絶縁基板と導体層とを接合する接合層であって、熱膨張率の異なる複数の構成層を積層して構成されており、絶縁基板側の構成層の熱膨張率は第１熱膨張率に近く、導体層側の構成層の熱膨張率は第２熱膨張率に近い接合層と、を備えることを特徴とする。   In order to achieve the above-described object, a semiconductor module according to the present invention includes an insulating substrate having a first coefficient of thermal expansion, a conductor layer formed on the insulating substrate and having a second coefficient of thermal expansion, and a conductor layer. A bonding layer that joins a fixed semiconductor element, an insulating substrate, and a conductor layer, and is formed by laminating a plurality of constituent layers having different thermal expansion coefficients. The thermal expansion coefficient of the constituent layer on the insulating substrate side And a bonding layer having a thermal expansion coefficient close to the first thermal expansion coefficient and a thermal expansion coefficient of the constituent layer on the conductor layer side being close to the second thermal expansion coefficient.

上述した半導体モジュールによれば、絶縁基板と導体層とを接合する接合層の熱膨張率が、絶縁基板側では第１熱膨張率に近く、導体層側では第２熱膨張率に近いため、絶縁基板および導体層の熱膨張または熱収縮により発生する熱応力を緩和することができ、接合層におけるクラックの発生を抑制することができる。   According to the semiconductor module described above, the thermal expansion coefficient of the bonding layer that joins the insulating substrate and the conductor layer is close to the first thermal expansion coefficient on the insulating substrate side, and close to the second thermal expansion coefficient on the conductor layer side. Thermal stress generated by thermal expansion or thermal contraction of the insulating substrate and the conductor layer can be alleviated, and the occurrence of cracks in the bonding layer can be suppressed.

上述した半導体モジュールにおいて、複数の構成層の成分比率が互いに異なることにより、熱膨張率が互いに異なっていることが好ましい。この構成によれば、複数の構成層の成分比率が互いに異なっており、複数の構成層の熱膨張率が互いに異なっている。このため、複数の構成層は成分比率が異なるだけであるため、複数の構成層どうしを互いに良好に接合することができ、接合層におけるクラックの発生を抑制することができる。   In the semiconductor module described above, it is preferable that the thermal expansion coefficients are different from each other because the component ratios of the plurality of constituent layers are different from each other. According to this configuration, the component ratios of the plurality of constituent layers are different from each other, and the thermal expansion coefficients of the plurality of constituent layers are different from each other. For this reason, since the plurality of constituent layers differ only in the component ratio, the plurality of constituent layers can be bonded to each other satisfactorily, and the occurrence of cracks in the bonding layer can be suppressed.

例えば、接合層は、絶縁基板と導体層とをロウ付けにより接合するものであり、構成層ごとにロウ材の成分比率が異なるものとすればよい。また、絶縁基板はセラミックスを材質とし、導体層は金属を材質とするものとすればよい。さらには、絶縁基板は窒化アルミニウムを材質とし、導体層はアルミニウムを材質とし、接合層はアルミニウム‐シリコン系合金を材質とするものとすればよい。   For example, the joining layer joins the insulating substrate and the conductor layer by brazing, and the component ratio of the brazing material may be different for each constituent layer. The insulating substrate may be made of ceramics, and the conductor layer may be made of metal. Furthermore, the insulating substrate may be made of aluminum nitride, the conductor layer may be made of aluminum, and the bonding layer may be made of an aluminum-silicon alloy material.

上述した半導体モジュールは、絶縁基板を基準として半導体素子とは反対側に設けられ、半導体素子が発生した熱を放熱する放熱部材を備えることが好ましい。この構成によれば、半導体素子が発生した熱は絶縁基板を介して放熱部材まで伝達され、放熱部材により放熱される。もし接合層にクラックが発生した場合には、絶縁基板と導体層との間の熱伝達率が低下し、放熱部材による放熱量が低下してしまう。よって、前述したように、熱膨張率の異なる複数の構成層を積層して構成された接合層により絶縁基板と導体層とを接合することにより、絶縁基板と導体層との間でクラックが発生することを抑制し、放熱部材による放熱量の低下を抑制することができる。   The semiconductor module described above preferably includes a heat dissipation member that is provided on the opposite side of the semiconductor element with respect to the insulating substrate and that dissipates heat generated by the semiconductor element. According to this configuration, the heat generated by the semiconductor element is transmitted to the heat radiating member via the insulating substrate, and is radiated by the heat radiating member. If a crack occurs in the bonding layer, the heat transfer coefficient between the insulating substrate and the conductor layer is lowered, and the heat radiation amount by the heat radiating member is lowered. Therefore, as described above, a crack is generated between the insulating substrate and the conductor layer by bonding the insulating substrate and the conductor layer with the bonding layer formed by laminating a plurality of constituent layers having different thermal expansion coefficients. It can suppress, and the fall of the thermal radiation amount by a heat radiating member can be suppressed.

上述した半導体モジュールにおいて、半導体素子は、電動機の駆動電流を生成するインバータ回路の一部であることが好ましい。このような半導体素子は、特に発熱量が大きい。よって、前述したように、熱膨張率の異なる複数の構成層を積層して構成された接合層により絶縁基板と導体層とを接合することにより、絶縁基板と導体層との間でクラックが発生することを顕著に抑制することができる。   In the semiconductor module described above, the semiconductor element is preferably a part of an inverter circuit that generates a drive current for the electric motor. Such a semiconductor element has a particularly large calorific value. Therefore, as described above, a crack is generated between the insulating substrate and the conductor layer by bonding the insulating substrate and the conductor layer with the bonding layer formed by laminating a plurality of constituent layers having different thermal expansion coefficients. This can be remarkably suppressed.

本発明によれば、絶縁基板と導体層との間で発生する熱応力を緩和することが可能な半導体モジュールを提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor module which can relieve | moderate the thermal stress which generate | occur | produces between an insulated substrate and a conductor layer can be provided.

以下、添付図面を参照して、本発明の好適な実施形態について詳細に説明する。なお、説明において、同一要素又は同一機能を有する要素には、同一符号を用いることとし、重複する説明は省略する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

図１は、半導体モジュール１０を示す側面図である。半導体モジュール１０は、半導体素子１１、ハンダ層１２、導体層１３、絶縁基板１５、導体層１７、ハンダ層１８、放熱部材１９、を備えている。本実施形態の半導体モジュール１０は、電動機（モータ）を回転駆動するためのインバータ回路の一部を構成するものであり、電動機を駆動源とする車両に搭載されるものである。   FIG. 1 is a side view showing the semiconductor module 10. The semiconductor module 10 includes a semiconductor element 11, a solder layer 12, a conductor layer 13, an insulating substrate 15, a conductor layer 17, a solder layer 18, and a heat dissipation member 19. The semiconductor module 10 of this embodiment constitutes a part of an inverter circuit for rotationally driving an electric motor (motor), and is mounted on a vehicle using the electric motor as a drive source.

絶縁基板１５は、窒化アルミニウム（ＡｌＮ）を材質とする板状の部材である。絶縁基板１５の上側表面には、所定パターンの導体層１３が形成されている。導体層１３は、アルミニウム（Ａｌ）を材質とする薄膜である。この導体層１３の上側表面には、半導体素子１１としてＩＧＢＴ（Insulated Gate Bipolar Transistor）素子が載置されている。半導体素子１１はハンダ付けにより導体層１３に接合されており、半導体素子１１と導体層１３との間にはハンダ金属からなるハンダ層１２が存在する。   The insulating substrate 15 is a plate-like member made of aluminum nitride (AlN). A conductor layer 13 having a predetermined pattern is formed on the upper surface of the insulating substrate 15. The conductor layer 13 is a thin film made of aluminum (Al). An IGBT (Insulated Gate Bipolar Transistor) element is mounted as the semiconductor element 11 on the upper surface of the conductor layer 13. The semiconductor element 11 is joined to the conductor layer 13 by soldering, and a solder layer 12 made of a solder metal exists between the semiconductor element 11 and the conductor layer 13.

なお、導体層１３は、ＩＧＢＴ素子１１を載置するために用いられるだけでなく、アルミニウムを材質とする複数のワイヤーを接続するためにも用いられる。ワイヤーを介してＩＧＢＴ素子１１がダイオードや電源など（不図示）と接続されることにより、インバータ回路が形成される。なお、インバータ回路が完成時には、ＩＧＢＴ素子１１の上側表面は、図示されない別の電極に接続される。   The conductor layer 13 is used not only for mounting the IGBT element 11 but also for connecting a plurality of wires made of aluminum. The IGBT element 11 is connected to a diode, a power source or the like (not shown) via a wire, thereby forming an inverter circuit. When the inverter circuit is completed, the upper surface of the IGBT element 11 is connected to another electrode (not shown).

一方、絶縁基板１５の下側表面には、所定パターンの導体層１７が形成されている。導体層１７は、アルミニウム（Ａｌ）を材質とする薄膜である。この導体層１７の下側表面には、ハンダ付けにより放熱部材１９が接合されており、放熱部材１９と導体層１７との間にはハンダ金属からなるハンダ層１８が存在する。放熱部材１９は、金属を材質とする板状の部材であり、半導体素子１１で発生して絶縁基板１５を介して伝達される熱を放熱するために用いられる。   On the other hand, a conductor layer 17 having a predetermined pattern is formed on the lower surface of the insulating substrate 15. The conductor layer 17 is a thin film made of aluminum (Al). A heat radiating member 19 is joined to the lower surface of the conductor layer 17 by soldering, and a solder layer 18 made of a solder metal exists between the heat radiating member 19 and the conductor layer 17. The heat radiating member 19 is a plate-like member made of metal and is used to radiate heat generated in the semiconductor element 11 and transmitted through the insulating substrate 15.

図２は、絶縁基板１５と導体層１３，１７との接合部分５０を拡大して示す拡大図である。絶縁基板１５と導体層１３との間には、絶縁基板１５と導体層１３とをロウ付けにより接合するための接合層１４が存在している。また、絶縁基板１５と導体層１７との間には、絶縁基板１５と導体層１７とをロウ付けにより接合するための接合層１６が存在している。   FIG. 2 is an enlarged view showing the joint portion 50 between the insulating substrate 15 and the conductor layers 13 and 17 in an enlarged manner. A bonding layer 14 for bonding the insulating substrate 15 and the conductor layer 13 by brazing exists between the insulating substrate 15 and the conductor layer 13. In addition, a bonding layer 16 for bonding the insulating substrate 15 and the conductor layer 17 by brazing exists between the insulating substrate 15 and the conductor layer 17.

接合層１４は、熱膨張率の異なる３層の構成層からなり、絶縁基板１５に近い側から順に、第１構成層１４ａ、第２構成層１４ｂおよび第３構成層１４ｃを有する。３つの構成層１４ａ，１４ｂ，１４ｃのロウ材の成分は互いに異なっており、第１構成層１４ａはＡＬ‐７５Ｓｉを成分とし、第２構成層１４ｂはＡＬ‐５０Ｓｉを成分とし、第３構成層１４ｃはＡＬ‐２５Ｓｉを成分としている。これらの構成層１４ａ，１４ｂ，１４ｃは互いに構成比率が異なるだけであるため、互いに高い強度で接合される。   The bonding layer 14 includes three constituent layers having different thermal expansion coefficients, and includes a first constituent layer 14a, a second constituent layer 14b, and a third constituent layer 14c in order from the side close to the insulating substrate 15. The components of the brazing materials of the three constituent layers 14a, 14b, and 14c are different from each other, the first constituent layer 14a contains AL-75Si, the second constituent layer 14b contains AL-50Si, and the third constituent layer. 14c contains AL-25Si as a component. These constituent layers 14a, 14b, and 14c are bonded to each other with high strength because they only differ in constituent ratio.

接合層１６は、熱膨張率の異なる３層の構成層からなり、絶縁基板１５に近い側から順に、第１構成層１６ａ、第２構成層１６ｂおよび第３構成層１６ｃを有する。３つの構成層１６ａ，１６ｂ，１６ｃのロウ材の成分は互いに異なっており、第１構成層１６ａはＡＬ‐７５Ｓｉを成分とし、第２構成層１６ｂはＡＬ‐５０Ｓｉを成分とし、第３構成層１６ｃはＡＬ‐２５Ｓｉを成分としている。これらの構成層１６ａ，１６ｂ，１６ｃは互いに構成比率が異なるだけであるため、互いに高い強度で接合される。   The bonding layer 16 includes three constituent layers having different thermal expansion coefficients, and includes a first constituent layer 16a, a second constituent layer 16b, and a third constituent layer 16c in order from the side closer to the insulating substrate 15. The components of the brazing material of the three constituent layers 16a, 16b, and 16c are different from each other, the first constituent layer 16a contains AL-75Si, the second constituent layer 16b contains AL-50Si, and the third constituent layer. 16c contains AL-25Si as a component. These constituent layers 16a, 16b, and 16c are bonded to each other with high strength because they only differ in constituent ratio.

図３は、絶縁基板１５と導体層１３，１７との接合部分における成分と熱膨張率との関係を示す表である。図３に示されるように、絶縁基板１５（ＡｌＮ）の熱膨張係数は４．３ｐｐｍ（第１熱膨張率）であり、導体層１３，１７（ＡＬ）の熱膨張係数は２５ｐｐｍ（第２熱膨張率）である。各構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃの熱膨張係数は、絶縁基板１５の熱膨張係数と導体層１３，１７の熱膨張係数の間であり、第１構成層１４ａ，１６ａ（ＡＬ‐７５Ｓｉ）の熱膨張係数は９．３ｐｐｍであり、第２構成層１４ｂ，１６ｂ（ＡＬ‐５０Ｓｉ）の熱膨張係数は１４．５ｐｐｍであり、第３構成層１４ｃ，１６ｃ（ＡＬ‐２５Ｓｉ）の熱膨張係数は１９．８ｐｐｍである。すなわち、構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃは、シリコンの比率が７５％、５０％、２５％と段階的に変化するアルミニウム合金であり、熱膨張係数が段階的に変化している。   FIG. 3 is a table showing the relationship between the component and the thermal expansion coefficient at the joint portion between the insulating substrate 15 and the conductor layers 13 and 17. As shown in FIG. 3, the thermal expansion coefficient of the insulating substrate 15 (AlN) is 4.3 ppm (first thermal expansion coefficient), and the thermal expansion coefficient of the conductor layers 13 and 17 (AL) is 25 ppm (second thermal expansion coefficient). Expansion coefficient). The thermal expansion coefficient of each constituent layer 14a, 14b, 14c, 16a, 16b, 16c is between the thermal expansion coefficient of the insulating substrate 15 and the thermal expansion coefficient of the conductor layers 13, 17, and the first constituent layers 14a, 16a ( AL-75Si) has a thermal expansion coefficient of 9.3 ppm, the second constituent layers 14b and 16b (AL-50Si) have a thermal expansion coefficient of 14.5 ppm, and the third constituent layers 14c and 16c (AL-25Si). The thermal expansion coefficient of is 19.8 ppm. That is, the constituent layers 14a, 14b, 14c, 16a, 16b, and 16c are aluminum alloys in which the ratio of silicon changes in steps of 75%, 50%, and 25%, and the thermal expansion coefficient changes in steps. Yes.

本実施形態に係る半導体モジュール１０によれば、絶縁基板１５と導体層１３，１７とを接合する接合層１４，１６は、熱膨張率の異なる複数の構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃを積層して構成されている。そして、絶縁基板１５側の構成層の熱膨張率は導体層１３，１７側の構成層の熱膨張率と比較して第１熱膨張率に近く、導体層１３，１７側の構成層の熱膨張率は絶縁基板１５側の構成層の熱膨張率と比較して第２熱膨張率に近い。すなわち、絶縁基板１５と導体層１３，１７とを接合する接合層１４，１６の熱膨張率が、絶縁基板１５側では第１熱膨張率に近く、導体層１３，１７側では第２熱膨張率に近いため、絶縁基板１５および導体層１３，１７の熱膨張または熱収縮により発生する熱応力を緩和することができ、接合層１４，１６においてクラックが発生し進展することを抑制することができる。   According to the semiconductor module 10 according to the present embodiment, the bonding layers 14 and 16 that bond the insulating substrate 15 and the conductor layers 13 and 17 have a plurality of constituent layers 14a, 14b, 14c, 16a, and 16b having different thermal expansion coefficients. , 16c are laminated. The thermal expansion coefficient of the constituent layer on the insulating substrate 15 side is closer to the first thermal expansion coefficient than the thermal expansion coefficient of the constituent layer on the conductor layers 13 and 17 side, and the heat of the constituent layer on the conductor layers 13 and 17 side. The expansion coefficient is close to the second thermal expansion coefficient as compared with the thermal expansion coefficient of the constituent layer on the insulating substrate 15 side. That is, the thermal expansion coefficient of the bonding layers 14 and 16 that join the insulating substrate 15 and the conductor layers 13 and 17 is close to the first thermal expansion coefficient on the insulating substrate 15 side, and the second thermal expansion coefficient on the conductor layers 13 and 17 side. Therefore, the thermal stress generated by the thermal expansion or contraction of the insulating substrate 15 and the conductor layers 13 and 17 can be relieved, and the occurrence of cracks in the bonding layers 14 and 16 can be suppressed. it can.

また、本実施形態に係る半導体モジュール１０によれば、複数の構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃの成分比率が互いに異なることにより、熱膨張率が互いに異なっている。この構成によれば、複数の構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃは成分比率が異なるだけであるため、複数の構成層１４ａ，１４ｂ，１４ｃ，１６ａ，１６ｂ，１６ｃどうしを互いに良好に接合することができ、接合層１４，１６においてクラックが発生し進展することを抑制することができる。   Further, according to the semiconductor module 10 according to the present embodiment, the thermal expansion coefficients are different from each other because the component ratios of the plurality of constituent layers 14a, 14b, 14c, 16a, 16b, and 16c are different from each other. According to this configuration, the plurality of component layers 14a, 14b, 14c, 16a, 16b, and 16c only differ in the component ratio, and therefore the plurality of component layers 14a, 14b, 14c, 16a, 16b, and 16c are mutually good. It is possible to prevent the cracks from occurring and progressing in the bonding layers 14 and 16.

なお、本実施形態では、熱膨張率が段階的に変化する複数のロウ材を積層することにより、接合層１４，１６に発生する熱応力を緩和したが、本発明はこれに限定されない。例えば、他の実施形態では、セラミックスおよび金属の複合材料として、熱膨張率が段階的に変化する傾斜機能材料を構成し、上述した実施形態のロウ材に代えてこの傾斜機能材料を用いてもよい。   In the present embodiment, the thermal stress generated in the bonding layers 14 and 16 is relaxed by laminating a plurality of brazing materials whose coefficient of thermal expansion changes stepwise, but the present invention is not limited to this. For example, in another embodiment, a functionally gradient material in which the coefficient of thermal expansion changes stepwise as a composite material of ceramics and metal may be used instead of the brazing material of the above-described embodiment. Good.

なお、本実施形態では、接合層１４，１６は３層で構成されているが、他の実施形態では、接合層１４，１６は２層または４層以上で構成されてもよい。接合層１４，１６が２層または４層以上で構成されても、熱膨張率を段階的に変化させるものであれば、接合層１４，１６に発生する熱応力を緩和する効果を得ることができる。   In the present embodiment, the bonding layers 14 and 16 are configured by three layers. However, in other embodiments, the bonding layers 14 and 16 may be configured by two layers or four or more layers. Even if the bonding layers 14 and 16 are composed of two layers or four or more layers, if the coefficient of thermal expansion is changed stepwise, the effect of relaxing the thermal stress generated in the bonding layers 14 and 16 can be obtained. it can.

なお、本実施形態では、半導体モジュール１０はインバータ回路の一部として用いられるが、その他の種類の電力変換モジュールに用いられてもよい。   In the present embodiment, the semiconductor module 10 is used as a part of the inverter circuit, but may be used in other types of power conversion modules.

半導体モジュールを示す側面図である。It is a side view which shows a semiconductor module. 絶縁基板と導体層との接合部分を示す拡大図である。It is an enlarged view which shows the junction part of an insulated substrate and a conductor layer. 絶縁基板と導体層との接合部分の成分を示す表である。It is a table | surface which shows the component of the junction part of an insulated substrate and a conductor layer.

符号の説明Explanation of symbols

１０…半導体モジュール、１１…半導体素子、１２…ハンダ層、１３…導体層、
１４…接合層、１４ａ…第１構成層、１４ｂ…第２構成層、１４ｃ…第３構成層、
１５…絶縁基板、１６…接合層、１６ａ…第１構成層、１６ｂ…第２構成層、
１６ｃ…第３構成層、１７…導体層、１８…ハンダ層、１９…放熱部材 DESCRIPTION OF SYMBOLS 10 ... Semiconductor module, 11 ... Semiconductor element, 12 ... Solder layer, 13 ... Conductor layer,
14 ... bonding layer, 14a ... first constituent layer, 14b ... second constituent layer, 14c ... third constituent layer,
15 ... Insulating substrate, 16 ... Bonding layer, 16a ... First component layer, 16b ... Second component layer,
16c ... third component layer, 17 ... conductor layer, 18 ... solder layer, 19 ... heat dissipation member

Claims (7)

第１熱膨張率を有する絶縁基板と、
前記絶縁基板上に形成され、第２熱膨張率を有する導体層と、
前記導体層上に固定された半導体素子と、
前記絶縁基板と前記導体層とを接合する接合層であって、熱膨張率の異なる複数の構成層を積層して構成されており、前記絶縁基板側の構成層の熱膨張率は第１熱膨張率に近く、前記導体層側の構成層の熱膨張率は第２熱膨張率に近い接合層と、
を備えることを特徴とする半導体モジュール。 An insulating substrate having a first coefficient of thermal expansion;
A conductor layer formed on the insulating substrate and having a second coefficient of thermal expansion;
A semiconductor element fixed on the conductor layer;
It is a bonding layer for bonding the insulating substrate and the conductor layer, and is formed by laminating a plurality of constituent layers having different thermal expansion coefficients, and the thermal expansion coefficient of the constituent layer on the insulating substrate side is the first heat. The thermal expansion coefficient of the component layer on the conductor layer side is close to the expansion coefficient, and the bonding layer close to the second thermal expansion coefficient,
A semiconductor module comprising: 前記接合層において、前記複数の構成層の成分比率が互いに異なることにより、熱膨張率が互いに異なっていることを特徴とする請求項１に記載の半導体モジュール。   2. The semiconductor module according to claim 1, wherein the bonding layers have different coefficient of thermal expansion due to different component ratios of the plurality of constituent layers. 前記接合層は、前記絶縁基板と前記導体層とをロウ付けにより接合するものであり、前記構成層ごとにロウ材の成分比率が異なることを特徴とする請求項１〜２のいずれか１項に記載の半導体モジュール。   The said joining layer joins the said insulating substrate and the said conductor layer by brazing, and the component ratio of brazing material differs for every said structural layer, The any one of Claims 1-2 characterized by the above-mentioned. The semiconductor module described in 1. 前記絶縁基板はセラミックスを材質とし、前記導体層は金属を材質とすることを特徴とする請求項１〜３のいずれか１項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the insulating substrate is made of ceramics, and the conductor layer is made of metal. 前記絶縁基板は窒化アルミニウムを材質とし、前記導体層はアルミニウムを材質とし、前記接合層はアルミニウム‐シリコン系合金を材質とすることを特徴とする請求項１〜４のいずれか１項に記載の半導体モジュール。   5. The insulating substrate according to claim 1, wherein the insulating substrate is made of aluminum nitride, the conductor layer is made of aluminum, and the bonding layer is made of an aluminum-silicon alloy material. Semiconductor module. 前記絶縁基板を基準として前記半導体素子とは反対側に設けられ、前記半導体素子が発生した熱を放熱する放熱部材を備えることを特徴とする請求項１〜５のいずれか１項に記載の半導体モジュール。   6. The semiconductor according to claim 1, further comprising a heat radiating member provided on a side opposite to the semiconductor element with respect to the insulating substrate and radiating heat generated by the semiconductor element. module. 前記半導体素子は、電動機を駆動するための電流を生成するためのものであることを特徴とする請求項１〜６のいずれか１項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the semiconductor element is for generating a current for driving an electric motor.
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US20130300248A1 (en) * 2012-05-09 2013-11-14 Aisin Aw Co., Ltd. Expansion sheet for rotary electric machine, stator for rotary electric machine using the same, and manufacturing method of stator for rotary electric machine
US9537364B2 (en) * 2012-05-09 2017-01-03 Toyota Jidosha Kabushiki Kaisha Rotary electric motor stator with thermally expanding layered slot liner
WO2014156507A1 (en) * 2013-03-27 2014-10-02 日本碍子株式会社 Composite substrate and elastic wave device
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