JP2009054745A - Method of manufacturing core substrate for semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost and improve yield by efficiently manufacturing a core substrate to be used as a base material for a semiconductor package. <P>SOLUTION: First, a plurality of flat plates 11-16 containing at least one grooved flat plate are prepared. Each flat plate is made of an insulative material and rectangular in a plan view. The grooved flat plates 13-16 have a plurality of grooves GR formed in parallel in one direction on at least one of their surfaces. Then, after the groove GR is filled with a conductive material 17, the respective flat plates are stacked while the grooved flat plates 13-16 are located inside and integrated by predetermined bonding technology. The integrated structure 20 is cut into a required thickness from a direction vertical to the direction where the groove GR is formed to obtain the core substrate 10. The groove GR forms a through hole TH of the core substrate 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for manufacturing a wiring board (also referred to as a “semiconductor package”) used for mounting chip components such as semiconductor elements, and more particularly to a multilayer wiring structure adapted to high density and high functionality. The present invention relates to a method for manufacturing a core substrate to be used as a base substrate of a semiconductor package having the following.

  When manufacturing semiconductor packages such as BGA (Ball Grid Array), LGA (Land Grid Array), and PGA (Pin Grid Array), a core layer (core substrate) generally used as a base material for the package On both sides or one side, for example, by build-up method, conductor pattern (wiring layer) formation, insulation layer formation, via hole formation in the insulation layer are repeated in order to form a multilayer wiring structure, and finally the outermost surface Is covered with a protective film, and a necessary portion of the protective film is opened to expose a part of the conductor pattern (pad portion or land portion). Further, in the case of BGA or PGA, balls or pins as external connection terminals are joined to the exposed pad portion or the like. Such a semiconductor package has a chip component such as a semiconductor element mounted on one surface and is mounted on a mounting substrate such as a printed circuit board via an external connection terminal provided on the other surface. . That is, the chip component and the mounting substrate are electrically connected via the semiconductor package.

  For this reason, a core layer (core substrate) used as a base substrate of a semiconductor package is formed with a through hole as a means for electrically conducting both surfaces, and the through hole is filled with a conductive material. ing. In the conventional method, a base substrate of a predetermined size and thickness (for example, a double-sided copper-clad laminate for a plastic package, a ceramic package for a ceramic package) If a ceramic package is used after preparing a through-hole by drilling with a mechanical drill or the like at the required location on the base substrate, a green sheet (alumina or aluminum nitride powder bonded with an organic resin) is prepared. Conduct the metallization process on the surface and fill the through-holes on the surface by electrolytic plating etc. for plastic packages and screen printing method using conductive paste for ceramic packages. A pattern is formed. In other words, one hole for each required package, drilling (through-hole formation), metalizing (metal layer formation), hole-filling (filling conductor into the through-hole) in the base substrate It was necessary to do etc.

As a technique related to such a conventional technique, for example, as described in Patent Document 1, a glass or sintered ceramic thin plate is sandblasted to process through holes and wiring grooves and filled with a conductive material. There is one in which a laminated wiring board is manufactured by stacking and heating to electrically connect through holes. In addition, as described in Patent Document 2, a columnar green body in which a metal wire made of a metal having a melting point higher than the sintering temperature of the sintered body is embedded in parallel to the axis is formed. The fired body is fired at a temperature higher than the melting point, pour point or softening point of the insulating base of the sintered body to obtain a sintered body, and then the sintered body is formed to a predetermined thickness from the direction perpendicular to the axis. Some of them are manufactured by cutting.
Japanese Patent Laid-Open No. 10-284836 JP-A-8-78580

  As described above, according to the conventional technology, when forming a through hole necessary to electrically connect both surfaces of a core substrate for a semiconductor package, depending on the type of the package, the function of the chip component to be mounted, and the like. One by one, the base substrate had to be processed such as drilling, metalizing, and hole filling.

  For this reason, it took a long time to produce a core substrate suitable for the package, and there was a problem that the target core substrate could not be produced efficiently. In addition, since the time required for manufacturing the core substrate is prolonged, there is a problem that the manufacturing cost increases and the yield decreases.

  In particular, in the case of a ceramic package, after the required processing (drilling, metalizing, hole filling, etc.) is performed on the green sheet, two or more layers of the processed green sheet are laminated and integrated, and then the binder removal process is performed. The ceramic substrate molded body is fired (sintered), and therefore, a phenomenon (shrinkage) occurs in which the size of the substrate obtained during the sintering is smaller than that of the molded body. . As a result, there is a problem that a fine through hole cannot be formed with high accuracy.

  The present invention has been created in view of the problems in the prior art, and can efficiently manufacture a core substrate used as a base substrate of a semiconductor package, and thus contributes to a reduction in manufacturing cost and an improvement in yield. An object of the present invention is to provide a method for manufacturing a core substrate for a semiconductor package.

  In order to solve the above-described problems of the prior art, according to the present invention, a step of preparing a plurality of flat plates including at least one grooved flat plate, each flat plate being made of an insulating material and planarly A step of preparing a plurality of flat plates including a shape that is rectangular when viewed and has a form in which a plurality of grooves are formed in parallel in one direction on at least one side of the flat plate with grooves; And stacking the plurality of flat plates and integrating them using a predetermined joining technique, and the integrated structure with a required thickness from a direction perpendicular to the direction in which the grooves are formed. And a method of manufacturing a core substrate for a semiconductor package.

  According to the method for manufacturing a core substrate for a semiconductor package according to the present invention, a plurality of flat plates including a grooved flat plate in which a plurality of grooves are formed in parallel in one direction on at least one surface, for example, using the core substrate Prepare the required number according to the customer's request for manufacturing the semiconductor package, and arrange these flat plates with the grooved flat plate inside and laminate them to produce an integrated structure. The core substrate is obtained by cutting out from the direction perpendicular to the direction in which the grooves constituting the holes are formed, for example, to a required thickness according to the customer's request.

  That is, it is not necessary to perform the required processing (drilling, metalizing, hole filling, etc.) one by one for each package as in the past, and a structure in which a plurality of flat plates including grooved flat plates are laminated and integrated, Since it is only necessary to cut this structure to a required thickness from a direction perpendicular to the direction of the groove, the target core substrate can be efficiently manufactured. Further, even when the thickness of the core substrate is changed according to the request from the customer side, it can be easily handled, so that even core substrates having different thicknesses can be easily manufactured.

  Further, since the target core substrate can be efficiently manufactured, the manufacturing cost can be reduced and the yield can be improved.

  Further, even when ceramics are used as the material constituting each flat plate, the problem of shrinkage (shrinkage) does not occur because the method of sintering the ceramic substrate compact is not used as in the prior art. As a result, it is possible to manufacture a core substrate having high precision and fine through holes.

  Other process features of the method for manufacturing a core substrate for a semiconductor package according to the present invention and specific processing based on the process features will be described with reference to the embodiments of the present invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a perspective view (partially a sectional view) showing a manufacturing process of a core substrate for a semiconductor package according to an embodiment of the present invention.

  In this embodiment, it is intended to produce a core substrate used as a base substrate of a plastic package. The manufactured core substrate 10 (FIG. 1D) is formed by penetrating a desired number (20 in the illustrated example) of through holes TH in the thickness direction of the substrate 10 (left and right in the illustrated example). Each through hole TH is filled with a conductive material (conductor 17 in FIG. 1B).

  The material, form, and the like of each member constituting the core substrate for semiconductor package (core substrate with through hole) 10 according to the present embodiment will be specifically described in relation to the process described below.

  First, in the first step (see FIG. 1A), a required number of rectangular flat plates are prepared in plan view. In the illustrated example, six flat plates 11 to 16 are prepared. The size, thickness, and number of flat plates to be prepared are appropriately determined according to the demands of the customer who manufactures a semiconductor package such as BGA using the finally obtained core substrate 10 (FIG. 1 (d)). Is done. The size, thickness, and number of flat plates determined in this way define the size in the surface direction of the finally obtained core substrate 10.

  In addition, a plurality of grooves GR are formed in parallel in the longitudinal direction of at least one of the prepared flat plates (in the example shown, four sheets indicated by 13 to 16). In the illustrated example, five grooves GR are formed on one side (upper side) of each of the flat plates 13 to 16 in parallel with the longitudinal direction. In this example, the groove GR is formed only on one side of the flat plate, but may be formed on both sides as necessary. Also, the direction in which the grooves are formed is not necessarily formed in the longitudinal direction, and in some cases, a plurality of grooves may be formed in parallel in a direction perpendicular thereto. The flat plates 13 to 16 with the grooves GR formed in this way are also referred to as “grooved flat plates” for the purpose of distinguishing them from the flat plates 11 and 12 with no grooves formed. Each groove GR formed in each of the grooved flat plates 13 to 16 constitutes a through hole TH of the core substrate 10 finally obtained.

  As a material of the flat plates 11 to 16, an insulating material is basically used, and for example, glass, ceramics, build-up material (resin), glass cloth, or the like is used. As the ceramic, low-temperature fired ceramics such as alumina (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), glass ceramics, and the like can be used.

  In this embodiment, a case where Pyrex glass (trade name of borosilicate glass manufactured by Corning) is used as a material for the flat plates 11 to 16 will be described as an example. The grooved flat plates 13 to 16 can be produced by, for example, blasting the Pyrex glass (flat plate) formed to a required size. Blasting uses silica sand, steel grit, etc. as a polishing material, and these are mixed with compressed air and sprayed onto the surface of the object to be processed (in this case, glass). GR formation).

  Although not shown in particular, a dry film resist as a mask is formed in a required shape on one surface of each glass substrate (a flat plate before the groove GR is formed) formed in a required size. Patterning is performed, and fine abrasive grains (for example, SiC # 700) are sprayed onto the glass substrate exposed from the opening of the resist (mask). Thereby, the said part is shaved by the pressure of the spray and the groove | channel GR is formed. The cross-sectional shape of the groove GR at this time has a trapezoidal shape having a taper surface of about 15 to 20 ° (FIG. 1B). Such grooves GR are formed with an opening width of about 120 μm and a pitch of about 500 μm.

  Since the cross-sectional shape of the formed groove GR is substantially trapezoidal, the cross-sectional shape of the through hole TH of the core substrate 10 finally obtained also has a substantially trapezoidal shape. Therefore, when a shape close to a general circle is desired as the cross-sectional shape of the through hole TH, the grooves GR may be formed at corresponding positions on the two opposing flat plates. That is, the two grooved flat plates in which the grooves GR are formed in the same manner may be stacked such that the surfaces on which the grooves GR are formed face each other and the positions of the grooves GR are aligned.

  As a method other than blasting, for example, wet etching using a hydrofluoric acid solution, ultrasonic machining, laser machining, machining with a mechanical drill, or the like can be used as appropriate. Ultrasonic machining is performed on a target workpiece using a tool such as a bit that vibrates ultrasonically with abrasive grains (high-hardness particles such as alumina, silicon carbide, boron carbide, diamond, or powdered substance) applied to it. (In this case, the groove GR is formed). In the case of laser processing, a CO2 laser, a YAG laser, an excimer laser, or the like can be used.

  The cross-sectional shape of the groove GR to be formed is a trapezoidal shape in the illustrated example. However, the shape is not limited to this shape, and may be any other shape such as a V shape or a U shape. It is enough. In addition, the size of the groove GR to be formed and the formation interval (pitch) thereof are the same size and are arranged at equal intervals in the illustrated example, but it is of course not limited thereto. For example, in order to use it for another purpose such as a thermal via, the size of the corresponding groove (through hole) may be formed larger than the groove (through hole) of other portions.

  In the next step (see FIG. 1B), a conductive material (conductor 17) is filled in each groove GR formed in each of the grooved flat plates 13-16. As the conductive material, copper (Cu), gold (Au), nickel (Ni), titanium (Ti), chromium (Cr), or the like is used. In addition, as a filling method, a method of filling by electrolytic plating after performing sputtering or electroless plating, a method of filling only by electroless plating, a method of filling by screen printing using a conductive paste, or the like can be used. .

  In the example of FIG. 1B, the groove GR is completely filled with the conductor 17, but it is considered that this conductor 17 is finally used as a means for electrically connecting both surfaces of the core substrate 10. Then, the groove GR does not necessarily need to be completely filled, and it is sufficient that a conductive material is deposited on at least the inner wall surface of the groove GR. For example, the conductor may be deposited only on the inner wall surface of the groove GR by electroless plating or sputtering. Further, in the example of FIG. 1B, all the grooves GR are embedded with the conductor 17, but it is needless to say that it is not always necessary to embed all the grooves GR depending on conditions required for the package. is there.

  In the next step (see FIG. 1 (c)), four grooved flat plates 13 to 16 each having five grooves GR formed on one side in parallel to the longitudinal direction are arranged in an overlapping manner, and these grooves are provided. One flat plate 11, 12 is arranged on each side of the flat plates 13 to 16 and stacked. And each flat plate 11-16 is integrated using a low temperature glass joining technique. In the figure, reference numeral 20 denotes a laminated / integrated structure. By this lamination / integration, each groove GR (conductor 17) formed in each grooved flat plate 13 to 16 becomes a through hole TH.

  In addition, when a “near circular shape” is desired as the cross-sectional shape of the finally obtained through hole TH (that is, when the grooves GR are formed at the corresponding positions of the two flat plates arranged opposite to each other), After aligning and laminating so that the position of each groove | channel GR of each flat plate with a groove | channel opposes, each flat plate is integrated.

  In this step, the flat plates 11 to 16 are integrated using a low-temperature glass bonding technique, but other methods such as thermocompression bonding, ultrasonic bonding, glass frit, and plasma bonding can also be used. It is also conceivable that the surface of each glass plate is slightly dissolved using a hydrofluoric acid-based solution to form a liquid, and the glass plates are bonded to each other through the liquid portion.

  In this example, four flat plates 13 to 16 are sandwiched and two flat plates 11 and 12 are arranged on both sides, but the number of flat plates prepared in advance as described above is the customer. Obviously, the order of stacking the flat plate and the grooved flat plate is not limited to the example shown in view of being appropriately determined according to the demand on the side.

  In the last step (see FIG. 1D), the structure 20 laminated / integrated in the previous step is moved in the direction in which the through hole TH (groove GR) is formed by a dicer, a slicer, a wire saw, or the like. Cut to the required thickness from the vertical direction. Thereby, the core substrate 10 with a through hole according to the present embodiment is obtained. At this time, the “required thickness” to be cut out is determined in accordance with a request from a customer who manufactures a semiconductor package such as a BGA using the core substrate 10. Moreover, you may make it a desired dimension and surface precision by performing a grinding | polishing process etc. with respect to the core substrate 10 after cutting out as needed.

  Through the above steps, the core substrate 10 with a through hole having a required size (size in the surface direction) and thickness according to the request from the customer side is produced.

  As described above, according to the method for manufacturing the semiconductor package core substrate 10 according to the present embodiment (see FIG. 1), grooves having five grooves GR formed in parallel to the longitudinal direction on at least one surface. A plurality of flat plates 11 to 16 including the attached flat plates 13 to 16 are prepared according to the demands of the customer side who manufactures the semiconductor package using the core substrate, and these flat plates 11 to 16 are provided with grooves. After the flat plates 13 to 16 are arranged and laminated to produce an integrated structure 20, the structure 20 is taken from a direction perpendicular to the direction in which the grooves GR constituting the through holes TH are formed. The core substrate 10 with a through hole is obtained by cutting out to a required thickness according to the customer's request.

  That is, it does not take a method of performing required processing (drilling, metalizing, hole filling, etc.) one by one for each semiconductor package required as in the prior art, and simply includes a plurality of flat plates 13 to 16 including grooves. Therefore, it is only necessary to cut out the structure 20 from a direction perpendicular to the direction of the groove GR, so that the target core substrate 10 can be efficiently manufactured. it can. Further, even when the thickness of the core substrate is changed due to the customer's request, it can be easily handled by “cutting out” the thickness according to the request in the process of FIG. . That is, it becomes possible to easily manufacture core substrates having different thicknesses.

  Moreover, since the target core substrate 10 with a through-hole can be manufactured efficiently, it can contribute to the reduction of the cost concerning the manufacture and the improvement of a yield.

  Also, even when ceramics are used as the material for each flat plate, there is no problem of shrinkage (shrinkage) because there is no conventional method of sintering a molded body of a ceramic substrate. It becomes possible to manufacture a core substrate with accuracy and fine through holes.

  In the embodiment described above (FIG. 1), after preparing the required number of flat plates 11 to 16, the grooved flat plate 13 is obtained at a stage before the flat plates 11 to 16 are stacked and integrated (FIG. 1B). The groove 17 is filled with the conductor 17, but the timing of filling the groove 17 with the conductor 17 is not limited to this stage, and various other embodiments are conceivable.

  For example, as shown in FIG. 2, a required number of flat plates 11 to 16 are prepared (the same figure (a)), and each flat plate 11 to 16 is laminated and integrated (the same figure (b)), and then this integration is performed. The conductor GR is filled in the groove GR constituting the through hole TH of the structured structure 20a (FIG. 5C), and the structure 20 in which each through hole TH is filled with the conductor 17 is filled with a required thickness. (Fig. 4D).

  Alternatively, as shown in FIG. 3, the required number of flat plates 11 to 16 are prepared (FIG. 3A), and the flat plates 11 to 16 are laminated and integrated (FIG. 3B). After the structure 20a is cut out to a required thickness ((c) in the same figure), the conductor 17 may be filled in the groove GR constituting the through hole TH of the cut out core substrate 10a (same as in FIG. (D).

  The core substrate 10 with a through hole manufactured by the manufacturing method according to each of the above-described embodiments (FIGS. 1 to 3) is suitably used as a base substrate when manufacturing various semiconductor packages such as BGA, LGA, and PGA. can do. FIG. 4 shows an example of this, and shows a process for manufacturing a BGA type package.

  First, in the first step (see FIG. 4A), a core substrate 10 with a through hole manufactured by any one of the above-described embodiments is prepared. In the figure, reference numeral 17 denotes a conductor filled in the through hole TH, and 18 denotes an insulating layer. The insulating layer 18 corresponds to a part of the flat plates 11 to 16 made of an insulating material (glass).

  From the next step onward, the conductor pattern (wiring layer) and the insulating layer (including via holes) are alternately stacked on both surfaces (upper and lower sides) of the core substrate 10 using the build-up method until the required number of layers is obtained. . First, in the process of FIG. 4B, a first buildup layer is formed. That is, wiring layers 31a and 31b having required shapes are formed on both surfaces of the core substrate 10 (insulating layer 18 and conductor 17), and insulating layers 32a and 32b are formed on the wiring layers 31a and 31b and the insulating layer 18, respectively. To do.

  The wiring layers 31a and 31b can be formed by the following method. First, a conductor (Cu) layer is formed on both surfaces of the core substrate 10 by electroless copper plating and electrolytic copper plating, and an etching resist is formed on each conductor layer using a patterning material. Open the part. This opening is patterned according to the shape of the required conductor pattern to be formed. As the patterning material, a photosensitive dry film or a liquid photoresist can be used. For example, when using a dry film, after cleaning the surface of each conductor layer, the dry film is attached by thermocompression bonding, and a mask (not shown) patterned in the shape of a required conductor pattern is applied to each dry film. In the case of a negative type resist, a developer containing an organic solvent is used, and in the case of a positive type resist, an alkaline type is used. The portion is etched away using a developing solution, and a resist layer corresponding to the shape of the required conductor pattern is formed. Next, using this patterned resist layer as a mask, the exposed portion of the conductor is removed by wet etching using a chemical solution that is soluble only in copper (Cu). Remove using an alkaline chemical such as sodium hydroxide. Thereby, the wiring layers 31a and 31b having a required shape are formed.

  Furthermore, a thermosetting resin such as an epoxy resin is applied to each wiring layer 31a, 31b and the insulating layer 18 to a required thickness, and cured by ultraviolet (UV) irradiation or the like to form the insulating layers 32a, 32b. .

  In the next step (see FIG. 4 (c)), via holes reaching the respective wiring layers 31a and 31b are formed at required positions of the respective insulating layers 32a and 32b by drilling with a CO2 laser, a YAG laser or the like. Then, each via hole is filled with conductors 33a and 33b by electrolytic copper plating or the like.

  In the next process (see FIG. 4D), the second layer is formed on the insulating layers 32a and 32b and the conductors 33a and 33b in the same manner as the process performed in the processes of FIGS. 4B and 4C. After forming the build-up layers (wiring layers 34a and 34b, insulating layers 35a and 35b), via holes reaching the respective wiring layers 34a and 34b are formed at required positions of the insulating layers 35a and 35b, respectively. Each via hole is filled with conductors 36a and 36b.

  In the last step (see FIG. 4 (e)), both surfaces are covered with a protective film, and a ball as an external connection terminal is formed on a conductor part (such as a pad part) exposed from a part opened in a required part of the protective film. Join. First, before the surface (the lower side in the illustrated example) to be mounted on a mounting board such as a printed board is covered with a protective film, an external connection terminal as a receiving pad is placed on the exposed conductor 36b. A pad 37 is formed. This can be formed in the same manner as the method for forming the wiring layers 31a and 31b having the required shapes described above.

  Next, the structure thus formed functions as a protective film so as to cover the entire surface except for the conductor 36a exposed on the upper side and the pad 37 exposed on the lower side. Solder resist layers 38a and 38b are formed. For example, the solder resist layers 38a and 38b can be formed by laminating a photosensitive dry film on both surfaces and patterning each dry film into a required shape.

  Further, a solder ball (semiconductor element pad) 39a for connecting an electrode terminal of a semiconductor element or the like mounted on this package is joined to the conductor 36a exposed from the upper solder resist layer 38a, and the lower solder Solder balls (external connection terminals) 39b used for mounting this package on the mounting substrate are joined to the pads 37 exposed from the resist layer 38b. As a result, the BGA type package is manufactured.

  In each of the above-described embodiments (see FIGS. 1 to 3), the case where an insulating material (glass) is used as an example of the material of the flat plates 11 to 16 prepared in advance has been described as an example. It is not necessary to be constituted, and it is sufficient that at least the surface (surface layer portion) has insulating properties. Therefore, it is also possible to use a semiconductor material such as silicon as the material of each of the flat plates 11 to 16.

  However, when silicon (Si) is used as the material of each flat plate 11-16, in the embodiment of FIG. 1, the stage before filling the grooves 17 of the grooved flat plates 13-16 with the conductors 17, the implementation of FIG. Regarding the form, the conductor 17 is filled in the through hole TH of the laminated / integrated structure 20a, and in the embodiment of FIG. 3, the conductor is formed in the through hole TH of the core substrate 10a cut to a required thickness. In the stage before filling 17, a treatment such as forming an insulating film (SiO 2) on the silicon surface by a thermal oxidation method, a CVD method or the like is required.

It is a perspective view (partly sectional drawing) which shows the manufacturing process of the core substrate for semiconductor packages which concerns on one Embodiment of this invention. It is a perspective view (partly sectional drawing) which shows the manufacturing process of the core substrate for semiconductor packages which concerns on other embodiment of this invention. It is a perspective view (partly sectional drawing) which shows the manufacturing process of the core board | substrate for semiconductor packages which concerns on other embodiment of this invention. It is sectional drawing which shows an example of the manufacturing process of the semiconductor package using the core board | substrate which concerns on each embodiment of this invention.

Explanation of symbols

10, 10a ... Core substrate for semiconductor package (core substrate with through hole),
11, 12 ... flat plate,
13, 14, 15, 16 ... flat plate with groove,
17: Conductor (conductive material),
18 ... Insulating layer (part of flat plate),
20, 20a ... laminated / integrated structure,
31a, 31b, 34a, 34b ... wiring layer,
32a, 32b, 35a, 35b ... insulating layer (resin layer),
33a, 33b, 36a, 36b ... (filled via holes) conductors,
37. Pad for external connection terminal,
38a, 38b ... protective film (solder resist layer),
39a ... pads for semiconductor elements (solder balls),
39b ... external connection terminals (solder balls),
GR ... groove,
TH: Through hole (groove after lamination / integration).

Claims (6)

A step of preparing a plurality of flat plates including at least one grooved flat plate, wherein each flat plate is made of an insulating material and has a rectangular shape in plan view, and the grooved flat plate includes a plurality of flat plates on at least one side thereof. Preparing a plurality of flat plates including one having a form in which the grooves are formed in parallel in one direction;
Laminating the grooved flat plate on the inside, laminating the plurality of flat plates, and integrating using a predetermined joining technique;
And a step of cutting the integrated structure to a required thickness from a direction perpendicular to the direction in which the grooves are formed.   2. The semiconductor according to claim 1, further comprising a step of filling the groove with a conductive material between the step of preparing the plurality of flat plates and the step of stacking and integrating the plurality of flat plates. Manufacturing method of core substrate for package.   A step of filling the groove constituting the through hole with a conductive material between the step of stacking and integrating the plurality of flat plates and the step of cutting the integrated structure to a required thickness. The method for manufacturing a core substrate for a semiconductor package according to claim 1.   2. The method according to claim 1, further comprising a step of filling a conductive material into the groove constituting the through-hole of the core substrate that has been cut out after the step of cutting the integrated structure to a required thickness. The manufacturing method of the core substrate for semiconductor packages of description.   2. The semiconductor package according to claim 1, further comprising a step of forming an insulating film on a surface of the flat plate when a semiconductor material is used instead of an insulating material as a material constituting each flat plate. A method for manufacturing a core substrate.   2. The method of manufacturing a core substrate for a semiconductor package according to claim 1, wherein any one of a low-temperature glass bonding technique, thermocompression bonding, ultrasonic bonding, glass frit, or plasma bonding is used as the predetermined bonding technique.

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