JP2009060427A - Video signal processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To appropriately extract luminance signals and chroma signals from video signals without the need of an A/D converter. <P>SOLUTION: The video signal processing circuit includes: a first switched capacitor filter wherein a horizontal high-pass filter function using first video signals for one horizontal scanning period and second video signals for which the former signals are delayed and a vertical low pass filter function are combined; a second switched capacitor wherein the horizontal high-pass filter function using the second video signals and third video signals for which the former signals are delayed and the vertical low pass filter function are combined; first and second comparators for outputting a first correlation degree between the first and second video signals and a second correlation degree between the second and third video signals by the size comparison of each output of the first and second switched capacitor filters; and a Y/C separation circuit for separating the video signals into the luminance signals and the chroma signals using the first and second video signals or the second and third video signals on the basis of the first and second correlation degrees. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video signal processing circuit.

  Among various analog color television systems, NTSC (National Television Standards Committee) or PAL (Phase Alternation by Line) exists as a color difference signal carrier system using quadrature two-phase amplitude modulation. In the quadrature two-phase amplitude modulation, two carrier waves having the same frequency and a phase difference of 90 degrees are amplitude-modulated and then combined.

On the side that transmits video signals compliant with NTSC or PAL, R (red), G (green), and B (blue) video signals captured by a TV camera are not transmitted as they are. The luminance signal Y constituting the brightness of the screen and the chroma signal C constituting the degree of shade of the screen color are converted and transmitted as a composite signal SC obtained by synthesizing the luminance signal Y and the chroma signal C.

  As shown in FIG. 8 (a), the chroma signal C is obtained by subtracting two color difference signals RY and BY obtained by subtracting the luminance signal Y from the R signal and the B signal, and an I / Q signal (NTSC system). Signal) or U / V signals (in the case of the PAL system), and these signals are combined and amplitude-modulated. The chroma signal C includes a color burst signal BS used as a reference for the phase and amplitude of the carrier color signal CA, and a carrier color signal CA whose phase indicates hue and whose amplitude indicates saturation.

  As shown in FIG. 8B, the luminance signal Y includes a horizontal synchronization signal HSYNC and a luminance signal component YA. The horizontal synchronization signal HSYNC is a signal indicating the start of one scanning line in the horizontal direction. A period between two adjacent horizontal synchronization signals HSYNC is called “1H period (one horizontal scanning period)”. The luminance signal component YA is a signal indicating the content of luminance.

  As shown in FIG. 8 (c), the composite signal SC is a combination of the chroma signal C shown in FIG. 8 (a) and the luminance signal Y shown in FIG. 8 (b). More specifically, the composite signal SC has a waveform in which the color burst signal BS of the chroma signal C is superimposed on the back porch of the luminance signal Y and the carrier color signal CA of the chroma signal C is superimposed on the luminance signal component YA. Become.

  On the other hand, a video signal receiving apparatus that receives a video signal conforming to NTSC or PAL and performs predetermined signal processing is a Y / C for separating the composite signal SC received by the antenna 2 into a chroma signal C and a luminance signal Y. It is necessary to provide a separation circuit.

  FIG. 9 is a diagram showing a configuration in a case where a conventional video signal receiving apparatus including a Y / C separation circuit is compatible with a video signal conforming to NTSC. The video signal receiving apparatus converts an analog composite signal SC received by the antenna 2 or the like into a digital signal and outputs the signal, and a signal obtained by delaying the composite signal SC (0H signal) by 1H period ( 1H delay circuit 612 for outputting 1H signal), 1H delay circuit 614 for outputting a signal (2H signal) obtained by further delaying the output of 1H delay circuit 612 by 1H period, and each of the above 0H, 1H, and 2H signals. And a Y / C separation circuit 616 that separates the luminance signal Y and the chroma signal C based on a two-dimensional digital Y / C separation method.

  Furthermore, the conventional video signal receiving apparatus has a correlation calculation circuit 618 for calculating the degree of correlation of three lines (0H, 1H, and 2H signals). Based on the degree of correlation calculated by the correlation calculation circuit 618, the Y / C separation circuit 616 does not have all three lines, but the upper two lines in the vertical direction (0H, 1H signal) or the lower two lines ( The composite signal SC is separated into the luminance signal Y and the chroma signal C by selecting and using (1H, 2H signals) and the like.

Note that the video signal receiving apparatus also calculates the degree of correlation of the three lines when separating the composite signal SC into the luminance signal Y and the chroma signal C in the same manner when the video signal conforms to the PAL. However, as the three lines in the case of PAL, the composite signal SC (0H signal) received by the antenna, the signal obtained by delaying the composite signal SC by 2H period (2H signal), and the signal delayed by 4H period (4H signal) ) Is used. This is because the chroma signal C has a phase difference of 180 degrees in the 1H period in the case of NTSC, while it has a phase difference of 90 degrees in the 1H period in the case of PAL.
JP 2002-118860 A

  As described above, in realizing the two-dimensional digital Y / C separation method based on the degree of correlation of three lines, the correlation of three lines is based on the video signal converted from the analog signal to the digital signal by the A / D converter. The degree was calculated. Therefore, in order to increase the calculation accuracy of the degree of correlation in order to improve the separation accuracy of the luminance signal Y and the chroma signal C, it is necessary to increase the resolution of the A / D converter. However, if the resolution of the A / D converter is increased, this increases the circuit scale of the A / D converter.

  A main invention for solving the above problems is that a first video signal for one horizontal scanning period of a video signal including a luminance signal and a chroma signal, and a second video signal obtained by delaying the first video signal. Based on the degree of correlation of the third video signal obtained by delaying the second video signal, the luminance of the video signal is converted into the luminance using at least one of the first to third video signals. A horizontal high-pass filter function for extracting a horizontal spatial frequency component higher than a predetermined horizontal spatial frequency component from the first and second video signals in a video signal processing circuit for separating the signal and the chroma signal; A first switched capacitor filter that combines a vertical low-pass filter function for extracting a vertical spatial frequency component lower than the vertical spatial frequency component from the first and second video signals. And a horizontal high-pass filter function for extracting a horizontal spatial frequency component higher than a predetermined horizontal spatial frequency component from the second and third video signals, a vertical spatial frequency component lower than a predetermined vertical spatial frequency component The second switched capacitor filter that combines a vertical low-pass filter function for extracting the second and third video signals from the second and third video signals, and the output of the second switched capacitor filter as a comparison reference, A first comparator that outputs a first degree of correlation between the first and second video signals based on a magnitude relationship between the outputs of the first and second switched capacitor filters; Based on the magnitude relationship between the outputs of the first and second switched capacitor filters, using the output of the first switched capacitor filter as a comparison reference. And a second comparator that outputs a second correlation degree between the second and third video signals, and the first and second correlation degrees based on the first correlation degree and the second correlation degree. A Y / C separation circuit that separates the video signal into the luminance signal and the chroma signal using the second video signal or the second and third video signals.

  According to the present invention, it is possible to provide a video signal processing circuit that appropriately extracts a luminance signal and a chroma signal from a video signal without requiring an A / D converter.

<<< Configuration of Video Signal Receiver >>>
FIG. 1 is a configuration diagram of a video signal receiving apparatus according to an embodiment of the present invention. The video signal processing circuit according to the embodiment of the present invention is a portion excluding the antenna 2 and the display 22 in the video signal receiving apparatus shown in FIG. Further, in the following embodiment, the case where the chroma signal C is an NTSC having a phase difference of 180 degrees in the 1H period will be described as an example, but a PAL having a phase difference of 90 degrees in the 1H period is adopted. Also good.

  The tuner 4 extracts the signal of the reception target channel from the video signal compliant with NTSC received by the antenna 2 and then amplifies and outputs it. The filter 6 extracts the intermediate frequency signal IF from the output of the tuner 4, and further detects the intermediate frequency signal IF to extract the composite signal SC.

  In addition to outputting the composite signal SC extracted by the filter 6 as it is, the delay circuit 8 delays the composite signal SC by 1H period, and outputs the output of the 1H delay circuit 82 for another 1H period. And a 1H delay circuit 84 that outputs the signal with a delay. The 1H period is one horizontal scanning period between two adjacent horizontal synchronization signals HSYNC as shown in FIG. The 1H delay circuits 82 and 84 of the present embodiment are cheaper than CCD (Charged Coupled Device) delay elements that have been mainly used so far, and have been used exclusively as analog filters until now in FIGS. A direct charge type switched capacitor delay circuit as shown is used. Of course, the present invention is not limited to the direct charge type, and is configured using a buffer type or charge transfer type switched capacitor delay circuit (see, for example, FIG. 4 or FIG. 8 of JP-A-2007-97020). Also good.

  Accordingly, the delay circuit 8 is a composite signal SC (a “first video signal” according to the present invention.) For 1H period indicating an arbitrary scanning line in the horizontal direction on the display screen of the display 22. "0H signal or simply 0H") and a signal obtained by delaying the 0H signal by the 1H period (a "second video signal" according to the present invention, hereinafter referred to as "1H signal or simply 1H"). A signal obtained by delaying the 1H signal by the 1H period (the “third video signal” according to the present invention, hereinafter referred to as “2H signal or simply 2H”) is output. These 0H, 1H, and 2H signals represent three scanning lines that are continuous in the vertical direction on the display screen of the display 22, and each of the 0H, 1H signals, 1H, and 2H signals has a 180 degree position. Have a phase difference.

  The correlation calculation circuit 9 compares the comparison signal CMP1 indicating the degree of correlation between the 0H and 1H signals as the degree of correlation between the 0H, 1H and 2H signals output from the delay circuit 8 and the comparison indicating the degree of correlation between the 1H and 2H signals. The signal CMP2 is output.

  The Y / C separation circuit 10 separates the luminance signal Y and the chroma signal C based on the two-dimensional analog Y / C separation method using the 0H, 1H, and 2H signals output from the delay circuit 8. The two-dimensional analog Y / C separation method is a luminance signal in a two-dimensional space constituted by a horizontal axis representing the horizontal spatial frequency component H and a vertical axis representing the vertical spatial frequency component V of the composite signal SC. An analog filter for extracting Y and an analog filter for extracting chroma signal C are separately provided.

  The Y / C separation circuit 10 is based on the comparison signals CMP1 and CMP2 output from the correlation operation circuit 9, and all three lines (0H, 1H, and 2H signals) are based on the current scanning line (1H signal). Instead, the upper two lines (0H, 1H signal) or the lower two lines (1H, 2H signal) in the vertical direction among the three lines are selectively used to separate the luminance signal Y and the chroma signal C.

  The luminance signal processing circuit 12 performs contrast adjustment and blanking adjustment of the luminance signal Y supplied from the Y / C separation circuit 10. The chroma signal processing circuit 14 performs gain adjustment and color killer processing for each channel of the chroma signal C supplied from the Y / C separation circuit 10. The color demodulation processing circuit 16 mainly demodulates the color difference signals RY and BY based on the chroma signal C subjected to various processes in the chroma signal processing circuit 14.

  The matrix circuit 18 synthesizes the color difference signals RY and BY demodulated by the color demodulation processing circuit 16 and the luminance signal Y subjected to various processes by the luminance signal processing circuit 12 to generate three R signals. , G signal and B signal are restored. The RGB driver 20 generates drive signals ROUT, GOUT, and BOUT for reproducing a desired color image on the display 22 based on the three R, G, and B signals supplied from the matrix circuit 18.

<<< Correlation Operation Circuit 9 >>>
The correlation calculation circuit 9 includes a switched capacitor filter unit 92 shown in FIG. 2 and a correlation calculation unit 94 shown in FIG. Hereinafter, these configurations and operations will be described.

=== Switched Capacitor Filter Unit 92 ===
As shown in FIG. 2, the switched capacitor filter unit 92 includes a first switched capacitor filter 100 and a second switched capacitor filter 200. FIG. 3 shows filter ranges in the two-dimensional space of the first and second switched capacitor filters 100 and 200 (shaded portions in FIG. 3).

  The first switched capacitor filter 100 is an index value (V-LPF1 to be described later) for obtaining the degree of correlation of the upper two lines (0H, 1H signals) in the vertical direction among the three lines (0H, 1H, 2H signals). ). Specifically, as shown in FIG. 3, the first switched capacitor filter 100 uses the 0H and 1H signals to generate a horizontal spatial frequency component higher than a predetermined horizontal spatial frequency component H1 (<H2). A horizontal high-pass filter function to extract (hereinafter referred to as an H-HPF function) and a vertical low-pass filter function to extract a vertical spatial frequency component lower than a predetermined vertical spatial frequency component V1 (hereinafter referred to as a V-LPF1 function). Is combined).

FIG. 2 shows a detailed configuration of the first switched capacitor filter 100 of the present embodiment. In FIG. 2, the following block (A) represents a switched capacitor delay circuit that delays n (n = 1 to 3) sampling periods.

The H-HPF function of the 0H signal (which is a first horizontal high-pass filter function according to the present invention, hereinafter referred to as the H-HPF1 function) and the 1H signal, which are functions of the first switched capacitor filter 100. H-HPF function (second horizontal high-pass filter function according to the present invention, hereinafter referred to as H-HPF2 function) is a filter as shown in the following formulas (1) and (2): This can be realized by an FIR type HPF having a length of 2.

  In the present embodiment, “FIR format” is described because the concept of a digital filter called FIR is not configured by a digital circuit such as a DSP (Digital Signal Processor) but a switched capacitor delay circuit is used. This is because it is constituted by an analog circuit, and the same applies to the following description of the FIR format. Also, in the expressions (1) and (2), the part of the symbol (B) represents that the k (k = 0, 1) H signal is delayed by n (n = 1, 3) sampling period. ing. That is, the H-HPF1 function is realized by adding the non-inverted signal and the inverted signal of the 0H signal with different sampling periods, and the H-HPF2 function samples the non-inverted signal and the inverted signal of the 1H signal, respectively. This is realized by adding different periods.

The V-LPF1 function, which is another function of the first switched capacitor filter 100, is an H-HPF1 function configured by the above formula (1) and an H-type configured by the above formula (2). By multiplying and adding each output of the HPF2 function by +1, the filter length is 2, and all can be realized as an FIR type LPF using positive filter coefficients (+1, +1). Specifically, the V-LPF1 function is expressed by the following equation (3).

  When Expression (3) is expressed in a block diagram, it is the contents of the first switched capacitor filter 100 shown in FIG. Reference numerals 101 and 103 denote a first switched capacitor delay circuit 500 (see FIG. 6) described later that outputs an output OUT obtained by delaying the input IN (0H, 1H) by one sampling period based on the clock CLK. Reference numerals 102 and 104 denote a second switched capacitor delay circuit 520 (see FIG. 7) described later that outputs an output OUT obtained by delaying the input IN (0H, 1H) by three sampling periods based on the clock CLK. Reference numerals 105, 108, 106, and 109 denote logic inversion units that realize the negative coefficient (−1) in Expression (3). Reference numeral 107 denotes an addition unit corresponding to the addition part of the first half factor and the second half factor in the expression (3). Although details will be described later, the logic inversion units 105, 108, 106, and 109 are realized by changing the connection of the first and second switched capacitor delay circuits 500 and 520. This is achieved by shorting the wires.

The second switched capacitor filter 200 calculates an index value (V-LPF2 described later) of the correlation degree of the lower two lines (1H, 2H signals) in the vertical direction among the three lines (0H, 1H, 2H signals). To do. The second switched capacitor filter 200, like the first switched capacitor filter 100, uses the 1H and 2H signals as shown in the following formula (6), and the H-HPF function of the 1H signal. (Third horizontal high-pass filter function according to the present invention; hereinafter referred to as H-HPF3 function) H-HPF function of 2H signal (fourth horizontal high-pass filter function according to the present invention) This can be realized as a vertical low-pass filter function (hereinafter referred to as V-LPF2 function) configured by adding each output of H-HPF4 function multiplied by +1. The H-HPF3 function is realized by adding the non-inverted signal and the inverted signal of the 1H signal with different sampling periods, and the H-HPF4 function samples the non-inverted signal and the inverted signal of the 1H signal, respectively. This is realized by adding different periods.

  When Expression (6) is expressed in a block diagram, it is the content of the second switched capacitor filter 200 shown in FIG. Reference numerals 201 and 203 denote a first switched capacitor delay circuit 500 (see FIG. 6) described later that outputs an output OUT obtained by delaying the input IN (1H, 2H) by one sampling period based on the clock CLK. Reference numerals 202 and 204 denote a second switched capacitor delay circuit 520 (see FIG. 7), which will be described later, that outputs an output OUT obtained by delaying the input IN (1H, 2H) by three sampling periods based on the clock CLK. 205, 208, 206, and 209 are logic inversion units for realizing the negative coefficient (−1) in the equation (6). Reference numeral 207 denotes an addition unit corresponding to the addition part of the first half factor and the second half factor in the equation (6).

=== Correlation Calculation Unit 94 ===
As shown in FIG. 4, the correlation calculation unit 94 includes a first absolute value circuit 301, a second absolute value circuit 302, a third absolute value circuit 303, a fourth absolute value circuit 304, and a first attenuator 305. , Second attenuator 306, first comparator 307, and second comparator 308.

  First, the first attenuator 305 and the second attenuator 306 are ignored and described.

  In the first comparator 307, the absolute value B1 of V-LPF2 (see Equation (6)) that has passed through the second absolute value circuit 302 is input to the inverting input terminal, and the first comparator 307 receives the first value in the non-inverting input terminal. The absolute value A1 of V-LPF1 (see equation (3)) that has passed through the absolute value circuit 301 is input. Then, the first comparator 307 outputs a comparison signal CMP1 indicating the degree of correlation between the 0H and 1H signals (first degree of correlation) based on the comparison result of the absolute values A1 and B1.

  That is, if the absolute value A1 of the V-LPF1 based on the 0H and 1H signals is larger than the absolute value B1 of the V-LPF2 based on the 1H and 2H signals, the first comparator 307 outputs the H-level comparison signal CMP1. Output. As a result, the Y / C separation circuit 10 identifies that there is a correlation between the 0H and 1H signals, and selects the upper two lines (0H and 1H signals). On the other hand, if the absolute value A1 is smaller than the absolute value B1, the first comparator 307 outputs an L level comparison signal CMP1. As a result, the Y / C separation circuit 10 identifies that there is no correlation between the 0H and 1H signals.

  The second comparator 308 receives the absolute value A2 of V-LPF1 (see Equation (3)) that has passed through the third absolute value circuit 303 at its inverting input terminal, and receives the fourth value at its non-inverting input terminal. The absolute value B2 of V-LPF2 (see equation (6)) that has passed through the absolute value circuit 304 is input. Then, according to the comparison result of the absolute values A2 and B2, the second comparator 308 outputs a comparison signal CMP2 indicating the degree of correlation between the 1H and 2H signals (second degree of correlation).

  That is, if the absolute value B2 of the V-LPF2 based on the 1H and 2H signals is greater than the absolute value A2 of the V-LPF1 based on the 0H and 1H signals, the second comparator 308 outputs the H level comparison signal CMP2. Output. As a result, the Y / C separation circuit 10 identifies that there is a correlation between the 1H and 2H signals, and selects and uses the lower two lines (1H and 2H signals). On the other hand, if the absolute value B2 is smaller than the absolute value A2, the second comparator 308 outputs an L level comparison signal CMP2. As a result, the Y / C separation circuit 10 identifies that there is no correlation between the 1H and 2H signals.

  By the way, when the first attenuator 305 and the second attenuator 306 are ignored, the absolute values A1 and A2 are equivalent, and the absolute values B1 and B2 are also equivalent. Therefore, the comparison signal CMP1 output from the first comparator 307 and the comparison signal CMP2 output from the second comparator 308 are in a complementary relationship. L level. Then, the Y / C separation circuit 10 always repeats selection of the upper 2 lines (0H, 1H signal) and the lower 2 lines (1H, 2H signal) among the 3 lines (0H, 1H, 2H signals).

  However, when the absolute values of V-LPF1 and V-LPF2 are close to each other, one of the upper two lines (0H, 1H signal) and the lower two lines (1H, 2H signal) is always correlated. It may be difficult to determine that it is a thing. Therefore, the first attenuator 305 is provided on the input side of the second absolute value circuit 302, and the second attenuator 306 is provided on the input side of the third absolute value circuit 303, so that the comparison signals CMP1 and CMP2 are both at the H level or The state to become L level was set. When both the comparison signals CMP1 and CMP2 are at the H level or the L level, the Y / C separation circuit 10 separates the luminance signal Y and the chroma signal C using all three lines (0H, 1H, and 2H signals). Decided to do. The first attenuator 305 attenuates the V-LPF 2 and outputs the attenuated V-LPF 2 to the second absolute value circuit 302, and the second attenuator 306 attenuates the V-LPF 1 and outputs it to the third absolute value circuit 303. Output.

  For example, it is assumed that the level of the V-LPF 1 is “+8”, the level of the V-LPF 2 is “+7”, and the attenuation amounts of the first attenuator 305 and the second attenuator 306 are both “−0.5”. In this case, the absolute value A1 is “8”, the absolute value B1 is “6.5”, the absolute value A2 is “6.5”, the absolute value B2 is “7”, and the comparison signals CMP1 and CMP2 are both at the H level. Become. Further, for example, when the level of the V-LPF 1 is “−6”, the level of the V-LPF 2 is “−5”, and the attenuation amounts of the first attenuator 305 and the second attenuator 306 are both “−1.5”. And In this case, the absolute value A1 is “6”, the absolute value B1 is “6.5”, the absolute value A2 is “7.5”, the absolute value B2 is “5”, and the comparison signals CMP1 and CMP2 are both at the L level. Become.

  In summary, as shown in the table of FIG. 5, when the comparison signal CMP1 is at the H level and the comparison signal CMP2 is at the L level, the upper two lines are selected, and the comparison signal CMP1 is at the L level and the comparison signal CMP2 is at the H level. In the case of the level, the lower two lines are selected, and in the case where both the comparison signal CMP1 and the comparison signal CMP2 are at the H level or the L level, the three lines are selected.

=== first switched capacitor delay circuit 500 ===
FIG. 6 shows a detailed configuration of the first switched capacitor delay circuit 500 used as 101 and 103 of the first switched capacitor filter 100 and 201 and 203 of the second switched capacitor filter 200. It is a figure.

  The switched capacitor basic circuit 501 includes a capacitor C1, a first switching element (M1, M2) for taking the capacitor C1 into the feedback loop of the operational amplifier at the output stage, and charges corresponding to the level of the input IN. And second switching elements (M3, M4) for storage in C1. Note that the gates of the NMOS transistors M3 and M4 of the switched capacitor basic circuit 501 are short-circuited and commonly connected to the gates of the NMOS transistors M5 and M6 of the switched capacitor basic circuit 502 of the next stage.

  More specifically, the NMOS transistors M1 and M3 are complementarily turned on and off in order to connect one end of the capacitor C1 to either the input IN or the output OUT of the operational amplifier 506. The NMOS transistors M2 and M4 are complementarily turned on and off in order to connect the other end of the capacitor C1 to either the inverting input terminal of the operational amplifier 506 or the ground. Therefore, when the NMOS transistors M3 and M4 are turned on, a charge corresponding to the level of the input IN is held in the capacitor C1, and when the NMOS transistors M1 and M2 are turned on, the capacitor C1 is taken into the feedback loop of the operational amplifier 506.

  Since the switched capacitor basic circuit 502 has the same configuration and operation as the switched capacitor basic circuit 501, description thereof is omitted.

  The shift register 505 outputs control signals P0 and P1 that repeat (1, 0) and (0, 1) based on the clock CLK having one sampling period. When the control signal P0 is 1, the first switching elements (M1, M2) on the switched capacitor basic circuit 501 side are turned on, and the second switching elements (M7, M2) on the switched capacitor basic circuit 502 side are turned on. M8) turns on. When the control signal P1 is 1, the second switching elements (M3, M4) of the switched capacitor basic circuit 501 are turned on, and the first switching elements (M5, M6) of the switched capacitor basic circuit 502 are turned on. Turns on. As described above, based on the control signals P0 and P1 output from the shift register 505, a voltage corresponding to the electric charge accumulated in one of the capacitors C1 and C2 before one sampling period is output from the operational amplifier 506. .

=== second switched capacitor delay circuit 520 ===
FIG. 7 shows a detailed configuration of a second switched capacitor delay circuit 520 used as 102 and 104 of the first switched capacitor filter 100 and 202 and 204 of the second switched capacitor filter 200. It is a figure. The difference from the first switched capacitor delay circuit 500 is that the second switched capacitor delay circuit 520 has a configuration in which four switched capacitor basic circuits 521 to 524 are connected in multiple stages. Further, the shift register 525 is different in that it outputs four control signals P0 to P3 that are switched to (1000), (0100), (0010), and (0001) every sampling cycle of the clock CLK. Based on these four control signals P0 to P3, the third switched capacitor delay circuit 520 has a voltage corresponding to the charge accumulated three sampling periods before in any one of the capacitors C1 to C4. Output from the operational amplifier 526.

  The above-described logic inversion units 105, 106, 205, and 206 can be realized by changing the connection of the second switched capacitor delay circuit 520. Specifically, the drains of the NMOS transistors M1, M5, M9, and M13 are connected to the inverting input terminal of the operational amplifier 506, and the sources of the NMOS transistors M2, M6, M10, and M14 are connected to the output of the operational amplifier 506. realizable.

  As described above, the video signal processing circuit according to the present invention correlates 0H, 1H, and 2H signals by the correlation calculation circuit 9 including the first and second switched capacitor filters 100 and 200 that are analog circuits. Calculate the degree. As a result, since it is not necessary to use an A / D converter as in the conventional example, an increase in circuit scale can be suppressed. In addition, unlike the conventional example, the input IN level is not limited by the resolution of the A / D converter. Further, since the Y / C separation processing is performed by the analog circuit, the radiation noise to the external peripheral circuit can be reduced.

  The sampling periods of the first and second switched capacitor delay circuits 500 and 520 can be freely adjusted by changing the period of the clock CLK of the shift registers 505 and 525. As a result, the calculation time of the correlation degree in the correlation calculation circuit 9 can be freely adjusted according to the specifications of the video signal processing circuit.

  The first switched capacitor filter 100 includes a first switched capacitor delay circuit 500 (1 sampling cycle delay) and a third switched capacitor delay circuit 520 (3 sampling cycle delay) having different sampling cycles. It was configured using. The same applies to the second switched capacitor filter 200. As a result, the first and second switched capacitor filters 100 and 200 can be configured with the total number of switched capacitor delay circuits being minimized.

  Further, when the first and second attenuators 305 and 306 are not provided in the correlation calculation unit 94, the configuration of the first comparator 307 and the second comparator 308 described above makes it possible to obtain a signal between 0H and 1H signals. The comparison signal CMP1 indicating the degree of correlation (H level is correlated and L level is not correlated) and the comparison signal CMP2 indicating the degree of correlation between 1H and 2H signals (H level is correlated and L level is not correlated) are: When one is at H level, the other is always at L level. As a result, the Y / C separation circuit 10 can easily select the upper two lines (0H, 1H signal) and the lower two lines (1H, 2H signal) based on the comparison signal CMP1, CMP2 that indicates the H level. Can be done.

  Also, the upper two lines (0H, 1H signal) and the lower two lines (1H, 2H signal) such that the absolute values of the outputs of the first and second switched capacitor filters 100, 200 are close to each other. If it is difficult to determine that either one is necessarily correlated, the first and second attenuators 305 and 306 are provided in the correlation calculation unit 94 so that the comparison signals CMP1 and CMP2 both indicate the H level or the L level. The Y / C separation circuit 10 uses all three lines (0H, 1H, and 2H signals). As a result, it is possible to improve the separation accuracy between the luminance signal Y and the chroma signal C.

  Although the present embodiment has been described above, the above-described examples are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

For example, the video signal receiving circuit according to the present invention may be compliant with the PAL in which the chroma signal C has a phase difference of 90 degrees every 1H period. In the case of conforming to PAL, the delay circuit 8 generates a 2H signal delayed from the 0H signal by the 2H period, and a 4H signal obtained by delaying the 0H signal by the 4H period in addition to the 0H signal. Output to the C separation circuit 10. Here, since there is a phase difference of 180 degrees between the 0H and 2H signals and between the 2H and 4H signals, the Y / C separation circuit 10 uses the 2H and 4H signals in place of the 1H and 2H signals. A configuration similar to that of NTSC can be adopted. Specifically, the first switched capacitor filter is used by using the symbol (D) indicating that the k (k = 0, 2, 4) H signal is delayed by n (n = 1, 3) sampling period. 100 is expressed by the following equation (7), and the second switched capacitor filter 200 is expressed by the following equation (8).

It is a figure which shows the structure of the video signal receiver which concerns on one Embodiment of this invention. It is a figure which shows the structure of the switched capacitor filter part of the correlation calculating circuit which concerns on one Embodiment of this invention. It is a figure which shows the filter range of the switched capacitor filter part of the correlation calculating circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the correlation calculating part of the correlation calculating circuit which concerns on one Embodiment of this invention. It is a figure explaining the usage method of the calculation result of the correlation calculation circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the 1st switched capacitor delay circuit based on one Embodiment of this invention. It is a figure which shows the structure of the 2nd switched capacitor delay circuit based on one Embodiment of this invention. It is a figure which shows an example of the waveform figure of the chroma signal C, the luminance signal Y, and the composite signal SC. It is a figure which shows the structure of the conventional video signal processing circuit.

Explanation of symbols

2 Antenna 4 Tuner 6 Filter 8 Delay circuit 82, 84 1H delay circuit 9 Correlation operation circuit 92 Switched capacitor filter unit 94 Correlation operation unit 10 Y / C separation circuit 12 Luminance signal processing circuit 14 Chroma signal processing circuit 16 Color demodulation process Circuit 18 Matrix circuit 20 RGB driver 22 Display 100 First switched capacitor filter 101-104 Switched capacitor delay circuit 105-106, 108-109 Logic inversion unit 107 Adder 200 Second switched capacitor filter 201 ˜204 Switched capacitor delay circuits 205 to 206, 208 to 209 Logic inversion unit 207 Adder unit 301 First absolute value circuit 302 Second absolute value circuit 303 Third absolute value circuit 304 Fourth absolute value circuit 305 First attenuator 30 6 second attenuator 307 first comparator 308 second comparator 500 first switched capacitor delay circuit 501 to 502, 521 to 524 switched capacitor basic circuit 520 second switched capacitor delay circuit 505, 525 Shift register 506, 526 Operational amplifier 610 A / D converter 612, 614 1H delay circuit 616 Y / C separation circuit 618 Correlation operation circuit

Claims (6)

A first video signal for one horizontal scanning period of a video signal including a luminance signal and a chroma signal, a second video signal obtained by delaying the first video signal, and a delay of the second video signal Video signal processing for separating the video signal into the luminance signal and the chroma signal using at least one of the first to third video signals based on the degree of correlation of the obtained third video signal In the circuit
A horizontal high-pass filter function for extracting a horizontal spatial frequency component higher than a predetermined horizontal spatial frequency component from the first and second video signals, and a vertical spatial frequency component lower than a predetermined vertical spatial frequency component A first switched-capacitor filter combining a vertical low-pass filter function extracted from the first and second video signals;
A horizontal high-pass filter function for extracting a horizontal spatial frequency component higher than a predetermined horizontal spatial frequency component from the second and third video signals; a vertical spatial frequency component lower than a predetermined vertical spatial frequency component; 2 and a second switched capacitor filter combined with a vertical low-pass filter function extracted from the third video signal;
Based on the magnitude relationship between the outputs of the first and second switched capacitor filters, using the output of the second switched capacitor filter as a comparison reference, between the first and second video signals. A first comparator that outputs a first degree of correlation of
Based on the magnitude relationship between the outputs of the first and second switched capacitor filters, using the output of the first switched capacitor filter as a reference for comparison, the second and third video signals A second comparator for outputting a second degree of correlation of
Based on the first correlation degree and the second correlation degree, the video signal is converted into the luminance signal using the first and second video signals or the second and third video signals. A Y / C separation circuit for separating the chroma signal;
A video signal processing circuit comprising: The video signal processing circuit according to claim 1,
The horizontal high-pass filter function of the first switched capacitor filter is:
A first horizontal high-pass filter function in which the non-inverted signal and the inverted signal of the first video signal are added with different sampling periods, and
A second horizontal high-pass filter function in which the non-inverted signal and the inverted signal of the second video signal are added with different sampling periods.
The vertical low-pass filter function of the first switched capacitor filter is:
Each output of the first and second horizontal high-pass filter function is added and configured,
The horizontal high-pass filter function of the second switched capacitor filter is:
A third horizontal high-pass filter function in which the non-inverted signal and the inverted signal of the second video signal are added with different sampling periods, and
A fourth horizontal high-pass filter function that adds the non-inverted signal and the inverted signal of the second video signal with different sampling periods, and
The vertical low-pass filter function of the second switched capacitor filter is:
A video signal processing circuit comprising the outputs of the third and fourth horizontal high-pass filter functions. The video signal processing circuit according to claim 2,
The first video signal is represented as 0H, the second video signal is represented as 1H, the third video signal is represented as 2H, and the k (k = 0 to 2) H signal is represented by n (n = 1, 3) sampling period. Symbol for delay

The first switched capacitor filter is

And the second switched capacitor filter is

A video signal processing circuit characterized by being expressed by The video signal processing circuit according to claim 2,
The first video signal is represented as 0H, the second video signal is represented as 2H, the third video signal is represented as 4H, and a k (k = 0, 2, 4) H signal is represented as n (n = 1, 3). Symbol for delaying sampling period

The first switched capacitor filter is

And the second switched capacitor filter is

A video signal processing circuit characterized by being expressed by The video signal processing circuit according to claim 1,
The first comparator is:
When the output of the first switched capacitor filter is larger than the output of the second switched capacitor filter, one level indicating that there is a correlation between the first and second video signals is set to the first level. Output as 1 degree of correlation,
When the output of the first switched capacitor filter is smaller than the output of the second switched capacitor filter, the other level indicating no correlation between the first and second video signals is set to the first level. Output as 1 degree of correlation,
The second comparator is:
When the output of the second switched capacitor filter is larger than the output of the first switched capacitor filter, one level indicating that there is a correlation between the second and third video signals is set to the first level. 2 as the degree of correlation,
When the output of the second switched capacitor filter is smaller than the output of the first switched capacitor filter, the other level indicating no correlation is set between the second and third video signals. 2 as the degree of correlation,
The Y / C separation circuit is
When the first correlation degree is the one level and the second correlation degree is the other level, the first and second video signals are used,
Using the second and third video signals when the first correlation degree is the other level and the second correlation degree is the one level;
A video signal processing circuit. The video signal processing circuit according to claim 5,
A first absolute value circuit that calculates an absolute value of an output of the first switched capacitor filter and outputs the absolute value to a non-inverting input terminal of the first comparator;
A first attenuator for attenuating the output of the second switched capacitor filter;
A second absolute value circuit that calculates an absolute value of an output of the first attenuator and outputs the absolute value to an inverting input terminal of the first comparator;
A second attenuator for attenuating the output of the first switched capacitor filter;
A third absolute value circuit that calculates an absolute value of the output of the second attenuator and outputs the absolute value to the inverting input terminal of the second comparator;
A fourth absolute value circuit that calculates an absolute value of an output of the second switched capacitor filter and outputs the absolute value to a non-inverting input terminal of the second comparator;
And the Y / C separation circuit uses the first to third video signals when both the first and second correlation degrees indicate the one level or the other level. Separating the video signal into the luminance signal and the chroma signal;
A video signal processing circuit.

Images