JP2009065304A - High frequency switch device - Google Patents

Abstract

The present invention provides a high-frequency switch device that suppresses a decrease in current driving capability due to a substrate bias effect in an on state of a transistor and has low insertion loss and low signal distortion.
The source and drain of a switch transistor are connected to input / output terminals of a high-frequency signal via DC cut capacitors, respectively, and the gate of the switch transistor is connected via a resistor. The second DC terminal 104 is connected and a fixed potential is applied, and the source and drain are connected to the first DC terminal 103 via resistors 108 and 109, and the control potential of the switch transistor is applied. A third DC terminal 105 is connected to the substrate of the switch transistor, and a fixed potential is applied.
[Selection] Figure 1

Description

  The present invention relates to a high-frequency switch device that switches a transmission / reception signal passing frequency band and a transmission / reception path.

  In a wireless communication system typified by a cellular phone, a high-frequency switch device that connects and disconnects an antenna and a transmission / reception device is used for switching a communication method and switching transmission / reception.

  FIG. 9 shows a circuit diagram of an SPDT (Single-Pole Double-Throw) switch which is a general high-frequency switch device. In the high frequency switch of FIG. 9, the source and drain of the first switch transistor 907 are connected to the first RF terminal 901 and the second RF terminal 902 via capacitors 912 and 911, respectively. The source / drain of 913 is connected to the first RF terminal 901 and the third RF terminal 903 via capacitors 912 and 917, respectively.

  By applying a high / low level potential V1 to the first DC terminal 905 to turn on / off the first switch transistor 907, the connection / cutoff of the high-frequency signal between the first and second RF terminals is controlled. is doing. Similarly, by connecting the second DC terminal 906 with a high / low level potential V2, connection / cutoff of a high-frequency signal between the first and third RF terminals is controlled. At this time, the substrate potentials of the first and second switch transistors are grounded through the die pad of the package.

  Each of the first and second switch transistors 907 and 913 is turned on and off between the potential applied to the first and second DC terminals 905 and 906 and the fixed potential V3 applied to the third DC terminal 904. It is controlled by the potential difference. When the switch transistor is in the ON state, the impedance of the switch transistor is sufficiently lower than the load impedance, and the influence of the voltage amplitude VA of the high frequency signal on the bias state of the switch transistor is small.

  When the switch transistor is in the OFF state, the source and drain voltages of the switch transistor vary in the range of V3 ± VA depending on the voltage amplitude VA of the high-frequency signal. For this reason, in order to stabilize the switch transistor in the OFF state, the low-level voltages V1L and V2L applied to the first and second DC terminals, respectively, and the fixed voltage V3 applied to the third DC terminal are: The gate threshold voltage of the switch transistor needs to be designed with V1L−V3 <Vth−VA (V2L−V3 <Vth−VA) in consideration of the voltage amplitude VA of the high frequency signal.

  Therefore, in order to turn off the switch transistor, it is necessary to design the low-level potentials V1 and V2 of the first and second control terminals to be low and the fixed potential V3 to be high. In order to apply a negative potential to the first and second DC terminals, the power supply circuit becomes complicated and large-scale, and therefore, a potential condition in which the low level potentials V1L and V2L are ground potentials and V3 is sufficiently high is generally used. It has been. At this time, since the substrate of the switch transistor is grounded, there is a potential difference of −V3 between the substrate and the source regardless of whether the switch transistor is on or off, and the negative substrate bias is effectively applied. Become.

As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP 2004-320439 A

  The influence of the negative substrate bias in the operation of the switch transistor operating under the above bias condition will be described.

  FIG. 10 shows an example of a cross-sectional structure of a gallium arsenide field effect transistor (GaAs FET) used as a switch transistor. On the semi-insulating substrate 1001, semiconductor layers are formed in the order of an undoped buffer layer 1002, a p-type buffer layer 1003, an undoped buffer layer 1004, a channel layer 1005, an n-type carrier supply layer 1006, and an undoped barrier layer 1007.

  In the off state of the GaAs-FET, a minute drain leak current flows between the drain and the source via the buffer layer and the substrate, which causes deterioration of isolation characteristics and signal distortion of the high frequency switching device. Therefore, a semiconductor layer that supplies a charge different from that of the channel conduction carriers is formed in the buffer layer, and by increasing the energy level with respect to the conduction carriers, the conduction carriers entering the buffer layer and the substrate are suppressed, and the drain leakage current is reduced. Suppress. In the cross-sectional structure example of FIG. 10, the p-type buffer layer 1003 is a semiconductor layer for the purpose of reducing drain leakage current.

  As described above, V3 is applied from the third DC terminal to the source / drain of the switch transistor, and the substrate of the switch transistor is grounded via the die pad of the package. A negative substrate bias -V3 is applied to.

  FIG. 7 shows a conduction band and a valence band in a state where an effective substrate bias of 0 V and −5 V is applied in the cross section A-A ′ of the GaAs-FET of FIG. From this figure, it can be seen that the conduction band at the substrate bias of −5V is raised at 0V, while the entire band including the channel layer is lifted.

  As a result, a shift of the gate threshold voltage occurs, the current drive capability of the switch element decreases, resulting in an increase in high-frequency signal loss and an increase in signal distortion. In particular, in the case of a semiconductor layer structure having a p-type semiconductor layer as a buffer layer, the electric field concentrates on the p-type semiconductor layer relatively close to the channel layer, and the potential of the channel layer is raised by pulling it, so that the current drive capability of the switch transistor The decrease in is greater.

  That is, in a conventional high frequency switching device, a control method in which a fixed potential is applied to the source and drain of a switch transistor and a high-level or low-level control potential is applied to a gate, isolation and signal distortion in the off state of the switch transistor There is a trade-off relationship between the characteristics, the insertion loss in the ON state of the switch element, and the signal distortion characteristics.

  The present invention has been made in view of the trade-off relationship in such a conventional high-frequency switch device, and the object thereof is to suppress a decrease in current driving capability due to the substrate bias effect in the ON state of the switch transistor, This eliminates the trade-off between the high frequency characteristics in the on state and the off state.

According to a first aspect of the present invention, there is provided a high-frequency switch device including high-frequency signal input and output terminals, first, second, and third terminals, one or a plurality of N switch transistors, and the same number of first switches. And a second resistor, one more than the switch transistor, and a first and a second capacitor,
The gates of the N switch transistors are connected to the second terminal via corresponding first resistors,
The substrate of N switch transistors is connected to the third terminal,
The source and drain of the N switch transistors are connected to the drain of the nth switch transistor and the source of the (n + 1) th switch transistor, and the connected node is connected to the first terminal via the corresponding second resistor. Connected to
The source of the first switch transistor is connected to a second resistor corresponding to the first capacitor, the first capacitor is connected to the input terminal of the high frequency signal, and the corresponding second resistor is connected to the first terminal. And
The drain of the Nth switch transistor is connected to a second resistor corresponding to the second capacitor, the second capacitor is connected to the input terminal of the high frequency signal, and the corresponding second resistor is connected to the first terminal. And
A first fixed potential is applied to the first terminal,
The control potential of the switch transistor is applied to the second terminal,
A constant potential is applied to the third terminal,
This is a high-frequency switch device.

According to a second aspect of the present invention, there is provided a high-frequency switch device comprising: a high-frequency signal input / output terminal; first, second, and third terminals; one or a plurality of N switch transistors; And a second resistor, one more than the switch transistor, and a first and a second capacitor,
The gates of the N switch transistors are connected to the second terminal via corresponding first resistors,
The substrate of N switch transistors is connected to the third terminal,
The source and drain of the N switch transistors are connected to the drain of the nth switch transistor and the source of the (n + 1) th switch transistor, and the connected node is connected to the first terminal via the corresponding second resistor. Connected to
The source of the first switch transistor is connected to the input terminal of the high-frequency signal through the first capacitor, and to the first terminal through the corresponding second resistor,
The drain of the Nth switch transistor is connected to the input terminal of the high frequency signal via the second capacitor, and to the first terminal via the corresponding second resistor,
The control potential of the switch transistor is applied to the first terminal and the third terminal,
The second fixed terminal is applied with a first fixed potential,
This is a high-frequency switch device.

According to a third invention, in the high-frequency switch device according to the first or second invention, a depletion mode n-type FET is used as the switch transistor.
This is a high-frequency switch device.

According to a fourth invention, in the high-frequency switch device according to the first to third inventions, in the semiconductor layer structure forming the switch transistor, the semiconductor layer that generates carriers having a charge opposite to the conduction carrier in the semiconductor layer deeper than the channel layer Using a switch transistor formed on an epitaxial structure comprising:
This is a high-frequency switch device.

According to a fifth invention, in the high-frequency switch device according to the first to fourth inventions, a ground potential and an arbitrary positive potential are applied to the control potential of the switch transistor to control on / off or off / on of the switch transistor. It is characterized by
This is a high-frequency switch device.

According to a sixth invention, in the high-frequency switch device according to the fifth invention, the high-level potential applied to the switch transistor is the same potential as the second fixed potential.
This is a high-frequency switch device.

According to a seventh invention, in the high-frequency switch device according to any one of the first and third to sixth inventions, the first fixed potential and the second fixed potential are each a ground potential.
This is a high-frequency switch device.

  ADVANTAGE OF THE INVENTION According to this invention, the high frequency characteristic trade-off in the ON state of a switch transistor and an OFF state can be eliminated, and the high frequency switch apparatus of a low loss, high isolation, and low signal distortion can be provided.

(Embodiment 1)
FIG. 1 shows a first embodiment of the present invention.

  The source and drain of the switch transistor 106 are connected to high-frequency signal input / output terminals 101 and 102 via DC cut capacitors 110 and 111, respectively. A second DC terminal 104 is connected to the gate of the switch transistor 106 via a resistor 107, and a fixed potential is applied. The source and drain are connected to the first DC terminal 103 via resistors 108 and 109, and the control potential of the switch transistor is applied. A third DC terminal 105 is connected to the substrate of the switch transistor, and a fixed potential is applied.

  At this time, the gate threshold voltage of the switch transistor 106 is Vth, the low level potential applied to the first DC terminal 103 is VL, the high level potential is VH, the fixed potential applied to the second DC terminal 104 is VGG, Assuming that the potential applied to the third DC terminal 105 is VBB, the switch transistor is turned on when VL satisfying VGG−VL> Vth is applied. Note that by increasing VGG-VL with respect to Vth, the drain current of the switch transistor can be increased, and low insertion loss and low signal distortion can be achieved. Further, when VH satisfying VGG−VH <Vth is applied, the switch transistor is turned off.

  In the case of a conventional high-frequency switch device, since a high fixed potential is applied to the source / drain and the substrate is operated in a grounded state, a negative substrate bias is effectively applied as described above. The conduction band is raised, and the carrier density generated at the same gate potential is low regardless of the on and off states.

  On the other hand, in the first embodiment of the present invention, when the switch transistor is on, the source potential of the switch transistor 106 is VL, the substrate potential is VBB, and the effective substrate bias is VBB-VL and an arbitrary bias state. It becomes possible to operate with. Further, by setting the source / drain low level potential VL and the substrate potential VBB equal to each other, the substrate bias is set to 0 V, and the effect of reducing the carrier density due to the substrate bias can be eliminated. Further, by designing as VBB> VL, it is possible to increase the carrier density and to realize low insertion loss and low signal distortion.

  When the switch transistor is off, the source potential of the switch transistor 106 is VH, the substrate potential is VBB, and the effective substrate bias can be operated in an arbitrary bias state of VBB-VH. At this time, the negative substrate bias effect is increased by setting VH to a sufficiently high potential, and isolation can be improved by depletion of carriers in the channel layer.

  FIG. 8 shows a comparison of the characteristics of the insertion loss and the second harmonic in the SPDT switch device having the conventional configuration shown in FIG. 9 and the SPDT switch device using the high frequency switch device according to the first embodiment of the present invention shown in FIG. Indicates. The same GaAs depletion mode FETs in FIGS. 6 and 9 were used as switch transistors. The threshold Vth of the switch transistor is −0.5 V and the gate width is 600 μm.

  In the high frequency switching device of FIG. 9, a high level potential 5V is applied to the first DC terminal 905, a low level potential 0V is applied to the second DC terminal 906, and a fixed potential 5V is applied to the third terminal 904. The substrate of each switch transistor is grounded. At this time, the first switch transistor 907 is turned on, the second switch transistor 913 is turned off, and the first RF terminal 901 and the second RF terminal 902 are turned on.

  In the high frequency switching device of FIG. 6, a low level potential 0V is applied to the first DC terminal 604, a high level potential 5V is applied to the second DC terminal 605, and a fixed potential 0V is applied to the third DC terminal 606. The fixed potential of 0 V is applied to the fourth and fifth DC terminals 619 and 620, respectively. At this time, the first switch transistor 607 is turned on, the second switch transistor 613 is turned off, and the first RF terminal 601 and the second RF terminal 602 are turned on.

  FIG. 8A shows an SPDT switch using the conventional high-frequency switch device shown in FIG. 9 and the high-frequency switch device according to the first embodiment of the present invention shown in FIG. 6, the first RF terminal and the second RF switch. The insertion loss between RF terminals is shown. It can be seen that the SPDT switch using the first embodiment is 0.1 to 0.2 dB lower than the conventional high frequency switch regardless of the input power when the input power is 25 dBm or less. This is because in the conventional high-frequency switch, the on-resistance is increased due to the carrier reduction due to the effective negative substrate bias effect. However, according to the first embodiment, the negative substrate bias is set to 0, and the carrier reduction and the on-resistance are reduced. Since the increase in the number was suppressed, insertion loss could be reduced.

  In addition, in the conventional high frequency switching device, an increase in insertion loss is seen from around the input power of 27 dBm, whereas in SPDT using the first embodiment of the present invention, the insertion loss increases to an input power of 30 dBm. Is not seen. This is because the channel is pinched off at a low drain-source voltage and the current is saturated due to a decrease in carrier density due to the negative substrate bias effect in the conventional high-frequency switching device. In the first embodiment of the present invention, since the negative substrate bias is 0, there is no decrease in carrier density, and linear operation is performed with a higher drain-source voltage, so that larger power is conducted with low loss. Is possible.

  FIG. 8B shows an SPDT switch using the conventional high-frequency switch device shown in FIG. 9 and the high-frequency switch device according to the first embodiment of the present invention shown in FIG. The second harmonic of the output signal at the second RF terminal relative to the RF signal is shown. The signal distortion of about 10 dB is low for a wide input power. This is because, as in the case of the insertion loss, in the first embodiment of the present invention, since the negative substrate bias is 0, the carrier density does not decrease and the linear operation is performed at a higher drain-source voltage. This is because the linearity is better than that of the high-frequency switch device.

  The characteristic improvement by the high-frequency switch device according to the first embodiment of the present invention has been described with the SPDT switch device using the n-type depletion mode FET as the switch transistor. However, the switch device using the enhancement mode FET as the switch transistor. The same effect can be obtained in. However, the high-frequency switching device using the enhancement mode FET is also limited to the case where the source potential is set high in order to increase the voltage amplitude of the RF signal allowed in the off state, and the gate threshold value is higher than the depletion mode, and thus is lower. Since the operation is performed with the drain and source potentials, the effect is low as compared with the case where the depletion mode FET is used as the switch transistor.

  In addition, when a FET having an epitaxial structure in which a semiconductor layer deeper than the channel layer has a doped layer that generates carriers opposite to the conduction carriers is used as a switch transistor, the increase in the conductance band due to the effective negative substrate bias is Therefore, the effect of the low insertion loss and low signal distortion due to the reduction of the negative substrate bias effect by the implementation of the first embodiment is large. When the doped layer that generates the opposite carriers is present in the vicinity of 1000 nm or less with respect to the channel layer, the effect of low insertion loss and low signal distortion is great.

  Note that, regarding the operation of the SPDT switch using the first embodiment of FIG. 6, the low level potential applied to the first DC terminal 604, the fixed potential applied to the third DC terminal 606, the fourth In the above description, the fixed potential applied to the DC terminal 619 is assumed to be 0 V. However, when the first switch transistor 607 is on, the fixed potential is applied to the source and drain of the switch transistor via the first DC terminal 604. The potential difference between the potential applied to the source and drain of the switch transistor via the third DC terminal 606 and the potential applied to the substrate via the fourth DC terminal 619, that is, negative substrate bias is reduced. If it is a potential condition, it can be operated under an arbitrary bias condition.

  FIG. 2 shows a second embodiment of the present invention.

  The source and drain of the switch transistor 205 are connected to high-frequency signal input / output terminals 201 and 202 via DC cut capacitors 209 and 210, respectively. Further, the second DC terminal 204 is connected to the gate of the switch transistor 205 via the resistor 206, and the control potential of the switch transistor is applied. The source and drain are connected to the first DC terminal 203 via resistors 207 and 208, and a fixed potential is applied. The same potential as that of the second DC terminal is applied to the substrate of the switch transistor.

  At this time, the gate threshold voltage of the switch transistor 205 is Vth, the low level potential applied to the second DC terminal 204 is VL, the high level potential is VH, the fixed potential applied to the first DC terminal 203 is VDD, When the potential applied to the third DC terminal is VBB, the switch transistor is turned on when VH satisfying VH−VDD> Vth is applied. Note that by increasing VH−VDD with respect to Vth, the drain current of the switch transistor can be increased, and low insertion loss and low signal distortion can be achieved.

  In the case of the conventional high-frequency switch device, when the potential VDD is applied to the source / drain of the switch transistor via the first terminal, an effective negative substrate bias −VDD is applied. Carrier density decreases, insertion loss and signal distortion increase. On the other hand, in the second embodiment of the present invention, since the same potential as the gate potential of the switch transistor is applied as the substrate potential from the second DC terminal, the effective negative substrate bias is VH−VDD. Can be suppressed.

  When a depletion mode FET is used as a switch transistor, the high level potential applied from the second DC terminal is often designed to be the same potential as the fixed potential VDD applied to the first terminal. When the transistor is in the on state, the effective substrate bias is 0, which is highly effective.

  Further, as described in the first embodiment, when a FET having an epitaxial structure in which a semiconductor layer deeper than a channel layer has a doped layer that generates carriers opposite to conductive carriers is used as a switch transistor, an effective negative Since the conductance band rises greatly due to the substrate bias, the effect of improving low insertion loss and low signal distortion is great.

  FIG. 3 shows a third embodiment of the present invention.

  The source and drain of the switch transistor 305 are connected to high-frequency signal input / output terminals 301 and 302 via DC cut capacitors 309 and 310, respectively. The gate of the switch transistor 305 is grounded via a resistor 306, and the source / drain is connected to the first DC terminal 303 via resistors 307 and 308, and a high-level or low-level control potential is applied. . The substrate of the switch transistor is grounded.

  The operation and effect of the switch are the same as in the first embodiment. By grounding the gate of the switch transistor and the substrate potential, the influence of fluctuations in applied voltage, noise, and the like can be reduced, and operational stability can be improved. Further, since the substrate of the switch transistor is installed, there is an advantage that a structure for applying a substrate potential and a structure for applying an arbitrary potential to the die pad are not required.

  When an enhancement mode FET is used as the switch transistor, the low level potential applied to the first DC terminal is a negative potential and a negative power supply is required. However, when a depletion mode FET is used, a negative potential is not required. Therefore, it can operate with only a positive power supply.

  FIG. 4 shows a fourth embodiment of the present invention.

  One of the source and drain of the first and second switch transistors 405 and 406 is connected to each other, and the other is connected to high-frequency signal input / output terminals 401 and 402 via DC cut capacitors 412 and 413, respectively. . The gates of the first and second switch transistors 405 and 406 are connected to the second DC terminal 404 via resistors 407 and 408, and a fixed potential is applied thereto. Sources and drains of the first and second switch transistors 405 and 406 are connected to the first DC terminal 403 via resistors 409, 410, and 411, and a high-level or low-level control potential is applied. The substrates of the first and second switch transistors 405 and 406 are connected to the third DC terminal 414, and a fixed potential is applied.

  The operation and effect of the switch are the same as in the first embodiment. In general, in a high-frequency switch using a transistor, a plurality of switch transistors are connected in series between RF terminals for the purpose of improving isolation and increasing an allowable voltage amplitude when off. The present invention can also be used when a plurality of switch transistors are connected in series.

  The fourth embodiment can also be applied to the high-frequency switches of the second and third embodiments.

  FIG. 5 shows a fifth embodiment of the present invention.

  The source and drain of the switch transistor 505 are connected to high-frequency signal input / output terminals 501 and 502 via DC cut capacitors 509 and 510, respectively. A second DC terminal 504 is connected to the gate of the switch transistor 505 via a resistor 506, and a fixed potential is applied. The source is connected to the first DC terminal 503 via the resistor 507, and the control potential of the switch transistor is applied. The drain is connected to the source via a resistor 508. A third DC terminal 511 is connected to the substrate of the switch transistor, and a fixed potential is applied.

  The operation and effect of the switch are the same as in the first embodiment. The number of resistors connected to the source / drain of the switch transistor is two for one switch transistor, and N + 1 for N switch transistors, but they do not have to have the same resistance value, as shown in FIG. The same effect can be obtained even with a switch device having a simple layout.

  The layout of the resistors connected to the source / drain of the switch transistor in the fifth embodiment is also applicable to the high-frequency switches in the second and third embodiments.

  As described above, as the substrate potential applying means of the switch transistor, substrate potential applying means generally used in a semiconductor device, such as forming an electrode on the epi and applying a potential to the die pad, can be used.

  The high-frequency switch device of the present invention can be used in a high-frequency signal switching device that requires particularly low insertion loss and low signal distortion in a wireless system such as a cellular phone.

1 is a circuit diagram of a first embodiment of a high-frequency switch device according to the present invention. The circuit diagram of 2nd Embodiment of the high frequency switch apparatus of this invention The circuit diagram of 3rd Embodiment of the high frequency switch apparatus of this invention The circuit diagram of 4th Embodiment of the high frequency switch apparatus of this invention The circuit diagram of 5th Embodiment of the high frequency switch apparatus of this invention Circuit diagram of SPDT switch device using first embodiment of high-frequency switch device of the present invention Figure showing comparison of band diagrams with and without substrate bias effect The figure which shows the comparison of the insertion loss of the SPDT switch apparatus of FIG. 6 and FIG. 9, and a 2nd harmonic characteristic Circuit diagram of SPDT switch device formed by conventional high frequency switch device Cross-sectional view of GaAs-HFET generally used for switch transistor

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Input / output terminal 102 Input / output terminal 103 1st DC terminal 104 2nd DC terminal 105 3rd DC terminal 106 Switch transistor 107 1st resistance 108,109 2nd resistance 110,111 DC cut capacity

Claims (7)

High-frequency signal input / output terminals, first, second, and third terminals, one or more N switch transistors, the same number of first resistors as the switch transistors, and one more than the switch transistors A second resistor and first and second capacitors;
The gates of the N switch transistors are connected to the second terminal via corresponding first resistors,
The substrate of N switch transistors is connected to the third terminal,
The source and drain of the N switch transistors are connected to the drain of the nth switch transistor and the source of the (n + 1) th switch transistor, and the connected node is connected to the first terminal via the corresponding second resistor. Connected to
The source of the first switch transistor is connected to a second resistor corresponding to the first capacitor, the first capacitor is connected to the input terminal of the high frequency signal, and the corresponding second resistor is connected to the first terminal. And
The drain of the Nth switch transistor is connected to a second resistor corresponding to the second capacitor, the second capacitor is connected to the input terminal for the high frequency signal, and the corresponding second resistor is connected to the first terminal. And
A first fixed potential is applied to the first terminal,
The control potential of the switch transistor is applied to the second terminal,
A second fixed potential is applied to the third terminal,
High frequency switch device. High-frequency signal input / output terminals, first, second, and third terminals, one or more N switch transistors, the same number of first resistors as the switch transistors, and one more than the switch transistors A second resistor and first and second capacitors;
The gates of the N switch transistors are connected to the second terminal via corresponding first resistors,
The substrate of N switch transistors is connected to the third terminal,
The source and drain of the N switch transistors are connected to the drain of the nth switch transistor and the source of the (n + 1) th switch transistor, and the connected node is connected to the first terminal via the corresponding second resistor. Connected to
The source of the first switch transistor is connected to the input terminal of the high-frequency signal through the first capacitor, and to the first terminal through the corresponding second resistor,
The drain of the Nth switch transistor is connected to the input terminal of the high frequency signal via the second capacitor, and to the first terminal via the corresponding second resistor,
The control potential of the switch transistor is applied to the first terminal and the third terminal,
The second fixed terminal is applied with a first fixed potential,
High frequency switch device. The high-frequency switch device according to claim 1 or 2, wherein a depletion mode n-type FET is used as the switch transistor.
High frequency switch device. 4. The high-frequency switching device according to claim 1, wherein in the semiconductor layer structure forming the switch transistor, a semiconductor layer that generates a carrier having a charge opposite to the conduction carrier is formed in a semiconductor layer deeper than the channel layer. Using a switch transistor comprising,
High frequency switch device. 5. The high frequency switching device according to claim 1, wherein a ground potential and an arbitrary positive potential are applied to a control potential of the switch transistor to control on / off or off / on of the switch transistor. Characterized by
High frequency switch device. The high-frequency switch device according to claim 5, wherein the high-level potential applied to the switch transistor is the same potential as the second fixed potential.
High frequency switch device. The high-frequency switch device according to any one of claims 1 and 3 to 6, wherein each of the first fixed potential and the second fixed potential is a ground potential.
High frequency switch device.

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