JP2009069562A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device adopting a storage capacitor line driving system, achieving low power consumption for partial display in simple circuit configuration. <P>SOLUTION: A polarity signal generating circuit 24 is formed of a first memory 241, a second memory 242, and an exclusive OR circuit 243. The first memory 241 stores first data showing the distinction between a display area where an image is displayed and a non-display area where an image is not displayed corresponding to each line. The first data are "1" in the display area and "0" in the non-display area. The second memory 242 is a memory storing second data showing the polarity of a polarity signal POL in one preceding frame, corresponding to each line. The first data read from the first memory 241 and the second data read from the second memory 242 are input to the exclusive OR circuit 243. The polarity signal POL is obtained from the exclusive OR circuit 243, and supplied to a storage capacitor line driving circuit 23. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage capacitor line driving type liquid crystal display device.

  Conventionally, a storage capacitor line driving method is known as a driving method of a liquid crystal display device. In this method, a storage capacitor is provided between the storage capacitor line and the pixel electrode, and after writing a display signal to the pixel electrode, the potential of the storage capacitor line is changed to change the potential of the pixel electrode in the positive or negative direction. Change. As a result, the dynamic range of the display signal can be reduced, and driving with low power consumption becomes possible. A liquid crystal display device using this storage capacitor line driving method is described in Patent Document 1.

  In addition, a partial display method is known as a display method of a liquid crystal display device. In this method, a part of the pixel area is a display area where an image is displayed, and the remaining area is a non-display area (a white or black display area) where no image is displayed.

When a partial display is performed in a storage capacitor line liquid crystal display device, power consumption can be reduced by stopping driving of the storage capacitor line in a non-display area. This type of liquid crystal display device is described in Patent Document 2.
JP 2002-196358 A JP 2007-140192 A

  However, in the partial display as described above, there is a problem that the circuit configuration becomes complicated in order to reduce power consumption by stopping the driving of the storage capacitor line in the non-display area.

  The liquid crystal display device of the present invention includes a pixel region including a plurality of pixels, a plurality of storage capacitor lines, a storage capacitor connected between the pixel electrode of the pixel and the storage capacitor line, and the plurality of storage capacitor lines. A polarity signal generation circuit that generates a polarity signal for determining the polarity of the potential of the display, the polarity signal generation circuit including a display area in which an image in the pixel area is displayed, and a non-display area in which no image is displayed A first memory storing first data representing the distinction between the first memory, a second memory storing second data representing the polarity of the polarity signal of one frame before, and reading from the first memory When the first data thus displayed represents a display area, the second data read from the second memory is inverted and output as a polarity signal, and the first data read from the first memory is output. If the data represents a non-display area, And an arithmetic circuit that outputs the second data read out from the memory as a polarity signal. When the first data is changed, the polarity signal is inverted every frame in the display area, In the display area, the polarity of the polarity signal one frame before is maintained.

  With this configuration, the polarity signal generation circuit does not display when shifting from full screen display that displays an image over the entire pixel area to partial display (or when the display area is changed in partial display). In the area, the polarity of the polarity signal is the state one frame before (the state of the full screen display one frame before the transition to the partial display or the state of the display area one frame before the display area is changed in the partial display). It can be maintained as it is. In addition, since the polarity signal generation circuit can be composed of two memories and an arithmetic circuit, the circuit configuration is simple.

  According to the present invention, low power consumption of partial display can be realized with a simple circuit configuration in a storage capacitor line driving type liquid crystal display device.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device. This liquid crystal display device employs a storage capacitor line driving system and can perform partial display.

  A plurality of pixels are arranged in a matrix to form a pixel region. In FIG. 1, nine pixels of 3 rows × 3 columns are shown for simplicity. Each pixel is arranged corresponding to each intersection of the gate lines GL1 to GL3 and the source lines SL1 to SL3, and includes a pixel transistor 10 made of an N-channel thin film transistor, a pixel electrode 11 connected to the drain of the pixel transistor 10, A liquid crystal 12 is provided between the pixel electrode 11 and the common electrode CE. A common potential VCOM is supplied to the common electrode CE.

  A first storage capacitor line SC1 is provided corresponding to the pixels in the first row, and a storage capacitor 13 is provided between the pixel electrode 11 and the first storage capacitor line SC1. A second storage capacitor line SC2 is provided corresponding to the pixels in the second row, and a storage capacitor 13 is provided between the pixel electrode 11 and the second storage capacitor line SC2. A third storage capacitor line SC3 is provided corresponding to the pixels in the third row, and a storage capacitor 13 is provided between the pixel electrode 11 and the third storage capacitor line SC3.

  The source of the pixel transistor 10 of each pixel in the first column is connected to the first source line SL1, and the source of the pixel transistor 10 of each pixel in the second column is connected to the second source line SL2. The source of the pixel transistor 10 of each pixel in the third column is connected to the third source line SL3.

  The gate of the pixel transistor 10 of each pixel in the first row is connected to the first gate line GL1, and the gate of the pixel transistor 10 of each pixel in the second row is connected to the second gate line GL2. The gate of the pixel transistor 10 of each pixel in the third row is connected to the third gate line GL3.

  In addition, a source line driving circuit 20 is provided for supplying a source signal Sig (display signal) to the first to third source lines SL1 to SL3. The polarity of the source signal Sig is inverted with respect to the reference potential at a constant cycle (for example, one horizontal cycle). Further, a DSG control circuit 21 that supplies the common potential VCOM to the first to third source lines SL1 to SL3 according to the control signal DSG is provided.

  Further, a gate line driving circuit 22 for supplying a gate signal to the first to third gate lines GL1 to GL3 is provided. Further, a storage capacitor line driving circuit 23 for driving the first to third storage capacitor lines SC1 to SC3 is provided. A polarity signal generation circuit 24 that generates a polarity signal POL that determines the polarity of the potential of the first to third storage capacitor lines SC1 to SC3 is provided. The storage capacitor line drive circuit 23 drives the potentials of the first to third storage capacitor lines SC1 to SC3 to the low potential VCOML or the high potential VCOMH based on the polarity signal POL output from the polarity signal generation circuit 24.

[Configuration of Retention Capacitor Line Drive Circuit and Polarity Signal Generation Circuit]
FIG. 2 is a diagram showing the configuration of the storage capacitor line drive circuit 23 and the polarity signal generation circuit 24. First, the configuration of the polarity signal generation circuit 24 will be described. The polarity signal generation circuit 24 is formed of a first memory 241, a second memory 242, and an exclusive OR circuit 243. In the first memory 241, first data representing a distinction between a display area where an image is displayed and a non-display area where an image is not displayed is stored corresponding to each line (each row). The The first data is “1” in the display area and “0” in the non-display area.

  The second memory 242 is a memory for storing second data representing the polarity of the polarity signal POL one frame before corresponding to each line. The first memory 241 and the second memory 242 can be formed by a shift register, for example, and hold data in synchronization with a clock HCLK that is a pulse signal having a cycle of one horizontal period (1H period). And the operation | movement which shifts is carried out. The first data read from the first memory 241 and the second data read from the second memory 242 are input to the exclusive OR circuit 243 in synchronization with the clock HCLK.

  In the case where the first data read from the first memory 241 represents the display area, that is, when the first data is “1”, the exclusive OR circuit 243 reads from the second memory 242. The read second data is inverted and output. Further, when the first data read from the first memory 241 represents a non-display area, that is, when the first data is “0”, the second data read from the second memory Output data as is. Then, the polarity signal POL that is the output signal of the exclusive OR circuit 243 is written into the second memory 242 in synchronization with the clock HCLK, and the contents of the second memory 242 are updated.

  Thus, in the display area, the polarity signal POL is inverted every frame. Also, when shifting from full screen display that displays an image over the entire pixel area to partial display (or when changing the display area in partial display), the polarity of the polarity signal is set to 1 in the non-display area. It is possible to maintain the state before the frame (the state of the full screen display one frame before the transition to the partial display or the state of the display region one frame before the change of the display area in the partial display). In addition, since the polarity signal generation circuit can be composed of two memories and an arithmetic circuit, the circuit configuration is simple.

  The Vreset signal is a signal synchronized with the vertical synchronization signal, and resets the read counters of the first memory and the second memory. FIG. 3 shows an operation example of the polarity signal generation circuit 24. In FIG. 3, n, n + 1, n + 2, n + 3, and n + 4 represent frame numbers. The number of lines will be described as 7 lines from the first line to the seventh line.

(A) Full screen display:
First data = “1” is stored in the first memory 241 for all lines. The output signal of the second memory 242 repeats “1” and “0” every frame for all lines. Therefore, the polarity signal POL repeats “1” and “0” for each frame for all lines.

(B) When shifting from full screen display to partial display:
A case where the fourth to seventh lines are set in the non-display area from the full screen display will be described. In the frame n + 1, the first data in the first memory 241 corresponding to the fourth to seventh lines is rewritten from “1” to “0”. Then, the display is shifted to the partial display from the next frame n + 2, but the output signal of the second memory 242 is fixed to “0”. Therefore, the polarity signal POL is fixed to “0” for the fourth to seventh lines. On the other hand, for the first to third lines as the display area, the output signal of the second memory 242 repeats “1” and “0” for each frame. Therefore, the polarity signal POL repeats “1” and “0” for each frame for the first to third lines.

(C) When changing the display area of the partial display:
In the partial display, a case where the non-display area is changed from the fourth to seventh lines to the second to fifth lines will be described. In the frame n + 1, the first data in the first memory 241 corresponding to the second to fifth lines is “0”. The first data corresponding to the remaining first and sixth to seventh lines is “1”. Then, for the second to fifth lines, the output signal of the second memory 242 from frame n + 1 is fixed to “0”. Therefore, the polarity signal POL is fixed to “0” for the second to fifth lines. On the other hand, for the first and sixth to seventh lines as the display area, the output signal of the second memory 242 repeats “1” and “0” for each frame. Therefore, the polarity signal POL repeats “1” and “0” for each frame for the first and sixth to seventh lines.

  Next, the configuration of the storage capacitor line driving circuit 23 will be described. The polarity signal POL output from the polarity signal generation circuit 24 is supplied to the first to third latch circuits LCH1 to LCH3 provided corresponding to the first to third storage capacitor lines SC1 to SC3, respectively. ~ Latched based on the third timing clocks TCLK1 to TCLK3. The first to third latch circuits LCH1 to LCH3 output and hold the latched polarity signal POL as the first to third latch signals POL1 to POL3. The first to third timing clocks TCLK1 to TCLK3 are generated by the timing control circuit 231 based on the gate signals G1 to G3 and the timing control signal TCLK.

  The inverted polarity signal POL is latched in the second latch circuit LCH2 corresponding to the even lines. This is because the potentials of the storage capacitor lines corresponding to the odd lines (first line, third line,...) And even lines (second line, fourth line,. This is to make it possible. For example, the potentials of the first storage capacitor line SC1 and the second storage capacitor line SC2 are opposite in polarity.

  The first to third latch signals POL1 to POL3 are used as signals for controlling the switching of the first to third switches SW1 to SW3 in the subsequent stage. For example, when the first latch signal POL1 is at the H level, the low potential VCOML is applied to the first storage capacitor line SC1, and when the first latch signal POL1 is at the L level, the first storage capacitor line SC1. Is applied with a high potential VCOMH.

  That is, the potentials of the first to third storage capacitor lines SC1 to SC2 are determined by the rising timing of the first to third timing clocks TCLK1 to TCLK3. In such a storage capacitor line driving system, such timing is generally after the gate signals G1 to G3 fall.

[Configuration of Source Line Driver Circuit and DSG Control Circuit]
FIG. 4 shows the configuration of the source line driver circuit 20 and the DSG control circuit 21 around the pixel region. FIG. 4 shows only the configuration related to the pixel corresponding to the first column of the pixel area. The output terminal of the source driver 14 is connected to one end of the first source line SL1 through the horizontal switch SWH. The horizontal switch SWH switches according to the horizontal scanning signal. When the horizontal switch SWH is turned on, the source signal Sig (display signal) is supplied from the source driver 14 to the first source line SL1. The output terminal of the common electrode driver 15 is connected to the other end of the first source line SL1 through the switch SWS. The switch SWS switches according to the DSG signal. The output terminal of the common electrode driver 15 is connected to the common electrode CE, and the common potential VCOM is supplied to the common electrode CE.

  Therefore, when the switch SWS is turned on, the first source line SL1 and the common electrode CE are short-circuited, and the common potential VCOM is also supplied to the first source line SL1.

Next, an operation example of the liquid crystal display device will be described with reference to a timing chart of FIG. This explanation is based on the circuit of FIG. In the figure, 1), 2) and 3) represent line numbers, ON represents a display area, and OFF represents a non-display area.
Initially, full screen display is performed. Since the first data = “1” is stored in the first memory 241 corresponding to the first to third lines, the output of the first memory 241 maintains “1”. The output of the second memory 242 repeats inversion between the H level and the L level every frame. Therefore, the polarity signal POL is a signal obtained by inverting the output of the second memory 242.

  Based on the first to third timing clocks TCLK1 to TCLK3 generated in time series, the polarity signal POL is successively latched by the first to third latch circuits LCH1 to LCH3 and inverted every frame. Repeated first to third latch signals POL1 to POL3 are generated. Therefore, the potentials of the first to third storage capacitor lines SC1 to SC3 are repeatedly inverted in synchronization with the first to third latch signals POL1 to POL3, and the storage capacitor line drive is performed. That is, after writing a display signal to the pixel electrode 11, the potential of the corresponding storage capacitor line is changed, and the potential of the pixel electrode 11 is changed in the positive or negative direction. As a result, the dynamic range of the display signal can be reduced, so that driving with low power consumption is possible.

  Next, a transition is made from full screen display to partial display. Assume that the contents of the first memory 241 are changed so that the first line corresponds to the display area and the second and third lines correspond to the non-display area. Then, the polarity signal POL of the previous frame is inverted for the first line, but the polarity signal POL changes while maintaining the polarity of the previous frame because the second and third lines are non-display areas. do not do. As a result, the driving of the second and third storage capacitor lines SC2 and SC3 is stopped.

  In the non-display area, the pixel is not displayed by writing the common potential VCOM to the corresponding pixel electrode 11. This will be described with reference to FIG. In the non-display region, the switch SWS is turned on in response to the DSG signal, the first source line SL1 and the common electrode CE are short-circuited, and the common potential VCOM is also supplied to the first source line SL1. When the pixel transistor 10 is turned on according to the gate signal G1, the common potential VCOM is applied to the pixel electrode 11. As a result, the voltage applied to the liquid crystal 12 becomes about 0 V, so that a non-display state (for example, black display in a normally black liquid crystal display device) is obtained.

  Subsequently, the display area is changed in the partial display. Here, it is assumed that the contents of the first memory 241 are changed so that the first and second lines correspond to the non-display area and the third line corresponds to the display area. Then, since the first and second lines are non-display areas, the polarity signal POL does not change while maintaining the polarity one frame before. That is, the driving of the first and second storage capacitor lines SC1 and SC2 is stopped. On the other hand, since the first line has been changed to the display area, the polarity signal POL of the previous frame is inverted. Thus, according to the present invention, it is possible to reduce power consumption in partial display.

It is a figure which shows the structure of the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the storage capacity line drive circuit and polarity signal generation circuit in the liquid crystal display device by embodiment of this invention. It is a figure explaining operation | movement of the polarity signal generation circuit in the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the source line drive circuit and DSG control circuit in the liquid crystal display device by embodiment of this invention. FIG. 5 is a timing diagram illustrating an operation of the liquid crystal display device according to the embodiment of the present invention.

Explanation of symbols

10 pixel transistor 11 pixel electrode 12 liquid crystal 13 holding capacitor 14 source driver 15 common electrode driver 20 source line driving circuit 21 DSG control circuit 22 gate line driving circuit 23 holding capacitor line driving circuit 24 polarity signal generating circuit 231 timing control circuit LCH1 to LCH3 1st-3rd latch circuit SW1-SW3 1st-3rd switch 241 1st memory 242 2nd memory 243 Exclusive OR circuit

Claims (4)

A pixel region composed of a plurality of pixels;
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
A polarity signal generation circuit that generates a polarity signal for determining the polarity of the potential of the plurality of storage capacitor lines,
The polarity signal generation circuit includes: a first memory storing first data representing a distinction between a display area where an image in the pixel area is displayed and a non-display area where no image is displayed;
A second memory storing second data representing the polarity of the polarity signal of one frame before;
When the first data read from the first memory represents a display area, the second data read from the second memory is inverted and output as a polarity signal, and the first data An operation circuit that outputs the second data read from the second memory as a polarity signal when the first data read from the memory represents a non-display area;
A liquid crystal display device characterized in that the polarity signal is inverted every frame in the display area, and the polarity of the polarity signal of the previous frame is maintained in the non-display area. The arithmetic circuit is an exclusive OR circuit to which the first data and the second data are input, and an output signal of the exclusive OR circuit is stored in the second memory. The liquid crystal display device according to claim 1. A latch circuit that latches the polarity signal generated by the polarity signal generation circuit based on a timing signal;
3. The liquid crystal display device according to claim 1, further comprising: a first switching element that switches a potential of the storage capacitor line in accordance with a polarity signal latched by the latch circuit. A common electrode to which a common potential is applied;
A liquid crystal disposed between the pixel electrode and the common electrode;
The liquid crystal display device according to claim 1, further comprising: a second switching element that applies the common potential to the pixel electrode in a non-display region.

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