JP2009099112A - Memory system - Google Patents

Abstract

To provide a memory system capable of reconfiguring a memory system only by changing a function of a second controller when a specification or the like of a nonvolatile memory is changed.
A memory system according to an embodiment of the present invention includes a first controller connected to a host device, and a second controller connected to the first controller and connected to a nonvolatile memory. And the non-volatile memory connected to the second controller, and the second controller exchanges data between the first controller and the non-volatile memory.
[Selection] Figure 1

Description

  The present invention relates to a memory system, and more particularly to a memory system including a nonvolatile memory.

  In a nonvolatile memory such as a NAND flash memory, as the line width forming the chip layout becomes finer, it is necessary to maintain the page size and erase block size during writing and reading, various command sequences, and reliability. A change occurs in the error correction code. For this reason, in a memory system including a nonvolatile memory such as a memory card and a controller, it is essential to change the controller function as the generation of the nonvolatile memory changes.

For example, in the memory card described in Patent Document 1, the controller stores a plurality of device codes of the memory device, compares the device code read from the memory device with the stored device code, and can cope with the types of memory devices And a memory device whose device code is not fixed can be handled.
JP 2005-157684 A

  The present invention provides a memory system capable of reconfiguring a memory system only by changing the function of a second controller when the specification or the like of a nonvolatile memory is changed.

  A memory system according to an embodiment of the present invention includes a first controller connected to a host device, a second controller connected to the first controller and connected to a nonvolatile memory, and the first controller. The non-volatile memory connected to the second controller, and the second controller exchanges data between the first controller and the non-volatile memory.

  A memory system according to an embodiment of the present invention includes a first controller connected to a host device, a second controller connected to the first controller and connected to a plurality of nonvolatile memories, A plurality of nonvolatile memories connected to the second controller, wherein the second controller exchanges data between the first controller and the plurality of nonvolatile memories. It is characterized by.

  According to the present invention, it is possible to provide a memory system that reconstructs a memory system only by changing the function of the second controller when the specification or the like of the nonvolatile memory is changed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, the memory system according to the embodiment will be described by taking a NAND flash memory as an example. Note that, in the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

(First embodiment)

FIG. 1 is a diagram showing a schematic configuration of a memory card according to a first embodiment to which a memory system of the present invention is applied. As shown in FIG. 1, the memory card 1 includes a controller A2, a controller B3, and a NAND flash memory 4. The controller A2 is connected to the host device 20 via the host bus 11, and is connected to the controller B3 via the NAND bus 12. The controller B3 is connected to the controller A2 via the NAND bus 12, and is connected to the NAND flash memory 4 via the NAND bus 13. The NAND flash memory 4 is connected to the controller B3 by a NAND bus 13. The NAND flash memory 4 may be a binary memory that stores 1-bit data in one memory cell, or may store multiple data (for example, 2 bits) larger than 1 bit in one memory cell. It may be a value memory. Here, a NAND flash memory will be described as an example of the nonvolatile memory. However, the nonvolatile memory is not limited to the NAND flash memory, and may be a NOR flash memory, for example.

  The terms “logical block address” and “physical block address” used in the following description mean a logical address and a physical address assigned to the block itself in the NAND flash memory 4, respectively. Further, “logical address” and “physical address” mainly mean the logical address and physical address of the block itself, but may be an address corresponding to a unit of resolution smaller than the block unit. .

  The host device 20 includes hardware and software for accessing the connected memory card 1. The host device 20 manages the internal physical state of the memory card 1 (where the physical block address includes what number and what number logical sector address data, or where the block is in the erased state). The NAND flash memory 4 in the memory card 1 is directly controlled.

  In addition, the host device 20 is assumed to use a NAND flash memory (not limited to the NAND flash memory 4) whose erase block size at the time of erasure is set to 16 kbytes. Make assignments. That is, in many cases, the host device 20 performs write access or read access sequentially (issues a corresponding command) for the logical address of 16 kbytes.

  The memory card 1 operates upon receiving power supply when connected to the host device 20, and performs processing in accordance with access from the host device 20. As shown in FIG. 2, the controller A2 includes a host interface (hereinafter referred to as host I / F) 21, a buffer RAM 22, a NAND interface (hereinafter referred to as NAND_I / F) 23, a CPU (Central Processing Unit) 24, and a ROM ( Read Only Memory) 25.

  The host I / F 21 is connected to the host bus 11 and performs interface processing between the host device 20 and the buffer RAM 22 and the CPU 24. The NAND_I / F 23 is connected to the NAND bus 12 and performs interface processing between the controller B3, the buffer RAM 22, and the CPU 24.

  The buffer RAM 22 temporarily stores a certain amount of data (for example, one page) when data input from the host device 20 is written to the NAND flash memory 4, and the data read from the NAND flash memory 4 is stored in the host RAM 20. When outputting to the device 20, a certain amount of data is temporarily stored. The buffer RAM 22 is used as a work area for the CPU 24 and stores a control program and the like.

  The CPU 24 controls the operation of the entire memory card 1. For example, when the memory card 1 is supplied with power, the CPU 24 loads firmware (a control program described later) stored in the ROM 25 into the buffer RAM 22 and executes a predetermined process, thereby executing the host device 20. In response to a write command, a read command, and an erase command, the access process for the corresponding area in the NAND flash memory 4 is executed with the controller B3, and the data transfer process through the buffer RAM 22 is controlled.

  The ROM 25 is a memory that stores a control program used by the CPU 24. The controller A2 is connected to the controller B3 via the NAND bus 13, and the CPU 24 executes various processes assuming that the controller B3 is the NAND flash memory 4. That is, when receiving a write command, a read command, and an erase command from the host device 20, the CPU 24 executes a process of transferring the write command, the read command, and the erase command to the controller B3.

  As illustrated in FIG. 3, the controller B3 includes a NAND_I / F 31, a buffer RAM 32, an ECC (Error Correcting Code) circuit 33, a NAND_I / F 34, a CPU 35, and a ROM 36.

  The NAND_I / F 31 is connected to the NAND bus 12 and performs interface processing between the controller A2, the buffer RAM 32, and the CPU 35. The NAND_I / F 34 is connected to the NAND bus 13 and performs interface processing between the NAND flash memory 4, the ECC circuit 33, and the CPU 35.

  When the data input from the controller A2 is written to the NAND flash memory 4, the buffer RAM 32 temporarily stores a certain amount of data (for example, for one page), and the data read from the NAND flash memory 4 is stored in the controller A2. A certain amount of data is temporarily stored when data is output. The buffer RAM 32 is used as a work area for the CPU 34, and stores a control program, various tables, and the like.

  The ECC circuit 33 performs error correction processing of the write data based on ECC data added to the write data to be written to the NAND flash memory 4, processing to add ECC data to the read data read from the NAND flash memory 4, etc. I do.

  The CPU 35 controls access processing to the NAND flash memory 4. For example, when the memory card 1 receives power supply, the CPU 35 loads firmware stored in the ROM 36 into the buffer RAM 32 and executes predetermined processing. In a predetermined process, the CPU 35 creates various tables, which will be described later, on the buffer RAM 32, receives a write command, a read command, and an erase command from the controller A2, and executes an access process for the corresponding area in the NAND flash memory 4. The data transfer process through the buffer RAM 32 is executed.

  The ROM 36 is a memory that stores a control program used by the CPU 35. Note that the controller B3 is connected to the controller A2 via the NAND bus 12, and the CPU 35 executes processing assuming that the controller A2 is the NAND flash memory 4. That is, when the CPU 35 receives a write command, a read command, and an erase command from the controller A2, the CPU 35 executes an access process for the corresponding area in the NAND flash memory 4.

  FIG. 4 shows the difference in data arrangement between the flash memory assumed by the host device 20 and the flash memory actually used, that is, the NAND flash memory 4 in the memory card 1. In the flash memory assumed by the host device 20, each page has 528 bytes (512 bytes of data storage unit + 16 bytes of redundant unit), and 32 pages have one erase unit, that is, 16 kbytes + 0.5 kbytes ( Here, k is 1024). Hereinafter, a card equipped with such a flash memory may be referred to as a “small block card”.

  On the other hand, in the NAND flash memory 4 to be actually used, each page has 2112 bytes (512 bytes of data storage unit × 4 + 24 bytes of management data storage unit), and 128 pages have one erasure unit, that is, 256 kBytes + 8 kBytes. It becomes. Hereinafter, a card equipped with such a NAND flash memory 4 may be referred to as a “large block card”. In the following description, for the sake of convenience, the erase unit of the small block card is referred to as 16 kbytes, and the erase unit of the large block card is referred to as 256 kbytes.

  Each of the flash memory assumed by the host device 20 and the NAND flash memory 4 that is actually used includes a page buffer for inputting / outputting data to / from the flash memory. The storage capacity of the page buffer provided in the flash memory assumed by the host device 20 is 528 bytes (512 bytes + 16 bytes). On the other hand, the storage capacity of the page buffer provided in the NAND flash memory 4 actually used is 2112 bytes (2048 bytes + 64 bytes). When writing data, etc., it is executed in units of one page corresponding to its own storage capacity.

  In the example of FIG. 4, the erase size of the NAND flash memory 4 actually used is 16 times the erase size of the flash memory assumed by the host device 20, but the present invention is not limited to this. It is not a thing, but it can also be comprised so that it may become another magnification if it is a substantially integer multiple.

  In order to make the large block card a practically effective product, it is desirable that the storage capacity of the NAND flash memory 4 shown in FIG. 4 is 1 Gbit or more. When the storage capacity of the NAND flash memory 4 is, for example, 1 Gbit, the number of 256 kByte blocks (erase units) is 512.

  FIG. 4 illustrates the case where the erasure unit is 256 kBytes, but it is also practically effective to construct the erasure unit to be, for example, a 128 kByte block. In this case, the number of 128 kByte blocks is 1024.

  FIG. 5 is a diagram showing each communication hierarchy of the system on the host device 20 side and the memory card 1 (large block card).

  The system on the host device 20 side includes application software 41, file system 42, driver software 43, and small block card physical access layer 44. On the other hand, the memory card 1 (large block card) includes a small block card physical access layer 51, a small block card physical / small block card logical conversion layer 52, a small block card physical / large block card logical conversion layer 53, and a large block card. It has a physical access layer 54.

  For example, when the application software 41 on the host device 20 side requests the file system 42 to write a file, the file system 42 instructs the driver software 43 to perform sequential sector writing based on the logical block address of the small block card. In response to this, the driver software 43 executes processing for realizing sequential writing for each 16 kByte block based on the logical block address of the small block card. In this case, the driver software 43 performs logical / physical block conversion, issues a random write command based on the physical block address of the small block card to the large block card through the small block card physical access layer 44, and transfers the data. I do.

  In write access, for both small block cards and large block cards, (1) command, (2) page address (row address), (3) column address, (4) data, ( 5) It is assumed that information is exchanged in the order of program confirmation commands.

  When receiving a write command based on the physical block address of the small block card from the host device 20, the small block card physical access layer 51 on the large block card side is included in the accompanying data accompanying the physical block address and data. Get the current logical block address.

  The small block card physical / small block card logical conversion layer 52 converts the logical block address of the small block card (corresponding to 16 kBytes) to the logical block address of the small block card (corresponding to 16 kBytes) when reading data. It has a first table for processing. The small block card physical / small block card logical conversion layer 52 reflects this in the first table when the small block card physical access layer 51 receives the write command and acquires the logical block address of the small block card. The small block card physical / small block card logical conversion layer 52 also reflects the physical block address in the first table.

  The small block card physical / large block card logical conversion layer 53 performs the physical block address (256 kByte physical block) of the large block card from the logical block address of the small block card (corresponding to 16 sequential 16 kByte blocks) at the time of data reading or the like. A second table for performing a conversion process to the corresponding (minute). The small block card physical / large block card logical conversion layer 53 reflects this in the second table when the small block card physical access layer 51 receives the read command and acquires the logical address of the small block card.

  The large block card physical access layer 54 determines the data arrangement in the NAND flash memory 4 based on the logical block address of the small block card acquired by the small block card physical access layer 51 upon receiving the write command, and determines a 256 kByte physical block. The data for 16 kBytes is sequentially written in units of 2 kBytes (one page). The large block card physical access layer 54 stores the acquired logical block address and physical block address of the small block card in a predetermined area in the management data area inside the NAND flash memory 4.

  Since the host device 20 issues a command based on the physical block address of the small block card in this way, on the large block card side, the data corresponding to the physical block address of the small block card exists in which 256 kByte physical block. Manage so that you know. Specifically, the correspondence between the logical and physical block addresses of the small block card is managed every 16 kbytes, and the data corresponding to the logical block addresses of 256 kbyte blocks of the small block card is stored in any 256 kbytes in the large block card. It is managed so that it can be seen whether it is stored in the physical block.

  Further, the host device 20 accesses a large block card having a 256 kByte physical block as an erasure unit on the assumption that the erasure unit is a 16 kByte block. On the other hand, the large block card responds flexibly in accordance with the control algorithm and physical format used by the host device 20. For example, “if a write operation has occurred with a new 16 kByte logical block address, the block corresponding to the 16 kByte physical block address of the small block card when the write operation has previously occurred with the same logical block address ( In view of the algorithm on the side of the host device 20 that “the data erasure of“ the old assignment logical block ”is performed” is emulated, the old assignment logical block to be erased is emulated. However, in practice, the large block card does not erase the 16 kByte block to be erased. As a result, the overhead related to the physical operation on the NAND flash memory 4 can be greatly reduced.

  FIG. 6 is a diagram showing a format of a command sent from the host device 20 side. As shown in FIG. 6A, the command packet sent from the host device 20 side includes command type information (here, “write”), address (physical block address), data (actual data such as contents). And various information such as accompanying data (512 bytes + 16 bytes).

  In a packet of such a format, as shown in FIG. 6B, the “logical block address” (logical address corresponding to the 16-byte block to be accessed) of the small block card at a predetermined position in the accompanying data 16-byte. Is arranged. The large block card acquires command type information, physical block address, and data, and particularly acquires the “logical block address”.

  FIG. 7 is a diagram showing a comparison between a block writing operation assumed on the host device 20 side and a writing process actually performed on the memory card 1 (large block card) side. On the host device 20 side (left side in the figure), when a sequential writing operation in units of 16 kByte physical blocks based on the logical address of the small block card occurs, random writing in units of 16 kByte blocks using the physical block address of the small block card Perform the operation. Along with this, it is assumed that the old assign logical block is erased in units of 16 kByte blocks.

  On the other hand, in the large block card (right side in the figure), when a write command is received from the host device 20 side, data in units of 16 kByte blocks based on the logical block address of the small block card is sequentially written in the NAND flash memory 4. . In this case, in accordance with the above assumption, the old assign logical block in the small block card on the large block card side corresponds to the host device 20 side as being in an erased state. For example, when there is a read access to the old assign logical block, the host device 20 is responded that the block is in the erased state. A small block is also handled as being in an erased state.

  As described above, the host device 20 performs a random writing operation in units of 16 kBytes using the physical address of the small block. In such a random writing operation, generally, a process for rewriting only a part of a large block (256 kBytes) frequently occurs. In NAND flash memory, erasing can only be performed in block units, so when rewriting only a part of the flock, new data to be rewritten is written into the erased new block, and from the old block including old data that is rewritten to new data, Since it involves a copy operation of data that cannot be rewritten (hereinafter referred to as “wrapping data copy”), overhead frequently increases if a process of rewriting only a part of the block occurs frequently.

  Therefore, in the present embodiment, according to the order of the logical addresses obtained from the host device 20, the physical addresses are reassigned on the large block card side, thereby reducing the occurrence of writing of only a part of the block and reducing the overhead. Suppress the increase.

  FIG. 8 is a diagram showing a block format of the NAND flash memory 4 in the large block card (for 256 kByte physical block which is an erasing unit). In the large block card, 16 blocks (hereinafter referred to as host management blocks) for writing data corresponding to 16 kBytes, which is a unit managed by the host device 20, are included in the 256 kByte physical blocks, which are erasure units. ing. At the time of data writing, individual data is arranged in the order of the logical block addresses of the small block card.

  Each host management block is composed of 8 pages. Each page includes four 512-byte data areas and a 10-byte ECC area corresponding to each data area. In addition, a 24-byte management data area is provided after the last 512-byte data area (fourth 512-byte data area) in the page. For this reason, the last 10-byte ECC area in the page has a configuration corresponding to both the fourth 512-byte data area and the 24-byte management data area.

  Of the 128 24-byte management data areas included in the 256 kByte physical block, which is an erasure unit, the last 24-byte management data area 60 corresponds to a physical block address acquired from a command sent from the host device 20 side. Address information (hereinafter referred to as “host management physical address”) and address information corresponding to the logical block address (hereinafter referred to as “host management logical block address”) are collectively stored.

  Specifically, each time 16 kByte data is written to one 16 kByte host management block, the corresponding host management physical address (for example, 10 bits) is stored in a predetermined area in the management data area 60. As a result, 16 host management physical addresses corresponding to 16 16 kByte host management blocks are stored in a predetermined area in the management data area 60. On the other hand, with respect to the host management logical address, the head logical block address (for example, 10 bits) is the host management logical address as a representative of 16 consecutive logical block addresses corresponding to 16 16 kByte host management blocks. Is stored in a predetermined area in the management data area 60.

  In the above configuration, by reading the information arranged in the last area (512 bytes + 24 bytes + 10 bytes area) in each 256 byte block and referring to the 24 bytes management data therein, the “host” corresponding to the 256 kbyte block “Management physical address” and “host management logical block address” can be acquired together.

  The “host management physical address” and “host management logical block address” stored in each 256-byte block are the same as the first table of the small block card physical / small block card logical conversion layer 52 described in FIG. It is used when creating the second table of the block card logic / large block card physical conversion layer 53.

  FIG. 9 is a diagram showing various tables created in the buffer RAM 32 of the controller B3. The “small block card logical / physical block address” table 32a and the “small block card logical block address / large block card physical block address” table 32b correspond to the first table and the second table, respectively. The “host management physical address” and the “host management logical address” stored in the data management area 60 (see FIG. 8) are created in the buffer RAM 32.

  The “small block card logical / physical block address” table 32a is changed from the physical block address of the small block card (corresponding to 16 kByte blocks) to the logical block address of the small block card (corresponding to 16 kByte blocks) at the time of data reading or the like. Used to perform the conversion process.

  The “small block card logical block address / large block card physical block address” table 32b is used to read the logic of the large block card from the logical block address of the small block card (corresponding to 16 sequential 16 kbyte blocks) when data is read. It is used to perform conversion processing to block addresses (corresponding to 256 kByte physical blocks).

  Next, a flow of various table creation processing will be described with reference to the flowchart of FIG. For example, when the memory card 1 (large block card) is supplied with power from the host device 20 side (step A1), the CPU 35 in the controller B3 starts operation, and the control program stored in the ROM 36 (in the small block card) A program for managing the correspondence between the physical / logical block address and the physical block address in the NAND flash memory 4) is loaded on the buffer RAM 32 and processed (step A2). At this time, the CPU 24 in the controller A2 also starts operating, and loads a control program (program for controlling the operation of the entire memory card 1) stored in the ROM 25 onto the buffer RAM 22 for processing.

  Next, the CPU 35 uses the “host management physical address” and the “host management logical block address” stored in the data management area 60 of the NAND flash memory 4, so that the “small block card logic” is stored on the buffer RAM 32. A "physical block address" table 32a and a "small block card logical block address / large block card physical block address" table 32b are created (step A3). Then, the CPU 35 waits for a command from the host device 20 (step A4), and can perform each processing for write access, read access, and erase access according to the control program.

  Next, the flow of processing for write access will be described with reference to the flowchart of FIG. When the CPU 35 receives a write command for, for example, a 16 kbyte block from the host device 20 via the controller A2 (step B1), the CPU 35 converts the physical block address and data of the small block card, and accompanying data associated therewith. An included logical block address is acquired (step B2).

  The CPU 35 writes 16 kByte data in the 256 kByte physical block in the order of the acquired logical block addresses of the small block card, and also “host management logical address” and “host” corresponding to the logical block address and physical block address of the small block card. "Management physical address" is stored in a predetermined area in the management data area 60 (step B3). In addition, the CPU 35 obtains the logical block address and physical block address of the small block card obtained from the “small block card logical / physical block address” table 32 a on the buffer RAM 32 and “small block card logical block address / large block card physical block”. It is reflected in the “address” table 32b (step B4). Finally, the CPU 35 notifies the host device 20 of the completion of the writing process (step B5).

  Next, details of the data writing process in step B3 shown in FIG. 11 will be described with reference to the flowchart of FIG. 12 and conceptual diagrams of FIGS.

  When writing data, the CPU 35 determines whether the target logical block address (corresponding to 16 kByte blocks) is consecutive to the preceding logical block address (corresponding to 16 kByte blocks) ( Step C1 in FIG. That is, as shown in FIG. 13, in the state where data writing to the 16 kByte physical block address X1 has been completed, whether or not the physical block to be written next corresponds to the 16 kByte physical block array X2 following the physical block X1. Determine.

  If it is continuous, the CPU 35 writes the 16 kByte data to be written in the 256 kByte physical block of the large block card following the previously written 16 kByte data (step C2 in FIG. 12). That is, as shown in FIG. 14, data is written to the aforementioned 16 kByte physical block X2.

  On the other hand, if it is not continuous, an accompanying data copy operation is performed on the latter half data in the 256 kByte physical block of the large block card (step C3 in FIG. 12). That is, as shown in FIG. 15, the target 256 kByte physical block includes the physical area Y1 of the old assignment 16 kByte logical block group having the old data that is no longer needed by writing (updating) up to the physical block X1. And a physical area Y2 having valid data that remains valid because there is no update. Therefore, the data of this physical block Y2 is copied to the physical area Y3 following the physical block X1 in the 256 kByte block of interest. Further, after copying, the CPU 35 erases data in the old 256 kByte block that is no longer needed.

  Next, writing to a new 256 kByte physical block (data erased) of the large block card is performed and waiting is performed (step C4 in FIG. 12). Note that the processing differs depending on whether or not the area to be written is at the head of a 256 kByte segment. That is, when the area to be written is at the head of 256 kBytes, as shown in FIG. 16A, 16 kByte data is written into the physical block Z1 at the head position. On the other hand, if the area to be written is not at the head of 256 kByte delimiters, a wrapping data copy operation is performed on the first half data. That is, as shown in FIG. 16B, the data of the old assignment 16 kByte physical block group is copied to the physical area Z2 from the beginning to immediately before the write target, and then the physical area X3 to be written is copied. Write 16 kByte data.

  Next, the flow of processing for read access will be described with reference to the flowchart shown in FIG. When the CPU 35 receives a read command for, for example, a 16 kByte block from the host device 20 (step D1), the CPU 35 acquires the physical block address of the small block card added to the command (step d2).

  Next, the CPU 35 refers to the “small block card logical / physical block address” table 32a to acquire the logical block address of the small block from the acquired physical block address of the small block card (step D3). Next, the CPU 35 acquires the physical block address of the large block card from the acquired logical block address of the small block by referring to the “small block card logical block address / large block card physical block address” table 32b (step D4). ).

  Next, the flow of processing for erase access will be described with reference to the flowchart shown in FIG. When the CPU 35 receives an erase command for, for example, a 16 kByte physical block from the host device 20 (step E1), it records information indicating that the corresponding block is in an erased state in a predetermined area on the buffer RAM 32 as necessary. (Update a predetermined table) (step E2).

  Note that the process of step E2 may be omitted. If the processing of step E2 is performed, when there is a request for confirmation of the erase state from the host device 20 side when the power is off or the power is on, the erase state can be correctly answered.

  Finally, the CPU 35 notifies the host device 20 that the erase has been performed without actually performing the erase process on the designated block (step E3).

  FIG. 19 is a timing chart showing an example of signals input to and output from the I / O pin and the R / B pin of the memory card 1 when the host device 20 writes to the memory card 1 of the present embodiment. is there.

  The host device 20 controls the memory card 1 on the assumption that the memory card 1 is a non-volatile memory having an erase block size of 16 kBytes. For example, when writing to the memory card 1, the host device 20 inputs a serial data input command 80H (H indicates hexadecimal) to the I / O pins 1 to 8. Next, the host device 20 inputs the column address C / A and the page address P / A to the I / O pins 1 to 8. Here, the column address C / A and the page address P / A are a column address and a page address in the virtual physical address space that the host device 20 assumes for the memory card 1.

  Further, the host device 20 inputs the write data 528 times for each of the I / O pins 1 to 8. Specifically, the host device 20 clocks the input signal to the write enable pin 528 times, and data of 528 bits (total 528 bytes for all I / O pins) for each I / O pin. Are sequentially shifted in. When the data shift-in is completed, the host device 20 inputs a program command 10H to the I / O pins 1-8. In response to this, the memory card 1 outputs a low level signal to its R / B pin, indicating that the memory card 1 is busy. Thereafter, a high level signal is output to the R / B pin after a predetermined time, indicating that the ready state has been reached.

  However, the state of the R / B pin in FIG. 19 only indicates the state of the memory card 1 with respect to the host device 20. That is, in FIG. 19, even if the R / B pin indicates a busy state (that is, outputs a low level) in response to the input of the program command 10H, the write operation (that is, the NAND flash memory 4) within the memory card 1 (that is, Data transfer from the page buffer to the memory cell array is not always actually performed. Even if the R / B pin returns to the ready state, the writing operation to the NAND flash memory 4 in the memory card 1 is not always completed.

  FIG. 20 shows the NAND flash memory 4 in the memory card 1 of the present embodiment with the I / O pin and R / B pin of the NAND flash memory 4 when the controller B3 in the memory card 1 performs writing. It is a timing chart which shows the example of the signal input / output.

  The controller B3 recognizes that the NAND flash memory 4 is a non-volatile memory having an erase block size of 256 kBytes. Similarly, the controller A2 recognizes that the NAND flash memory 4 is a non-volatile memory having an erase block size of 256 kBytes. For example, when writing to the NAND flash memory 4, the controller B3 inputs a serial data input command 80H (H indicates hexadecimal) to the I / O pins 1-8. Next, the controller B3 inputs the column address C / A and the page address P / A to the I / O pins 1 to 8. Here, the column address C / A and the page address P / A do not necessarily match the column address and the page address in the real physical address space assumed by the controller B3 for the NAND flash memory 4.

  Further, the controller B3 inputs write data 2112 times for each of the I / O pins 1 to 8. Specifically, the controller B3 clocks the input signal to the write enable pin 2112 times and outputs 2112 bits of data for each I / O pin (2112 bytes in total for all I / O pins). Shift in sequentially. When the data shift-in is completed, the controller B3 inputs a program command 10H to the I / O pins 1-8. In response to this, the memory card 1 outputs a low level signal to its R / B pin, indicating that the memory card 1 is busy. Thereafter, a high level signal is output to the R / B pin after a predetermined time, indicating that the ready state has been reached.

  The state of the R / B pin in FIG. 20 indicates what state the NAND flash memory 4 is actually with respect to the controller B3.

  In FIG. 19 and FIG. 20, the column address C / A and the page address P / A are each input in one cycle, but depending on the capacity of the memory card 1 or the capacity of the NAND flash memory 4 In some cases, the number of cycles may be two or more.

  FIG. 21 is a diagram schematically showing a method of using the memory card 1 of the present embodiment.

  For example, it is assumed that the controller mounted in advance in the host device 20 is premised on the use of the small block card 100 having an erase block unit of 16 kbytes. In this case, if a large block card is realized using a memory having an erase block unit of 256 kBytes without incorporating an appropriate controller in the memory card, there is a possibility that normal access cannot be performed because the erase unit is different. On the other hand, if the large block card 1 including the memory controller B3 having an erase block unit of 256 kBytes is realized based on the present embodiment, the large block card 1 can be used for the host device 20 corresponding to the small block card. It can be inserted and used.

  As described above, according to the present embodiment, a continuous logical block address is acquired from information attached to a write command sent from the host device 20 side to which a small block card is to be accessed, and a large block card is obtained. Data placement is optimized by arranging data in the order of logical block addresses of small block cards in the physical block of the card, thereby reducing overhead during writing. Also, by managing the correspondence between the physical / logical block address of the small block card and the physical block address of the large block card, the consistency between the small block card and the large block card can be efficiently maintained. Also, the erase command from the host device 20 is not actually reflected in a part of the erase block size of the large block card (partially erased), but as if it is in the memory card. By acting as if the erase block has been erased, it is possible to reduce the operation load inside the large block card.

  In addition, the memory card 1 of the present embodiment has a configuration including a controller A2 that controls the operation of the entire memory card 1 and a controller B3 that controls access processing to the NAND flash memory 4. The controller B3 is connected to the controller A2 via the NAND bus 12 so that the controller B3 is recognized as a NAND flash memory by the controller A2. For this reason, for example, when the generation of the NAND flash memory 4 is changed, a protocol such as a control command performed via the NAND bus 13 needs to be changed, or the ECC circuit 33 for maintaining reliability needs to be changed. In such a case, by changing the NAND_I / F 34 and the ECC circuit 33 of the controller B3, the memory card 1 can be reconstructed without changing the controller A2 or the host device 20 connected to the host bus 11. become.

  When constructing the memory card 1 shown in FIG. 1, the two controllers A2 and B3 and the NAND flash memory 4 may be configured as separate packages. For example, as shown in FIG. 22, the memory card 1 may be configured as a controller chip 201 including a controller A2 and a memory chip 202 including a controller B3 and a NAND flash memory 4. With this configuration, even if the generation of the NAND flash memory 4 changes, it is possible to reconstruct the memory card 1 without affecting the entire memory card 1 simply by replacing the memory chip 202. .

(Second Embodiment)
In the second embodiment, a memory card having a controller B configured to form a path for directly connecting the NAND bus 12 and the NAND bus 13 is provided. FIG. 23 is a diagram showing a schematic configuration of a memory card according to the second embodiment to which the memory system of the present invention is applied. In FIG. 23, the same components as those of the memory card 1 shown in FIG. 22 in the first embodiment are denoted by the same reference numerals, and the description of the same configuration is omitted.

  As shown in FIG. 23, the memory card 200 includes a controller chip 201 including a controller A2 and a memory chip 202 including a controller B2021 and the NAND flash memory 4. The controller A2 is connected to the host device 20 via the host bus 11, and is connected to the controller B2021 via the NAND bus 12. The controller B 2021 is connected to the controller A 2 via the NAND bus 12 and connected to the NAND flash memory 4 via the NAND bus 13. The NAND flash memory 4 is connected to the controller B3 by a NAND bus 13. The NAND flash memory 4 may be a binary memory that stores 1-bit data in one memory cell, or may store multiple data (for example, 2 bits) larger than 1 bit in one memory cell. It may be a value memory. Here, a NAND flash memory will be described as an example of the nonvolatile memory. However, the nonvolatile memory is not limited to the NAND flash memory, and may be a NOR flash memory, for example.

  In the second embodiment, it is assumed that the host device 20 is electrically connected to the memory card 200 as a tester during a shipping test of the memory card 200. The controller B 2021 converts the address received by the NAND_I / F 31, accesses the NAND flash memory 4 using the converted address, and directly accesses the NAND flash memory 4 using the address received by the NAND_I / F 31. And switching the operation mode between the first mode and the second mode according to the command.

  Hereinafter, the switching operation from the first mode to the second mode is referred to as a transition operation, and the switching operation from the second mode to the first mode is referred to as a return operation. The “first mode” is an operation mode in which the host device 20 does not directly access the NAND flash memory 4 and means an operation mode similar to that when the memory card 200 is actually used.

  During the shipping test, the host device 20 individually tests the controller B 2021 and the NAND flash memory 4. In the following description, a test executed only for the controller B 2021 is called a “controller unit test”, and a test executed only for the NAND flash memory 4 is called a “NAND unit test”. In the controller unit test, the operation mode is set to the first mode, and in the NAND unit test, the operation mode is set to the second mode.

  For example, the NAND flash memory 4 has a storage capacity of 1 Gbit or more, an erase block size as an erase unit is set to 256 kbytes, and data writing and reading are performed in 16 kbyte units. The NAND flash memory 4 is manufactured using, for example, a 0.09 μm process technology, and the design rule is less than 0.1 μm.

  As shown in FIG. 24, the controller B 2021 includes a NAND_I / F 31, a buffer RAM 32, an ECC circuit 33, a NAND_I / F 34, a CPU 35, a ROM 36, and an access path setting unit 2022.

  The CPU 35 controls access processing to the NAND flash memory 4. In the first mode, the CPU 35 loads firmware stored in the ROM 36 into the buffer RAM 32 and executes predetermined processing. The CPU 35 creates various tables in the buffer RAM 32 by processing executed in the first mode, receives write commands, read commands, and erase commands from the host device 20 and executes access to the NAND flash memory 4, Data transfer processing through the buffer RAM 32 is controlled.

  The access path setting unit 2022 sets an access path for the host device 20 to directly access the NAND flash memory 4 in the second mode. As shown in FIG. 24, the access path setting unit 2022 includes a first switch SW1 connected between the NAND_I / F 31 and the buffer RAM 32, and a second switch connected between the ECC circuit 33 and the NAND_I / F 34. It has SW2. The first and second switches SW1 and SW2 switch the connection relationship of the NAND_I / F 31, the buffer RAM 32, the ECC circuit 33, and the NAND_I / F 34 according to the switching control signal input from the CPU 35. By this switching, in the second mode, write data, read data, etc. can bypass the buffer RAM 32 and the ECC circuit 33, and commands issued by the host device 20 can be directly transmitted to the NAND flash memory 4.

  As described above, since the controller B 2021 is configured to control the transition operation and the return operation according to the command, the second mode can be realized without increasing the number of external connection pins of the memory card 200.

  An arrangement example of the external connection pins of the memory card 200 is shown in FIG. FIG. 25 is a plan view of the memory card 200 as viewed from the pin forming surface. The memory card 200 has a total of 18 external connection pins of first to 18th pins P1 to P18. FIG. 26 shows an example of signals assigned to the first to eighteenth pins P1 to P18 and the pins. In the attribute “type” of FIG. 26, the symbol “S” indicates a power supply voltage, the symbol “I” indicates an input to the memory card 200, and the symbol “O” indicates an output from the memory card 200. The symbol “I / O” indicates an input / output to / from the memory card 200. The symbol “-” added to the head of the pin name (symbol name) indicates that the signal is a low true signal, that is, a signal that is activated at the “Low” level.

  In FIG. 26, the first and ninth pins P1, P9 are assigned to the ground voltage GND, and the eighteenth pin P18 is assigned to the power supply voltage Vcc.

  The second pin P2 is assigned to a ready / busy (R / -B) signal for notifying the host device 20 of the internal operation state of the memory card 200. In the memory card 200, a busy signal is output from the second pin P2 during operations such as data writing, reading, and erasing, and a ready signal is output from the second pin P2 when the operation is completed.

  The third pin P3 is assigned to a read enable (-RE) signal for outputting data from the memory card 200, and the fourth pin P4 is assigned to a card enable (-CE) signal for making the memory card 200 operable. It has been.

  The fifth pin P5 is a command latch enable (CLE) signal for controlling command fetching, and the sixth pin P6 is an address latch enable (ALE) signal for controlling address fetching. Assigned.

  The seventh pin P7 is a write enable (-WE) signal for writing data to the memory card 200, and the eighth pin P8 is a write protect (-WP) signal for forcibly prohibiting writing and erasing. Assigned to each.

  The tenth to seventeenth pins P10 to P17 are assigned to the bits D0 to D7 of the command, address, and data, respectively. The example of the arrangement of the external connection pins shown in FIG. 26 is the same as the pin (not shown) of the host I / F 21 (see FIG. 2) in the controller A2 connected to the host bus 11 shown in FIG. One-to-one correspondence.

  On the other hand, the NAND flash memory 4 and the NAND_I / F 34 have the same pin configuration as that of the host I / F 21 shown in FIG. Specifically, the NAND flash memory 4 and the NAND_I / F 34 output input / output (I / O) pins 1 to 8 for inputting / outputting commands, addresses, and data, and R / -B for outputting a ready / busy signal. A pin, a -RE pin to which a read enable signal is input, a -CE pin to which a chip enable signal is input, a CLE pin to which a command latch enable signal is input, and an ALE to which an address latch enable signal is input A pin, a -WE pin to which a write enable signal is input, and a -WP pin to which a write protect signal is input.

  As described above, the memory card 200 has a pin configuration corresponding to the pin configuration of the NAND flash memory 4, and the host device 20 can access the memory card 200 by a command sequence for the NAND flash memory 4. It is. Here, the “command sequence” means a combination of one command and an address, a combination of a plurality of commands, or a combination of any one or all of commands, addresses, and data.

  As described above, the controller B 2021 controls the transition operation and the return operation according to the command. However, the controller B 2021 may recognize a command related to the transition operation and the return operation input from the host device 20 as a write command or a read command and malfunction. In addition, when the same address or data as a command (for example, “FFh” command (h; indicating hexadecimal)) instructing a return operation is input from the host device 20, the controller B2021 executes an unintended return operation. There is a risk of doing.

Therefore, in the second embodiment, the controller B 2021 controls the transition operation and the return operation according to the command sequence input from the host device 20, thereby making it possible to avoid the malfunction of the controller B 2021. Specifically, when executing the NAND unit test, the host device 20 issues a command sequence for instructing a migration operation after the memory card 200 is powered on. The controller B 2021 sets the operation mode to the second mode by receiving the command sequence, and maintains the second mode until a command sequence instructing the return operation is issued from the host device 20.
By using the command sequence in this way, it is possible to avoid the controller B 2021 from executing an unintended return operation during the second mode.

  Further, in the first mode, the host device 20 assigns logical addresses and physical addresses in units of 16 kbytes on the assumption that the NAND flash memory 4 whose erase block size is set to 16 kbytes is used. In the first mode, the host device 20 issues a corresponding command in order to perform sequential write access or read access for the logical address of 16 kbytes. Note that the terms “logical block address” and “physical block address” used in the following description mean a logical address and a physical address assigned to the block itself in the NAND flash memory 4, respectively. Further, “logical address” and “physical address” mainly mean the logical address and physical address of the block itself, but may be an address corresponding to a unit of resolution smaller than the block unit. .

  The host device 20 also determines the internal physical state of the memory card 200, for example, what physical block address contains the number of logical sector address data, or what block is in the erased state. It is constructed to manage and directly control the NAND flash memory 4 in the memory card 200.

  When the host device 20 operates assuming that the NAND flash memory 4 whose erase block size is set to 16 kbytes is used, the actual erase block size of the NAND flash memory 4 is 256 kbytes. It cannot operate normally and malfunctions.

  In order to avoid this malfunction of the memory card 200, the controller B 2021 processes a command sequence issued by the host device 20 assuming an erase block size smaller than the erase block size of the NAND flash memory 4 in the first mode, Controls write, read, and erase operations on the NAND flash memory 4.

  The difference in data arrangement between the NAND flash memory assumed by the host device 20 and the NAND flash memory 4 actually used will be described with reference to FIG.

  In the NAND flash memory assumed by the host device 20, each page has a storage capacity of 528 bytes consisting of a data storage part for 512 bytes and a redundant part for 16 bytes, and 32 pages have one erasure unit. (16 kByte + 0.5 kByte). Hereinafter, for convenience of explanation, a memory card equipped with a NAND flash memory having such a page configuration may be referred to as a “small block card”.

  On the other hand, in the NAND flash memory 4 that is actually used, each page has, for example, a storage of 2112 bytes including four data storage units for 512 bytes, four redundant units for 10 bytes, and a management data storage unit for 24 bytes. It has a capacity, and 128 pages are one erasure unit (256 kByte + 8 kByte). Hereinafter, for convenience of explanation, the memory card 200 on which the NAND flash memory 4 having such a page configuration is mounted may be referred to as a “large block card”.

  As shown in FIG. 27, the NAND flash memory assumed by the host device 20 and the NAND flash memory 4 actually used include page buffers 401 and 402 for inputting / outputting data to / from the NAND flash memory, respectively. I have. The storage capacity of the page buffer 401 provided in the NAND flash memory assumed by the host device 20 is 528 bytes (512 bytes + 16 bytes). On the other hand, the storage capacity of the page buffer 402 included in the NAND flash memory 4 that is actually used is 2112 bytes (2048 bytes + 64 bytes). At the time of data writing or the like, data input / output with respect to the NAND flash memory is executed in units of one page corresponding to the storage capacity of each of the page buffers 401 and 402.

  As described above, since the NAND flash memory 4 that the host device 20 assumes and the NAND flash memory 4 that is actually used have different page configurations, the controller B 2021 allows the host device 20 to access the NAND flash memory 4. Various processes are executed.

  FIG. 28 shows functional configuration examples of the host device 20 and the controller B 2021 in the memory card 200. The host device 20 executes a program stored in a ROM (not shown) or the like on the host device 20 side by a CPU (not shown) or the like, thereby causing the application processing unit 71 and the file system unit 72 shown in FIG. Each function of the driver unit 73 and the physical access unit 74 is realized.

  On the other hand, the controller B 2021 executes, for example, a control program stored in the ROM 36 by the CPU 35, whereby the first physical access unit 81, the physical / logical conversion unit 82, the logical / physical conversion unit 83, and the like shown in FIG. Each function of the second physical access unit 84 is realized.

  When the application processing unit 71 on the host device 20 side requests the file system unit 72 to write a file, the file system unit 72 instructs the driver unit 73 to perform sequential sector writing based on the logical block address of the small block card. In response to this, the driver unit 73 performs logical / physical block conversion in order to realize sequential writing every 16 kbytes based on the logical block address of the small block card, and passes the physical block of the small block card through the physical access unit 74. A random write command by address is issued to the large block card to perform data transfer.

  In the write access, in the case of a small block card and a large block card, according to the protocol, (1) command, (2) page address (row address), (3) column address, (4) data, (5) Information is exchanged in the order of program confirmation commands.

  When the first physical access unit 81 on the controller B 2021 side receives a write command based on the physical block address of the small block card from the host device 20, the logical block included in the accompanying data associated with the physical block address and data is received. Get block address.

  The physical / logical conversion unit 82 performs a first conversion process for converting the physical block address of the small block card (corresponding to 16 kBytes) to the logical block address of the small block card (corresponding to 16 kBytes) when reading data. Create a table. The first table is stored in the first table storage area 321 of the buffer RAM 32. When the first physical access unit 81 receives the write command and acquires the logical block address of the small block card, the physical / logical conversion unit 82 reflects the logical block address in the first table. Further, the physical / logical conversion unit 82 also reflects the physical block address in the first table.

  The logical / physical conversion unit 83 converts the logical block address of the small block card (corresponding to 16 sequential 16 kbytes) to the physical block address of the large block card (corresponding to 256 kbyte physical blocks) when reading data. A second table for processing is created. The second table is stored in the second table storage area 322 of the buffer RAM 32. When the first physical access unit 81 receives a write command and acquires the logical block address of the small block card, the logical / physical conversion unit 83 reflects the logical block address in the second table.

  The second physical access unit 84 determines the data arrangement inside the NAND flash memory 4 based on the logical block address of the small block card acquired by the first physical access unit 81 receiving the write command, and 2 kBytes in the 256 kByte physical block. Data for 16 kBytes is written sequentially in units of (1 page). The second physical access unit 84 stores the acquired logical block address and physical block address of the small block card in a predetermined area in the management data area in the NAND flash memory 4.

  As described above, since the host device 20 issues a command based on the physical block address of the small block card, on the memory card 200 side, data corresponding to the physical block address of the small block card exists in any 256 kByte physical block. Manage so that you know what to do. Specifically, the controller B 2021 manages the correspondence relationship between the logical / physical block addresses of the small block card for every 16 kByte block, and data corresponding to the logical block addresses for 256 kBytes of the continuous small block card is stored in the memory card 200. The NAND flash memory 4 is managed so that it can be seen where it is stored in a 256 kByte physical block.

  Next, a format example of a command sent from the host device 20 to the memory card 200 will be described with reference to FIG. As shown in FIG. 29A, the command packet sent from the host device 20 includes command type information (for example, a write command), an address (physical block address), and data (actual data such as contents and accompanying data). Various information such as data (512 bytes + 16 bytes) is included.

  In the packet of such a format, as shown in FIG. 29B, the logical block address of the small block card (logical address corresponding to the 16 kByte block to be accessed) is arranged at a predetermined position in the accompanying data 16 bytes. ing. The memory card 200 acquires command type information, a physical block address, and data from a command sent from the host device 20, and particularly acquires a logical block address. The logical block address is not added in the case of a read command.

  Next, with reference to FIG. 30, the block write operation assumed by the host device 20 in the first mode and the write process actually performed by the memory card 200 will be compared.

  On the host device 20 side, as shown in FIG. 30 (a), when a sequential writing operation in units of 16 kByte blocks based on the logical address of the small block card occurs, random in units of 16 kByte blocks based on the physical block address of the small block card. A write operation is performed.

  On the other hand, on the memory card 200 side, as shown in FIG. 30B, when a write command is received from the host device 20, 16 kByte block unit data based on the logical block address of the small block card is stored in the NAND flash memory 4. Sequentially written.

  As described above, the host device 20 performs a random writing operation in units of 16 kByte blocks using the physical address of the small block card. In such a random write operation, generally, a process of rewriting only a part of a large block (256 kBytes) frequently occurs. Since the NAND flash memory 4 can be erased only in units of blocks, when only a part of the block is rewritten, new data to be rewritten is written into the erased new block and cannot be rewritten from the old block rewritten with the new data. The remaining data needs to be copied to the new block.

  As described above, since the process of rewriting only a part of the block involves a copy operation of data that cannot be rewritten (wrapped data copy), if the process of rewriting only a part of the block occurs frequently, the overhead increases. . Therefore, in the second embodiment, by reassigning physical addresses on the memory card 200 side according to the order of logical addresses obtained from the host device 20 side, the occurrence of rewriting of only a part of the block is reduced, An increase in overhead can be suppressed.

  Next, with reference to FIG. 31, the block format of the NAND flash memory 4 (for 256 kByte physical blocks as an erase unit) will be described.

  In the NAND flash memory 4, 16 blocks (hereinafter referred to as “host management block”) for writing data corresponding to 16 kByte, which is a unit managed by the host device 20, are included in the 256 kByte physical block, which is an erase unit. include. When data is written, individual data is arranged according to the order of logical block addresses of the small block card.

  Each host management block is composed of 8 pages. Each page includes four 512-byte data areas and a 10-byte error correction code (ECC) area corresponding to each data area. Also, a 24-byte management data area is provided after the last 512-byte data area (fourth 512-byte data area) in the page. For this reason, the last 10-byte ECC area in the page has a configuration corresponding to both the fourth 512-byte data area and the 24-byte management data area.

  Of the 128 24-byte management data areas included in the 256 kByte physical block that is an erasure unit, for example, the last 24-byte management data area corresponds to the physical block address acquired from the command sent from the host device 20 Address information corresponding to the logical block address and the address information corresponding to the logical block address are stored together. These pieces of address information are used when creating the first and second tables described above.

  Next, referring to FIG. 32, when the host device 20 writes to the memory card 200 in the first mode, the input / output (I / O) pins (10th to 17th pins) of the memory card 200 are displayed. An example of signals input / output to / from the ready / busy (R / -B) pin (second pin P2) will be described.

  The host device 20 controls the memory card 200 on the assumption that the memory card 200 is a non-volatile memory having an erase block size of 16 kBytes. Therefore, the host device 20 inputs the serial data input command “80H” to the I / O pins (10th to 17th pins P10 to P17) when writing to the memory card 200. Next, the host device 20 inputs the column address “C / A” and the page address “P / A” to the I / O pins (10th to 17th pins P10 to P17). Here, the column address “C / A” and the page address “P / A” are the column address and page address in the virtual physical address space that the host device 20 assumes for the memory card 200.

  Further, the host device 20 inputs the write data 528 times to each of the I / O pins (10th to 17th pins P10 to P17). Specifically, the host device 20 clocks the input signal to the write enable pin (seventh pin P7) to each I / O pin (10th to 17th pins P10 to P17) while clocking 528 times. On the other hand, data of 528 bits (a total of 528 bytes in total for all I / O pins) is sequentially shifted in. When the data shift-in is completed, the host device 20 inputs the program command “10H” to the I / O pins (10th to 17th pins P10 to P17). In response to this, the memory card 200 outputs an “L” signal to its ready / busy (R / −B) pin, and notifies the host device 20 that the memory card 200 is busy. Thereafter, by outputting an “H” signal to the ready / busy (R / −B) pin after a predetermined period, it is transmitted to the host device 20 that the memory card 200 has become ready.

  However, the ready / busy (R / -B) pin state in FIG. 32 only indicates the state of the memory card 200 with respect to the host device 20. That is, in FIG. 32, even if the ready / busy (R / -B) pin of the memory card 200 indicates the busy state (that is, outputs the “L” signal) in response to the input of the program command “10H”. In the memory card 200, the write operation (data transfer from the page buffer 401 to the memory cell array) to the NAND flash memory 4 is not always actually performed. Further, even if the ready / busy (R / -B) pin returns to the ready state, the writing operation to the NAND flash memory 4 is not necessarily actually finished inside the memory card 200.

  On the other hand, in the first mode, when the controller B 2021 in the memory card 200 performs writing to the NAND flash memory 4 in the memory card 200, the I / O pins 1 to 8 and R / An example of signals input to and output from the -B pin is shown in FIG.

  The controller B 2021 recognizes that the NAND flash memory 4 is a nonvolatile memory having an erase block size of 256 kBytes. For example, the controller B 2021 inputs a serial data input command “80H” to the I / O pins 1 to 8 when writing to the NAND flash memory 4. Next, the controller B 2021 inputs the column address “C / A” and the page address “P / A” to the I / O pins 1 to 8. Here, the column address “C / A” and the page address “P / A” are the column address and the page address in the real physical address space of the NAND flash memory 4. Therefore, the column address and page address in FIG. 32 do not necessarily match the column address and page address in FIG.

  Further, the controller B 2021 inputs write data to the I / O pins 1 to 8 2112 times. Specifically, the controller B 2021 clocks the input signal to the write enable pin 2112 times, and performs 2112 bits for each of the I / O pins 1 to 8 (2112 bytes in total for all I / O pins). Shift data in sequentially. When the data shift-in is completed, the controller B 2021 inputs the program command “10H” to the I / O pins 1 to 8. In response to this, the memory card 200 outputs an “L” signal to its R / −B pin to notify the host device 20 that the memory card 200 is busy. Thereafter, by outputting an “H” signal to the R / −B pin after a predetermined period, it is transmitted to the host device 20 that the memory card 200 is ready. The state of the R / -B pin in FIG. 33 indicates what state the NAND flash memory 4 is actually with respect to the controller B2021.

  32 and 33, the input of the column address “C / A” and the page address “P / A” is shown in one cycle, but the capacity of the memory card 200 or the NAND flash memory 4 Depending on the capacity, there may be two or more cycles as appropriate.

  32 and 33, the write operation in the first mode has been described. In the second mode, the host device 20 directly executes the write operation shown in FIG. 33 to the NAND flash memory 4 of the memory card 200. Will do.

  Hereinafter, the memory card test method according to the second embodiment will be described with reference to the flowchart shown in FIG.

  First, in step F1, the controller B 2021 determines whether or not to execute a NAND unit test. When the NAND unit test is executed (step F1: YES), the process proceeds to step F2. When the NAND unit test is not executed (step F1: NO), the process proceeds to step F5.

  In step F2, the host device 20 outputs a command sequence for instructing the migration operation to the memory card 200, for example, “XX-YY-ZZ”. The CPU 35 in the controller B 2021 sets the operation mode to the second mode in accordance with the command sequence for instructing the transition operation. Specifically, the CPU 35 supplies the switching control signal to the first and second switches SW1 and SW2 of the access path setting unit 2022, so that the access path is set. When the operation mode is set to the second mode, the process proceeds to Step F3.

  In step F3, the host device 20 executes a NAND unit test. For example, the host device 20 determines whether the NAND flash memory 4 includes a defective portion by confirming the consistency between the write data and the read data. As a result, in the NAND flash memory 4, the presence / absence of a bit (fail bit) in which erroneous data is held, a bit (bad block) that cannot be written or read, and the like are determined. When the NAND unit test is completed, the process proceeds to step F4.

  In step F4, the host device 20 outputs a command sequence for instructing the memory card 200 to perform a return operation. When the command sequence for instructing the return operation is transmitted to the memory card 200, the process proceeds to Step F5.

  In step F5, the CPU 35 sets the operation mode to the first mode.

  In step F6, the controller B 2021 determines whether or not to execute a controller unit test. When executing the controller unit test (step F6: YES), the controller B 2021 proceeds to step F7. When the controller unit test is not executed (step F6: NO), the process returns to step F5.

  In step F7, the host device 20 executes a controller unit test. As an example, the host device 20 inputs an arbitrary command or the like to the controller B 2021, and a test is performed to determine whether the controller B 2021 responds normally. When the controller unit test is completed, the process proceeds to step F8.

  In step F8, the controller B2021 determines whether or not to execute the NAND unit test. When the NAND unit test is executed (step F8: YES), the process returns to step F2. When the NAND unit test is not executed (step F8: NO), the test operation is terminated.

  As described above, in the memory card 200 according to the second embodiment, the transition operation and the return operation are controlled by the command sent from the host device 20, so that the number of pins of the memory card 200 is not increased. Two modes can be realized. Furthermore, by controlling the second mode with a specific command sequence, it is possible to avoid erroneous recognition that the memory card 200 is in writing or reading. Further, since the host device 20 handles an erase block size larger in the second mode than in the first mode, the time required for the unit test of the NAND flash memory 4 can be shortened.

  The memory card 200 according to the second embodiment is configured as a controller chip 201 including the controller A2 and a memory chip 202 including the controller B2021 and the NAND flash memory 4. With this configuration, it is possible to replace the controller B 2021 with a NAND flash memory having a different block size or reliability without changing the controller B 2021 simply by replacing the memory chip 202.

  In the second embodiment, the case where the access path setting unit 2022 sets an access path by a command sent from the host device 20 to the memory card 200 is shown. For example, a memory card 200 shown in FIG. 35 may be used, and the access path setting unit 2022 may detect the power-on and automatically set the access path.

  In the controller B 2021 shown in FIG. 24 described above, if a problem occurs during the activation of the CPU 35 or the like, the controller 20202 cannot shift to the second mode, and the host device 20 cannot proceed with the analysis (test). Therefore, the NAND unit test can be executed by automatically setting the second mode when the power is turned on.

  When the ground voltage GND is applied to the first and ninth pins P1 and P9 shown in FIGS. 25 and 26 and the power supply voltage Vcc is applied to the 18th pin P18, the access path setting unit 2022, for example, the power supply voltage Vcc The access path is set using the rising edge of

  When returning to the first mode from the second mode that is automatically set when the memory card 200 is turned on, not only the command sequence that instructs the return operation, but also a command that instructs the return operation, for example, “FFH” Use the command. That is, the controller B 2021 shown in FIG. 35 can execute the return operation by either a command or a command sequence. However, as in the case of the controller B 2021 shown in FIG. 24, when the second mode is set by a command sequence instructing a transition operation, it is not possible to return to the first mode unless a command sequence instructing a return operation.

  Hereinafter, a memory card test method by the controller B 2021 shown in FIG. 35 will be described with reference to a flowchart shown in FIG. However, the same steps as those in the memory card test method shown in FIG.

  First, in step G1, the memory card 200 is inserted into a card slot (not shown) of the host device 20, and power is supplied from the host device 20 to the memory card 200. When power is supplied to the memory card 200, the access path setting unit 2022 in the controller B 2021 automatically sets the access path, and the operation mode is automatically set to the second mode.

  In step F1, the controller B 2021 determines whether or not to execute the NAND unit test. When the NAND unit test is executed (step F1: YES), the process proceeds to step F2. When the NAND unit test is not executed (step F1: NO), the process proceeds to step F5.

  In step G 2, a command for instructing a return operation is input from the host device 20 to the memory card 200. When a command for instructing a return operation is input from the host device 20 to the memory card 200, the process proceeds to step F5.

  Each process of step F2 to step F8 is executed in the same manner as in FIG.

  As described above, according to the configuration of the controller B 2021 shown in FIG. 35, the NAND unit test can be executed even when the controller B 2021 has an abnormality by automatically setting the second mode immediately after the power is turned on. .

(Third embodiment)
The third embodiment exemplifies a configuration when the memory card 1 shown in the first embodiment is packaged. FIG. 37 is a cross-sectional view showing a configuration when the memory card 300 according to the third embodiment is packaged. In FIG. 37, the same components as those of the memory card 1 shown in FIG. 1 in the first embodiment are denoted by the same reference numerals.

  In FIG. 37, reference numeral 70 denotes a substrate. The NAND flash memory 4 is formed on the substrate 70 with an interlayer film 71 interposed therebetween. On the NAND flash memory 4, the controller A2 and the controller B3 are formed via an interlayer film 71, respectively. In the substrate 70, the NAND flash memory 4, and the controller B 3, pads 73 to 75 for connecting the bonding wires 72 are formed on each upper surface at the left end portion in the drawing. Also, pads 76 and 77 for connecting the bonding wires 72 are formed on the upper surface of the right end portion of the controller B3 in the drawing and the upper surface of the left end portion of the controller A2 in the drawing, respectively. Also, external connection pins 78 corresponding to the first to eighteenth pins P1 to P18 shown in FIG. 25 are formed on the lower surface side of the left end portion of the substrate 70 in the drawing.

  FIG. 38 is a cross-sectional view showing another configuration when the memory card 300 according to the third embodiment is packaged. In FIG. 38, the same components as those of the memory card 1 shown in FIG. 1 in the first embodiment and the same components as those shown in FIG. The description is omitted.

  In FIG. 38, a controller B 3 is formed on the NAND flash memory 4 via an interlayer film 71. On the controller B3, a controller A2 is formed via an interlayer film 71. In the substrate 70, the NAND flash memory 4, the controller B3, and the controller A2, pads 73 to 75 and 77 for connecting the bonding wires 72 are formed on the respective upper surfaces at the left end in the drawing.

  The cross-sectional views of the packages shown in FIGS. 37 and 38 exemplify the case where the controller B3 and the controller A2 are stacked on the NAND flash memory 4. 37 and 38, the controller B3 and the controller A2 are stacked on the NAND flash memory 4, the bonding wires 72 are connected, and then the whole except for the external connection pins 78 is sealed with resin or the like. Is done.

  As described above, the stacked structure allows the memory card 300 to be formed with the size of the substrate 70 on which the NAND flash memory 4 can be substantially mounted, and the size of the package as the memory card 300 is reduced. It becomes possible to do.

  FIG. 39 is a cross-sectional view showing another configuration when the memory card according to the third embodiment is packaged. 39, the same reference numerals are given to the same components as those of the memory card 1 shown in FIG. 1 and the same components as those shown in FIG. 37 in the first embodiment. The description is omitted.

  In FIG. 39, on the substrate 70 of the memory card 400, the NAND flash memory 4, the controller B3, and the controller A2 are formed via the interlayer film 71, respectively. A pad 75 for connecting the bonding wire 72 is formed on the upper surface of the left end portion of the controller B3 in the drawing. Also, pads 76 and 77 for connecting the bonding wires 72 are formed on the upper surface of the right end portion of the controller B3 in the drawing and the upper surface of the left end portion of the controller A2 in the drawing, respectively. Pads 81 and 82 for connecting bonding wires 72 are formed on the upper surface of the right end portion of the controller A2 in the drawing and the upper surface of the left end portion of the NAND flash memory 4 in the drawing, respectively.

  In the memory card 400 shown in FIG. 39, the NAND flash memory 4, the controller B3, and the controller A2 are formed on the substrate 70, the bonding wires 72 are connected, and the whole except the external connection pins 78 is sealed with resin or the like. Is done.

  The sectional view of the package shown in FIG. 39 exemplifies the case where the NAND flash memory 4, the controller B3, and the controller A2 are arranged on the substrate 70. With such a structure, when the generation of the NAND flash memory 4 is changed, the NAND flash memory 4 and the controller B3 can be easily replaced.

  The configurations of the packages shown in FIGS. 37 to 39 are shown as corresponding to the memory cards 1 and 200, but other than the memory card, for example, a multi-chip package (MCM), a system-in-package It can also be applied as (SiP) or the like.

(Fourth embodiment)
The fourth embodiment exemplifies a configuration when the package exemplified in the third embodiment is applied as a USB (Universal Serial Bus) memory. FIG. 40 is a cross-sectional view showing the configuration of the USB memory according to the third embodiment. In FIG. 40, the same components as those in the package configuration of the memory card shown in FIG. 37 in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the USB memory 500 shown in FIG. 40, reference numeral 501 denotes a circuit board. On the upper surface side of the circuit board 501, a control chip 503 such as an electronic component 502 and a USB controller is mounted, and a conductor layer 504 serving as an input / output terminal of a USB connector is formed. The packaged memory card 300 shown in FIG. 37 is mounted on the lower surface side of the circuit board 501. Reference numeral 505 denotes an exterior case of the USB memory 500.

  In the USB memory 500 shown in FIG. 40, the memory card 300 is mounted on the circuit board 501 as it is, so that the USB memory can be easily manufactured and the range of use of the memory card 300 can be expanded. . Further, when the generation of the NAND flash memory 4 in the USB memory 500 is changed, it can be mounted using the memory card 300 manufactured according to the generation, and the specification change as the USB memory is easy. become.

  In the fourth embodiment, the case where the memory card 300 shown in FIG. 37 is applied to the USB memory is illustrated. However, the present invention is not limited to this, and the memory card 300 and the memory card 300 shown in FIG. The memory card 400 shown in FIG. 39 may be applied.

(Fifth embodiment)
In the fifth embodiment, two NAND flash memories having different configurations are connected to the controller B, and the write data to the two NAND flash memories is based on the number of rewrites of the write data input from the host device 20. A case of changing the storage destination of will be described. FIG. 41 is a diagram showing a schematic configuration of the memory card according to the fifth embodiment. In FIG. 41, the same components as those in the memory card 1 shown in FIG. 1 in the first embodiment are denoted by the same reference numerals.

 As shown in FIG. 41, the memory card 600 includes a controller A601, a controller B602, and NAND flash memories M1 and M2. The controller A 601 is connected to the host device 20 via the host bus 11 and is connected to the controller B 602 via the NAND bus 611. The controller B 602 is connected to the controller A 601 via the NAND bus 611, connected to the NAND flash memory M1 via the NAND bus 612, and connected to the NAND flash memory M2 via the NAND bus 613. The NAND flash memory M1 is connected to the controller B 602 via a NAND bus 612. The NAND flash memory M2 is connected to the controller B 602 via a NAND bus 613.

  The NAND flash memories M1 and M2 may be binary memories that store 1-bit data in one memory cell, or store more data (for example, 2 bits) than 1 bit in one memory cell. It may be a multi-valued memory. Here, a NAND flash memory will be described as an example of the nonvolatile memory. However, the nonvolatile memory is not limited to the NAND flash memory, and may be a NOR flash memory, for example. In addition, although an example in which two NAND flash memories M1 and M2 are connected has been shown, a plurality of NAND flash memories may be further connected.

  For example, the NAND flash memories M1 and M2 have different storage capacities (large capacity and small capacity), different numbers of bits of data to be stored (binary and multivalued), different design rules, Those having different configurations such as those having different block sizes (large block and small block) are used. In the fifth embodiment, a large capacity memory is used as the NAND flash memory M1, and a small capacity memory is used as the NAND flash memory M2. In general, NAND flash memory has a reduced design rule in order to realize a larger capacity and a smaller chip area. However, as the design rule is reduced, the guaranteed number of data rewrites tends to decrease, and there is a concern that the reliability of the NAND flash memory is lowered. For this reason, using two types of NAND flash memories with different design rules and appropriately changing the NAND flash memory at the storage destination according to the data with different number of rewrite requests can avoid a decrease in reliability. Is possible.

  The terms “logical block address” and “physical block address” used in the following description mean a logical address and a physical address assigned to the blocks in the NAND flash memories M1 and M2, respectively. Further, “logical address” and “physical address” mainly mean the logical address and physical address of the block itself, but may be an address corresponding to a unit of resolution smaller than the block unit. .

  The host device 20 includes hardware and software for accessing the connected memory card 600. The host device 20 manages the internal physical state of the memory card 600 (which physical block address includes what number and what logical sector address data, or which block is in an erased state). The NAND flash memories M1 and M2 in the memory card 600 are directly controlled.

  Further, the host device 20 is assumed to use a NAND flash memory (not limited to the NAND flash memories M1 and M2) in which the erase block size at the time of erasure is set to 16 kbytes. Assign physical addresses. That is, in many cases, the host device 20 performs write access or read access sequentially (issues a corresponding command) for the logical address of 16 kbytes.

  The memory card 600 operates upon receiving power supply when connected to the host device 20, and performs processing in accordance with access from the host device 20. As shown in FIG. 42, the controller A 601 includes a host interface (hereinafter referred to as host I / F) 621, a buffer RAM 622, a NAND interface (hereinafter referred to as NAND_I / F) 623, a CPU (Central Processing Unit) 624, and a ROM ( Read Only Memory) 625.

  The host I / F 621 is connected to the host bus 11 and performs interface processing between the host device 20 and the buffer RAM 622 and the CPU 624. The NAND_I / F 623 is connected to the NAND bus 611 and performs interface processing between the controller B 602, the buffer RAM 622, and the CPU 624.

  The buffer RAM 622 temporarily stores a certain amount of data (for example, one page) when data input from the host device 20 is written to the NAND flash memories M1 and M2, and is read from the NAND flash memories M1 and M2. When outputting data to the host device 20, a certain amount of data is temporarily stored. The buffer RAM 622 is used as a work area for the CPU 624 and stores a control program and the like.

  The CPU 624 controls the operation of the entire memory card 600. For example, when the memory card 600 is supplied with power, the CPU 624 loads firmware (a control program described later) stored in the ROM 625 into the buffer RAM 622 and executes predetermined processing, thereby executing the host device 20. In response to a write command, a read command, and an erase command from, an access process for the corresponding area in the NAND flash memories M1 and M2 is executed with the controller B602, and a data transfer process through the buffer RAM 622 is controlled.

  The ROM 625 is a memory that stores a control program used by the CPU 624. The controller A601 is connected to the controller B602 via the NAND bus 611, and the CPU 624 executes various processes assuming that the controller B602 is the NAND flash memories M1 and M2. That is, when the CPU 624 receives a write command, a read command, and an erase command from the host device 20, the CPU 624 executes a process of transferring the write command, the read command, and the erase command to the controller B 602.

  As shown in FIG. 43, the controller B 602 includes a NAND_I / F 631, a buffer RAM 632, an ECC (Error Correcting Code) circuit 633, NAND_I / Fs 634 and 635, a CPU 636, a ROM 637, and a counter 638.

  The NAND_I / F 31 is connected to the NAND bus 12 and performs interface processing between the controller A2, the buffer RAM 32, and the CPU 35. The NAND_I / F 34 is connected to the NAND bus 13 and performs interface processing between the NAND flash memory 4, the ECC circuit 33, and the CPU 35.

  The buffer RAM 632 temporarily stores a certain amount of data (for example, one page) when the data input from the controller A601 is written to the NAND flash memories M1 and M2, and is read from the NAND flash memories M1 and M2. When outputting data to the controller A601, a certain amount of data is temporarily stored. The buffer RAM 632 is used as a work area for the CPU 636 and stores a control program, various tables, and the like.

  The ECC circuit 633 performs error correction processing of the write data based on the ECC data added to the write data written to the NAND flash memories M1 and M2, and ECC data for the read data read from the NAND flash memories M1 and M2. Perform additional processing.

  The CPU 636 controls access processing to the NAND flash memories M1 and M2. For example, when the memory card 600 is supplied with power, the CPU 636 loads firmware stored in the ROM 637 into the buffer RAM 632 and executes predetermined processing. In a predetermined process, the CPU 636 creates various tables, which will be described later, on the buffer RAM 632, receives a write command, a read command, and an erase command from the controller A601, and performs an access process for the corresponding area in the NAND flash memories M1 and M2. And execute data transfer processing through the buffer RAM 632.

  The ROM 637 is a memory that stores a control program used by the CPU 636, a write control program, and the like. Note that the controller B 602 is connected to the controller A 601 via the NAND bus 611, and the CPU 636 executes processing on the controller A 601 assuming that the NAND flash memories M1 and M2 are provided. That is, when the CPU 636 receives a write command, a read command, and an erase command from the controller A601, the CPU 636 executes an access process for the corresponding area in the NAND flash memories M1 and M2. Further, when the CPU 636 receives a write command and write data from the controller A 601, the CPU 636 executes a write process (see the flowchart shown in FIG. 45) according to the write control program.

  The counter 638 counts the number of rewrites n for each write logical block address LBA of the write data in the write process. The counter 638 counts up the number of rewrites n for each write logical block address LBA of the write data under the control of the CPU 636, and outputs the counted number of rewrites n to the CPU 636.

  FIG. 44 is a diagram showing a configuration related to the writing process of the controller B602. In FIG. 44, the same components as those in the controller B 602 shown in FIG. 43 are denoted by the same reference numerals. As shown in FIG. 44, the controller B 602 stores the logical block address LBA and physical block address PBA of the write data whose storage destination is changed for the NAND flash memories M1 and M2 based on the number of times of rewriting n in the buffer RAM 632. As areas, a first data LBA / PBA storage unit M1P and a second data LBA / PBA storage unit M2P are provided. The first data LBA / PBA storage unit M1P stores a rewrite count n, a logical block address LBA, and a physical block address PBA of data with a small rewrite count n (hereinafter referred to as first data) as a write logical block address block (hereinafter referred to as a “write logical block address block”). This is an area to be stored for each write LBA block). The second data LBA / PBA storage unit M2P stores, for each write LBA block, the number of times of rewriting of data having a large number of times of rewriting n (hereinafter referred to as second data), the logical block address LBA, and the physical block address PBA. It is an area.

  As shown in FIG. 44, the NAND flash memory M1 is a first data storage unit, and the NAND flash memory M2 is a second data storage unit. Accordingly, the logical block address LBA and physical block address PBA of the first data stored in the NAND flash memory M1 are stored in the first data LBA / PBA storage unit M1P, and the logical block address of the second data stored in the NAND flash memory M2 The LBA and physical block address PBA are stored in the second data LBA / PBA storage unit M2P.

  Next, the writing process executed in the controller B 602 will be described with reference to the flowchart shown in FIG.

  When the CPU 636 receives a write request command and write data from the host device 20 via the controller A 601 (step G1), the CPU 636 acquires a logical block address LBA included in the additional data added to the write request command. To do. Next, the CPU 636 confirms whether or not the acquired logical block address LBA is registered in the first data LBA / PBA storage unit M1P (step G2). When the CPU 636 confirms that it is registered in the first data LBA / PBA storage unit M1P (step G2: YES), the counter 638 indicates the number n of rewrites of the write logical block address (hereinafter referred to as write LBA). Count up (step G3).

  Next, the CPU 636 calculates a difference nd1 between the maximum value nmax and the minimum value nmin of the number of rewrites n in the write LBA block in which the write LBA is registered in the first data LBA / PBA storage unit M1P (step S1). G4). Next, the CPU 636 determines whether or not the difference nd1 is larger than a reference value N1 (a value for determining the number of times of rewriting the first data) (nd1> N1) (step G5). When the difference nd1 is larger than the reference value N1 (step G5: YES), the CPU 636 changes the registration destination of the write LBA from the first data LBA / PBA storage unit M1P to the second data LBA / PBA storage unit M2P ( Step G6).

  Next, the CPU 636 changes the storage destination from the NAND flash memory M1 to the NAND flash memory M2 using the write data as second data (step G7). At this time, the CPU 636 registers a write physical address (hereinafter referred to as a write PBA) in the NAND flash memory M2 storing the second data in the second data LBA / PBA storage unit M2P in association with the write LBA. (Step G7). Note that before the second data is stored in the NAND flash memory M2, the ECC circuit 633 performs an error correction process on the write data based on the ECC data added to the write data. Next, the CPU 636 resets the rewrite count n of the write LBA whose registration destination is changed in the first data LBA / PBA storage unit M1P (sets it to “0”) (step G8).

  When the difference nd1 is equal to or less than the reference value N1 (step G5: NO), the CPU 636 stores the write data, that is, the first data in the NAND flash memory M1 (step G9). At this time, the CPU 636 registers the write PBA in the NAND flash memory M1 storing the first data in the first data LBA / PBA storage unit M1P. Note that before the first data is stored in the NAND flash memory M1, the ECC circuit 633 performs an error correction process on the write data based on the ECC data added to the write data.

  In step G2, if the write LBA is not registered in the first data LBA / PBA storage unit M1P (step G2: NO), the write LBA is registered in the second data LBA / PBA storage unit M2P. ing. At this time, the CPU 636 counts up the number of rewrites n of the write LBA by the counter 638 (step G10).

  Next, the CPU 636 calculates a difference nd2 between the maximum value nmax and the minimum value nmin of the number of rewrites n in the write LBA block in which the write LBA is registered in the second data LBA / PBA storage unit M2P (step S3). G11). Next, the CPU 636 determines whether or not the difference nd2 is smaller than a reference value N2 (a value for determining the number of times of rewriting the second data) (nd2 <N1) (step G12). When the difference n2 is smaller than the reference value N2 (step G11: YES), the CPU 636 changes the registration destination of the write LBA from the second data LBA / PBA storage unit M2P to the first data LBA / PBA storage unit M1P ( Step G14).

  Next, the CPU 636 changes the storage destination from the NAND flash memory M2 to the NAND flash memory M1 using the write data as first data (step G15). At this time, the CPU 636 registers the write PBA in the NAND flash memory M1 storing the first data in the first data LBA / PBA storage unit M1P in association with the write LBA (step G15). Note that before the first data is stored in the NAND flash memory M1, the ECC circuit 633 performs an error correction process on the write data based on the ECC data added to the write data. Next, the CPU 636 resets the rewrite count n of the write LBA whose registration destination has been changed in the second data LBA / PBA storage unit M1P (sets it to “0”) (step G16).

  If the difference nd2 is greater than or equal to the reference value N2 (step G12: NO), the CPU 636 stores the write data, that is, the second data in the NAND flash memory M2 (step G13). At this time, the CPU 636 registers the write PBA in the NAND flash memory M2 storing the second data in the second data LBA / PBA storage unit M2P. Note that before the second data is stored in the NAND flash memory M2, the ECC circuit 633 performs an error correction process on the write data based on the ECC data added to the write data.

  As described above, in the memory card 600 according to the fifth embodiment, two NAND flash memories M1 and M2 having different storage capacities are connected to the controller B602, and the controller B602 sets the write data rewrite count n. Based on this, the storage location of the write data for the NAND flash memories M1 and M2 is changed. In this case, the first data with a small number of rewrites n is stored in the large capacity NAND flash memory M1, and the second data with a large number of rewrites n is stored in the small capacity NAND flash memory M2. In addition, when the difference nd1 of the number of rewrites n regarding the first data becomes larger than the reference value N1, the storage destination is changed from the NAND flash memory M1 to the NAND flash memory M2 as the second data. Furthermore, when the difference nd2 of the number of rewrites n regarding the second data becomes smaller than the reference value N2, the storage destination is changed from the NAND flash memory M2 to the NAND flash memory M1 as the first data.

  Therefore, when two NAND flash memories having different storage capacities are mounted in the memory card, the storage destination can be dynamically changed according to the number of rewrites of the write data received from the host device. For example, as write data received from the host device, large-capacity data (first data) with a small number of rewrites such as an application program or image data and small-capacity data (second data) with a large number of rewrites such as a file system are large. It becomes possible to distribute and store in the NAND flash memory M1 having a capacity and the NAND flash memory M2 having a small capacity. As a result, it is possible to provide a memory card that can effectively use two NAND flash memories M1 and M2 having different configurations.

  Furthermore, in the NAND flash memories M1 and M2 that write data in units of blocks, the data moving operation associated with the writing of the second data can be stopped in one NAND flash memory M2. As a result, it is possible to limit the influence of overhead associated with the rewriting operation of the second data, and the performance and reliability of the memory card can be improved.

  In the memory card 600 according to the fifth embodiment, the NAND flash memories M1 and M2 having different storage capacities are connected to the controller B602. However, the present invention is not limited to this configuration. For example, a configuration of a memory card 700 as shown in FIG. 46 may be adopted. In the memory card 700 shown in FIG. 46, the same components as those of the memory card 600 shown in FIG.

  In the memory card 700 shown in FIG. 46, the controller A601 is a controller chip 701, the controller B602 and the NAND flash memory M1 are mixedly mounted, and the NAND flash memory M2 is configured as a separate chip.

  With this configuration, when the generation (design rule) of the NAND flash memory M2 is changed, only the NAND flash memory M2 is replaced, and only the control program of the controller B602 is changed. It becomes possible to update the memory system without affecting the design of the entire card.

  The reference values N1 and N2 set in the flowchart shown in FIG. 45 are appropriately changed according to the specifications of the NAND flash memories M1 and M2, the type of data input from the host to which the memory card 600 is connected, and the like. May be. In short, the reference values N1 and N2 may be set so as to reduce the number of times the storage destination of the first data and the second data is changed between the NAND flash memories M1 and M2.

(Sixth embodiment)
In the sixth embodiment, two NAND flash memories having different configurations are connected to the controller B, and write data and additional data (parity data, etc.) input from the host device 20 are separated, and two NAND flash A case will be described in which write data and additional data storage destinations are allocated to the memory. FIG. 47 is a diagram showing a schematic configuration of a memory card 800 according to the sixth embodiment. In FIG. 47, the same components as those of the memory card 600 shown in FIG. 41 in the fifth embodiment are denoted by the same reference numerals.

  The memory card 800 shown in FIG. 47 is different from the memory card 600 shown in FIG. 41 in that the controller B 802 is used, and the connection between the other components is the same.

  The NAND flash memories M1 and M2 may be binary memories that store 1-bit data in one memory cell, or store more data (for example, 2 bits) than 1 bit in one memory cell. It may be a multi-valued memory. Here, a NAND flash memory will be described as an example of the nonvolatile memory. However, the nonvolatile memory is not limited to the NAND flash memory, and may be a NOR flash memory, for example. In addition, although an example in which two NAND flash memories M1 and M2 are connected has been shown, a plurality of NAND flash memories may be further connected.

  For example, the NAND flash memories M1 and M2 have different storage capacities (large capacity and small capacity), different numbers of bits of data to be stored (binary and multivalued), different design rules, Those having different configurations such as those having different block sizes (large block and small block) are used. In the fifth embodiment, a large capacity memory is used as the NAND flash memory M1, and a small capacity memory is used as the NAND flash memory M2.

The terms “logical block address” and “physical block address” used in the following description mean a logical address and a physical address assigned to the blocks in the NAND flash memories M1 and M2, respectively. Further, “logical address” and “physical address” mainly mean the logical address and physical address of the block itself, but may be an address corresponding to a unit of resolution smaller than the block unit. .

  As shown in FIG. 48, the controller B 802 includes a NAND_I / F 631, a buffer RAM 803, an ECC (Error Correcting Code) circuit 633, a data distribution unit 804, a NAND_I / F 634, 635, a CPU 805, a ROM 806, and an access path setting unit 807. Have. In FIG. 48, the same components as those of the controller B 602 shown in FIG. 42 in the fifth embodiment are denoted by the same reference numerals. The description of the components with the same reference numerals is omitted.

  The buffer RAM 803 temporarily stores a certain amount of data (for example, one page) when the data input from the controller A 601 is written to the NAND flash memories M1 and M2, and is read from the NAND flash memories M1 and M2. When outputting data to the controller A601, a certain amount of data is temporarily stored. The buffer RAM 803 is used as a work area for the CPU 805 and stores a control program, various tables, and the like. Further, the buffer RAM 803 has an actual data LBA / PBA storage unit M1P and an ECC data LBA / PBA storage unit M2P for managing the storage destinations of the actual data and ECC data distributed and stored in the NAND flash memories M1 and M2.

  The CPU 805 controls access processing to the NAND flash memories M1 and M2. For example, when the memory card 800 is supplied with power, the CPU 805 loads firmware stored in the ROM 806 into the buffer RAM 803 and executes predetermined processing. In a predetermined process, the CPU 805 creates various tables, which will be described later, on the buffer RAM 803, receives a write command, a read command, and an erase command from the controller A601 and performs an access process for the corresponding area in the NAND flash memories M1 and M2. And execute data transfer processing through the buffer RAM 803.

  The ROM 806 is a memory that stores a control program used by the CPU 805, a write control program, and the like. Note that the controller B 802 is connected to the controller A 601 via the NAND bus 611, and the CPU 636 executes processing with respect to the controller A 601 as the NAND flash memories M1 and M2. That is, when the CPU 805 receives a write command, a read command, and an erase command from the controller A 601, the CPU 805 executes an access process for the corresponding area in the NAND flash memories M1 and M2.

  Further, when the CPU 805 receives a write command and write data from the controller A 601, the CPU 805 executes a write process (see the flowchart shown in FIG. 50) according to the write control program. Furthermore, when receiving a read command from controller A601, CPU 805 executes a read process (see the flowchart shown in FIG. 51) according to the read control program. Further, when the CPU 805 receives an erase command from the controller A601, it executes an erase process (see the flowchart shown in FIG. 52) according to the erase control program.

  When the CPU 805 executes the writing process, the data distribution unit 804 executes an operation of distributing the storage destination of the actual data and the ECC data to the NAND flash memories M1 and M2. In addition, when the CPU 805 executes a read process, the data distribution unit 804 executes an operation of reading out corresponding real data and ECC data from the NAND flash memories M1 and M2.

  The access path setting unit 807 sets an access path for the host device 20 to directly access the NAND flash memories M1 and M2. As shown in FIG. 48, the access path setting unit 807 is connected between the first switch SW1 connected between the NAND_I / F 631 and the buffer RAM 803, and between the data distribution unit 804 and the NAND_I / Fs 634 and 635. It has a second switch SW2 and a third switch SW3. The first to third switches SW1 to SW3 switch the connection relationship between the NAND_I / F 631, the buffer RAM 803, the data distribution unit 804, and the NAND_I / Fs 634 and 635 in accordance with a switching control signal input from the CPU 805. By this switching, write data, read data, and the like can bypass the buffer RAM 803, the ECC circuit 33, and the data distribution unit 804, and a command issued by the host device 20 can be directly transmitted to the NAND flash memories M1 and M2.

  FIG. 49 is a diagram showing a configuration relating to the writing process of the controller B 802. 49, the same components as those in the controller B 802 shown in FIG. 48 are denoted by the same reference numerals. As shown in FIG. 49, the controller B 802 is an area in the buffer RAM 803 that stores the actual data that is allocated to the NAND flash memories M1 and M2, the logical block address LBA of the ECC data, and the physical block address PBA. A data LBA / PBA storage unit M1P and an ECC data LBA / PBA storage unit M2P are provided. The actual data LBA / PBA storage unit M1P includes the logical block address LBA of the storage destination of the data body (referred to as actual data in the sixth embodiment) separated from the write data requested to be written from the host device 20. This is an area for storing the physical block address PBA. The ECC data LBA / PBA storage unit M2P is an area for storing a logical block address LBA and a physical block address PBA of a storage destination of ECC data (additional data) added to actual data.

  As shown in FIG. 49, the NAND flash memory M1 is an actual data storage unit, and the NAND flash memory M2 is an ECC data storage unit. Accordingly, the logical block address LBA and physical block address PBA of the actual data stored in the NAND flash memory M1 are stored in the actual data LBA / PBA storage unit M1P, and the logical block address LBA and the physical block of the ECC data stored in the NAND flash memory M2 are stored. The block address PBA is stored in the ECC data LBA / PBA storage unit M2P. The actual data LBA / PBA storage unit M1P stores erasure information indicating the erasure state of the actual data in association with each other. The ECC data LBA / PBA storage unit M2P stores erasure information indicating the erasure state of the ECC data in association with each other.

  Next, the writing process executed in the controller B 802 will be described with reference to the flowchart shown in FIG.

  When the CPU 805 receives a write request command and write data from the host device 20 via the controller A 601 (step H1), the write logical block address LBA included in the additional data added to the write request command. ECC data added to the write data is extracted (step H2). By this process, the actual data and the ECC data are separated.

  Next, the CPU 805 distributes and stores the actual data and ECC data separated in the order of the write logical block addresses LBA in the NAND flash memories M1 and M2 (step H3). In this processing, the data distribution unit 804 distributes and stores the actual data and the ECC data separated from the CPU 805 in the NAND flash memories M1 and M2 in the order of the write logical block address LBA input from the CPU 805. Note that before the actual data is stored in the NAND flash memory M1, the ECC circuit 633 performs an error correction process on the actual data based on the ECC data added to the actual data.

  Next, the CPU 805 stores the logical block address LBA and physical block address PBA in the NAND flash memory M1 storing actual data in the actual data LBA / PBA storage unit M1P, and stores the logical data in the NAND flash memory M2 storing ECC data. The block address LBA and the physical block address PBA are stored in the ECC data LBA / PBA storage unit M2P (step H4).

  Next, the CPU 805 notifies the host device 20 of the completion of the writing process (step H5). This write processing completion notification is sent from the controller B 802 to the host device 20 through the controller A 601.

  Next, the reading process executed in the controller B 802 will be described with reference to the flowchart shown in FIG.

  When the CPU 805 receives a read request command from the host device 20 via the controller A 601 (step I1), the CPU 805 refers to the physical block address PBA included in the read request command (step I2). Next, based on the physical block address PBA referred from the read request command, the CPU 805 refers to the actual data LBA / PBA storage unit M1P and acquires the logical block address LBA and the physical block address PBA of the read target actual data (step). I3).

  Next, the CPU 805 acquires the logical block address LBA and the physical block address PBA of the ECC data to be read from the ECC data LBA / PBA storage unit M2P based on the physical block address PBA referred from the read request command (step I4).

  Next, the CPU 805 reads the actual data from the area in the NAND flash memory M1 corresponding to the logical block address LBA of the actual data acquired in step I3 and the physical block address PBA, and the logical block address LBA of the ECC data acquired in step I4. ECC data is read from the area in the NAND flash memory M2 corresponding to the physical block address PBA and returned to the host device 20 (step I5). In this processing, the data allocating unit 804 receives the actual data and ECC data from each area in the NAND flash memories M1 and M2 based on each logical block address LBA and each physical block address PBA of the actual data and ECC data input from the CPU 805. Is output to the ECC circuit 633. The ECC circuit 633 adds ECC data to the input actual data and outputs it to the CPU 805. Then, the read target data is returned from the controller B 802 to the host device 20 through the controller A 601.

  Next, the erasing process executed in the controller B 802 will be described with reference to the flowchart shown in FIG.

  When the CPU 805 receives an erase request command from the host device 20 via the controller A 601 (step J1), the CPU 805 refers to the physical block address PBA included in the erase request command (step J2).

  Next, in step J3, the CPU 805 stores the storage area of the corresponding logical block address LBA and physical block address PBA of the actual data in the actual data LBA / PBA storage unit M1P based on the physical block address PBA referenced from the erase request command. Stores erasure information indicating the erasure state. Further, in step J3, the CPU 805 stores the corresponding ECC data logical block address LBA and physical block address PBA in the ECC data LBA / PBA storage unit M2P based on the physical block address PBA referenced from the erase request command. Erase information indicating the erase state is stored.

  Next, the CPU 805 does not erase the actual data and ECC data in the NAND flash memories M1 and M2 corresponding to the physical block address PBA requested to be erased, but notifies the host device 20 that the erase has been performed (step J4). ). This deletion notification is sent from the controller B 802 to the host device 20 through the controller A 601.

  As described above, in the memory card 800 according to the sixth embodiment, the two NAND flash memories M1 and M2 having different storage capacities are connected to the controller B802, and the host device is connected by the controller B802 and the data distribution unit 804. The write data requested to be written from 20 is separated into actual data and ECC data, and distributed and stored in the NAND flash memories M1 and M2.

  Therefore, when two NAND flash memories M1 and M2 having different storage capacities are mounted in the memory card, the write data received from the host device is separated into actual data and ECC data, and distributed to the NAND flash memories M1 and M2. It is possible to go ahead. As a result, it is possible to provide a memory card that can effectively use two NAND flash memories M1 and M2 having different configurations.

  Further, the memory card 800 according to the sixth embodiment is configured to have the access path setting unit 807 in the controller B 802. Therefore, as shown in the second embodiment, when the memory card 800 is tested for shipping, the host device 20 can be electrically connected to the memory card 800 as a tester. In this case, the controller B 802 converts the address received from the host device 20, uses the converted address to access the NAND flash memories M1 and M2, and uses the address received from the host device 20 to perform NAND. It becomes possible to operate in the second mode in which the flash memories M1 and M2 are directly accessed. In addition, the controller B 802 executes switching control for switching between the first mode and the second mode in accordance with an operation mode switching command received from the host device 20.

  As shown in the second embodiment, the host device 20 can individually test the controller B 802 and the NAND flash memories M1 and M2 in the memory card 800 during the shipping test. Further, the controller B 802 is configured to control the transition operation for shifting from the first mode to the second mode and the return operation for returning from the second mode to the first mode in accordance with a command received from the host device 20. The second mode can be realized without increasing the number of external connection pins of the memory card 800.

  When executing the NAND unit test, the host device 20 issues a command sequence for instructing a migration operation after the memory card 800 is powered on. The controller B 802 sets the operation mode to the second mode by receiving the command sequence, and maintains the second mode until a command sequence instructing the return operation is issued from the host device 20. By using the command sequence in this way, it is possible to avoid that the controller B 802 performs an unintended return operation during the second mode.

  48 shows a case where the access path setting unit 807 sets an access path by a command sent from the host device 20 to the memory card 800. The configuration is not limited to this configuration. For example, a configuration in which the access path setting unit 2022 detects power-on and automatically sets an access path as in the memory card 200 illustrated in FIG. You may make it apply. In this case, the NAND unit test can be executed even if there is an abnormality in the controller B802 by automatically setting the second mode immediately after the power is turned on.

  In the memory card 800 according to the sixth embodiment, NAND flash memories M1 and M2 having different storage capacities are connected to the controller B 802. However, the present invention is not limited to this configuration. For example, a memory card 900 as shown in FIG. 53 may be configured. In the memory card 900 shown in FIG. 53, the same components as those of the memory card 800 shown in FIG.

  In the memory card 900 shown in FIG. 53, the controller A601 is a controller chip 901, the NAND flash memory M1 is connected to the controller A601 through the NAND bus 613, and the controller B802 and the NAND flash memory M2 are mixedly mounted as a memory chip 902. It is composed.

  With this configuration, when the generation (design rule) of the NAND flash memory M1 is changed, only the NAND flash memory M1 is replaced and only the control program of the controller A601 is changed. It becomes possible to update the memory system without affecting the design of the entire card. In addition, when the generation (design rule) of the NAND flash memory M2 is changed, it is possible to cope only by exchanging only the memory chip 902 and changing the control program of the controller B802, which affects the design of the entire memory card. It becomes possible to update the memory system without giving.

(Seventh embodiment)
In the seventh embodiment, a configuration when the memory card 600 shown in the fifth embodiment is packaged is exemplified. FIG. 54 is a cross-sectional view showing a configuration when the memory card 600 according to the seventh embodiment is packaged. In FIG. 54, the same components as those of the memory card 600 shown in FIG. 41 in the fifth embodiment are denoted by the same reference numerals.

  In FIG. 54, reference numeral 650 denotes a substrate. On the substrate 650, the NAND flash memories M1 and M2 are stacked via an interlayer film 651. On the NAND flash memory M2, the controller A601 and the controller B602 are formed via an interlayer film 651, respectively. In the substrate 650, the NAND flash memories M1 and M2, and the controller B602, pads 652 to 655 for connecting the bonding wires 658 are formed on the upper surfaces of the left end portions in the drawing. Also, pads 656 and 657 for connecting bonding wires 658 are formed on the upper surface of the right end portion of the controller B602 in the drawing and the upper surface of the left end portion of the controller A601 in the drawing, respectively. Further, external connection pins 659 corresponding to the first to eighteenth pins P1 to P18 shown in FIG. 25 are formed on the lower surface side of the left end portion of the substrate 650 in the drawing.

  FIG. 55 is a cross-sectional view showing another configuration when the memory card 600 according to the seventh embodiment is packaged. In FIG. 55, the same components as those of the memory card 600 shown in FIG. 41 in the fifth embodiment and the same components as those shown in FIG. The description is omitted.

  In FIG. 55, a controller B 602 is formed on the NAND flash memory M 2 via an interlayer film 651. On the controller B 602, a controller A 601 is formed via an interlayer film 651. In the substrate 650, the NAND flash memories M1 and M2, the controller B601, and the controller A601, pads 652 to 656 for connecting bonding wires 658 are formed on the upper surfaces of the left end portions in the drawing.

  The cross-sectional views of the packages shown in FIGS. 54 and 55 exemplify the case where the controller B 602 and the controller A 603 are stacked on the NAND flash memory M2. 54 and 55, the controller B602 and controller A601 are stacked on the NAND flash memory M2, and after bonding wires 658 are connected, the whole except the external connection pins 659 is sealed with resin or the like. Is done.

  As described above, the stacked structure allows the memory card 600 to be formed with the size of the substrate 650 on which the NAND flash memories M1 and M2 can be substantially mounted. The size of the package as the memory card 600 Can be reduced.

  FIG. 56 is a cross-sectional view showing another configuration when the memory card according to the seventh embodiment is packaged. In FIG. 56, the same components as those of the memory card 600 shown in FIG. 41 in the fifth embodiment and the same components as those shown in FIG. The description is omitted.

  In FIG. 56, on the substrate 650 of the memory card 600, a NAND flash memory M1, a controller B602, and a controller A601 are respectively formed via an interlayer film 651. On the NAND flash memory M1, a NAND flash memory M2 is formed via an interlayer film 651. A pad 655 for connecting a bonding wire 658 is formed on the upper surface of the left end portion of the controller A601 in the drawing. Further, pads 656 and 657 for connecting the bonding wires 658 are formed on the upper surface of the right end portion of the controller A601 in the drawing and the upper surface of the left end portion of the controller B602 in the drawing, respectively. Also, pads 661 and 662 for connecting bonding wires 658 are formed on the upper surface of the right end portion of the controller B601 in the drawing and the upper surface of the left end portion of the NAND flash memory M1 in the drawing, respectively. Further, a pad 663 for connecting the bonding wire 658 is formed on the upper surface of the left end portion of the NAND flash memory M2 in the drawing.

  The memory card 600 shown in FIG. 56 includes NAND flash memories M1 and M2, a controller B602, and a controller A601 formed on a substrate 650. After the bonding wires 658 are connected, the whole except for the external connection pins 659 is made of resin or the like. Sealed.

  The cross-sectional view of the package shown in FIG. 56 exemplifies a case where the NAND flash memories M1 and M2, the controller B602, and the controller A601 are arranged on the substrate 650. With such a structure, when changing the generation of the NAND flash memories M1 and M2, the NAND flash memory M1 and the controller B602 can be easily replaced.

  The configurations of the packages shown in FIGS. 54 to 56 are shown as corresponding to the memory card 600, but other than the memory card, for example, a multi-chip package (MCM), a system-in-package (SiP) ) And the like.

(Eighth embodiment)
The eighth embodiment exemplifies a configuration when the package exemplified in the seventh embodiment is applied as a USB (Universal Serial Bus) memory. FIG. 57 is a cross-sectional view showing the configuration of the USB memory according to the eighth embodiment. 57, the same reference numerals are given to the same components as those of the memory card package shown in FIG. 54 in the seventh embodiment, and the description thereof is omitted.

  In the USB memory 1000 shown in FIG. 57, reference numeral 1001 denotes a circuit board. On the upper surface side of the circuit board 1001, an electronic component 1002 and a control chip 1003 such as a USB controller are mounted, and a conductor layer 1004 serving as an input / output terminal of a USB connector is formed. The packaged memory card 600 shown in FIG. 54 is mounted on the lower surface side of the circuit board 1001. Reference numeral 1005 denotes an outer case of the USB memory 1000.

  In the USB memory 1000 shown in FIG. 57, the memory card 600 is mounted on the circuit board 1001 as it is, so that the USB memory can be easily manufactured and the use range of the memory card 600 can be expanded. . In addition, when the generation of the NAND flash memories M1 and M2 in the USB memory 1000 is changed, it can be mounted using the memory card 600 manufactured according to the generation, and the specification changes as the USB memory. Will also be easier.

  In the eighth embodiment, the case where the memory card 600 shown in FIG. 54 is applied to the USB memory is illustrated. However, the present invention is not limited to this, and the memory card 600 shown in FIG. The memory card 600 shown in FIG. 56 may be applied.

  In the fifth to eighth embodiments, the memory system of the present invention is applied to a memory card and a USB memory. However, the present invention is not limited to these. For example, the present invention can be applied to various electronic devices such as a digital camera, a digital video camera, and a personal computer that are equipped with a plurality of NAND flash memories and can be used by an application program or the like.

It is a figure which shows schematic structure of the memory card based on the 1st Embodiment of this invention. It is a figure which shows schematic structure of the controller A which concerns on the 1st Embodiment of this invention. It is a figure which shows schematic structure of the controller B which concerns on the 1st Embodiment of this invention. It is a figure which shows the difference in the data arrangement of the flash memory which the host apparatus which concerns on the 1st Embodiment of this invention assumes, and the NAND flash memory actually used. It is a figure which shows each communication hierarchy of the host side system which concerns on the 1st Embodiment of this invention, and a memory card (large block card). (A) according to the first embodiment of the present invention is a diagram showing a format of a command sent from the host device side, and (b) is a diagram showing a command format processed inside the memory card. FIG. 5 is a diagram showing a comparison between a block writing operation assumed by the host device according to the first embodiment of the present invention and a writing process actually performed on the memory card (large block card) side. It is a figure which shows the block format (for 256 kByte physical block) of the flash memory in the large block card based on the 1st Embodiment of this invention. It is a figure which shows the various tables produced on the buffer RAM in the controller B which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of the creation process of the various tables which concern on the 1st Embodiment of this invention. It is a flowchart which shows the flow of the process with respect to the write access which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the detail of the data writing process in step B3 of FIG. 11 which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the process of step C1 of FIG. 12 which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the process of step C2 of FIG. 12 which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the process of step C3 of FIG. 12 which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the process of step C4 of FIG. 12 which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of the process with respect to the read access which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the flow of a process with respect to the erase access which concerns on the 1st Embodiment of this invention. 4 is a timing chart illustrating an example of signals input to and output from an I / O pin and an R / B pin when the host device writes to the memory card according to the first embodiment of the present invention. 4 is a timing chart showing an example of signals input to and output from the I / O pin and the R / B pin when the controller B writes to the nonvolatile memory in the memory card according to the first embodiment of the present invention. is there. It is a figure which shows typically the usage method of the memory card based on the 1st Embodiment of this invention. It is a figure which shows schematic structure of the other memory card based on the 1st Embodiment of this invention. It is a figure which shows schematic structure of the memory card based on the 2nd Embodiment of this invention. It is a figure which shows schematic structure of the controller B which concerns on the 2nd Embodiment of this invention. It is a figure which shows the example of arrangement | positioning of the external connection pin of the memory card based on the 2nd Embodiment of this invention. It is a figure which shows the example of a signal allocated to each external connection pin of the memory card based on the 2nd Embodiment of this invention. It is a figure which shows the difference in the data arrangement of the flash memory which the host apparatus which concerns on the 2nd Embodiment of this invention assumes, and the NAND flash memory actually used. It is a figure which shows each function structural example of the host apparatus which concerns on the 2nd Embodiment of this invention, and the controller B in a memory card. (A) according to the second embodiment of the present invention is a diagram showing a format of a command sent from the host device side, and (b) is a diagram showing a command format processed inside the memory card. (A) according to the second embodiment of the present invention is a block write operation assumed by the host device, and (b) is compared with a write process actually performed by the memory card (large block card) side. FIG. It is a figure which shows the block format (for 256 kByte physical block) of the flash memory in the large block card based on the 2nd Embodiment of this invention. 10 is a timing chart illustrating an example of signals input to and output from an I / O pin and an R / B pin when a host device writes to a memory card according to a second embodiment of the present invention. 6 is a timing chart showing an example of signals input to and output from the I / O pin and the R / B pin when the controller B performs writing to the nonvolatile memory in the memory card according to the second embodiment of the present invention. is there. It is a flowchart which shows the test operation example in the memory card based on the 2nd Embodiment of this invention. It is a figure which shows schematic structure of the other controller B which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the other test operation example in the memory card based on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure at the time of packaging the memory card based on the 3rd Embodiment of this invention. It is sectional drawing which shows the other structure at the time of packaging the memory card based on the 3rd Embodiment of this invention. It is sectional drawing which shows the other structure at the time of packaging the memory card based on the 3rd Embodiment of this invention. It is sectional drawing which shows USB memory schematic structure to which the memory card based on the 4th Embodiment of this invention is applied. It is a figure which shows schematic structure of the memory card based on the 5th Embodiment of this invention. It is a figure which shows schematic structure of the controller A which concerns on the 5th Embodiment of this invention. It is a figure which shows schematic structure of the controller B which concerns on the 5th Embodiment of this invention. It is a figure which shows the structure in connection with the write-in process of the controller B which concerns on the 5th Embodiment of this invention. It is a flowchart which shows the write-in process performed in the controller B which concerns on the 5th Embodiment of this invention. It is a figure which shows schematic structure of the other memory card based on the 5th Embodiment of this invention. It is a figure which shows schematic structure of the memory card based on the 6th Embodiment of this invention. It is a figure which shows schematic structure of the controller B which concerns on the 6th Embodiment of this invention. It is a figure which shows the structure in connection with the write-in process of the controller B which concerns on the 6th Embodiment of this invention. It is a flowchart which shows the write-in process performed in the controller B which concerns on the 6th Embodiment of this invention. It is a flowchart which shows the read-out process performed in the controller B which concerns on the 6th Embodiment of this invention. It is a flowchart which shows the erasure | elimination process performed in the controller B which concerns on the 6th Embodiment of this invention. It is a figure which shows schematic structure of the other memory card based on the 6th Embodiment of this invention. It is sectional drawing which shows the structure at the time of packaging the memory card based on the 7th Embodiment of this invention. It is sectional drawing which shows the other structure at the time of packaging the memory card based on the 7th Embodiment of this invention. It is sectional drawing which shows the other structure at the time of packaging the memory card based on the 7th Embodiment of this invention. It is sectional drawing which shows USB memory schematic structure to which the memory card based on the 8th Embodiment of this invention is applied.

Explanation of symbols

1,200,600,700,800,900 ... memory card, 2,601 ... controller A, 3,602,802 ... controller B, 4, M1, M2 ... NAND flash memory, 11 ... host bus, 12,13, 611 to 613: NAND bus, 20: host device, 31, 34, 634, 635 ... NAND_I / F, 35, 624, 636, 805 ... CPU, 2022, 807 ... access path setting unit, M1P: first data LBA PBA storage unit, actual data LBA / PBA storage unit, M2P... Second data LBA / PBA storage unit, ECC data LBA / PBA storage unit.

Claims (8)

A first controller connected to the host device;
A second controller connected to the first controller and connected to a non-volatile memory;
The nonvolatile memory connected to the second controller,
The memory system, wherein the second controller exchanges data between the first controller and the nonvolatile memory.   The second controller has a first memory interface connected to the first controller, and a second memory interface connected to the nonvolatile memory, and the first memory interface and the second memory interface 2. The memory system according to claim 1, wherein the memory interface exchanges the same control signal between the first controller and the nonvolatile memory.   The memory system according to claim 1, wherein the first controller and the second controller are configured by individual semiconductor elements. The second controller has a path for directly connecting the first memory interface and the second memory interface;
4. The memory system according to claim 1, wherein the second controller and the non-volatile memory are sealed in the same semiconductor package. A circuit board having a USB terminal serving as an input / output terminal of a USB connector at one end is provided.
5. The memory system according to claim 4, wherein a semiconductor package enclosing the second controller and the nonvolatile memory is mounted on the circuit board. A first controller connected to the host device;
A second controller connected to the first controller and connected to a plurality of nonvolatile memories;
A plurality of nonvolatile memories connected to the second controller;
The memory system, wherein the second controller exchanges data between the first controller and the plurality of nonvolatile memories.   The second controller has a counter that counts the number of rewrites of write data input from the host device, and the write to the plurality of nonvolatile memories is performed based on the number of rewrites counted by the counter. 7. The memory system according to claim 6, wherein a data storage destination is changed.   The second controller separates write data input from the host device and additional data of the write data, and allocates storage destinations of the write data and the additional data to the plurality of nonvolatile memories. 7. The memory system according to claim 6, further comprising a data distribution unit.

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