JP2009099824A - Thin film transistor device, display device and manufacturing method thereof - Google Patents

Abstract

A thin film transistor device capable of improving characteristics of a TFT is provided.
A thin film transistor device according to the present invention includes a semiconductor layer formed over a substrate, a conductive film formed over the semiconductor layer and at least in a region serving as a storage capacitor, and formed over the semiconductor layer and the conductive film. Formed on the gate insulating film, the upper electrode formed on the gate insulating film at a position facing the conductive film, the gate electrode formed on the position facing the channel region, and formed on the gate electrode and the upper electrode A first interlayer insulating film, a source electrode formed on the first interlayer insulating film and connected to the source region via the first contact hole, and formed on the first interlayer insulating film via the second contact hole A drain electrode connected to the drain region, and an angle formed between the side surface of the end portion of the semiconductor layer and the bottom surface of the semiconductor layer is 20 ° to 50 °, and the side surface of the end portion of the conductive film The angle between the bottom surface of the conductive film is less than 50 degrees than 0 degrees.
[Selection] Figure 2

Description

  The present invention relates to a thin film transistor device, a display device, and a manufacturing method thereof, and more particularly, to an active matrix display device having a thin film transistor (TFT) and a storage capacitor.

  In recent years, thin display devices such as liquid crystal display devices using TFTs have been developed. A switch element such as a TFT is formed in the pixel region of such a display device. For example, a MOS (Metal Oxide Semiconductor) TFT is widely used. The MOS structure TFT has an inverted stagger type or a top gate type. In addition, semiconductor films using a silicon film or the like include an amorphous semiconductor film and a polycrystalline semiconductor film. The structure of these TFTs and the type of semiconductor film are appropriately selected depending on the application and performance of the display device. For example, in a display device having a medium-sized or large-sized panel, an a-Si TFT (a-Si: amorphous silicon) using a-Si which is an amorphous semiconductor film is used. On the other hand, in a display device having a small panel, a TFT using a polycrystalline semiconductor film (LTPS TFT: Low Temperature Poly Silicon TFT) is often used.

  When the LTPS TFT is used in the display area of the display device, the capacity of the switching transistor for each pixel can be reduced. In addition, the area of the storage capacitor connected to the drain side can be reduced. For this reason, a display device using LTPS TFTs can have high resolution and a high aperture ratio. Furthermore, by using LTPS TFTs not only in the display area but also in circuits around the display area, ICs and IC mounting substrates can be reduced. Therefore, the peripheral circuit of the display device can be simplified and a highly reliable display device with a narrow frame can be realized. From the above, LTPS TFTs are widely used in high-resolution liquid crystal display devices such as QVGA (number of pixels: 240 × 320) or VGA (number of pixels: 480 × 640) used for small panels such as cellular phones.

  Hereinafter, a method for forming a polycrystalline semiconductor film used for the LTPS TFT will be described. First, an amorphous semiconductor film is formed on a silicon oxide film or the like formed as a base film on a substrate. Then, laser light is irradiated. As a result, the amorphous semiconductor film is polycrystallized to form a polycrystalline semiconductor film. Thus, after forming the polycrystalline semiconductor film, a TFT is formed (see, for example, Patent Documents 1 and 2). Hereinafter, a method for forming a TFT after forming a polycrystalline semiconductor film will be described. First, a gate insulating film made of silicon oxide or the like is formed on a polycrystalline semiconductor film formed on a substrate. A gate electrode is formed on the gate insulating film. Then, using the gate electrode as a mask, an impurity such as phosphorus or boron is implanted into the polycrystalline semiconductor film through the gate insulating film to form source / drain regions. Thereafter, an interlayer insulating film is formed over the gate electrode and the gate insulating film. Next, contact holes are formed in the gate insulating film and the interlayer insulating film so as to reach the source / drain regions. Then, a metal film is formed on the interlayer insulating film, and a source electrode and a drain electrode connected to the source / drain region through contact holes are formed. Next, a pixel electrode connected to the drain electrode, a self-luminous element, or the like is formed. Thus, an active matrix display device is formed.

  The LTPS TFT used in the active matrix display device described above is a top gate type TFT. In the top gate type TFT, a silicon oxide film having a very thin film thickness of about 100 nm is formed as a gate insulating film between a gate electrode and a polycrystalline semiconductor film to form a MOS structure. Since the silicon oxide film has a very thin film thickness, the area of the storage capacitor can be reduced by using it as a dielectric insulating film of the storage capacitor formed simultaneously with the TFT. Here, an example of a method for manufacturing a display device using LTPS TFTs will be described. In a display device using an LTPS TFT, for example, as described in Patent Document 3, an impurity is implanted into a region that is a polycrystalline semiconductor film and serves as a lower electrode of a storage capacitor. It is common to make resistance.

  Meanwhile, the structure of the storage capacitor formed for each pixel of the active matrix display device is different between the LTPS TFT and the a-Si TFT. In the storage capacitor formed at the same time as the LTPS TFT, the lower electrode of the storage capacitor is a polycrystalline semiconductor film in which impurities are implanted to reduce the resistance. Further, a gate insulating film having a very thin film thickness is used as the dielectric insulating film of the storage capacitor. On the other hand, in a storage capacitor formed at the same time as an a-Si TFT, a metal film used for a gate wiring and a source wiring is often arranged to face each other with a gate insulating film having a thickness of about 300 to 700 nm. That is, the LTPS TFT has a smaller insulating film thickness than the a-Si TFT. For this reason, when a storage capacitor having the same capacity is formed in the a-Si TFT and the LTPS TFT, the area of the required storage capacitor can be made smaller in the LTPS TFT.

  However, in the case of LTPS TFT, since a polycrystalline semiconductor film is used as a lower electrode of a storage capacitor instead of a metal film, there is a problem that the polycrystalline semiconductor film has a higher resistance than the metal film. As described above, the storage capacitor formed at the same time as the LTPS TFT is reduced in resistance by injecting impurities such as phosphorus into the polycrystalline semiconductor film, but is reduced to about several kΩ / □ at most in terms of sheet resistance. I can't. For this reason, for example, when the polycrystalline semiconductor film is routed from the TFT to the storage capacitor, there is a problem that the wiring becomes a high resistance wiring. In addition, in a polycrystalline semiconductor film, when the resistance of the polycrystalline semiconductor film cannot be sufficiently reduced, a storage capacitor using the polycrystalline semiconductor film as one electrode has voltage dependency. In this case, it is difficult to obtain a desired capacitance value corresponding to the thickness of the gate insulating film. As a result, the display quality of an active matrix display device using LTPS TFTs is degraded.

  In order to solve such a problem, for example, a technique of forming a conductive film such as a metal film under the polycrystalline semiconductor film can be considered. Patent Document 4 discloses a liquid crystal display panel in which a conductive film such as a metal film is formed under a polycrystalline semiconductor film. In the liquid crystal display panel described in Patent Document 4, a metal electrode is formed on a glass substrate, and a polycrystalline silicon layer is formed on the metal electrode. A silicon oxide film and an upper electrode are formed. A storage capacitor is formed by the metal electrode, the silicon oxide film, and the upper electrode.

Here, it is described in Patent Document 5 that the shape of the end portion greatly affects the characteristics of the TFT at the end portion of the polycrystalline semiconductor film. In the thin film transistor described in Patent Document 5, the end portion of the semiconductor film is tapered. When the taper angle of the semiconductor film is larger than a certain value, a breakdown voltage failure occurs. On the other hand, when the taper angle of the semiconductor film is smaller than a certain value, a state in which a parasitic transistor is formed in the semiconductor film is obtained. For this reason, it is preferable to make the shape of the edge part of a semiconductor film into the taper shape which has a desired taper angle.
JP 2003-75870 A (FIG. 1) Japanese Patent Laid-Open No. 11-261076 (FIG. 1) JP-A-10-177163 (FIG. 10) Japanese Patent Laid-Open No. 2000-206566 (FIG. 1) Japanese Patent Laying-Open No. 2005-57042 (FIG. 8), (FIG. 9)

  However, in the liquid crystal display panel described in Patent Document 4, for example, when polycrystalline silicon is formed by high-temperature treatment using laser light or the like, ions of the conductive film formed under the polycrystalline silicon layer are thermally diffused. May occur. Thereby, the characteristic of TFT formed using a polycrystalline silicon layer falls. In the capacitor element in the thin film transistor described in Patent Document 5, the lower electrode is formed of a polysilicon film. For this reason, there exists a problem that a capacitive element has voltage dependence and it is difficult to obtain a desired voltage value.

  The present invention has been made to solve such a problem, and provides a thin film transistor device capable of forming a storage capacitor with reduced voltage dependency and improving gate insulating film resistance and TFT characteristics. For the purpose.

  In order to solve the above-described problems, a thin film transistor device according to the present invention is formed on a substrate and has a semiconductor layer having a source region, a drain region, and a channel region, and at least a storage capacitor on the semiconductor layer. A conductive film formed in a region, a gate insulating film formed on the semiconductor layer and the conductive film, and the storage capacitor formed on the gate insulating film at a position facing the conductive film. An upper electrode; a gate electrode formed at a position facing the channel region; a first interlayer insulating film formed on the gate electrode, the upper electrode, and the gate insulating film; and the first interlayer insulation. A source electrode formed on the film and connected to the source region via the first contact hole; and a second contact hole formed on the first interlayer insulating film. A drain electrode connected to the drain region, and an angle formed between a side surface of the end portion of the semiconductor layer and a bottom surface of the semiconductor layer is 20 degrees or more and 50 degrees or less, and an end portion of the conductive film An angle formed between the side surface of the conductive film and the bottom surface of the conductive film is greater than 0 degree and equal to or less than 50 degrees.

  In order to solve the above-described problem, a method of manufacturing a thin film transistor device according to the present invention includes a step of forming a semiconductor layer having a source region, a drain region, and a channel region on a substrate, and at least on the semiconductor layer, Forming a conductive film in a region to be a storage capacitor; an angle formed between a side surface of the end portion of the semiconductor layer and a bottom surface of the semiconductor layer; Forming an angle between the bottom surface of the conductive film and the bottom surface of the conductive film so as to be greater than 0 degree and less than 50 degrees; forming a gate insulating film on the semiconductor layer and the conductive film; and forming a gate electrode on the gate insulating film And a step of forming an upper electrode of a storage capacitor, a step of forming a first interlayer insulating film on the gate electrode, the upper electrode, and the gate insulating film, and a step of forming on the first interlayer insulating film, Forming a source electrode connected to the source region through a first contact hole formed by etching the gate insulating film and the first interlayer insulating film; and forming the source electrode on the first interlayer insulating film. And forming a drain electrode connected to the drain region through a second contact hole formed by etching the gate insulating film and the first interlayer insulating film.

  According to the thin film transistor device of the present invention, it is possible to form a storage capacitor with reduced voltage dependency, and to improve gate insulating film resistance and TFT characteristics.

Embodiment 1 FIG.
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a liquid crystal display device having a thin film transistor device, but a flat display device (flat panel display) such as an organic EL display device can also be used.

  The display device according to this embodiment has a TFT substrate. The TFT substrate is, for example, a TFT array substrate. FIG. 1 is a schematic plan view showing a configuration of a TFT array substrate used in the display device according to the present embodiment. The TFT array substrate 1 according to the present embodiment has a display area 2 and a frame area 3 provided so as to surround the display area 2. In the display area 2, a plurality of gate lines (scanning signal lines) 4 and a plurality of source lines (display signal lines) 5 are formed. The plurality of gate lines 4 are provided in parallel. Similarly, the plurality of source lines 5 are provided in parallel. The gate wiring 4 and the source wiring 5 are orthogonal to each other. A region surrounded by the gate wiring 4 and the source wiring 5 is a pixel 6. That is, on the TFT array substrate 1, the pixels 6 are arranged in a matrix. A storage capacitor line 52 a is formed so as to be parallel to the gate line 4 and cross the pixel 6.

  Further, a scanning signal driving circuit 7 and a display signal driving circuit 8 are provided in the frame region 3 of the TFT array substrate 1. The gate line 4 and the source line 5 are each extended from the display area 2 to the frame area 3. The gate wiring 4 is connected to the scanning signal driving circuit 7 at the end of the TFT array substrate 1. In the vicinity of the scanning signal driving circuit 7, an external wiring 9 is formed and connected to the scanning signal driving circuit 7. The source line 5 is connected to the display signal driving circuit 8 at the end of the TFT array substrate 1. Further, an external wiring 10 is formed in the vicinity of the display signal driving circuit 8 and connected to the display signal driving circuit 8. The external wirings 9 and 10 are made of a wiring board such as an FPC (flexible printed circuit).

  Various signals are supplied from the outside to the scanning signal driving circuit 7 and the display signal driving circuit 8 through the external wiring. The scanning signal driving circuit 7 supplies a gate signal (scanning signal) to the gate wiring 4 based on a control signal supplied from the outside. The gate wiring 4 is sequentially selected by this gate signal. The display signal drive circuit 8 supplies a display signal to the source line 5 based on a control signal or display data supplied from the outside. As a result, a display voltage corresponding to the display data can be supplied to each pixel 6.

  In the pixel 6, at least one TFT 51 and a storage capacitor 52 connected to the TFT 51 are formed. The TFT 51 is formed in the vicinity where the gate line 4 and the source line 5 intersect. The TTFT 51 serves as a switching element for supplying a display voltage to the pixel electrode. That is, the TFT 51 serving as a switching element is turned on by a gate signal supplied from the gate wiring 4. Thereby, a display voltage is applied from the source line 5 to a pixel electrode (not shown) connected to the drain electrode of the TFT 51. An electric field corresponding to the display voltage is generated between the pixel electrode and a counter electrode (not shown) formed on a counter substrate, which will be described later, disposed to face the pixel electrode.

  On the other hand, the storage capacitor 52 is connected to the TFT 51, and is also electrically connected to the counter electrode via the storage capacitor wiring 52a. Therefore, the storage capacitor 52 is connected in parallel with the capacitor between the pixel electrode and the counter electrode. An alignment film (not shown) is formed on the surface of the TFT array substrate 1.

  Further, the TFT array substrate 1 is formed with a counter substrate (not shown) at a position facing the TFT array substrate 1. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side of the liquid crystal display device. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed. The counter electrode may be formed on the TFT array substrate 1 side. A liquid crystal layer is sandwiched between the TFT array substrate 1 and the counter substrate. That is, liquid crystal is injected between the TFT array substrate 1 and the counter substrate. Furthermore, in the TFT array substrate 1 and the counter substrate, a polarizing plate (not shown), a phase difference plate (not shown), or the like is provided on the surface opposite to the counter surface. Further, a backlight unit (not shown) or the like is disposed on the opposite side of the liquid crystal display device from the viewing side. Light emitted from the backlight passes through the liquid crystal layer through a polarizing plate or the like formed on the counter substrate.

  As described above, an electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode formed on the counter substrate. That is, the liquid crystal is driven by the electric field generated at this time. Thereby, the alignment direction of the liquid crystal injected between the TFT array substrate 1 and the counter substrate changes. That is, the deflection state of light passing through the liquid crystal layer changes. Therefore, the light irradiated from the backlight becomes linearly polarized light by passing through the polarizing plate formed on the counter substrate, and the polarization state is further changed by passing through the liquid crystal layer. For this reason, the light quantity which passes the polarizing plate by the side of a counter substrate changes according to the polarization state of the light which passes a liquid crystal layer. That is, among the transmitted light that passes through the liquid crystal display panel from the backlight, the amount of light that passes through the polarizing plate on the viewing side changes according to the polarization state of the light that passes through the liquid crystal layer. On the other hand, the alignment direction of the liquid crystal changes depending on the applied display voltage. For this reason, the light quantity which passes the polarizing plate by the side of visual recognition can be changed by controlling a display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel. Note that the storage capacitor 52 can hold the display voltage by forming an electric field in parallel with the electric field between the pixel electrode and the counter electrode.

Next, the TFT array substrate 1 configured as described above will be described in more detail. FIG. 2 shows a cross-sectional view of the TFT 51 and the storage capacitor 52 of the thin film transistor device (hereinafter referred to as TFT device) constituting the TFT array substrate 1 according to the present embodiment. As shown in FIG. 2, for example, a SiN film 12 a and a SiO ₂ film 12 b are formed as a base film 12 on a glass substrate 11 that is an insulating substrate. A polycrystalline semiconductor layer 16 (hereinafter referred to as a semiconductor layer) made of polysilicon or the like is formed on the base film 12. The semiconductor layer 16 includes a source region 16a, a drain region 16b, and a channel region 16c in the TFT 51, and a storage capacitor lower region 16d in the storage capacitor 52. Impurities are implanted into the source region 16a and the drain region 16b, and the resistance is lower than that of the channel region 16c. A conductive film 15 is formed on the storage capacitor lower region 16d. The stacked structure of the storage capacitor lower region 16 d and the conductive film 15 functions as a lower electrode of the storage capacitor 52. In FIG. 2, the boundary between the storage capacitor lower region 16d and the drain region 16b is not described, but a region corresponding to the lower portion of the conductive film 15 is referred to as a storage capacitor lower region 16d. In addition, the angle formed by the bottom surface and the side surface of the semiconductor layer 16 at the end portion of the semiconductor layer 16 is 20 degrees or more and 50 degrees or less. Further, the angle formed between the bottom surface and the side surface of the conductive film 15 is more than 0 degree and not more than 50 degrees. That is, the end portion of the semiconductor layer 16 is formed in a taper shape of 20 degrees or more and 50 degrees or less (hereinafter, a region where the taper shape is formed is referred to as a taper portion), and the conductive film 15 exceeds 0 degree and exceeds 50 degrees. The following taper shape is formed. A gate insulating film 18 made of SiO ₂ is formed on the semiconductor layer 16, the conductive film 15, and the SiO ₂ film 12b. A gate electrode 19 a is formed on the gate insulating film 18 so as to face the channel region 16 c which is a part of the semiconductor layer 16. Further, the upper electrode 19b of the storage capacitor 52 is formed so as to face the conductive film 15. That is, the storage capacitor 52 includes a lower electrode having a laminated structure of the semiconductor layer 16 and the conductive film 15, an upper electrode 19b, and the gate insulating film 18 as a dielectric insulating film. A first interlayer insulating film 20 is formed on the gate insulating film 18, the gate electrode 19 a, and the upper electrode 19 b of the storage capacitor 52. A first contact hole 21 a and a second contact hole 21 b are formed in the first interlayer insulating film 20 and the gate insulating film 18. The source electrode 22a formed on the first interlayer insulating film 20 is connected to the source region 16a of the semiconductor layer 16 through the first contact hole 21a. In addition, the drain electrode 22b formed on the first interlayer insulating film 20 is connected to the drain region 16b of the semiconductor layer 16 through the second contact hole 21b. Here, the source electrode 22 a may be formed integrally with the source wiring 5.

  In the TFT device shown in FIG. 2, by making the conductive film 15 having a low resistance function as the lower electrode of the storage capacitor 52, a desired voltage can be reliably applied to the lower electrode. Therefore, there is an effect that a stable capacity can be formed. That is, since the storage capacitor 52 with reduced voltage dependency can be formed, a TFT device having a desired capacitance value corresponding to the thickness of the insulating film can be formed. Thereby, the initial failure of the TFT device can be reduced. Further, the end portion of the semiconductor layer 16 is formed in a tapered shape of 20 degrees or more and 50 degrees or less. Further, the end portion of the conductive film 15 is formed in a tapered shape of 50 degrees or less. By setting the taper angle of the taper portions of the conductive film 15 and the semiconductor layer 16 to 50 degrees or less, the coverage defect of the gate insulating film 18 can be reduced. Therefore, it is possible to reduce gate insulating film breakdown due to electric field concentration between the gate electrode 19a and the semiconductor layer 16 and the upper electrode 19b of the storage capacitor 52 and the conductive film 15 at the end portions of the semiconductor layer 16 and the conductive film 15. it can. In addition, by setting the taper angle of the taper portion of the semiconductor layer 16 to 20 degrees or more, the formation of a parasitic transistor due to an increase in the region of the taper portion having a smaller film thickness than the flat film thickness of the semiconductor layer 16 is achieved. It can be suppressed to a negligible level. As described above, the characteristics of the TFT can be improved.

Next, a manufacturing method of the TFT device shown in FIG. 2 will be described with reference to FIGS. 3 to 7 are manufacturing process sectional views showing the manufacturing method of the TFT device according to this embodiment. As shown in FIG. 3A, SiN, which is a light-transmitting insulating film, is formed on a glass substrate 11 which is an insulating substrate made of a light-transmitting material such as glass or quartz using a CVD method. The film 12 a and the SiO ₂ film 12 b are formed as a base film for the semiconductor layer 16. In the present embodiment, for example, the SiN film 12a is formed to a thickness of 40 to 60 nm on the glass substrate, and the SiO ₂ film 12b is formed to a thickness of 180 to 220 nm. That is, the base film 12 has a laminated structure. The base film 12 is formed mainly to prevent mobile ions such as Na from diffusing from the glass substrate 11 to the semiconductor layer 16, and is not limited to the above-described film configuration and film thickness. An amorphous semiconductor film 13 is formed on the base film 12 using a CVD method. In this embodiment mode, the amorphous semiconductor film 13 is formed using a silicon film with a thickness of 30 to 100 nm, preferably 60 to 80 nm. The base film 12 and the amorphous semiconductor film 13 are preferably formed continuously in the same apparatus or the same chamber. Thereby, it is possible to prevent contaminants such as boron present in the air atmosphere from being taken into the interface of each film. Further, it is preferable to perform annealing at a high temperature after forming the amorphous semiconductor film 13. This is performed in order to reduce hydrogen contained in a large amount in the amorphous semiconductor film 13 formed by the CVD method. In this embodiment mode, the inside of the chamber held in a low vacuum state in a nitrogen atmosphere is heated to about 480 ° C., and the substrate on which the amorphous semiconductor film 13 is formed is held for 45 minutes. Thereby, when the amorphous semiconductor film 13 is crystallized, radical detachment of hydrogen can be prevented even when the temperature rises. Then, surface roughness that occurs after the crystallization of the amorphous semiconductor film 13 can be prevented.

  Next, the natural oxide film formed on the surface of the amorphous semiconductor film 13 is removed by etching with hydrofluoric acid or the like. Then, laser light is irradiated while blowing a gas such as nitrogen to the amorphous semiconductor film 13. By irradiating the amorphous semiconductor film 13 with laser light while blowing nitrogen, the height of the ridge generated at the crystal grain boundary portion can be suppressed. Here, the laser light is converted into a linear beam through a predetermined optical system, and then irradiated to the amorphous semiconductor film 13. In this embodiment, the second harmonic (oscillation wavelength: 532 nm) of a YAG laser is used as the laser light. An excimer laser may be used instead of the second harmonic of the YAG laser. As described above, the polycrystalline semiconductor film 14 is formed by irradiating the amorphous semiconductor film 13 with laser light. The polycrystalline semiconductor film 14 is patterned into a semiconductor layer 16 in a later step.

  Next, a conductive film 15 for forming a lower electrode of the storage capacitor 52 is formed on the polycrystalline semiconductor film 14. The conductive film 15 is preferably made of Cr, Mo, W, Ta, or an alloy film containing these as a main component. In the present embodiment, as the conductive film 15, a Mo alloy film is formed to a thickness of 20 nm by using a DC Magretron sputtering method (hereinafter referred to as a DC sputtering method). Although the thickness of the conductive film 15 is 20 nm, it may be 25 nm or less. By setting the film thickness of the conductive film 15 to 25 nm or less, impurity ions reach the lower semiconductor layer 16 in the subsequent impurity ion doping, so that the conductive film 15 is good between the conductive film 15 and the semiconductor layer 16. The effect that an ohmic contact can be obtained.

  Then, as shown in FIG. 3B, the conductive film 15 is patterned. The conductive film 15 is patterned on the storage capacitor lower region 16d of the semiconductor layer 16 (polycrystalline semiconductor film 14), which is a region to be the storage capacitor 52 later. First, a photoresist, which is a photosensitive resin, is applied on the conductive film 15 by spin coating. The photoresist is exposed and developed by a known photolithography method. Thereby, the photoresist is patterned into a desired shape. In the present embodiment, the conductive film 15 is formed over the storage capacitor lower region 16 d of the semiconductor layer 16 (polycrystalline semiconductor film 14), which is a region that will later become the storage capacitor 52. Then, the storage capacitor 52 with reduced voltage dependency can be formed by causing the conductive layer 15 and the semiconductor layer 16 formed below the conductive film 15 to function as a lower electrode of the storage capacitor 52. Thereby, a TFT device having a desired capacitance value corresponding to the film thickness of the insulating film can be formed, and initial failure of the TFT device can be reduced.

  The conductive film 15 is patterned by, for example, a wet etching method using a chemical solution in which nitric acid and phosphoric acid are mixed. At this time, a chemical solution adjusted so that the end portion of the conductive film 15 has a tapered shape of 50 degrees or less is used. Specifically, the concentration of nitric acid is adjusted so that the chemical solution can easily penetrate into the interface between the conductive film 15 and the photoresist. Alternatively, the concentration of the chemical solution is adjusted by adding acetic acid. Thereby, the angle formed between the side surface and the bottom surface of the end portion of the conductive film 15 can be set to 50 degrees or less.

Next, as shown in FIG. 3C, the polycrystalline semiconductor film 14 is patterned into a desired shape using a known photolithography method, thereby forming a semiconductor layer 16. At this time, the end portion of the semiconductor layer 16 is formed in a tapered shape of 20 degrees or more and 50 degrees or less. In this embodiment mode, the semiconductor layer 16 is formed in an island shape by a dry etching method using a gas in which CF ₄ and O ₂ are mixed. Further, since O ₂ is mixed in the etching gas, the etching can be performed while the photoresist formed by the photoengraving method is retracted. Thereby, the shape of the edge part of the semiconductor layer 16 can be made into a taper shape. Further, it is preferable that the dry etching conditions have a selection ratio with respect to the SiO ₂ film 12b serving as a base film. In the case of dry etching, even if it has a high etching selection ratio with respect to the base film 12, the base film 12 is etched at the time of overetching. Therefore, it is almost inevitably that SiO 2 directly below the semiconductor layer 16 is etched. _The film thickness of the SiO ₂ film 12b in the region where the semiconductor layer 16 is not formed is thinner than the film thickness of the _two film 12b. At this time, the SiO ₂ film 12b in the vicinity of the end portion of the semiconductor layer 16 has an inclination with respect to the horizontal plane. This inclination can be reduced by increasing the etching selection ratio that represents the etching rate of the polycrystalline semiconductor film 14 with respect to the etching rate of the SiO ₂ film 12b. That is, by adjusting the dry etching conditions so as to obtain a high etching selectivity, it is possible to make the inclination of the SiO ₂ film 12b near the edge of the semiconductor layer 16 relative to the horizontal plane smaller than the inclination of the semiconductor layer 16 relative to the horizontal plane. Become. Thus, it is possible to prevent the stress can be reduced, occurrence of cracks in the semiconductor layer 16 and the SiO ₂ film 12b on the gate is formed an insulating film 18 between the semiconductor layer 16 and the SiO ₂ film 12b . Further, it is possible to prevent the coverage defect of the gate insulating film 18. For this reason, it is possible to prevent the gate electrode 19a from being disconnected when the etching solution for wet etching the gate electrode 19a permeates the gate insulating film 18.

  Here, FIGS. 8A to 8D show a part of the TFT device shown in FIG. 2, and the influence of the shape of the end portions of the conductive film 15 and the semiconductor layer 16 will be described. 8A and 8B show a case where the taper angle at the end of the semiconductor layer 16 is larger than 50 degrees and the taper angle at the end of the conductive film 15 on the semiconductor layer 16 is larger than 50 degrees. It is sectional drawing which shows a part of TFT device. FIG. 8C shows a part of the TFT device in which the taper angle at the end of the semiconductor layer 16 is smaller than 20 degrees and the taper angle at the end of the conductive film 15 on the semiconductor layer 16 is smaller than 20 degrees. FIG. FIG. 8D shows the TFT device according to this embodiment, in which the conductive film 15 is formed on the semiconductor layer 16 and the shape of the end of the semiconductor layer 16 is 20 degrees or more and 50 degrees or less. 4 is a cross-sectional view showing a part of a TFT device in which the shape of an end portion of a film 15 is 50 degrees or less.

  As shown in FIG. 8A, when the taper angle of the end portions of the semiconductor layer 16 and the conductive film 15 is larger than 50 degrees, the film thickness b of the gate insulating film 18 formed on the end portions of the conductive film 15 is The film thickness a of the gate insulating film 18 formed on the flat portion of the conductive film 15 is smaller. The film thickness d of the gate insulating film 18 formed on the end portion of the semiconductor layer 16 is smaller than the film thickness c of the gate insulating film 18 formed on the flat portion of the semiconductor layer 16. Therefore, when the upper electrode 19b of the storage capacitor 52 is formed on the gate insulating film 18 so as to cover the end of the conductive film 15 and the end of the semiconductor layer 16, the gate insulating film 18 is partially thin. The electric field concentration between the upper electrode 19b and the conductive film 15 and between the upper electrode 19b and the semiconductor layer 16 is caused, and the gate insulating film is easily broken.

  On the other hand, as shown in FIG. 8B, when the taper angle of the end portions of the semiconductor layer 16 and the conductive film 15 is larger than 50 degrees, depending on the film formation conditions of the gate insulating film 18, the coverage shape is caused. For example, a coverage defect may occur in the upper electrode 19b of the storage capacitor 52 formed on the gate insulating film 18. As a result, when the upper electrode 19b of the storage capacitor 52 is wet-etched, the etching solution penetrates into the defective coverage portion, causing disconnection of the upper electrode 19b of the storage capacitor 52. As shown in FIG. 8C, when the taper angle at the end of the semiconductor layer 16 is smaller than 20 degrees and the taper angle at the end of the conductive film 15 is smaller than 20 degrees, the effective of the semiconductor layer 16 is achieved. The ratio of the thin taper region to the entire semiconductor layer region including the flat portion of the semiconductor layer 16 increases. In this case, the influence of parasitic transistors with different threshold voltages formed in parallel cannot be ignored, and a desired TFT operation cannot be obtained.

  As shown in FIG. 8D, in the TFT device according to this embodiment, the conductive film 15 is formed on the semiconductor layer 16, and the angle α formed between the side surface and the bottom surface of the end portion of the conductive film 15 is 50 degrees. The angle β between the side surface and the bottom surface of the end portion of the semiconductor layer 16 is set to 20 degrees or more and 50 degrees or less. By setting the taper angle of the conductive film 15 and the semiconductor layer 16 to 50 degrees or less, it is possible to prevent the coverage defect of the gate insulating film 18. Further, breakdown of the gate insulating film due to electric field concentration between the upper electrode 19b of the storage capacitor 52 and the semiconductor layer 16 and the upper electrode 19b of the storage capacitor 52 and the conductive film 15 at the ends of the semiconductor layer 16 and the conductive film 15 is prevented. can do. Further, by setting the taper angle of the semiconductor layer 16 to 20 degrees or more, the formation of a parasitic transistor due to an increase in the region of the taper portion having a smaller thickness than the thickness of the flat portion of the semiconductor layer 16 is prevented. Can do. Thereby, the characteristics of the TFT can be improved.

Further, in the present embodiment, the SiO ₂ film 12b is shaped to have an inclination γ with respect to the horizontal plane in the vicinity of the region where the semiconductor layer 16 of the SiO ₂ film 12b is formed by over-etching. This inclination γ is smaller than the angle β formed between the side surface and the bottom surface of the end portion of the semiconductor layer 16. Thus, it is possible to prevent the stress can be reduced, occurrence of cracks in the semiconductor layer 16 and the SiO ₂ film 12b on the gate is formed an insulating film 18 between the semiconductor layer 16 and the SiO ₂ film 12b . Further, it is possible to prevent the coverage defect of the gate insulating film 18. For this reason, it is possible to prevent the gate electrode 19a from being disconnected when the etching solution for wet etching the upper electrode 19b of the storage capacitor 52 permeates the gate insulating film 18.

  In the manufacturing method of the TFT device described above, a known photolithography method is used for patterning the polycrystalline semiconductor film 14 and the conductive film 15, but patterning is performed in one photolithography process using a known halftone mask. May be. Hereinafter, a method of patterning using a halftone mask when patterning the polycrystalline semiconductor film 14 and the conductive film 15 will be described with reference to FIGS. 4A shows a structure in which a conductive film 15 is formed on the polycrystalline semiconductor film 14 and is the same as FIG. 3A. Next, as shown in FIG. 4B, a photoresist 17 is applied on the conductive film 15. First, a photoresist 17 is applied over the entire surface of the conductive film 15. Thereafter, on the region where the semiconductor layer 16 is formed, the photoresist 17a other than the region where the conductive film 15 is formed is thinned by half exposure and development processing, and the storage capacitor is a region where the conductive film 15 is formed. The photoresist 17b in the lower region 16d is thickened.

  In this embodiment, for example, a positive photoresist is used. The positive type photoresist 17 has a film thickness of a resist remaining later as the exposure amount increases. For this reason, when the resist having the shape shown in FIG. 4B is formed, the amount of light applied to the photoresist 17a on the region where the semiconductor layer 16 is formed and other than the region where the conductive film 15 is formed is 15 is larger than the amount of light applied to the photoresist 17b in the storage capacitor lower region 16d, which is the region where the semiconductor layer 16 is formed, and smaller than the amount of light applied to the region where the semiconductor layer 16 is not formed. In the present embodiment, exposure is performed using a half-exposure photomask having regions where the transmitted light amount is different in at least two stages so that the irradiation light amount is adjusted for each exposure region. By using such a photomask, the number of exposures can be reduced to one. When exposure is performed using a photomask having different regions with at least two levels of transmitted light, the number of exposures can be set to one, but a region other than the photoresist 17b in the storage capacitor lower region 16d is irradiated with a weak amount of light. The exposure process may be divided into the exposure process for irradiating a region other than the region where the semiconductor layer 16 is formed with a strong light amount. In this case, the exposure process is required twice, but a photomask having different regions where the amount of transmitted light is different in at least two steps is not required. That is, the photoresist 17 shown in FIG. 4B can be formed using a normal photomask. Note that when a negative resist is used, the magnitude relationship of the amount of irradiation light at the time of exposure is reversed.

  FIG. 4C shows a state where the semiconductor layer 16 is formed by etching the polycrystalline semiconductor film 14 after the conductive film 15 is etched using the photoresist 17 as shown in FIG. 4B as a mask.

In this embodiment, since a Mo alloy film is used as the conductive film 15, dry etching using a mixed gas of CF ₄ and O ₂ is used. Since O ₂ is mixed in the etching gas, etching can be performed while the end of the photoresist 17 is retracted. Thus, the ends of the conductive film 15 and the semiconductor layer 16, and the SiO ₂ film 12b in the vicinity of the semiconductor layer 16 is formed, it can be processed to have an inclination relative to the horizontal plane.

At this time, as described above, the taper angle of the semiconductor layer 16 is set to 20 degrees or more and 50 degrees or less. By setting the taper angle to 50 degrees or less, it is possible to prevent the gate insulating film from being broken due to electric field concentration, and the upper electrode 19b due to poor coverage of the gate insulating film 18 and the upper electrode 19b of the storage capacitor 52 to be formed later. Disconnection can be reduced. On the other hand, by setting the taper angle to 20 degrees or more, formation of a parasitic transistor can be prevented. Furthermore, the SiO ₂ film 12b in the vicinity where the semiconductor layer 16 is formed has an inclination with respect to the horizontal plane, and this inclination is made smaller than the taper angle of the semiconductor layer 16, thereby making the semiconductor layer 16 and the SiO ₂ film 12b. And the resistance of the gate insulating film 18 can be improved. Further, since the coverage of the gate insulating film 18 and the upper electrode 19b of the storage capacitor 52 is also good in the same portion, it is possible to avoid disconnection due to penetration of the etching solution when the upper electrode 19b is wet-etched. Become.

Next, after patterning the conductive film 15 and the semiconductor layer 16 as shown in FIG. 4C, only the photoresist 17b in the storage capacitor lower region 16d is left as shown in FIG. 5A. In the present embodiment, the thickness of the photoresist 17 is uniformly reduced by ashing using O ₂ gas. At this time, the time for the ashing process may be determined in advance, or may be determined by monitoring the light emission phenomenon that occurs when the conductive film 15 is exposed to the plasma used in the ashing process. Here, after the conductive film 15 and the polycrystalline semiconductor film 14 are patterned by etching, the thickness of the photoresist 17 is uniformly reduced. However, these two steps may be performed simultaneously. That is, the state shown in FIG. 4B may be shifted to the state shown in FIG. 5A by etching in consideration of the ratio of the film thickness to be etched and the etching rate.

Then, as shown in FIG. 5B, the conductive film 15 is removed by etching using the photoresist 17b in the storage capacitor lower region 16d as a mask. At this time, it is preferable to perform etching with selectivity so that the semiconductor layer 16 under the conductive film 15 is not etched. Note that the reaction layer generated at the interface between the conductive film 15 and the semiconductor layer 16 may be removed by etching. For example, the reaction layer is a Mo silicide layer and is removed by dry etching using a mixed gas of CF ₄ and Ar. As described above, in this embodiment, since the Mo alloy film is used as the conductive film 15, the conductive film 15 is removed by wet etching using a chemical solution in which nitric acid and phosphoric acid are mixed. At this time, the concentration of nitric acid is adjusted so that the chemical solution can easily penetrate into the interface between the conductive film 15 and the photoresist. Thereby, the shape of the end portion of the conductive film 15 can be a tapered shape having a taper angle of 50 degrees or less. By making the end portion of the conductive film 15 into a tapered shape having a taper angle of 50 degrees or less, it is possible to prevent the coverage defect of the gate insulating film 18. In addition, the gate insulating film can be prevented from being broken due to electric field concentration between the gate electrode 19a and the conductive film 15 at the end of the conductive film 15. As described above, the characteristics of the TFT can be improved.

  Through the above steps, the conductive film 15 can be patterned at a desired position on the semiconductor layer 16 as shown in FIG. 5B by one photolithography. That is, as shown in FIG. 5B, the conductive film 15 is formed inside the region where the semiconductor layer 16 is formed. Further, in the case of such a structure, the photolithography process can be reduced once compared with the case where the conductive film 15 and the semiconductor layer 16 are separately patterned. Thereby, the productivity of the TFT device can be improved.

Next, in FIG. 5B, after removing the photoresist 17b, a gate insulating film 18 is formed on the conductive film 15, the semiconductor layer 16, and the base film 12, as shown in FIG. 6A. As the gate insulating film 18, a SiN film, a SiO ₂ film, or the like is used. In the present embodiment, a SiO ₂ film is used as the gate insulating film 18. And it forms in 80 nm or more and 100 nm or less of film thickness using CVD method. By setting the thickness of the gate insulating film 18 to 80 nm or more, it is possible to avoid surface irregularities of the polycrystalline semiconductor layer 16 and breakdown of the gate insulating film at the end portion of the semiconductor layer 16. This makes it possible to introduce a desired impurity amount into the semiconductor layer 16 in a later implantation step. Further, the surface roughness of the semiconductor layer 16 is set to about 3 nm or less. Then, the end of the semiconductor layer 16 intersecting the gate electrode 19a and the vicinity of the region where the semiconductor layer 16 of the SiO ₂ film 12b is formed are tapered. Thereby, the coverage of the gate insulating film 18 can be improved, so that the initial failure of the TFT device can be reduced.

  Then, a conductive film is formed on the gate insulating film 18 to form the gate electrode 19a and wirings. The conductive film is patterned into a desired shape using a known photoengraving method to form the gate electrode 19a, the upper electrode 19b of the storage capacitor, and the gate wiring 4 (see FIG. 1). The upper electrode 19 b of the storage capacitor 52 is formed to face the conductive film 15. As the gate electrode 19a and the upper electrode 19b, Cr, Mo, W, Ta, or an alloy film containing these as main components is used. In this embodiment, an alloy film containing Mo as a main component is formed to a thickness of 200 to 400 nm by DC sputtering. The conductive film was etched by a wet etching method using a chemical solution in which nitric acid and phosphoric acid were mixed.

  Next, impurities are implanted into the semiconductor layer 16 through the gate insulating film 18 using the gate electrode 19a as a mask. Here, P (phosphorus) or B (boron) or the like is used as the impurity. When P is implanted, an n-type TFT can be formed. Further, when the gate electrode 19a is processed in two steps, an n-type TFT gate electrode and a p-type TFT gate electrode, an n-type TFT and a p-type TFT are separately formed on the same substrate, and a CMOS structure TFT is formed. A device can be formed (not shown). The implantation of the P or B impurity is performed using an ion doping method. In this ion doping method, ions may be irradiated from a direction perpendicular to the surface of the glass substrate 11, but ions may be irradiated from an oblique direction.

  By ion doping, a source region 16a and a drain region 16b in which impurities are implanted into the semiconductor layer 16 are formed, and at the same time, a channel region 16c that is masked by the gate electrode 19a and not implanted with impurities is formed. As described above, the conductive film 15 is formed on the storage capacitor lower region 16d of the semiconductor layer 16, and the thickness of the conductive film 15 is as thin as approximately 25 nm or less. For this reason, for example, when there is a region where the conductive film 15 protrudes without being covered by the upper electrode 19b of the storage capacitor 52, the impurity is also implanted into the storage capacitor lower region 16d of the semiconductor layer 16 in the protruding region. Thereby, an ohmic contact between the conductive film 15 and the semiconductor layer 16 can be obtained. Further, even when the conductive film 15 is not covered with the upper electrode 19b and there is no protruding region, the impurity is introduced into the storage capacitor lower region 16d by performing ion irradiation from an oblique direction with respect to the surface of the glass substrate 11. Can be injected. 6A, a stacked structure of the gate electrode 19a, the gate insulating film 18, and the semiconductor layer 16 is formed in the region where the TFT 51 is formed. In the region where the storage capacitor 52 is formed, a stacked structure of the storage capacitor upper electrode 19b, the gate insulating film 18, the conductive film 15, and the storage capacitor lower region 16d is formed.

Next, as shown in FIG. 6B, a first interlayer insulating film 20 is formed on the gate electrode 19 a, the upper electrode 19 b, and the gate insulating film 18. In the present embodiment, the first interlayer insulating film 20 forms a SiO ₂ film having a thickness of 500 to 700 nm by using a CVD method. And it hold | maintains for about 1 hour in the annealing furnace heated at 450 degreeC in nitrogen atmosphere. This is performed to activate the impurity element implanted into the source region 16a and the drain region 16b of the semiconductor layer 16. The first interlayer insulating film 20 is not limited to the SiO ₂ film but may be a SIN film or an organic film.

Then, the gate insulating film 18 and the first interlayer insulating film 20 are patterned into a desired shape using a known photolithography method. Here, the first contact hole 21a reaching the source region 16a and the second contact hole 21b reaching the drain region 16b of the semiconductor layer 16 are formed. By forming the first contact hole 21a and the second contact hole 21b, the source region 16a and the drain region 16b of the semiconductor layer 16 are exposed. In the present embodiment, the first contact hole 21a and the second contact hole 21b are formed by dry etching using a mixed gas of CHF ₃ , O ₂ , and Ar.

Thereafter, a conductive film is formed in the first contact hole 21 a, the second contact hole 21 b, and the first interlayer insulating film 20. Then, the conductive film is patterned into a desired shape using a known photolithography method. Thus, the source electrode 22a, the drain electrode 22b, and the source wiring 5 (see FIG. 1) which are signal lines are formed. In the present embodiment, the source electrode 22a, the drain electrode 22b, and the source wiring 5 have a Mo / Al / Mo laminated structure in which a Mo film, an Al film, and a Mo film are continuously formed by DC sputtering. . The film thickness of the Al film is 200 to 400 nm, and the film thickness of the Mo film is 50 to 150 nm. The source electrode 22a and the drain electrode 22b are etched by a dry etching method using a mixed gas of SF ₆ and O _{2 and} a mixed gas of Cl ₂ and Ar. Through the above steps, the source electrode 22a connected to the semiconductor layer 16 is formed on the source region 16a. Further, a drain electrode 22b connected to the semiconductor layer 16 is formed on the drain region 16b.

  Through the series of steps described above, the TFT 51 and the storage capacitor 52 can be formed. In this embodiment, the lower electrode of the storage capacitor 52 connected in series to the TFT 51 has a stacked structure of the semiconductor layer 16 and the conductive film 15. That is, by using the conductive film 15 having a low resistance and the semiconductor layer 16 formed below the conductive film 15 as the lower electrode of the storage capacitor 52, a desired voltage can be reliably applied to the lower electrode. it can. Therefore, there is an effect that the storage capacitor 52 having a stable capacity can be formed. Further, the end portion of the semiconductor layer 16 has a tapered shape having a taper angle of 20 ° to 50 °, and the end portion of the conductive film 15 has a tapered shape having a taper angle of 50 ° or less, whereby the gate insulating film Breaking can be reduced, and further, disconnection of the upper electrode 19b of the storage capacitor 52 can be reduced. In addition, formation of parasitic transistors can be prevented. As described above, the characteristics of the TFT can be improved.

  When the TFT device formed in the above-described process is applied to an active matrix display device, a pixel electrode or the like is further connected to the drain electrode 22b. Hereinafter, the manufacturing method will be described with reference to FIG. 7 showing a TFT device in which pixel electrodes and the like are formed on the TFT device shown in FIG.

As shown in FIG. 7, a second interlayer insulating film 23 is formed on the first interlayer insulating film 20, the source electrode 22a, and the drain electrode 22b. Then, a third contact hole 24 is formed in the second interlayer insulating film 23 so as to reach the drain electrode 22b using a known photolithography method. In the present embodiment, the second interlayer insulating film 23 forms a SiN film having a thickness of 200 to 300 nm using a CVD method. The third contact hole 24 is formed by dry etching using a mixed gas of CF ₄ and O ₂ . Then, a transparent conductive film such as ITO or IZO is formed on the second interlayer insulating film 23, and patterned into a desired shape by a known photolithography method, thereby forming the pixel electrode 25. In this embodiment, an amorphous transparent conductive film with excellent workability is formed by a DC sputtering method using a gas in which Ar gas, O ₂ gas, and H ₂ O gas are mixed. Here, the pixel electrode 25 is patterned so as to be connected to the drain electrode 22 b through the third contact hole 24. The conductive film is etched by a wet etching method using a chemical solution containing oxalic acid as a main component. Thereafter, unnecessary resist is removed and annealing is performed to crystallize the pixel electrode 25 made of an amorphous transparent conductive film. Thereby, a TFT device used for the display device is formed.

In the present embodiment, the conductive film 15 is formed only on the storage capacitor lower region 16 d of the semiconductor layer 16. That is, by forming the low-resistance conductive film 15 on the semiconductor layer 16 to be the lower electrode of the storage capacitor 52 and causing the conductive film 15 and the semiconductor layer 16 below the conductive film 15 to function as the lower electrode of the storage capacitor. A storage capacitor with reduced voltage dependency can be formed. At this time, the shape of the end portion of the semiconductor layer 16 is a shape having a taper angle of 20 degrees or more and 50 degrees or less. The shape of the end portion of the conductive film 15 is a shape having a taper angle of 50 degrees or less. By setting the taper angle of the semiconductor layer 16 and the conductive film 15 to 50 degrees or less, the coverage defect of the gate insulating film 18 can be reduced, the gate insulating film is broken due to electric field concentration, and the upper electrode 19b of the storage capacitor 52 is disconnected. Can be prevented. As a result, a stable capacitor with reduced voltage dependency can be formed. Further, by setting the taper angle of the semiconductor layer 16 to 20 degrees or more, it is possible to prevent a parasitic transistor from being formed in the semiconductor layer 16. As described above, the characteristics of the TFT can be improved. Further, the vicinity of the region where the semiconductor layer 16 of the SiO ₂ film 12b is formed has an inclination with respect to the horizontal plane. This inclination is smaller than the angle formed by the bottom surface and the side surface of the semiconductor layer 16 at the end of the semiconductor layer 16. Thereby, since the stress between the semiconductor layer 16 and the gate insulating film 18 can be reduced, the generation of cracks in the gate insulating film 18 can be prevented, and thus the disconnection of the gate electrode 19a can be prevented. .

Embodiment 2. FIG.
Next, a display device according to a second embodiment will be described with reference to FIG. FIG. 9A is a cross-sectional view of the TFT device according to the second embodiment, in which the source electrode 22a and the drain electrode 22b are formed. FIG. 9B is a cross-sectional view of the TFT device in which the pixel electrode 25 is further formed in FIG. 9A. In the TFT device according to the second embodiment shown in FIG. 9, the same components as those in the first embodiment shown in FIGS. 2 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The TFT device shown in FIG. 9 differs from the first embodiment shown in FIGS. 2 to 7 in that the conductive film 15 is not only on the storage capacitor lower region 16d of the semiconductor layer 16, but also the drain region 16b of the semiconductor layer 16 and It is also a point formed on the source region 16a.

  Hereinafter, the TFT device according to the second embodiment will be described in detail. That is, as shown in FIGS. 9A and 9B, the conductive film 15 is formed not only on the storage capacitor lower region 16 d of the semiconductor layer 16 but also on the source region 16 a and the drain region 16 b of the semiconductor layer 16. Is done. Thereby, when the first contact hole 21a and the second contact hole 21b are formed, the first contact hole 21a and the second contact hole 21b can be prevented from penetrating the semiconductor layer 16. Further, by extending the conductive film 15 from the storage capacitor 52 to the TFT 51, the wiring connection resistance between the TFT 51 and the storage capacitor 52 can be reduced. Further, when Mo or a film containing Mo as a main component is used for the conductive film 15, deposits generated by dry etching gas are less likely to adhere when forming the first contact hole 21a and the second contact hole 21b. Become. Therefore, contact characteristics between the source electrode 22a and the drain electrode 22b and the semiconductor layer 16 can be improved. As described above, the display quality of the display device can be improved.

  Further, the TFT device manufacturing method according to the second embodiment is different from the first embodiment only in that the patterning shape of the conductive film 15 is different. When the photoresist 17 is formed using a known halftone mask, the photoresist in a region where the photoresist 17 is formed to be thickest extends from the storage capacitor lower region 16d of the semiconductor layer 16 to the drain region 16b. Except for the formation on the source region 16a, the detailed description is omitted because it is the same as the first embodiment. In the TFT device shown in FIG. 9, the conductive film 15 extends from the storage capacitor lower region 16d to the drain region 16b, but it does not necessarily have to be extended. That is, the conductive film 15 may be formed only on the drain region 16b and the storage capacitor lower region 16d. In this case, although there is no effect of reducing the wiring connection resistance between the TFT 51 and the storage capacitor 52, the second contact hole 21b is prevented from penetrating the semiconductor layer 16 when the second contact hole 21b is opened. There is an effect that can be. Thereby, the display quality of the display device can be improved. Also in the second embodiment, the thickness of the conductive film 15 is set to about 25 nm or less. For this reason, even in the lower layer of the conductive film 15, it is possible to implant impurities into the source region 16a and the drain region 16b of the semiconductor layer 16 by ion doping.

  In the present embodiment, the conductive film 15 is formed on the storage capacitor lower region 16 d of the semiconductor layer 16. As a result, the same effects as those of the first embodiment can be obtained. In addition, the shape of the end portion of the semiconductor layer 16 is a tapered shape of 20 degrees or more and 50 degrees or less, and the shape of the end portion of the conductive film 15 is a tapered shape of 50 degrees or less. Thereby, the characteristics of the TFT can be improved. Furthermore, since the conductive film 15 is formed not only on the storage capacitor lower region 16d of the semiconductor layer 16 but also on the source region 16a and the drain region 16b, when the first and second contact holes 21a and 21b are opened, There is an effect that it is possible to prevent the layer 16 from being penetrated.

Embodiment 3 FIG.
A TFT device according to the third embodiment will be described with reference to FIG. The TFT device shown in FIG. 10 differs from the TFT device according to the first embodiment shown in FIGS. 2 to 7 in that the conductive film 15 is not only on the storage capacitor lower region 16 d of the semiconductor layer 16 but also on the semiconductor layer 16. A point formed in the drain region 16b and the source region 16a, the source electrode 26 is not directly connected to the source region 16a, but a connection electrode 29 formed on the second interlayer insulating film 23, a first upper contact hole 27a described later, In addition, the pixel electrode 28 formed on the second interlayer insulating film 23 is connected to the drain region 16b via a second upper contact hole 27b, which will be described later, and the pixel electrode 28 formed on the second interlayer insulating film 23 is connected to the source region 16a via the fourth contact hole 27c. It is a point.

  Hereinafter, the TFT device according to the third embodiment will be described in detail with reference to FIG. In the TFT device shown in FIG. 10C, the conductive film 15 formed on the semiconductor layer 16 is also formed in the source region 16a and the drain region 16b. A source electrode 26 is formed on the first interlayer insulating film 20. A first contact hole 21a and a second contact hole 21b are formed in the gate insulating film 18 and the first interlayer insulating film 20. A second interlayer insulating film 23 is formed on the first interlayer insulating film 20 and the source electrode 26, and a fifth contact hole 23 a and a sixth contact hole 23 b are formed in the second interlayer insulating film 23. The first contact hole 21a and the fifth contact hole 23a are formed to overlap each other at the same position. Further, the second contact hole 21b and the sixth contact hole 23b are formed to overlap each other at the same position. Then, the conductive film 15 formed on the source region 16a and the conductive film 15 formed on the drain region 16b are reached. Further, a fourth contact hole 27 c is formed in the second interlayer insulating film 23 so as to reach the source electrode 26. A pixel electrode 28 and a connection electrode 29 are formed on the second interlayer insulating film 23. The pixel electrode 28 is connected to the conductive film 15 formed on the drain region 16b through the second upper contact hole 27b including the second contact hole 21b and the sixth contact hole 23b. The connection electrode 29 is connected to the conductive film 15 formed on the source region 16a through the first upper contact hole 27a including the first contact hole 21a and the fifth contact hole 23a. The source electrode 26 is connected through the fourth contact hole 27c. That is, the connection electrode 29 connects the source electrode 26 and the conductive film 15 formed on the source region 16a through the fourth contact hole 27c and the first upper contact hole 27a. Although not illustrated here, display is performed on the display device by applying a voltage to the electro-optical material such as liquid crystal or a self-luminous material by the pixel electrode 28.

  In the first and second embodiments, the first contact hole 21a and the second contact hole 21b are formed in the first interlayer insulating film 20 and the gate insulating film 18, the source electrode 22a and the drain electrode 22b are formed, and then, further, In order to form the second interlayer insulating film 23 and connect the pixel electrode 25 and the drain electrode 22b, the third contact hole 24 had to be formed. On the other hand, in the present embodiment, the first upper contact hole 27a, the second upper contact hole 27b, and the fourth contact hole 27c are simultaneously patterned, so that the source electrode 26 and the conductive film 15 are transparent as in the pixel electrode 28. The connection is made by a connection electrode 29 which is a conductive film. Thereby, the number of photolithography processes can be reduced, and the productivity of the display device is improved. Further, since the conductive film 15 is formed at the bottoms of the first upper contact hole 27a and the second upper contact hole 27b, it is possible to prevent penetration during the formation of the contact hole. In addition, by causing the conductive film 15 having a low resistance to function as the lower electrode of the storage capacitor 52, a desired voltage can be applied to the lower electrode, and a stable capacitance can be formed. Thus, a storage capacitor with reduced voltage dependency can be formed. Therefore, a storage capacitor having a desired capacitance value corresponding to the insulating film thickness can be formed, and a display device with few initial failures can be obtained.

  Next, a method for manufacturing the display device according to the third embodiment will be described with reference to FIGS. As shown in FIG. 10A, the conductive film 15 formed on the semiconductor layer 16 extends to the drain region 16b and is also formed on the source region 16a. Then, similarly to the first embodiment, the gate insulating film 18, the gate electrode 19a, the upper electrode 19b, and the first interlayer insulating film 20 are formed. Then, after forming up to the first interlayer insulating film 20, a conductive film is formed on the first interlayer insulating film 20, and patterned into a desired shape using a known photolithography method. Thereby, the source electrode 26 and the source wiring 5 (see FIG. 1) are formed. As described above, the Mo / Al / Mo laminated structure is used as the source electrode 26 and the source wiring 5. In the third embodiment, the source electrode 26 is connected to another wiring at the source electrode 26 and the source wiring 5. Only the upper layer 22a. That is, since the source electrode 26 is not connected to other wiring on the first interlayer insulating film 20 side, the Mo film on the first interlayer insulating film 20 side need not be formed, the upper layer is the Mo film and the lower layer is the Al film. Alternatively, a laminated film made of an Al alloy film may be used.

Next, as shown in FIG. 10B, the second interlayer insulating film 23 is formed on the source electrode 26 and the source wiring 5. In the present embodiment, the second interlayer insulating film 23 forms a SiN film having a thickness of 200 to 300 nm by a CVD method. Thereafter, a fourth contact hole 27c reaching the source electrode 26 is formed in the second interlayer insulating film 23 by using a known photolithography method and etching method. At this time, the first upper contact hole 27a is formed in the second interlayer insulating film 23, the first interlayer insulating film 20, and the gate insulating film 18 so as to reach the conductive film 15 formed on the source region 16a. A second upper contact hole 27b is formed in the second interlayer insulating film 23, the first interlayer insulating film 20, and the gate insulating film 18 so as to reach the conductive film 15 formed on the drain region 16b. In the present embodiment, the opening of the first upper contact hole 27a, the second upper contact hole 27b, and the fourth contact hole 27c is performed by a dry etching method using a mixed gas of CF ₄ and O ₂ .

Then, as illustrated in FIG. 10C, the pixel electrode 28 and the connection electrode 29 are formed on the second interlayer insulating film 23. The pixel electrode 28 and the connection electrode 29 are made of a transparent conductive film such as ITO or IZO. Then, it is patterned into a desired shape by a known photolithography method. Here, the connection electrode 29 is connected to the source electrode 26 through the fourth contact hole 27c, and is connected to the conductive film 15 formed on the source region 16a through the first upper contact hole 27a. Formed. The pixel electrode 28 is formed so as to be connected to the conductive film 15 formed on the drain region 16b through the second upper contact hole 27b. In the present embodiment, the conductive film to be the pixel electrode 28 and the connection electrode 29 is a non-processed material having excellent workability by a DC sputtering method using a gas in which Ar gas, O ₂ gas, and H ₂ O gas are mixed. A crystalline transparent conductive film is used. The conductive film is etched by a wet etching method using a chemical solution containing oxalic acid as a main component. Thereafter, unnecessary resist is removed and annealing is performed to crystallize the pixel electrode 28 and the connection electrode 29 made of an amorphous transparent conductive film. Thereby, a TFT device used for the display device is formed.

  In the present embodiment, the conductive film 15 is formed on the storage capacitor lower region 16 d of the semiconductor layer 16. As a result, the same effects as those of the first embodiment can be obtained. The shape of the end portion of the semiconductor layer 16 is a taper shape of 20 degrees or more and 50 degrees or less. And the shape of the edge part of the electrically conductive film 15 is made into the taper shape of 50 degrees or less. As described above, the characteristics of the TFT can be improved. Further, since the conductive film 15 is formed not only on the storage capacitor lower region 16d of the semiconductor layer 16 but also on the source region 16a and the drain region 16b, when the first and second upper contact holes 27a and 27b are opened, It is possible to prevent the semiconductor layer 16 from penetrating. Also, a process of forming a second upper contact hole 27b that connects the pixel electrode 28 and the conductive film 15 on the drain region 16b, and a process of forming a contact hole that connects the connection electrode 29 and the conductive film 15 on the source region 16a. Since one step is used, the number of manufacturing steps can be reduced. Thereby, the productivity of the display device can be improved. Further, since the pixel electrode 28 and the conductive film 15 on the drain region 16b, and the connection electrode 29 and the conductive film 15 on the source region 16a are connected by one contact hole, the contact resistance can be reduced.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the second and third embodiments, the conductive film 15 extends from the storage capacitor lower region 16d of the semiconductor layer 16 to the drain region 16b. The conductive film 15 may be formed only at the bottom of at least one of the first contact hole 21a and the second contact hole 21b.

3 is a schematic plan view illustrating a configuration of a TFT array substrate used in the display device according to Embodiment 1. FIG. 1 is a cross-sectional view showing a TFT device according to a first embodiment. FIG. 6 is a manufacturing process sectional view showing the method of manufacturing the TFT device according to the first embodiment; FIG. 6 is a manufacturing process sectional view showing the method of manufacturing the TFT device according to the first embodiment; FIG. 6 is a manufacturing process sectional view showing the method of manufacturing the TFT device according to the first embodiment; FIG. 6 is a manufacturing process sectional view showing the method of manufacturing the TFT device according to the first embodiment; FIG. 2 is a cross-sectional view illustrating the TFT device according to the first embodiment, the TFT device including a pixel electrode. It is sectional drawing which shows a part of TFT device. 6 is a cross-sectional view showing a TFT device according to a second embodiment; FIG. FIG. 10 is a manufacturing process sectional view showing the method of manufacturing the TFT device according to the third embodiment;

Explanation of symbols

1 TFT array substrate, 2 display area, 3 frame area, 4 gate wiring, 5 source wiring, 6 pixels, 7 gate signal driving circuit, 8 source signal driving circuit, 9 TFT, 10 holding capacitor, 11 substrate, 12, 91 bottom Base film, 12a SiN film, 12b SiO ₂ film, 13 amorphous semiconductor film, 14 polycrystalline semiconductor film, 15, 93 conductive film, 16, 92 semiconductor layer, 17 photoresist, 18, 94 gate insulating film, 19a gate electrode 19b Upper electrode, 20 First interlayer insulating film, 21a First contact hole, 21b Second contact hole, 22a, 26 Source electrode, 22b Drain electrode, 23 Second interlayer insulating film, 23a Fifth contact hole, 23b Sixth Contact hole, 24 3rd contact hole, 25, 28 Pixel electrode, 27a First upper contact hole, 2 b second upper contact hole, 27c fourth contact hole, 29 connection electrodes, 51 TFT, 52 storage capacitor, 52a retention capacitor line

Claims (15)

A semiconductor layer formed over a substrate and having a source region, a drain region, and a channel region;
A conductive film formed over the semiconductor layer and at least in a region serving as a storage capacitor;
A gate insulating film formed on the semiconductor layer and the conductive film;
An upper electrode of the storage capacitor formed on the gate insulating film at a position facing the conductive film; and a gate electrode formed at a position facing the channel region;
A first interlayer insulating film formed on the gate electrode, the upper electrode, and the gate insulating film;
A source electrode formed on the first interlayer insulating film and connected to the source region through a first contact hole;
A drain electrode formed on the first interlayer insulating film and connected to the drain region through a second contact hole;
The angle formed between the side surface of the end portion of the semiconductor layer and the bottom surface of the semiconductor layer is 20 ° to 50 °, and the angle formed between the side surface of the end portion of the conductive film and the bottom surface of the conductive film is 0 °. A thin film transistor device which is more than 50 degrees and less. A second interlayer insulating film formed on the source electrode and the drain electrode;
The thin film transistor device according to claim 1, further comprising: a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode through a third contact hole. 3. The thin film transistor device according to claim 1, wherein the conductive film is formed on the semiconductor layer and further on a bottom portion of at least one of the first contact hole and the second contact hole. A semiconductor layer formed over a substrate and having a source region, a drain region, and a channel region;
A conductive film formed over the semiconductor layer and at least in a region serving as a storage capacitor;
A gate insulating film formed on the semiconductor layer and the conductive film;
An upper electrode of the storage capacitor formed on the gate insulating film at a position facing the conductive film; and a gate electrode formed at a position facing the channel region;
A first interlayer insulating film formed on the gate electrode, the upper electrode, and the gate insulating film;
A source electrode formed on the first interlayer insulating film;
A second interlayer insulating film formed on the source electrode and the first interlayer insulating film;
A connection electrode formed on the second interlayer insulating film, connected to the source electrode via a fourth contact hole, and connected to the source region via a first upper contact hole;
A pixel electrode formed on the second interlayer insulating film and connected to the drain region through a second upper contact hole;
The angle formed between the side surface of the end portion of the semiconductor layer and the bottom surface of the semiconductor layer is 20 ° to 50 °, and the angle formed between the side surface of the end portion of the conductive film and the bottom surface of the conductive film is 0 °. A thin film transistor device which is more than 50 degrees and less. The thin film transistor device according to claim 4, wherein the conductive film is formed on the semiconductor layer and further on a bottom of at least one of the first upper contact hole and the second upper contact hole. A base film formed under the semiconductor layer;
The base film has an inclination with respect to a horizontal plane in the vicinity of the region where the semiconductor layer of the base film is formed,
The inclination is smaller than an angle formed between a side surface of the end portion of the semiconductor layer and a bottom surface of the semiconductor layer, and an angle formed between a side surface of the end portion of the conductive film and the bottom surface of the conductive film. Item 6. The thin film transistor device according to any one of Items 1 to 5. The thin film transistor device according to claim 1, wherein the gate insulating film has a thickness of 80 nm to 100 nm. The thin film transistor device according to any one of claims 1 to 7, wherein the conductive film is formed of Mo or an alloy film containing Mo as a main component. The thin film transistor device according to claim 1, wherein the conductive film is formed inside a region where the semiconductor layer is formed. Forming a semiconductor layer having a source region, a drain region, and a channel region over a substrate;
Forming a conductive film on the semiconductor layer at least in a region to be a storage capacitor;
The angle formed between the side surface of the end portion of the semiconductor layer and the bottom surface of the semiconductor layer is 20 ° to 50 °, and the angle formed between the side surface of the end portion of the conductive film and the bottom surface of the conductive film exceeds 0 °. Forming at 50 degrees or less;
Forming a gate insulating film on the semiconductor layer and the conductive film;
Forming a gate electrode and an upper electrode of a storage capacitor on the gate insulating film;
Forming a first interlayer insulating film on the gate electrode, the upper electrode, and the gate insulating film;
Forming a source electrode formed on the first interlayer insulating film and connected to the source region through a first contact hole formed by etching the gate insulating film and the first interlayer insulating film; When,
Forming a drain electrode formed on the first interlayer insulating film and connected to the drain region through a second contact hole formed by etching the gate insulating film and the first interlayer insulating film; A method for manufacturing a thin film transistor device. Forming a second interlayer insulating film on the source electrode, the drain electrode, and the first interlayer insulating film;
The method of manufacturing a thin film transistor device according to claim 10, further comprising: forming a pixel electrode formed on the second interlayer insulating film and connected to the drain electrode through a third contact hole. . 12. The thin film transistor device according to claim 10, wherein the conductive film is formed on the semiconductor layer and further at a bottom of at least one of the first contact hole and the second contact hole. Production method. Forming a semiconductor layer formed on a substrate and having a source region, a drain region, and a channel region;
Forming a conductive film on the semiconductor layer at least in a region to be a storage capacitor;
The angle formed between the side surface of the end portion of the semiconductor layer and the bottom surface of the semiconductor layer is 20 ° to 50 °, and the angle formed between the side surface of the end portion of the conductive film and the bottom surface of the conductive film exceeds 0 °. Forming at 50 degrees or less;
Forming a gate insulating film on the semiconductor layer and the conductive film;
Forming a gate electrode and an upper electrode of the storage capacitor on the gate insulating film;
Forming a first interlayer insulating film on the gate electrode, the upper electrode, and the gate insulating film;
Forming a source electrode on the first interlayer insulating film;
Forming a second interlayer insulating film on the source electrode and the first interlayer insulating film;
Forming a connection electrode on the second interlayer insulating film, connected to the source electrode via a fourth contact hole, and connected to the source region via a first upper contact hole;
Forming a pixel electrode on the second interlayer insulating film and connected to the drain region through a second upper contact hole. 14. The thin film transistor device according to claim 13, wherein the conductive film is formed on the semiconductor layer and further at a bottom of at least one of the first upper contact hole and the second upper contact hole. Production method.   A display device comprising the thin film transistor device according to claim 1.

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