JP2009009544A - Clock supply circuit and clock supply method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock supply circuit for switching clock signals seamlessly. <P>SOLUTION: A multiplexer 110 outputs a clock signal designated by a clock designation signal SEL, out of a plurality of supplied clock signals as a first intermediate clock CLK_M1. An inversion circuit 120 outputs the supplied first intermediate clock CLK_M1 as it is or inverts the signal level to output a second intermediate clock CLK_M2, in response to a clock inversion signal INVERT. D flip-flops 130 and 131 synchronize a stop signal STOP with a rising edge and a falling edge of the second intermediate clock CLK_M2 to generate a mask signal MASK. An AND gate 140 generates an output clock CLK_O from the second intermediate clock CLK_M2 and the mask signal MASK and outputs the output clock. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clock supply circuit and a clock supply method.

  In recent years, a technique related to hardware capable of dynamically switching a circuit configuration when an application program (hereinafter referred to as an application) is executed, that is, a so-called dynamic reconfigurable technique has been developed. With dynamic reconfigurable technology, it is possible to create an environment in which software can easily realize the performance of a dedicated logic circuit with little awareness of the hardware structure.

  Along with this, a mechanism that simplifies complicated design work such as designing ASIC (Application Specific Integrated Circuit) and shortens the development period such as IC (Integrated Circuit) and LSI (Large Scale Integration) is prepared. It's getting on. If the simulation at the time of application development passes, the execution of the dynamic reconfigurable processor on the actual chip is completely guaranteed. For this reason, it is not swayed by complicated work such as ASIC verification work.

  Also, with the dynamic reconfigurable technology, the circuit configuration can be switched at high speed, so that a single chip can be instantly changed into various dedicated LSIs. In other words, it is possible to switch to a necessary circuit configuration from time to time, like a virtual memory of a computer.

The above-described dynamic reconfigurable technique is disclosed in, for example, Patent Document 1.
Japanese Patent No. 3540796

  When an LSI is realized using the above-described dynamic reconfigurable technology, the clock used is usually different among the circuits to be mounted. For example, when switching between DES (Data Encryption Standard), JPEG (Joint Photographic Experts Group), and wireless LAN (Wireless Local Area Network) as an application, the circuits implemented to execute each application are efficiently used. The clock signals for operating each are different. Even in the same application, it may be preferable in terms of power consumption or the like to change the clock signal depending on the mode and situation. For this reason, a circuit that stops, inverts, and divides the clock signal, or switches to a different clock signal and supplies it to each circuit is required.

  However, the conventional clock supply circuit has a problem that a hazard occurs in the clock signal when switching to a different clock signal or when the clock signal is inverted. For this reason, a circuit that is not initialized after the circuit configuration is changed cannot be mounted. Further, the circuit configuration cannot be quickly changed by the method of changing the circuit configuration after stopping the clock signal so as not to cause the hazard and then shifting to the return operation.

  Further, as another method, there is a method in which only a circuit that operates with clock signals having the same frequency and the same phase is mounted without providing a clock signal switching mechanism. However, with this method, it is not possible to implement hardware that is as efficient as an FPGA, and the applications that can be used are limited.

  The present invention has been made in view of the above problems, and an object thereof is to provide a small-sized and simple clock supply circuit capable of seamless switching of clock signals, and a clock supply method thereof.

In order to achieve the above object, a clock supply circuit according to a first aspect of the present invention includes:
A multiplexer that outputs a clock signal designated by the clock designation signal among the plurality of supplied clock signals in response to the clock designation signal;
In response to the clock inversion signal, the clock inversion unit outputs the clock signal output from the multiplexer as it is or by inverting the signal level;
An output stop signal for instructing a timing for stopping the output of the clock signal and a timing for releasing the stop of the output of the clock signal, and a clock signal output by the clock inverting unit are supplied, and the output stop signal indicates A mask signal generation unit that generates a mask signal for masking the clock signal output from the clock inversion unit by synchronizing the stop timing and the release timing with the edge of the clock signal, respectively.
A mask unit that generates a masked clock signal by masking the clock signal output from the clock inversion unit with the mask signal generated by the mask signal generation unit, and supplies the masked clock signal to the hardware;
It is characterized by comprising.

  The mask signal generation unit includes a first D flip-flop of an edge trigger type having a data input terminal, a clock input terminal, and a data output terminal, respectively, and has a trigger polarity opposite to that of the first D flip-flop. The second D flip-flop of the edge trigger type is provided, and the first and second D flip-flops are supplied with the clock signal output from the clock inverting unit from the clock input terminal, and the first D flip-flop is the data An output stop signal is supplied from the input terminal, a signal output from the data output terminal of the first D flip-flop is supplied from the data input terminal to the second D flip-flop, and a data output terminal is supplied to the second D flip-flop. May output a mask signal.

  The output stop signal has a predetermined setup time at a time obtained by multiplying the period of the first clock signal by 1.5 when the clock designation signal instructs switching from the first clock signal to the second clock signal. The stop timing is instructed as a stop timing for a time that is equal to or longer than the time obtained by adding TsetupA and the predetermined hold time TholdB, and after the time that is equal to or longer than the time that the predetermined hold time TholdD is added to the predetermined setup time TsetupC. The timing may be designated as the release timing.

  When the clock stop signal instructs the clock inversion signal to invert the signal level of the clock signal or to cancel the inversion of the signal level, the output stop signal has a cycle of the clock signal of 1 than the timing of the instruction. The stop timing is designated as a timing that is more than the time obtained by adding the predetermined setup time TsetupA and the predetermined hold time TholdB to the time multiplied by 5 times, and the predetermined hold time TholdD is set to the predetermined setup time TsetupC from the timing of the previous instruction. You may instruct | indicate the timing which added time passed as a cancellation | release timing.

A stop signal generator for generating the output stop signal in response to a clock switching instruction signal for instructing switching of the clock signal;
A clock designation signal generation unit that generates the clock designation signal in response to the clock switching instruction signal;

The stop signal generator is supplied with a first delay circuit that delays and outputs the supplied clock switching instruction signal, and the clock switching instruction signal and the signal output from the first delay circuit. A coincidence circuit for generating an output stop signal instructing a timing at which the signal level of the generated signal changes from a matching state to a mismatching state as a stop timing, and a timing at which the signal level changes from a mismatching state to a matching state as a release timing; With
The clock designation signal generation unit may include a second delay circuit that delays the supplied clock switching instruction signal and outputs the delayed clock designation signal as a clock designation signal.

A frequency-divided clock generation signal generation unit that divides the clock signal to generate a frequency-divided clock generation signal;
The mask signal generation unit is supplied with the divided clock generation signal generated by the divided clock generation signal generation unit and the clock signal output by the clock inversion unit, instead of the output stop signal. The mask signal may be generated by synchronizing the edge of the peripheral clock generation signal with the edge of the clock signal.

The frequency-divided clock generating signal generator is
A counter that counts the edges of the clock signal and outputs the count value as digital data;
Based on the digital data output from the counter, a signal generation unit that generates and outputs a divided clock generation signal obtained by dividing the clock signal;
A register that outputs a reset value indicating a count value for resetting the counter;
The reset value output from the register is compared with the count value indicated by the digital data output from the counter, and if the reset value and the count value match, a reset signal for resetting the counter is output to the counter. And a comparison unit.

  In order to use the clock signal supplied from the previous clock supply circuit as the clock signal supplied to the dynamic reconfigurable hardware, the previous clock supply circuit may be incorporated in the dynamic reconfigurable circuit.

In order to achieve the above object, a clock supply method according to a second aspect of the present invention includes:
A designated clock output step for outputting a clock signal designated by the clock designation signal among the plurality of supplied clock signals in response to the clock designation signal;
In response to the clock inversion signal, the clock inversion step for outputting the clock signal output in the designated clock output step as it is or by inverting the signal level;
A mask for generating a mask signal by synchronizing the timing of stopping the output of the clock signal indicated by the output stop signal and the timing of releasing the stop of the output of the clock signal with the edge of the clock signal output in the clock inversion step, respectively. A signal generation step;
A mask step of generating a masked clock signal by masking the clock signal output in the clock inversion step with the mask signal generated in the mask signal generation step;
A clock signal supplying step of supplying the masked clock signal generated in the masking step to hardware;
It is characterized by comprising.

  According to the clock supply circuit and the clock supply method according to the present invention, it is possible to supply various clock signals and seamlessly switch them with a small and simple circuit.

  The configuration and operation of the clock supply circuit according to the embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of a system to which a clock supply circuit 100 according to an embodiment of the present invention is applied.

  The clock supply circuit 100 is a circuit that supplies a clock signal to the dynamic reconfigurable hardware 200 based on the control signal supplied from the control signal generation unit 700.

  The clock supply circuit 100 receives a system clock CLK_SYS from the system clock generator 300, a first clock signal CLK_IA from the first clock signal generator 400, and a second clock signal CLK_IB from the second clock signal generator 600, respectively. Supplied as a signal.

  The clock supply circuit 100 also includes a stop signal STOP for stopping the clock signal from the control signal generator 700, a clock designation signal SEL for designating a specific clock signal from a plurality of clock signals, and the signal level of the clock signal. And a clock inversion signal INVERT for instructing whether or not to invert the signal. Further, the clock supply circuit 100 is supplied with the divided clock generation signal CLK_DIV from the divided clock generation signal generation unit 500. The clock supply circuit 100 supplies the output clock CLK_O generated based on these clock signals and control signals to the dynamic reconfigurable hardware 200.

  The clock supply circuit 100 directly supplies the system clock CLK_SYS supplied from the system clock generation unit 300 to the dynamic reconfigurable hardware 200.

  The dynamically reconfigurable hardware 200 executes an application corresponding to the circuit configuration while dynamically switching the circuit configuration (hardware configuration).

  In the dynamically reconfigurable hardware 200, the circuit for each application is operated by the output clock CLK_O supplied from the clock supply circuit 100. Note that the circuit portion that does not depend on the application is operated by the system clock CLK_SYS supplied from the clock supply circuit 100.

  The system clock generator 300 is a circuit that generates the system clock CLK_SYS, the first clock signal generator 400 is a circuit that generates the first clock signal CLK_IA, and the second clock signal generator 600 is This is a circuit for generating the second clock signal CLK_IB. Each of these circuits includes an oscillation circuit using a crystal oscillator or the like. A PLL (Phase Locked Loop) circuit or the like may be included.

  The system clock generation unit 300 supplies the generated system clock CLK_SYS to the clock supply circuit 100 and the control signal generation unit 700. The first clock signal generation unit 400 supplies the generated first clock signal CLK_IA to the clock supply circuit 100 and the divided clock generation signal generation unit 400. The second clock signal generation unit 600 supplies the generated second clock signal CLK_IB to the clock supply circuit 100.

  The frequency-divided clock generation signal generation unit 500 generates a frequency-divided clock generation signal CLK_DIV from the first clock signal CLK_IA supplied from the first clock signal generation unit 400 and supplies it to the clock supply circuit 100. Details of the frequency-divided clock generation signal generator 500 will be described later.

  The control signal generation unit 700 generates each control signal and supplies it to the clock supply circuit 100 in order for the clock supply circuit 100 to realize seamless switching of the clock signal. Specifically, the control signal generation unit 700 generates a stop signal STOP, a clock designation signal SEL, and a clock inversion signal INVERT based on the system clock CLK_SYS supplied from the system clock generation unit 400, and supplies the clock. Supply to circuit 100. The control signal generation unit 700 includes a CPU and the like.

  Next, the configuration of the clock supply circuit 100 according to the embodiment of the present invention will be described in detail with reference to FIG.

  As shown in FIG. 2, the clock supply circuit 100 includes a multiplexer 110, an inverting circuit 120, D flip-flops 130 and 131, and an AND gate 140.

  The multiplexer 110 outputs one of the clock signals supplied from the two input terminals from the output terminal based on the signal supplied to the control terminal. The multiplexer 110 includes a logic gate and the like, and includes two input terminals, one output terminal, and one control terminal. One input terminal is connected to the first clock signal generation unit 400, and the other input terminal is connected to the second clock signal generation unit 600. The control terminal is connected to the control signal generation unit 700, and the output terminal is connected to the input terminal of the inverting circuit 120.

  The multiplexer 110 is supplied with the first clock signal CLK_IA from one input terminal, the second clock signal CLK_IB from the other input terminal, and the clock designation signal SEL from the control terminal. The multiplexer 110 outputs the first clock signal CLK_IA as the first intermediate clock signal CLK_M1 when the clock designation signal SEL supplied to the control terminal is at the H level and the second clock signal CLK_IB when the clock designation signal SEL is at the L level. Output from the terminal.

  The inverting circuit 120 outputs the clock signal supplied from the input terminal as it is or after inverting it based on the signal supplied from the inverting control terminal. The inverting circuit 120 includes a logic gate XNOR and the like, and includes one input terminal, one output terminal, and one inversion control terminal.

  The input terminal is connected to the output terminal of the multiplexer 110, and the inversion control terminal is connected to the control signal generator 700. The output terminal is connected to the clock input terminal of the D flip-flop 130, the clock input terminal of the D flip-flop 131, and one input terminal of the AND gate 140.

  The inverting circuit 120 is supplied with the first intermediate clock signal CLK_M1 from the input terminal, and is supplied with the clock inversion signal INVERT from the inverting control terminal. Further, the inverting circuit 120 outputs the second intermediate clock signal CLK_M2 from the output terminal. The inverting circuit 120 outputs the first intermediate clock signal CLK_M1 as it is from the output terminal when the clock inversion signal INVERT is at the H level, and inverts the first intermediate clock signal CLK_M1 when it is at the L level and outputs it from the output terminal. To do.

  The D flip-flop 130 is a flip-flop that outputs the held internal data from the output terminal, and the internal data is updated with the data supplied from the input terminal at every rising edge of the signal supplied from the clock input terminal. The D flip-flop 130 includes a logic gate and the like, and includes one data input terminal, one clock input terminal, and one output terminal.

  The data input terminal is connected to the control signal generation unit 700, the clock input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is connected to the data input terminal of the D flip-flop 131.

  The D flip-flop 130 is supplied with the stop signal STOP from the data input terminal and is supplied with the second intermediate clock signal CLK_M2 from the clock input terminal. The D flip-flop 130 outputs a synchronization stop signal STOP_S, which is a signal obtained by synchronizing the stop signal STOP with the rising edge of the second intermediate clock signal CLK_M2, from the output terminal.

  The D flip-flop 131 has substantially the same configuration as the D flip-flop 130, but the clock input terminal is an inverting input terminal. Therefore, the internal data of the D flip-flop 131 is updated at every falling edge of the signal supplied to the clock input terminal.

  The data input terminal is connected to the output terminal of the D flip-flop 130, the clock input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is connected to one input terminal of the AND gate 140.

  The D flip-flop 131 is supplied with the synchronization stop signal STOP_S from the data input terminal and supplied with the second intermediate clock signal CLK_M2 from the clock input terminal. Further, the D flip-flop 131 outputs a mask signal MASK, which is a signal obtained by synchronizing the synchronization stop signal STOP_S with the falling edge of the second intermediate clock signal CLK_M2, from the output terminal.

  The AND gate 140 is a logic gate that calculates a logical product of values corresponding to signals input from two input terminals and outputs a signal corresponding to the calculated logical product from an output terminal. The AND gate 140 includes two input terminals and one output terminal.

  One data input terminal is connected to the output terminal of the D flip-flop 131, the other input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is a clock input (not shown) of the dynamic reconfigurable hardware 200. Connected to the terminal.

  The AND gate 140 is supplied with a mask signal MASK from one data input terminal and supplied with a second intermediate clock CLK_M2 from the other input terminal. The AND gate 140 outputs an output clock CLK_O, which is a clock obtained by masking the second intermediate clock CLK_M2 with the mask signal MASK, from the output terminal.

  The clock supply circuit 100 outputs the system clock CLK_SYS supplied from the system clock generation unit 300 directly to the dynamic reconfigurable hardware 200.

(Clock signal stop operation)
Next, the operation of stopping the clock signal using the clock supply circuit shown in FIG. 2 will be described with reference to the time chart shown in FIG. 3, 5, 6, 8, and 11 are time charts assuming that there is no setup time, hold time, and path delay for easy understanding.

  First, each signal shown in the time chart of FIG. 3 will be briefly described. In order to facilitate understanding, the clock designation signal SEL is fixed at the H level (first clock signal CLK_IA is designated), and the clock inversion signal INVERT is fixed at the H level (no inversion). Therefore, the first intermediate clock signal CLK_M1 and the second intermediate clock signal CLK_M2 are not shown in FIG. 3 because they are the same signal as the first clock signal CLK_IA.

  The first clock signal CLK_IA is a clock signal having a frequency different from that of the second clock signal CLK_IB, and is continuously supplied from one input terminal of the multiplexer 110.

  The stop signal STOP and the synchronization stop signal STOP_S are signals for generating the mask signal MASK. The mask signal MASK is a signal for masking the output clock CLK_O in order to stop the output of the output clock CLK_O when the clock signal is being switched or when the clock signal is unnecessary as an application. The stop signal STOP, the synchronization stop signal STOP_S, and the mask signal MASK are turned off at H level (no masking) and turned on at L level (masked).

  The output clock CLK_O is a clock signal that is supplied from the clock supply circuit 100 to the dynamic reconfigurable hardware 200.

  Next, the operation of the clock supply circuit 100 at each time will be described.

  Until the time t1, the stop signal STOP is at the L level. Therefore, the synchronization stop signal STOP_S and the mask signal MASK are all at the L level. Since the mask signal MASK is at L level, the AND gate 140 outputs a signal at L level as the output clock CLK_O.

  At time t1, the control signal generator 700 sets the stop signal STOP to the H level.

  When the time reaches t2, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes H level.

  When the time reaches t3, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes H level. Therefore, the masking by the mask signal MASK is released, and the AND gate 140 outputs the first clock signal CLK_IA (second intermediate clock CLK_M2) as the output clock CLK_O.

  When the time reaches t4, the control signal generator 700 sets the stop signal STOP to the L level.

  When the time reaches t5, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes L level.

  When the time reaches t6, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes L level. Therefore, the AND gate 140 outputs an L level signal as the output clock CLK_O.

  As described above, when the control signal generation unit 700 changes the level of the stop signal STOP, the clock supply circuit 100 can stop the output of the output clock CLK_O without causing a hazard. According to this circuit configuration, the level of the stop signal STOP may be changed asynchronously with the first clock signal CLK_IA.

(Divided clock generation operation)
Next, the operation of generating a divided clock using the clock supply circuit shown in FIG. 2 will be described. First, the configuration of the divided clock generation signal generation unit 500 will be described in detail with reference to FIG.

  The frequency division clock generation signal generation unit 500 generates a frequency division clock generation signal using the supplied clock signal.

  As illustrated in FIG. 4, the divided clock generation signal generation unit 500 includes a counter 510, a signal generation circuit 520, a comparison circuit 530, and a register 540.

  The counter 510 is a counter with a synchronous reset terminal that counts the rising edge of the supplied clock signal and outputs it as a 4-bit value. The counter 510 is composed of, for example, four T flip-flops.

  The counter 510 is supplied with the first clock signal CLK_IA from the first clock signal generation unit 400 and the reset signal RST from the comparison circuit 530. The counter 510 outputs a 4-bit digital signal to the signal generation circuit 520 and the comparison circuit 530.

  The signal generation circuit 520 generates a divided clock generation signal CLK_DIV from the digital signal supplied from the counter 510 and outputs it to the clock supply circuit 100. The signal generation circuit 520 includes a logic gate and the like, and generates a divided clock generation signal CLK_DIV by taking an AND or OR of an arbitrary digital signal among 4-bit digital signals. This circuit can be realized by a 4-input OR circuit for detecting 0 if only N: 1 frequency division is made.

  The signal generation circuit 520 is supplied with a 4-bit digital signal from the counter 510, and outputs the generated divided clock generation signal CLK_DIV to the clock supply circuit 100.

  The comparison circuit 530 compares the value of the digital signal supplied from the counter 510 with the value of the digital signal supplied from the register 540, and outputs a reset signal to the counter 510 if they match. The comparison circuit 530 includes a logic gate.

  The comparison circuit 530 is supplied with 4-bit digital signals from the counter 510 and the register 540 and outputs a reset signal RST to the counter 510.

  The register 540 supplies a 4-bit digital signal to the comparison circuit 530. The register 540 is composed of, for example, a flip-flop, and is a 4-bit general-purpose register in which data can be written from a CPU (not shown) via a bus.

  Next, the operation of the divided clock generation signal generator 500 will be described.

  The counter 510 is supplied with the first clock signal CLK_IA from the first clock signal generator 400. The counter 510 counts at the rising edge of the supplied clock signal.

  Here, a CPU (not shown) writes “0011” as 4-bit digital data in the register 540 in advance. Then, after the value of the digital signal supplied from the counter 510 becomes “0011”, the comparison circuit 530 outputs the reset signal RST to the counter 510. Then, the value of the flip-flop in the counter 510 is cleared, and as a result, a clock signal divided by 4 is generated.

  Note that when the value to be reset is “0011”, the frequency is divided by 4. However, the signal generation circuit 520 performs logical OR of 4 bits in order to detect 0, so that one clock as shown in FIG. The divided clock generation signal CLK_DIV is obtained. If this circuit configuration is used, it is possible to switch to a clock signal having an arbitrary division ratio without any hazard by switching the register value.

  Next, a frequency-divided clock generation operation using the clock supply circuit 100 shown in FIG. 2 will be described using the time chart shown in FIG. However, in the operation of generating the divided clock, the divided clock generation signal CLK_DIV is supplied to the clock supply circuit 100 instead of the stop signal STOP for easy understanding. In the control signal generation unit 700 and the clock supply circuit 100, the stop signal STOP and the divided clock generation signal CLK_DIV are ANDed, and the obtained signal is used as the stop signal STOP in the clock supply circuit 100. Also good. Similar to the clock signal stop operation, the clock designation signal SEL is fixed at the H level (first clock signal CLK_IA is designated), and the clock inversion signal INVERT is fixed at the H level (no inversion).

  Until the time t1, the frequency-divided clock generation signal CLK_DIV is at the L level, and therefore the synchronization stop signal STOP_S and the mask signal MASK are all at the L level. Since the mask signal MASK is at L level, the AND gate 140 outputs a signal at L level as the output clock CLK_O.

  At time t1, the divided clock generation signal CLK_DIV supplied from the divided clock generation signal generation unit 500 becomes H level.

  When the time reaches t2, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes H level.

  When the time reaches t3, the divided clock generation signal CLK_DIV supplied from the divided clock generation signal generation unit 500 becomes L level.

  When the time reaches t4, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes H level. Therefore, the masking by the mask signal MASK is released, and the AND gate 140 outputs the first clock signal CLK_IA (second intermediate clock CLK_M2) as the output clock CLK_O.

  When the time reaches t5, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes L level.

  When the time reaches t6, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes L level. Therefore, the AND gate 140 outputs an L level signal as the output clock CLK_O.

  As described above, the divided clock (output clock CLK_O) obtained by masking the first clock signal CLK_IA with the mask signal MASK based on the divided clock generation signal CLK_DIV supplied from the divided clock generation signal generation unit 500 is dynamically generated. It can be supplied to the reconfigurable hardware 200. Note that, even in the case where the frequency division ratio is changed in the frequency division clock generation signal generation unit 500, it is possible to supply the clock signal switched without any hazard. The subsequent circuit to which the output clock CLK_O is supplied has a pulse width (when the frequency of the second intermediate clock CLK_M2 is the highest and the frequency is not divided when the clock pulse width of the output clock CLK_O is the shortest (in other words, Design in advance so as to operate normally with the minimum pulse width. By doing so, even if the DUTY ratio is changed by changing the frequency division ratio, the pulse width does not become smaller than the minimum pulse width, and the subsequent circuit operates without any problem.

(Switching operation to different clock signal)
Next, a switching operation to a different clock signal using the clock supply circuit shown in FIG. 2 will be described using the time chart shown in FIG. For easy understanding, the clock inversion signal INVERT is fixed at the H level (no inversion). Therefore, the first intermediate clock CLK_M1 is not shown in FIG. 6 because it is the same signal as the second intermediate clock CLK_M2.

  First, each signal shown in the time chart of FIG. 6 will be briefly described. The explanation of the already explained signals is omitted here.

  The second clock signal CLK_IB is a clock signal that is asynchronous with the first clock signal CLK_IA and is continuously supplied from the other input terminal of the multiplexer 110. The clock designation signal SEL is a signal that designates one of the first clock signal CLK_IA and the second clock signal CLK_IB.

  Next, the operation of the clock supply circuit 100 at each time will be described.

  Until the time t1, the stop signal STOP is at the H level, and therefore the synchronization stop signal STOP_S and the mask signal MASK are all at the H level. Since the clock designation signal SEL is at the H level, the first clock signal CLK_IA is output as it is as the second intermediate clock CLK_M2. Since the mask signal MASK is at the H level, the AND gate 140 outputs the first clock signal CLK_IA as the output clock CLK_O.

  At time t1, the control signal generator 700 sets the stop signal STOP to the L level.

  When the time reaches t2, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes L level.

  When the time reaches t3, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes L level. For this reason, the AND gate 140 is in a state of not outputting the output clock CLK_O.

  When the time reaches t4, the control signal generation unit 700 sets the clock designation signal SEL to the L level. For this reason, the second intermediate clock CLK_M2 is switched to the second clock signal CLK_IB.

  When the time reaches t5, the control signal generator 700 sets the stop signal STOP to the H level.

  When the time reaches t6, a rising edge of the second intermediate clock CLK_M2 (second clock signal CLK_IB) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes H level.

  When the time reaches t7, a falling edge of the second intermediate clock CLK_M2 (second clock signal CLK_IB) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes H level. Therefore, the AND gate 140 outputs the second clock signal CLK_IB as the output clock CLK_O.

  As described above, even when the control signal generation unit 700 changes the levels of the stop signal STOP and the clock designation signal SEL asynchronously with respect to the first clock signal CLK_IA and the second clock signal CLK_IB, the following description will be given. By keeping the switching time, the clock signal supplied to the dynamic reconfigurable hardware 200 can be switched seamlessly.

  Next, switching time to a different clock signal will be described.

  FIG. 7 is a time chart for explaining the switching time when switching to a different clock signal using the clock supply circuit shown in FIG.

  As described above, the clock signal can be switched without causing a hazard in the output clock CLK_O by switching the level of the clock designation signal SEL while the mask signal MASK is at the L level. Here, the time until the stop signal STOP is set to the L level and the stop signal STOP is set to the H level again is the switching time T.

  First, under the condition that no hazard is generated, the minimum necessary switching time T is maximized from the rising edge (time = t2) of the second intermediate clock CLK_M2 (first clock signal CLK_IA). The stop signal STOP is set to the L level at a time before the time TsetupA (time = t1), and a time (time = t5) after the hold time ToldB from the falling edge (time = t4) 1.5 cycles after the rising edge. ) When the clock designation signal SEL is set to the L level. The reason will be described below.

  If the rising edge and the falling edge of the second intermediate clock CLK_M2 occur in order after the stop signal STOP is set to the L level, the mask signal MASK becomes the L level. In order to generate these two edges, a time corresponding to 1.5 periods of the second intermediate clock CLK_M2 is required. However, strictly speaking, it is necessary to consider the setup time TsetupA and the hold time TholdB.

Here, the setup time TsetupA is a time when data must be input earlier with respect to the clock in order to satisfy the setup margin of the flip-flop. The setup time TsetupA can be expressed as shown in Equation (1).
(Equation 1)
TsetupA = StopDelay1 + SetupMargin−CLK_IADelay1 (1)

  Note that StopDelay1 is a propagation time (delay time) until the stop signal STOP propagates from an appropriate point on the system clock CLK_SYS to the D flip-flop 130. SetupMargin is a setup margin of the D flip-flop 130. CLK_IADelay1 is a propagation time (delay time) until the first clock signal CLK_IA propagates from an appropriate point to the D flip-flop 130.

  Here, for example, if the stop signal STOP is set to L level at a time when the setup time TsetupA can be secured (before time = t1), the synchronization stop signal STOP_S is surely set to L level at the immediately following rising edge (time t = 2). be able to. Therefore, the minimum necessary switching time T is maximized when the synchronization stop signal STOP_S is set to L level after one clock from the time when the setup time TsetupA cannot be secured.

The hold time TholdB is a time that satisfies the pulse width limitation defined for each library of flip-flops and that data must be delayed with respect to the clock in order to ensure the MASK processing by the AND gate 140 with certainty. . The hold time TholdB can be expressed as shown in Expression (2).
(Equation 2)
TholdB = CLK_IADelay2 + CLKPulseLimit1-SelDelay1 (2)

  CLK_IADelay2 is a propagation time (delay time) until the first clock signal CLK_IA propagates from the appropriate point to the multiplexer 110. CLKPulseLimit1 is a pulse width limitation of the D flip-flops 130 and 131. SelDelay1 is a propagation time (delay time) until the clock designation signal SEL propagates from the appropriate point on the system clock CLK_SYS to the multiplexer 110.

  Here, when CLKPulseLimit1 is not satisfied, the second intermediate clock CLK_M2 is switched before the output of the D flip-flop 131 is switched to the L level and is stabilized, and an irregular clock signal is supplied to the clock input terminal of the D flip-flop 131. Is done. For this reason, it is not guaranteed that the mask signal MASK will become L level at the expected timing, and normal mask operation by the AND gate 140 at the subsequent stage is not guaranteed.

  If the clock designation signal SEL is set to L level at a time when the hold time TholdB cannot be secured (before time = t5), the second intermediate clock CLK_M2 is switched before the mask signal MASK becomes L level, and the output is performed. A hazard may propagate to the clock CLK_O. Therefore, the case where the clock designation signal SEL is set to the L level at a time when the hold time TholdB can be ensured at the very limit is a limit that does not cause a hazard.

  Further, when considering the time from when the clock designation signal SEL is set to L level to when the stop signal STOP is returned to H level, it is necessary to consider the setup time TsetupC and the hold time TholdD.

Here, the setup time TsetupC is a time that satisfies the pulse width limitation defined for each library of flip-flops, and that the data must be input early with respect to the clock in order to ensure the MASK processing by the AND gate 140. is there. The setup time TsetupC can be expressed as Equation (3).
(Equation 3)
TsetupC = SelDelay2 + CLKPulseLimit2-CLK_IBDelay1 (3)

  SelDelay2 is a propagation time (delay time) until the clock designation signal SEL propagates from the appropriate point on the system clock CLK_SYS to the multiplexer 110. CLKPulseLimit2 is a pulse width limitation of the D flip-flops 130 and 131. Further, CLK_IBDelay1 is a propagation time (delay time) until the second clock signal CLK_IB propagates from the appropriate point to the multiplexer 110.

  Here, it is assumed that the input data of the D flip-flop 131 does not change, and the output is stable in a general flip-flop library. Therefore, CLKPulseLimit2 is used to remove the edge generated by switching the multiplexer from the clock edge. Usually, it should be 0 or more so as to ensure that there is nothing. However, CLKPulseLimit2 is set when it is necessary to define it by a library such as a flip-flop or an AND gate to be used.

  If the clock designation signal SEL is set to L level at a time when the setup time TsetupC cannot be secured (after time = t5), the mask signal MASK becomes H level before the second intermediate clock CLK_M2 is switched, and output A hazard may propagate to the clock CLK_O. Therefore, the case where the clock designation signal SEL is set to the L level at a time when the setup time TsetupC can be secured at the limit is a limit that does not cause a hazard.

The hold time TholdD is a time during which data must be delayed with respect to the clock in order to satisfy the hold margin of the flip-flop. The hold time TholdD can be expressed as shown in Equation (4).
(Equation 4)
TholdD = CLK_IBDelay2 + HoldMargin−StopDelay2 (4)

  Note that CLK_IBDelay2 is a propagation time (delay time) until the second clock signal CLK_IB propagates from an appropriate point to the D flip-flop 130. HoldMargin is a hold margin of the D flip-flop 130. Further, StopDelay2 is a propagation time (delay time) until the stop signal STOP is propagated from an appropriate point on the system clock CLK_SYS to the D flip-flop 130.

  Note that when the stop signal STOP is set to H level at a time when the hold time TholdD cannot be secured (before time = t7), the immediately preceding falling edge (time = t6: where a rising edge occurs simultaneously due to a hazard by the clock designation signal SEL) Assuming that the synchronization stop signal STOP_S and the mask signal MASK change at the same time), the mask signal MASK changes during an unstable clock period immediately after the clock switching, and the mask release operation is not performed at a normal timing, and output A hazard may propagate to the clock CLK_O. Therefore, when the stop signal STOP is set to the H level at a time when the hold time TholdD can be secured at the very limit, there is a limit that the mask can be released.

Therefore, when the minimum value of the switching time T under the condition that no hazard is generated is the minimum time Tmin, the cycle of the first clock signal CLK_IA is Ta and the equation (5) is obtained.
(Equation 5)
Tmin = Ta × 1.5 + TsetupA + ToldB + TsetupC + ToldD (5)

The switching time T can be expressed as Equation (6) using the switching time T1 and the switching time T2. Hereinafter, a description will be given of how to obtain the minimum values of the switching time T1 and the switching time T2 that can set the switching time T to the minimum under the condition that no hazard is generated.
(Equation 6)
T = T1 + T2 (6)

First, the switching time T1 will be described. The switching time T1 is a time from when the stop signal STOP is set to L level to when the clock designation signal SEL is switched. When the minimum value of the switching time T1 under the condition that does not cause a hazard is the minimum switching time T1min, the equation (7) is obtained.
(Equation 7)
T1min = Ta × 1.5 + TsetupA + ToldB (7)

  When the switching time T1 is smaller than the minimum switching time T1min, for example, when the clock designation signal SEL is switched between time = t4 and time = t5, the hold time TholdB from t4 is not secured, and the output clock CLK_O Hazard may propagate.

Next, the switching time T2 will be described. The switching time T2 is a time from when the clock designation signal SEL is switched to when the stop signal STOP is set to the H level. If the minimum value of the switching time T2 under the condition that does not cause a hazard is the minimum switching time T2min, the equation (8) is obtained.
(Equation 8)
T2min = TsetupC + ToldD (8)

  When the switching time T2 is smaller than the minimum switching time T2min, for example, when the clock designation signal SEL is switched between time = t6 and time = t7, the hold time TholdD until t6 is not secured and the output clock CLK_O Hazard may propagate.

  Here, “TsetupA + ToldB” on the right side of Equation (7) includes −term CLK_IADelay1 and + term CLK_IADelay2 as the delay time of the first clock signal CLK_IA, and cancel each other out. For this reason, the starting point of the delay time of the first clock signal CLK_IA may be anywhere.

  Similarly, “TsetupC + ToldD” on the right side of Equation (8) includes −term CLK_IBDelay1 and + term CLK_IBDelay2 as the delay time of the second clock signal CLK_IB, and cancel each other out. For this reason, the origin of the delay time of the second clock signal CLK_IB may be anywhere.

  Also, “TsetupA + ToldB” on the right side of Expression (7) includes StopDelay 1 in the + term and SelDelay 1 in the − term as data delay times. In addition, “TsetupC + ToldD” on the right side of Expression (8) includes + term SelDelay2 and −term StopDelay2 as data delay times. Here, the clocks of the flip-flops that generate the stop signal STOP and the clock designation signal SEL are both the system clock CLK_SYS. For this reason, if the time before the point where the clocks input to the respective flip-flops join is set as the starting point of the delay time, the starting point may be set anywhere.

  Further, the setup time TsetupA and the hold time TholdD are simply offset by the specifications of the system clock CLK_SYS and the second intermediate clock CLK_M2 (because they are canceled by the setup time + hold time, the origin of an arbitrary clock signal that does not need to be specifically limited). The setup time and hold time in the D flip-flop 130 at the time of setting can be defined. The hold time TholdB and the setup time TsetupC are the same values, the second value that can be obtained from the pulse width that guarantees the operation immediately before and after the mask generation unit AND gate 140 and the clock input unit of the D flip-flops 130 and 131. It is defined as the minimum time interval for the edge of the intermediate clock CLK_M2.

  The control signal generator 700 can switch the clock signal in the minimum time without generating a hazard by providing each control signal with a switching time as shown in equations (7) and (8). Become.

  Specifically, since the system clock CLK_SYS is supplied from the system clock generation unit 300 to the control signal generation unit 700, the signal is delayed by a predetermined clock by counting it with a counter.

That is, assuming that the period of the system clock CLK_SYS is Tsys, a minimum integer n that satisfies the equation (9) and a minimum integer m that satisfies the equation (10) are obtained. Then, after setting the stop signal STOP to the L level, the system clock CLK_SYS is counted n times to change the clock designation signal SEL, and the signal is generated so as to count m times and return the stop signal STOP.
(Equation 9)
Ta × 1.5 + TsetupA + ToldB ≦ Tsys × n (9)
(Equation 10)
TsetupC + ToldD ≦ Tsys × m (10)

  In addition, regarding the setup times TsetupA and TsetupC and the hold times ThresholdB and ThresholdD, strictly speaking, it is necessary to consider the path delay, but the system clock CLK_SYS and the first clock signal CLK_IA are both synchronized at an appropriate point. If verification is performed, it can be easily obtained using a STA (Static Timing Analysis) tool or the like. This is because the clock delay is canceled because the calculation formula is obtained by adding the setup time and the hold time.

  In the above example, the time for switching the hardware configuration of the dynamic reconfigurable hardware 200 is not taken into consideration. However, if the synchronized mask signal MASK is used, there is no difficulty in switching in synchronization with this operation. .

(Clock signal inversion operation)
Next, the inversion operation of the clock signal in the clock supply circuit shown in FIG. 2 will be described using the time chart shown in FIG. For ease of understanding, the clock designation signal SEL is fixed at the H level (designation of the first clock signal CLK_IA). Therefore, the first intermediate clock CLK_M1 is not shown in FIG. 8 because it is the same signal as the first clock signal CLK_IA.

  First, each signal shown in the time chart of FIG. 8 will be briefly described. The explanation of the already explained signals is omitted here.

  The second intermediate clock CLK_M2 is a clock signal for generating the output clock CLK_O, and is the first intermediate clock CLK_M1 itself or a signal obtained by inverting the signal level. The clock inversion signal INVERT is a signal that specifies whether to invert the signal level of the first intermediate clock CLK_M1, and is supplied from the control signal generation unit 700.

  Next, the operation of the clock supply circuit 100 at each time will be described.

  Until the time t1, the stop signal STOP is at the H level, and therefore the synchronization stop signal STOP_S and the mask signal MASK are all at the H level. Since the clock inversion signal INVERT is at the H level, the first intermediate clock CLK_M1 (first clock signal CLK_IA) is output as it is as the second intermediate clock CLK_M2. Since the mask signal MASK is at the H level, the AND gate 140 outputs the first clock signal CLK_IA as the output clock CLK_O.

  At time t1, the control signal generation unit 700 sets the stop signal STOP to the L level.

  When the time reaches t2, a rising edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes L level.

  When the time reaches t3, a falling edge of the first clock signal CLK_IA (second intermediate clock CLK_M2) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes L level. Therefore, the AND gate 140 outputs an L level signal as the output clock CLK_O.

  When the time reaches t4, the control signal generation unit 700 sets the clock inversion signal INVERT to the L level. Therefore, the second intermediate clock CLK_M2 is switched to a clock signal obtained by inverting the first intermediate clock CLK_M1 (first clock signal CLK_IA).

  When the time reaches t5, the control signal generator 700 sets the stop signal STOP to the H level.

  At time t6, the rising edge of the second intermediate clock CLK_M2 (the falling edge of the first clock signal CLK_IA) occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes H level.

  When the time reaches t7, the falling edge of the intermediate clock CLK_M (the rising edge of the first clock signal CLK_IA) occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes H level. Therefore, the AND gate 140 outputs a clock obtained by inverting the first clock signal CLK_IA as the output clock CLK_O.

  As described above, even when the control signal generation unit 700 changes the level of the clock inversion signal INVERT asynchronously with the first clock signal CLK_IA, the clock signal supplied to the dynamic reconfigurable hardware 200 can be seamlessly inverted. Can do.

  Note that the inversion time of the clock signal can be considered in the same manner as the switching time to the above-described different clock signal. That is, the timing for changing the level of the clock inversion signal INVERT may be considered as the timing for changing the level of the clock designation signal SEL. Therefore, the description is omitted here.

(Modification)
In the above embodiment, the control signal generation unit 700 generates all of the stop signal STOP, the clock designation signal SEL, and the clock inversion signal INVERT as control signals, and supplies them to the clock supply circuit 100.

  However, for example, the stop signal STOP and the clock designation signal SEL can be generated by the clock supply circuit 101 based on the clock switching instruction signal SW_CLK that designates the timing of switching the clock signal and the type of the clock signal. is there. The configuration and operation of the clock supply circuit according to the modification will be described below.

  FIG. 9 is a configuration diagram of a system to which the clock supply circuit 101 according to the modification is applied.

  Only the control signal output from the control signal generation unit is different from the system shown in FIG.

  The control signal generation unit 701 supplies the clock switching instruction signal SW_CLK and the clock inversion signal INVERT to the clock supply circuit 101.

  Next, the configuration of the clock supply circuit 101 according to the modification will be described in detail with reference to FIG.

  As shown in FIG. 10, the clock supply circuit 101 includes a multiplexer 110, an inverting circuit 120, D flip-flops 130 and 131, an AND gate 140, a first delay circuit 150, and a second delay circuit 151. , XNOR gate 160.

  The description of the configuration of the multiplexer 110 is omitted here, and only the connection destination and operation of each terminal will be described. One input terminal is connected to the first clock signal generation unit 400, and the other input terminal is connected to the second clock signal generation unit 600. The control terminal is connected to the output terminal of the first delay circuit 151, and the output terminal is connected to the input terminal of the inverting circuit 120.

  The multiplexer 110 is supplied with the first clock signal CLK_IA from one input terminal, is supplied with the second clock signal CLK_IB from the other input terminal, and is supplied with the second delay signal DELAY2 from the control terminal.

  The multiplexer 110 uses the first clock signal CLK_IA as the first intermediate clock CLK_M1 when the second delay signal DELAY2 input to the control terminal is at the H level and the second clock signal CLK_IB when the second delay signal DELAY2 is at the L level. Output from the output terminal.

  The description of the configuration of the inverting circuit 120 is omitted here, and only the connection destination and operation of each terminal will be described. The input terminal is connected to the output terminal of the multiplexer 110, and the inversion control terminal is connected to the control signal generator 700. The output terminal is connected to the clock input terminal of the D flip-flop 130, the clock input terminal of the D flip-flop 131, and one input terminal of the AND gate 140.

  The inverting circuit 120 is supplied with the first intermediate clock signal CLK_M1 from the input terminal, and is supplied with the clock inversion signal INVERT from the inverting control terminal. The inverting circuit 120 outputs the second intermediate clock signal CLK_M2 from the output terminal.

  The inverting circuit 120 outputs the first intermediate clock signal CLK_M1 as it is from the output terminal when the clock inversion signal INVERT is at the H level, and inverts the first intermediate clock signal CLK_M1 when it is at the L level and outputs it from the output terminal. To do.

  The description of the configuration of the D flip-flop 130 is omitted here, and only the connection destination and operation of each terminal will be described. The data input terminal is connected to the output terminal of the XNOR gate 160, the clock input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is connected to the data input terminal of the D flip-flop 131.

  The D flip-flop 130 is supplied with the stop signal STOP from the data input terminal and is supplied with the second intermediate clock CLK_M2 from the clock input terminal. The D flip-flop 130 outputs a synchronization stop signal STOP_S from the output terminal.

  The description of the configuration of the D flip-flop 131 is omitted here, and only the connection destination and operation of each terminal will be described. The data input terminal is connected to the output terminal of the D flip-flop 130, the clock input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is connected to one input terminal of the AND gate 140.

  The D flip-flop 131 is supplied with the synchronization stop signal STOP_S from the data input terminal and supplied with the second intermediate clock CLK_M2 from the clock input terminal. The D flip-flop 131 outputs a mask signal MASK from the output terminal.

  The description of the configuration of the AND gate 140 is omitted here, and only the connection destination and operation of each terminal will be described. One data input terminal is connected to the output terminal of the D flip-flop 131, the other input terminal is connected to the output terminal of the inverting circuit 120, and the output terminal is a clock input (not shown) of the dynamic reconfigurable hardware 200. Connected to the terminal.

  The AND gate 140 is supplied with a mask signal MASK from one data input terminal and supplied with a second intermediate clock CLK_M2 from the other input terminal. The AND gate 140 outputs an output clock CLK_O, which is a clock signal obtained by masking the second intermediate clock CLK_M2 with the mask signal MASK, from the output terminal.

  The first delay circuit 150 is a delay circuit including a counter, a D flip-flop, a D latch, a logic gate constituting a memory, and the like. The first delay circuit 150 includes one input terminal, one clock input terminal, and one output terminal. The first delay circuit 150 delays the signal supplied to the input terminal by the first delay time D1 and outputs the signal from the output terminal.

  The input terminal is connected to the control signal generation unit 701, the clock input terminal is connected to the system clock generation unit 300, and the output terminal is connected to one input terminal of the XNOR gate 160.

  The first delay circuit 150 is supplied with a clock switching instruction signal SW_CLK from an input terminal and is supplied with a system clock CLK_SYS from a clock input terminal. The first delay circuit 150 outputs the first delay signal DELAY1 obtained by delaying the clock switching instruction signal SW_CLK by the first delay time D1 from the output terminal.

  The second delay circuit 151 is a delay circuit that delays the signal supplied from the input terminal by the second delay time D2 and outputs the signal from the output terminal. The second delay circuit 151 has the same configuration as the first delay circuit 150, but has a different delay time.

  The input terminal is connected to the control signal generation unit 701, the clock input terminal is connected to the system clock generation unit 300, and the output terminal is connected to the control terminal of the multiplexer 110.

  The second delay circuit 151 is supplied with the clock switching instruction signal SW_CLK from the input terminal and is supplied with the system clock CLK_SYS from the clock input terminal. The second delay circuit 151 outputs a second delay signal DELAY2 obtained by delaying the clock switching instruction signal SW_CLK by the second delay time D2 from the output terminal.

  The XNOR gate 160 is a logic gate that calculates an exclusive OR of values corresponding to signals supplied from two input terminals and outputs a signal corresponding to a value obtained by inverting the obtained exclusive OR from an output terminal. . The XNOR gate 160 has two input terminals and one output terminal.

  One input terminal is connected to the control signal generator 701, the other input terminal is connected to the output terminal of the first delay circuit 150, and the output terminal is connected to the data input terminal of the D flip-flop 130. .

  The XNOR gate 160 is supplied with a clock switching instruction signal SW_CLK from one input terminal and is supplied with a first delay signal DELAY1 from the other input terminal. The XNOR gate 160 outputs a stop signal STOP from the output terminal.

  Next, the switching operation to the different clock signal in the clock supply circuit shown in FIG. 10 will be described using the time chart shown in FIG. Note that the system clock CLK_SYS is used only by the first delay circuit 150 and the second delay circuit 151 and does not affect other circuits, and is omitted here for easy understanding. For easy understanding, the clock inversion signal INVERT is fixed at the H level (no inversion).

  First, each signal shown in the time chart of FIG. 11 will be briefly described. The signals already described are not described here.

  The clock switching instruction signal SW_CLK is a signal instructing the setting of the first clock signal CLK_IA at the H level and instructing the second clock signal CLK_IB setting at the L level.

  The first delay signal DELAY1 is a signal obtained by delaying the clock switching instruction signal SW_CLK by the delay time D1, and is a signal that serves to turn off the stop signal STOP (return to H level) at the delayed edge. The second delay signal DELAY2 is a signal obtained by delaying the clock switching instruction signal SW_CLK by the delay time D2, and is a signal that plays a role of selecting a clock signal output from the multiplexer 110.

  Next, the operation of the clock supply circuit 101 at each time will be described.

  Until the time t1, the clock switching instruction signal SW_CLK is at the H level, and the stop signal STOP, the synchronization stop signal STOP_S, the mask signal MASK, the first delay signal DELAY1, and the second delay signal DELAY2 are all at the H level. Further, since the second delay signal DELAY2 is at the H level, the second intermediate clock CLK_M2 becomes the first clock signal CLK_IA. Since the mask signal MASK is at the H level, the AND gate 140 outputs the first clock signal CLK_IA as the output clock CLK_O.

  At time t1, when the control signal generation unit 701 sets the clock switching instruction signal SW_CLK to L level, the stop signal STOP becomes L level.

  When the time reaches t2, the rising edge of the second intermediate clock CLK_M2 occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S becomes L level.

  When the time reaches t3, a falling edge of the second intermediate clock CLK_M2 occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes L level. Therefore, the AND gate 140 outputs an L level signal as the output clock CLK_O.

  When the time reaches t4, the second delay time D2 elapses from t1, and the second delay signal DELAY2 becomes L level. For this reason, the second intermediate clock CLK_M2 is switched to the second clock signal CLK_IB.

  When the time reaches t5, the first delay time D1 elapses from t1, and the first delay signal DELAY1 becomes L level. For this reason, the stop signal STOP returns to the H level. Here, the delay time D1 is larger than the delay time D2, but the delay time D1 may be smaller. These delay times can be obtained by the method shown in the switching operation to the different clock signal described above.

  When the time reaches t6, a rising edge of the second intermediate clock CLK_M2 occurs. For this reason, the internal data of the D flip-flop 130 is updated, and the synchronization stop signal STOP_S returns to the H level.

  When the time reaches t7, the falling edge of the second intermediate clock CLK_M2 occurs. For this reason, the internal data of the D flip-flop 131 is updated, and the mask signal MASK becomes H level. The AND gate 140 outputs the second clock signal CLK_IB as the output clock CLK_O.

  Through the operation as described above, the clock supply circuit 101 can generate the stop signal STOP and the clock designation signal SEL by itself based on the clock switching instruction signal SW_CLK. Even with such a configuration, an effect of seamlessly switching the clock signal supplied to the dynamic reconfigurable hardware 200 can be obtained.

  In addition, this invention is not limited to the said embodiment and the said modification, A various deformation | transformation and application are possible.

  In the modification, the first delay circuit 150, the second delay circuit 151, and the XNOR gate 160 are used to generate the first delay signal DELAY1, the second delay signal DELAY2, and the stop signal STOP. . However, the configuration is arbitrary as long as the timing for switching the levels of these signals can be controlled.

  In the above embodiment, the case where two clock signals are switched has been described. However, three or more clock signals may be switched. For example, when switching three clock signals, the clock switching instruction signal SW_CLK is composed of a 2-bit digital signal. Two delay circuits 150 and 151 and two XNOR gates 160 are prepared.

  Then, an AND gate is prepared separately, the outputs of the two XNOR gates 160 are connected to the two input terminals, and the output terminal is connected to the data input terminal of the D flip-flop 130. The multiplexer 110 may include two control terminals and three input terminals.

  Further, in the present embodiment, when metastable occurs, two stages of D flip-flops are connected in series so that the clock signal supplied to the dynamic reconfigurable hardware 200 does not become an unstable value. did. However, for example, when the frequency of the clock signal is high, the number of stages of the third and fourth stages and the D flip-flops may be further increased according to the occurrence probability of the metastable.

  In the modification, an example in which the stop signal STOP and the clock designation signal SEL are generated based on the clock switching instruction signal SW_CLK is shown. However, the stop signal STOP and the clock inversion signal INVERT may be generated based on the clock switching instruction signal SW_CLK.

1 is a configuration diagram of a system to which a clock supply circuit according to an embodiment of the present invention is applied. It is a block diagram of the clock supply circuit which concerns on embodiment of this invention. 3 is a time chart for explaining a clock signal stop operation in the clock supply circuit shown in FIG. 2. It is a block diagram which shows an example of the signal generation part for frequency division clock generation. It is a time chart for demonstrating the operation | movement which produces | generates a frequency-divided clock signal from the signal for frequency-divided clock generation. 3 is a time chart for explaining a switching operation to a different clock signal in the clock supply circuit shown in FIG. 2. 3 is a time chart for explaining a switching time when switching to a different clock signal using the clock supply circuit shown in FIG. 2. 3 is a time chart for explaining an inversion operation of a clock signal in the clock supply circuit shown in FIG. It is a block diagram of a system to which a clock supply circuit according to a modification is applied. It is a block diagram of the clock supply circuit which concerns on a modification. 11 is a time chart for explaining a switching operation to a different clock signal in the clock supply circuit shown in FIG. 10.

Explanation of symbols

100, 101 Clock supply circuit 110 Multiplexer 120 Inverting circuit 130, 131, 132 D flip-flop 140 AND gate 150 First delay circuit 151 Second delay circuit 160 XNOR gate 200 Dynamic reconfigurable hardware 300 System clock generator 400 First clock signal generation unit 500 Divided clock generation signal generation unit 600 Second clock signal generation unit 700, 701 Control signal generation unit

Claims (10)

A multiplexer that outputs a clock signal designated by the clock designation signal among the plurality of supplied clock signals in response to the clock designation signal;
In response to the clock inversion signal, the clock inversion unit outputs the clock signal output from the multiplexer as it is or by inverting the signal level;
An output stop signal for instructing a timing for stopping the output of the clock signal and a timing for releasing the stop of the output of the clock signal, and a clock signal output by the clock inverting unit are supplied, and the output stop signal indicates A mask signal generation unit that generates a mask signal for masking the clock signal output from the clock inversion unit by synchronizing the stop timing and the release timing with the edge of the clock signal, respectively.
A mask unit that generates a masked clock signal by masking the clock signal output from the clock inversion unit with the mask signal generated by the mask signal generation unit, and supplies the masked clock signal to the hardware;
A clock supply circuit comprising: The mask signal generation unit includes a first D flip-flop of an edge trigger type having a data input terminal, a clock input terminal, and a data output terminal, respectively, and has a trigger polarity opposite to that of the first D flip-flop. The second D flip-flop of the edge trigger type is provided, and the first and second D flip-flops are supplied with the clock signal output from the clock inverting unit at the clock input terminal, and the first D flip-flop is the data The output stop signal is supplied to the input terminal, the signal output from the data output terminal of the first D flip-flop is supplied to the data input terminal of the second D flip-flop, and the data output terminal is supplied to the second D flip-flop. Output mask signal from
The clock supply circuit according to claim 1. The output stop signal has a predetermined setup time at a time obtained by multiplying the period of the first clock signal by 1.5 when the clock designation signal instructs switching from the first clock signal to the second clock signal. The stop timing is instructed as a stop timing for a time that is equal to or longer than the time obtained by adding TsetupA and the predetermined hold time TholdB, and after the time that is equal to or longer than the time that the predetermined hold time TholdD is added to the predetermined setup time TsetupC. Instruct the timing as the release timing,
The clock supply circuit according to claim 1. When the clock stop signal instructs the clock inversion signal to invert the signal level of the clock signal or to cancel the inversion of the signal level, the output stop signal has a cycle of the clock signal of 1 than the timing of the instruction. The stop timing is designated as a timing that is more than the time obtained by adding the predetermined setup time TsetupA and the predetermined hold time TholdB to the time multiplied by 5 times, and the predetermined hold time TholdD is set to the predetermined setup time TsetupC from the timing of the previous instruction. Instruct the timing when the added time has passed as the release timing,
The clock supply circuit according to claim 1. A stop signal generator for generating the output stop signal in response to a clock switching instruction signal for instructing switching of the clock signal;
A clock designation signal generator that generates the clock designation signal in response to the clock switching instruction signal;
The clock supply circuit according to claim 1. The stop signal generator is supplied with a first delay circuit that delays and outputs the supplied clock switching instruction signal, and the clock switching instruction signal and the signal output from the first delay circuit. A coincidence circuit that generates an output stop signal that instructs a timing at which the signal level of the received signal changes from a matching state to a non-matching state as a stop timing and a timing at which the signal level changes from a non-matching state to a matching state as a release timing; With
The clock designation signal generator includes a second delay circuit that delays the supplied clock switching instruction signal and outputs the delayed clock designation signal as a clock designation signal.
The clock supply circuit according to claim 5. A frequency-divided clock generation signal generation unit that divides the clock signal to generate a frequency-divided clock generation signal;
The mask signal generation unit is supplied with the divided clock generation signal generated by the divided clock generation signal generation unit and the clock signal output by the clock inversion unit, instead of the output stop signal. Generating a mask signal by synchronizing the edge of the peripheral clock generation signal with the edge of the clock signal;
The clock supply circuit according to claim 1. The frequency-divided clock generating signal generator is
A counter that counts the edges of the clock signal and outputs the count value as digital data;
Based on the digital data output from the counter, a signal generation unit that generates and outputs a divided clock generation signal obtained by dividing the clock signal;
A register that outputs a reset value indicating a count value for resetting the counter;
The reset value output from the register is compared with the count value indicated by the digital data output from the counter, and if the reset value and the count value match, a reset signal for resetting the counter is output to the counter. A comparison unit,
The clock supply circuit according to claim 7. A clock supply circuit according to claim 1;
Dynamic reconfigurable hardware that constitutes the hardware and is supplied with a clock signal from the clock supply circuit;
Dynamic reconfigurable circuit consisting of A designated clock output step for outputting a clock signal designated by the clock designation signal among the plurality of supplied clock signals in response to the clock designation signal;
In response to the clock inversion signal, the clock inversion step for outputting the clock signal output in the designated clock output step as it is or by inverting the signal level;
A mask for generating a mask signal by synchronizing the timing of stopping the output of the clock signal indicated by the output stop signal and the timing of releasing the stop of the output of the clock signal with the edge of the clock signal output in the clock inversion step, respectively. A signal generation step;
A mask step of generating a masked clock signal by masking the clock signal output in the clock inversion step with the mask signal generated in the mask signal generation step;
A clock signal supplying step of supplying the masked clock signal generated in the masking step to hardware;
A clock supply method comprising:

Images