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JP2009016378A - Multilayer wiring board and multilayer wiring board manufacturing method - Google Patents

Multilayer wiring board and multilayer wiring board manufacturing method Download PDF

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Publication number
JP2009016378A
JP2009016378A JP2007172939A JP2007172939A JP2009016378A JP 2009016378 A JP2009016378 A JP 2009016378A JP 2007172939 A JP2007172939 A JP 2007172939A JP 2007172939 A JP2007172939 A JP 2007172939A JP 2009016378 A JP2009016378 A JP 2009016378A
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chip
wiring circuit
circuit board
adhesive layer
double
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JP5007164B2 (en
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Shoji Ito
彰二 伊藤
Masahiro Okamoto
誠裕 岡本
Satoru Nakao
知 中尾
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Fujikura Ltd
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Fujikura Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

【課題】簡便且つコストがかからない工法によって製造上の煩雑さと材料の浪費がなく作製することが可能で、ＩＣチップを基板内に内包し、且つ、両面に実装が可能な多層配線板を提供する。
【解決手段】ＩＣチップ２０と、絶縁性基材１０の片面に第１配線回路１１、他面側に接着剤層１２が配置され、絶縁性機材１０と接着剤層１２を貫通して第１配線回路１１と導通する導電性ペーストビア１５を有する片面配線回路基板１と、硬質絶縁性基材３０の両面に導電性ペーストビア１５と導通している第２配線回路３１が配置されており、硬質絶縁性基材３０には導電性ペーストビア１５と導通しているＩＣチップ２０を内包するように開口が施された両面配線回路基板３とを備える。
【選択図】図１Provided is a multilayer wiring board that can be manufactured by a simple and cost-effective method without manufacturing complexity and waste of materials, and in which an IC chip is enclosed in a substrate and can be mounted on both sides. .
A first wiring circuit 11 is disposed on one side of an IC chip 20 and an insulating substrate 10, and an adhesive layer 12 is disposed on the other side, and the first through the insulating equipment 10 and the adhesive layer 12 is provided. A single-sided wiring circuit board 1 having a conductive paste via 15 that is electrically connected to the wiring circuit 11, and a second wiring circuit 31 that is electrically connected to the conductive paste via 15 are disposed on both surfaces of the hard insulating substrate 30. The hard insulating substrate 30 is provided with a double-sided wiring circuit board 3 having an opening so as to enclose the IC chip 20 that is electrically connected to the conductive paste via 15.
[Selection] Figure 1

Description

本発明は、多層配線板及び多層配線板製造方法に関し、特に、パッケージ基板等に使用される多層配線板及び多層配線板製造方法に関する。   The present invention relates to a multilayer wiring board and a multilayer wiring board manufacturing method, and more particularly to a multilayer wiring board and a multilayer wiring board manufacturing method used for a package substrate or the like.

ウエハプロセスで製造される素子からの信号伝達および素子への給電を外部から行うため、素子と外部の回路または機器を電気的に接続するパッケージ基板が使われている。従来のパッケージ基板には、図８に示すように、個片化された集積回路（ＩＣ）チップ１００を、再配線層１１２が形成されたＩＣチップ１００よりも大きな基板１１０上に搭載し、金ワイヤ１１４などで接続しているものが用いられている。また、図９に示すように、ベアチップのＩＣチップ１００に金属バンプ１２０を形成し、異方性導電接着剤層１２４を用いて、再配線層１２２が形成された基板に実装するパッケージ方法も採用されている。しかしながら、近年の携帯電子機器の多機能化に伴い、半導体デバイスにも更なる小型化が要求されており、その多くはＩＣの高集積化よりもパッケージの小型化に焦点が当てられている。   2. Description of the Related Art A package substrate that electrically connects an element and an external circuit or device is used to transmit a signal from the element manufactured by the wafer process and to supply power to the element from the outside. In a conventional package substrate, as shown in FIG. 8, an individualized integrated circuit (IC) chip 100 is mounted on a substrate 110 larger than the IC chip 100 on which the rewiring layer 112 is formed, and gold What is connected with the wire 114 etc. is used. Further, as shown in FIG. 9, a packaging method is adopted in which metal bumps 120 are formed on a bare chip IC chip 100 and mounted on a substrate on which a rewiring layer 122 is formed using an anisotropic conductive adhesive layer 124. Has been. However, with the recent increase in the number of functions of portable electronic devices, further miniaturization of semiconductor devices is required, and many of them are focused on miniaturization of packages rather than high integration of ICs.

近年、実装技術において、小型化、薄品化、軽量化が可能であり高信頼性、低コストを特徴とするパッケージング製法であるウエハレベル・チップ・スケール・パッケージ（ＷＬＣＳＰ）の研究開発や実用化が活発に行われている。ＷＬＣＳＰは、図１０に示すように、シリコンウエハを土台としてＩＣチップ１００上に直接配線をビルドアップ法で形成するものある。ＷＬＣＳＰにおいては、製造工程中にシリコンウエハをチップ切断することなくＩＣ絶縁層１３０、再配線層１３２、封止樹脂層１３４、はんだバンプ１３６を形成し、ウエハのまま一括してパッケージまでを行い、最終工程においてウエハのダイシングを行うため、切断した半導体チップの大きさがそのままパッケージの大きさとなり、ＷＬＣＳＰ技術を用いれば、実装基板に対して最小の投影面積を有する半導体パッケージを得ることができる。しかし、実装基板の端子ピッチのルールによってパッケージ上に配置できる端子数が制限されるため、ＷＬＣＳＰの適用はピン数の少ない素子に限定される。   In recent years, R & D and practical use of wafer level chip scale package (WLCSP), which is a packaging method characterized by high reliability and low cost that can be reduced in size, thickness, and weight in packaging technology. Is being actively promoted. In the WLCSP, as shown in FIG. 10, wiring is directly formed on the IC chip 100 by a build-up method using a silicon wafer as a base. In WLCSP, the IC insulating layer 130, the rewiring layer 132, the sealing resin layer 134, and the solder bump 136 are formed without cutting the silicon wafer into chips during the manufacturing process. Since the wafer is diced in the final process, the size of the cut semiconductor chip becomes the size of the package as it is, and if the WLCSP technology is used, a semiconductor package having a minimum projected area with respect to the mounting substrate can be obtained. However, since the number of terminals that can be arranged on the package is limited by the rule of the terminal pitch of the mounting substrate, the application of WLCSP is limited to an element having a small number of pins.

ＷＬＣＳＰの上記制約を拡大する技術としてエンベデッド・ウエハレベル・パッケージ（ＥＷＬＰ）技術がある（例えば、特許文献１参照）。ＥＷＬＰは、図１１に示すように、ウエハレベルの再配線では端子ピッチを大幅に拡大せず、ダイシングしたＩＣチップ１００を樹脂板（絶縁樹脂１４０及び埋め込み材１４２）に埋め込んでウエハレベルの再配線層１４４と樹脂板１４０，１４２の表面を同一平面とし、ビルドアップ配線１４６をＷＬＣＳＰの範囲から樹脂板１４０，１４２の表面に拡大して形成するため、端子の配置に必要な面積を確保することができるパッケージ基板の技術である。ＥＷＬＰの場合もビルドアップ技術のみによる配線を持つため、パッケージ基板全体の配線密度は極めて高いものとなる。   There is an embedded wafer level package (EWLP) technique as a technique for expanding the above-mentioned restrictions of WLCSP (for example, see Patent Document 1). As shown in FIG. 11, the EWLP does not greatly increase the terminal pitch in the wafer level rewiring, but embeds the diced IC chip 100 in a resin plate (the insulating resin 140 and the embedding material 142) to perform the wafer level rewiring. The surface of the layer 144 and the resin plates 140 and 142 are flush with each other, and the build-up wiring 146 is formed to be enlarged from the range of WLCSP to the surface of the resin plates 140 and 142, so that an area necessary for terminal arrangement is secured. This is a technology for package substrates. In the case of EWLP, the wiring density of the entire package substrate is extremely high because it has wiring based only on the build-up technology.

しかし、ＥＷＬＰ技術ではコスト増、作製期間の長期化といった問題があったために、図１２に示すように、より簡便な工法によるＩＣチップの内蔵化形態が提案されている（例えば、特許文献２参照）。   However, since the EWLP technology has problems such as an increase in cost and a long manufacturing period, as shown in FIG. 12, an IC chip built-in form by a simpler construction method has been proposed (see, for example, Patent Document 2). ).

しかしながら、特許文献２で提案された構造の場合、ＩＣチップ１００を基板内に内蔵し、且つ、基板表面にも部品を実装する構造を得ることができない。基板表面には配線が施されているが、本基板を別基板に実装するためのはんだバンプが基板表面に形成されているため部品を実装することができない。そして、基板裏面には、配線が施されていないため部品を実装することができない。   However, in the case of the structure proposed in Patent Document 2, it is impossible to obtain a structure in which the IC chip 100 is built in the substrate and components are mounted on the substrate surface. Although wiring is provided on the substrate surface, components cannot be mounted because solder bumps for mounting this substrate on another substrate are formed on the substrate surface. And since wiring is not given to the back surface of the board, components cannot be mounted.

また、ＩＣチップ１００を基板内に完全に封止するということは、封止する領域の基材の厚さを確保する必要性があり、電気的機能としては意味をなさない絶縁層や回路層を設けることによる製造上の煩雑さと材料の浪費を避けることができない。
特開２００４−９５８３６号公報 特願２００６−１２５７２８号公報 In addition, completely sealing the IC chip 100 in the substrate requires securing the thickness of the base material in the region to be sealed, and does not make sense as an electrical function. It is not possible to avoid manufacturing complexity and waste of materials.
JP 2004-95836 A Japanese Patent Application No. 2006-125728

本発明は、簡便且つコストがかからない工法によって製造上の煩雑さと材料の浪費がなく作製することが可能で、ＩＣチップを基板内に内包し、且つ、両面に実装が可能な多層配線板及び多層配線板製造方法を提供することを目的とする。   The present invention provides a multilayer wiring board and a multilayer wiring board that can be manufactured by a simple and cost-effective method without manufacturing complexity and waste of materials, and in which an IC chip is included in a substrate and can be mounted on both sides. An object is to provide a method for manufacturing a wiring board.

本願発明の一態様によれば、ＩＣチップと、絶縁性基材の片面に第１配線回路、他面側に接着剤層が配置され、絶縁性機材と接着剤層を貫通して第１配線回路と導通する導電性ペーストビアを有する片面配線回路基板と、硬質絶縁性基材の両面に導電性ペーストビアと導通している第２配線回路が配置されており、硬質絶縁性基材には導電性ペーストビアと導通しているＩＣチップを内包するように開口が施された両面配線回路基板とを備え、接着剤層によってＩＣチップ及び両面配線回路基板が保持される多層配線板であることを要旨とする。   According to one aspect of the present invention, the first wiring circuit is disposed on one side of the IC chip and the insulating base, and the adhesive layer is disposed on the other side, and the first wiring passes through the insulating equipment and the adhesive layer. A single-sided wiring circuit board having a conductive paste via that is electrically connected to the circuit, and a second wiring circuit that is electrically connected to the conductive paste via are arranged on both sides of the hard insulating base material. A multilayer wiring board having a double-sided wiring circuit board having an opening so as to enclose an IC chip electrically connected to the conductive paste via, and holding the IC chip and the double-sided wiring circuit board by an adhesive layer Is the gist.

本願発明の他の態様によれば、絶縁性基材の片面に第１配線回路、他面側に接着剤層が配置され、絶縁性機材と接着剤層を貫通して第１配線回路と導通する導電性ペーストビアを有する片面配線回路基板を用意する工程と、ＩＣチップを用意し、ＩＣチップと導電性ペーストビアの仮留めを行う工程と、硬質絶縁性基材の両面に導電性ペーストビアと導通している第２配線回路が配置されており、硬質絶縁性基材には導電性ペーストビアと導通しているＩＣチップを内包するように開口が施された両面配線回路基板を用意する工程と、両面配線回路基板の開口の位置にＩＣチップを配置するように、両面配線回路基板を接着剤層に位置合わせして配置する工程と、片面配線回路基板と両面配線回路基板を加熱加圧して多層化する工程とを含む多層配線板製造方法であることを要旨とする。   According to another aspect of the present invention, the first wiring circuit is disposed on one side of the insulating base material, the adhesive layer is disposed on the other side, and is electrically connected to the first wiring circuit through the insulating equipment and the adhesive layer. Preparing a single-sided wiring circuit board having conductive paste vias, preparing an IC chip and temporarily fastening the IC chip and the conductive paste via, and conductive paste vias on both sides of the hard insulating substrate A double-sided wiring circuit board is provided in which a hard wiring substrate is provided with an IC chip that is electrically connected to a conductive paste via. A step, a step of positioning the double-sided wiring circuit board in alignment with the adhesive layer so as to place the IC chip at the position of the opening of the double-sided wiring circuit board, Pressing and multilayering And summarized in that a layer wiring board manufacturing method.

本発明によれば、簡便且つコストがかからない工法によって製造上の煩雑さと材料の浪費がなく作製することが可能で、ＩＣチップを基板内に内包し、且つ、両面に実装が可能な多層配線板及び多層配線板製造方法を提供することができる。   According to the present invention, a multilayer wiring board which can be manufactured without complicated manufacturing and waste of materials by a simple and cost-effective construction method, and can be mounted on both sides by including an IC chip in the substrate. And the manufacturing method of a multilayer wiring board can be provided.

以下に図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号で表している。但し、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なる。したがって、具体的な厚みや寸法は以下の説明を照らし合わせて判断するべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。   Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in light of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

（第１の実施の形態）
（多層配線板）
本発明の第１の実施の形態に係る多層配線板は、図１に示すように、ＩＣチップ２０と、絶縁性基材１０の片面に第１配線回路１１、他面側に接着剤層１２が配置され、絶縁性機材１０と接着剤層１２を貫通して第１配線回路１１と導通する導電性ペーストビア１５を有する片面配線回路基板１と、硬質絶縁性基材３０の両面に導電性ペーストビア１５と導通している第２配線回路３１が配置されており、硬質絶縁性基材３０には導電性ペーストビア１５と導通しているＩＣチップ２０を内包するように開口が施された両面配線回路基板３とを備え、接着剤層１２によってＩＣチップ２０及び両面配線回路基板３が保持される。 (First embodiment)
(Multilayer wiring board)
As shown in FIG. 1, the multilayer wiring board according to the first embodiment of the present invention includes an IC chip 20, a first wiring circuit 11 on one side of the insulating substrate 10, and an adhesive layer 12 on the other side. Is disposed on the both sides of the hard insulating substrate 30 and the single-sided wiring circuit board 1 having the conductive paste vias 15 that are electrically connected to the first wiring circuit 11 through the insulating material 10 and the adhesive layer 12. The second wiring circuit 31 that is electrically connected to the paste via 15 is disposed, and the hard insulating substrate 30 is provided with an opening so as to enclose the IC chip 20 that is electrically connected to the conductive paste via 15. The double-sided wiring circuit board 3 is provided, and the IC chip 20 and the double-sided wiring circuit board 3 are held by the adhesive layer 12.

絶縁性基材１０としては、例えばポリイミド（ＰＩ）フィルム、ポリエチレンテレフタレート（ＰＥＴ）フィルム、ポリエチレンナフタレート（ＰＥＮ）フィルム、液晶ポリマー等のプラスチックフィルムを用いることができる。絶縁性基材１０の厚さは、２５μｍ、１２．５μｍ、８μｍ、６μｍ等を採用することができる。   As the insulating substrate 10, for example, a plastic film such as a polyimide (PI) film, a polyethylene terephthalate (PET) film, a polyethylene naphthalate (PEN) film, or a liquid crystal polymer can be used. As the thickness of the insulating substrate 10, 25 μm, 12.5 μm, 8 μm, 6 μm, or the like can be adopted.

第１配線回路１１は、絶縁性基材１０上に形成された導体の回路パターンである。第１配線回路１１を形成する方法としては、銅箔にポリイミドワニスを塗布してワニスを硬化させるキャスティング法により作製された片面銅張板（ＣＣＬ）をパターン加工して形成する方法がある。第１配線回路１１を形成する他の方法としては、絶縁性基材１０上にシード層をスパッタしてメッキにより銅を成長させたＣＣＬや、絶縁性基材１０上に圧延銅箔または電解銅箔等を貼り合わせたＣＣＬをパターン加工して形成する方法もある。第１配線回路１１には、銅箔以外の金属箔を導体として使うことも可能である。第１配線回路１１の厚さは、３５μｍ、１８μｍ、１２μｍ、９μｍ等を採用することができる。   The first wiring circuit 11 is a circuit pattern of a conductor formed on the insulating base material 10. As a method of forming the first wiring circuit 11, there is a method of patterning a single-sided copper-clad plate (CCL) produced by a casting method in which a polyimide varnish is applied to a copper foil and the varnish is cured. Other methods for forming the first wiring circuit 11 include CCL in which a seed layer is sputtered on the insulating base material 10 and copper is grown by plating, or rolled copper foil or electrolytic copper on the insulating base material 10. There is also a method in which a CCL formed by bonding foil or the like is formed by pattern processing. For the first wiring circuit 11, a metal foil other than copper foil can be used as a conductor. The thickness of the first wiring circuit 11 may be 35 μm, 18 μm, 12 μm, 9 μm, or the like.

接着剤層１２には、エポキシ系やアクリル系の熱硬化性フィルム接着剤、及び熱可塑性ポリイミド等の熱可塑性接着剤を用いることができる。また、接着剤層１２は、必ずしもフィルム状でなくともよく、ワニス状の樹脂を塗布して用いることもできる。   For the adhesive layer 12, an epoxy or acrylic thermosetting film adhesive and a thermoplastic adhesive such as thermoplastic polyimide can be used. Moreover, the adhesive layer 12 does not necessarily have to be a film, and a varnish-like resin can be applied and used.

導電性ペーストビア１５は、導電性ペーストにより形成される。導電性ペーストビア１５に用いられる導電性ペーストとしては、ニッケル（Ｎｉ）、銀（Ａｇ）、銅（Ｃｕ）から選択される少なくとも１種類の低電気抵抗の金属粒子と、錫（Ｓｎ）、ビスマス（Ｂｉ）、インジウム（Ｉｎ）、鉛（Ｐｂ）から選択される少なくとも１種類の低融点金属粒子を含み、エポキシ樹脂を主成分とするバインダ成分を混合したペーストを用いる。   The conductive paste via 15 is formed of a conductive paste. Examples of the conductive paste used for the conductive paste via 15 include at least one kind of low electrical resistance metal particles selected from nickel (Ni), silver (Ag), and copper (Cu), tin (Sn), and bismuth. A paste containing at least one kind of low melting point metal particles selected from (Bi), indium (In), and lead (Pb) and mixed with a binder component mainly composed of an epoxy resin is used.

硬質絶縁性基材３０は、ガラス、アラミド、紙のいずれかにエポキシ、ポリイミドのいずれかを含有させて得られた、例えばガラスエポキシ基材、ガラスコンポジット基材、紙エポキシ基材等の硬質基材を用いることができる。硬質絶縁性基材３０は硬質であるので、ＩＣチップ２０周辺のたわみや折れによってＩＣチップ２０と導電性ペーストビア１５の間に応力が生じないよう形状保持することができる。硬質絶縁性基材３０の厚さは、ＩＣチップ２０と略同等の厚さを有するものであり、例えば２．４ｍｍ、２．０ｍｍ、１．６ｍｍ、１．２ｍｍ、１．０ｍｍ、０．８ｍｍ、０．６ｍｍ、０．４ｍｍ、０．２ｍｍ、０．１ｍｍ等を採用することができる。   The hard insulating base material 30 is obtained by adding any of epoxy and polyimide to any of glass, aramid, and paper, for example, a hard base such as a glass epoxy base material, a glass composite base material, and a paper epoxy base material. Materials can be used. Since the hard insulating substrate 30 is hard, the shape can be maintained so that no stress is generated between the IC chip 20 and the conductive paste via 15 due to bending or bending around the IC chip 20. The thickness of the hard insulating substrate 30 is substantially the same as that of the IC chip 20, for example, 2.4 mm, 2.0 mm, 1.6 mm, 1.2 mm, 1.0 mm, 0.8 mm. 0.6 mm, 0.4 mm, 0.2 mm, 0.1 mm, etc. can be employed.

両面配線回路基板３は、ＩＣチップ２０の外形から例えば５０μｍの遊びを持つような貫通する開口を有する。両面配線回路基板３は、両面に第２配線回路３１が配置され、それぞれの第２配線回路３１が導通されている。両面配線回路基板３は、スルーホールタイプのポリイミド両面板や、片側の銅箔とポリイミドに穴を施し、穴の開いていない銅箔の裏面とメッキ３２によって導通を得るいわゆるレーザービアホールタイプ、メッキではなく導電性ペーストによって導通を得るタイプ等の両面板を適用することが可能である。第２配線回路３１は、第１配線回路１１と同様の方法で形成することができ、同様の材料を用いることができる。第２配線回路３１の厚さは、３５μｍ、１８μｍ、１２μｍ、９μｍ等を採用することができる。   The double-sided wiring circuit board 3 has an opening penetrating from the outer shape of the IC chip 20 so as to have a play of, for example, 50 μm. The double-sided wiring circuit board 3 has second wiring circuits 31 arranged on both sides, and the respective second wiring circuits 31 are electrically connected. The double-sided wiring circuit board 3 is a through-hole type polyimide double-sided board, or a so-called laser via hole type in which a hole is made in one side copper foil and polyimide, and conduction is obtained by plating 32 on the back side of the copper foil without holes. It is possible to apply a double-sided plate of a type that obtains conduction with a conductive paste. The second wiring circuit 31 can be formed by the same method as the first wiring circuit 11, and the same material can be used. The thickness of the second wiring circuit 31 can be 35 μm, 18 μm, 12 μm, 9 μm, or the like.

片面配線回路基板１の第１配線回路１１上にはソルダレジスト４０が設けられ、ソルダレジスト４０上には別途ＩＣチップ５０が搭載される。ＩＣチップ５０のＩＣ電極パット５１は、第１配線回路１１と金ワイヤ５２によって接続されている。   A solder resist 40 is provided on the first wiring circuit 11 of the single-sided wiring circuit board 1, and an IC chip 50 is separately mounted on the solder resist 40. The IC electrode pad 51 of the IC chip 50 is connected to the first wiring circuit 11 by a gold wire 52.

両面配線回路基板３の接着剤層１２で接着された面の他面側に配置された第２配線回路３１上には、はんだバンプ４１が設けられる。はんだバンプ４１は、別途回路基板と接続される。   Solder bumps 41 are provided on the second wiring circuit 31 disposed on the other surface side of the surface bonded by the adhesive layer 12 of the double-sided wiring circuit board 3. The solder bump 41 is separately connected to the circuit board.

（多層配線板製造方法）
以下に、本発明の第１の実施の形態に係る多層配線板製造方法を図２及び図３を参照しながら説明する。 (Multilayer wiring board manufacturing method)
The multilayer wiring board manufacturing method according to the first embodiment of the present invention will be described below with reference to FIGS.

（イ）まず、図２（ａ）に示すように、ポリイミド樹脂フィルムからなる絶縁性基材１０の片面に導電層となる銅箔１１が設けてあるＣＣＬを用意する。用意したＣＣＬはフォトリソグラフィ技術により、第１配線回路１１の回路パターンを形成する。具体的には、銅箔１１上にエッチングレジストを形成した後に、塩化第二鉄を主成分とするエッチャントを用いて、化学エッチングをすることにより、図２（ｂ）に示すような、第１配線回路１１の回路パターンを形成して、片面配線回路基板１とする。ここでは、ＣＣＬとして、２５μｍ厚のポリイミド樹脂フィルムからなる絶縁性基材１０に、１２μｍ厚の銅箔１１が張り合わされているものを使用した。また、銅のエッチャントとしては、塩化第二鉄を主成分とするものに限らず、塩化第二銅を主成分とするエッチャントを用いてもよい。   (A) First, as shown in FIG. 2A, a CCL in which a copper foil 11 serving as a conductive layer is provided on one surface of an insulating base material 10 made of a polyimide resin film is prepared. The prepared CCL forms a circuit pattern of the first wiring circuit 11 by photolithography. Specifically, after an etching resist is formed on the copper foil 11, chemical etching is performed using an etchant containing ferric chloride as a main component, whereby a first as shown in FIG. A circuit pattern of the wiring circuit 11 is formed to form a single-sided wiring circuit board 1. Here, a CCL in which a 12 μm thick copper foil 11 is bonded to an insulating base material 10 made of a 25 μm thick polyimide resin film was used. Further, the copper etchant is not limited to one containing ferric chloride as a main component, and an etchant containing cupric chloride as a main component may be used.

（ロ）次に、図２（ｃ）に示すように、絶縁性基材１０の第１配線回路１１を形成した面とは反対側の面に、接着剤層１２及び樹脂フィルム１３を加熱圧着により貼り合わせる。接着剤層１２には、２５μｍ厚のエポキシ系熱硬化性フィルム接着材を使用し、樹脂フィルム１３には、２５μｍ厚のポリイミドフィルムを使用した。加熱圧着には真空ラミネータを用い、減圧下の雰囲気中にて、接着剤層１２の硬化温度以下の温度で、０．３ＭＰａの圧力でプレスして貼りあわせた。なお、接着剤層１２は、エポキシ系の熱硬化性フィルム接着材に限定されることはなく、アクリル系などの接着材も使用できるし、熱可塑性ポリイミドなどに代表される熱可塑性接着材であってもよい。また、接着剤層１２は、必ずしもフィルム状でなくともよく、ワニス状の樹脂を塗布して用いてもよい。また、樹脂フィルム１３としては、絶縁性基材１０と同様の材料を用いることができ、紫外線（ＵＶ）照射によって接着や剥離が可能なフィルムを使用することもできる。なお、絶縁性基材１０として、熱可塑性を有する樹脂または半硬化状態の熱硬化樹脂からなる接着性を有するものを用いれば、接着剤層１２を貼り合わせる必要はない。   (B) Next, as shown in FIG. 2 (c), the adhesive layer 12 and the resin film 13 are thermocompression bonded to the surface of the insulating substrate 10 opposite to the surface on which the first wiring circuit 11 is formed. Paste together. The adhesive layer 12 was an epoxy thermosetting film adhesive having a thickness of 25 μm, and the resin film 13 was a polyimide film having a thickness of 25 μm. For thermocompression bonding, a vacuum laminator was used, and pressed and bonded at a pressure not higher than the curing temperature of the adhesive layer 12 at a pressure of 0.3 MPa in an atmosphere under reduced pressure. The adhesive layer 12 is not limited to an epoxy-based thermosetting film adhesive, and an acrylic-based adhesive can also be used, and is a thermoplastic adhesive typified by thermoplastic polyimide. May be. Moreover, the adhesive layer 12 does not necessarily have to be in the form of a film, and may be used by applying a varnish-like resin. Moreover, as the resin film 13, the material similar to the insulating base material 10 can be used, and the film which can be adhere | attached or peeled by ultraviolet-ray (UV) irradiation can also be used. Note that if the insulating base 10 is made of a thermoplastic resin or a semi-cured thermosetting resin, it is not necessary to bond the adhesive layer 12 together.

（ハ）次に、図２（ｄ）に示すように、前述の絶縁性基材１０、接着剤層１２、及び樹脂フィルム１３に、ＹＡＧレーザを用いて、直径１００μｍのビアホール１４ａを成形するとともに、第１配線回路１１には、直径３０μｍ程度の小孔１４ｂを開ロする。そして、ＣＦ4及びＯ2混合ガスによるプラズマデスミア処理を施した後に、図２（ｅ）に示すように、スクリーン印刷法により、ビアホール１４ａ及び小孔１４ｂに導電性ペーストを充填して導電性ペーストビア１５とし、樹脂フィルム１３を剥離する。このとき、印刷充填した導電性ペーストからなる導電性ペーストビア１５の先端は、剥離した樹脂フィルム１３の厚さ分だけ、接着剤層１２の表面より突出し、突起を形成している。なお、ビアホール１４ａ及び小孔１４ｂの形成のために使用するレーザは、ＹＡＧレーザの他に、炭酸ガスレーザ、エキシマレーザなどを使用することもできる。また、ドリル加工や化学的なエッチングによって、ビアホール１４ａ及び小孔１４ｂを形成してもよい。プラズマデスミア処理は、使用するガスの種類が、ＣＦ4及びＯ2の混合ガスに限定されることはなく、Ａｒなど、その他の不活性ガスを使用することもできる。また、ドライ処理ではなく、薬液を用いたウェットデスミア処理でもよい。 (C) Next, as shown in FIG. 2D, a via hole 14a having a diameter of 100 μm is formed on the insulating base material 10, the adhesive layer 12, and the resin film 13 by using a YAG laser. In the first wiring circuit 11, a small hole 14b having a diameter of about 30 μm is opened. Then, after performing a plasma desmear process using a mixed gas of CF 4 and O 2 , as shown in FIG. 2E, the conductive paste is filled in the via holes 14a and the small holes 14b by a screen printing method. Vias 15 are formed, and the resin film 13 is peeled off. At this time, the tip of the conductive paste via 15 made of the printed conductive paste protrudes from the surface of the adhesive layer 12 by the thickness of the peeled resin film 13 to form a protrusion. As a laser used for forming the via hole 14a and the small hole 14b, a carbon dioxide laser, an excimer laser, or the like can be used in addition to the YAG laser. Further, the via hole 14a and the small hole 14b may be formed by drilling or chemical etching. In the plasma desmear process, the type of gas used is not limited to the mixed gas of CF 4 and O 2 , and other inert gases such as Ar can be used. Further, instead of dry treatment, wet desmear treatment using a chemical solution may be used.

（ニ）次に、図２（ｆ）に示すように、ＩＣ電極パット２１、ＩＣ絶縁層２２、ＩＣ再配線層２３を備えるＩＣチップ２０を用意する。そして、ＩＣチップ２０を、半導体チップ用マウンタで位置合わせして、接着剤層１２及び導電性ペーストビア１５をなす導電性ペーストの硬化温度以下で加熱し、ＩＣ再配線層２３と導電性ペーストビア１５の仮留めを行う。   (D) Next, as shown in FIG. 2F, an IC chip 20 including an IC electrode pad 21, an IC insulating layer 22, and an IC rewiring layer 23 is prepared. Then, the IC chip 20 is aligned with a semiconductor chip mounter and heated below the curing temperature of the conductive paste forming the adhesive layer 12 and the conductive paste via 15, and the IC rewiring layer 23 and the conductive paste via are heated. Perform 15 temporary fixings.

（ホ）次に、ＩＣチップ２０の外形から例えば５０μｍの遊びを持つような開口を有し、厚さ１００μｍのガラスエポキシ両面板を硬質絶縁性基材３０とする両面配線回路基板３を用意する。ここで用いる両面配線回路基板３は、スルーホール３３によって両面に配置した第２配線回路３１の導通を得るスルーホールタイプである。両面配線回路基板３は、図３（ｇ）に示すように、片面配線回路基板１の接着剤層１２に、パターン（図示せず）を用いて位置合わせして配置し、加熱することで仮留めをする。   (E) Next, a double-sided wiring circuit board 3 having an opening having a play of, for example, 50 μm from the outer shape of the IC chip 20 and having a 100 μm-thick glass epoxy double-sided board as the hard insulating substrate 30 is prepared. . The double-sided wiring circuit board 3 used here is a through-hole type that obtains conduction of the second wiring circuit 31 arranged on both sides by the through-hole 33. As shown in FIG. 3 (g), the double-sided wiring circuit board 3 is positioned and arranged on the adhesive layer 12 of the single-sided wiring circuit board 1 using a pattern (not shown), and is temporarily heated. Fasten.

（ヘ）次に、図３（ｈ）に示すように、図３（ｇ）で示した積層体を、真空キュアプレス機を用いて、１ｋＰａ以下の減圧雰囲気中で加熱圧着する。このとき、接着剤層１２を硬化させると同時に、導電性ペーストビア１５をなす導電性ペーストの硬化及び合金化が行われる。なお、ここで「硬化」とは、熱硬化（架橋反応）のみならず、加熱により軟化した材料が冷えて硬化する場合も含んでいる。ここで、再配線層の一部となる片面配線回路基板１として、予め回路形成がなされた片面ＣＣＬを用い、また、層間接続に印刷充填した導電性ペーストによる導電性ペーストビア１５を使用することにより、全ての工程においてめっき工程を排除することができ、従来のビルドアップ方式に比べて、生産時間を大幅に短縮することができる。さらに、各層を構成する基材は、予め作成されているため、各工程で発生する不良品をその都度排除することができ、歩留まりの累積を避けることが可能となる。層間接続用の導電性ペーストには、例えば、特開２０００−４９４６０公報に記載されているように、層間接着材の硬化温度程度の低温で合金化する組成のものを適用することで、導電性ペースト内の金属粒子同士、また、銅の接続パッドと導電性ペースト内の金属粒子とが拡散接合し、バルクの金属やめっきによる層間接続と同等の接続信頼性を確保することができる。また、加熱加圧工程では、両面配線回路基板３とＩＣチップ２０に同時に圧力を印加する必要があり、段差を緩和するクッション材（図示せず）を積層体の上下に配置して加圧を実行することが好ましい。クッション材の種類にもよるが、両面配線回路基板３とＩＣチップ２０との厚さの違いは５０μｍ以内であることが好ましい。   (F) Next, as shown in FIG. 3 (h), the laminate shown in FIG. 3 (g) is heat-pressed in a reduced pressure atmosphere of 1 kPa or less using a vacuum curing press. At this time, the adhesive layer 12 is cured, and at the same time, the conductive paste forming the conductive paste via 15 is cured and alloyed. Here, “curing” includes not only thermal curing (crosslinking reaction) but also a case where a material softened by heating is cooled and cured. Here, as the single-sided wiring circuit board 1 to be a part of the rewiring layer, a single-sided CCL on which a circuit is formed in advance is used, and a conductive paste via 15 made of a conductive paste printed and filled in an interlayer connection is used. Thus, the plating process can be eliminated in all the processes, and the production time can be greatly reduced as compared with the conventional build-up method. Furthermore, since the base material constituting each layer is prepared in advance, defective products generated in each process can be eliminated each time, and accumulation of yield can be avoided. As the conductive paste for interlayer connection, for example, as described in JP 2000-49460 A, a paste having a composition that forms an alloy at a low temperature about the curing temperature of the interlayer adhesive is applied. The metal particles in the paste, and the copper connection pads and the metal particles in the conductive paste are diffusion-bonded to ensure connection reliability equivalent to interlayer connection by bulk metal or plating. In the heating and pressurizing step, it is necessary to apply pressure to the double-sided wiring circuit board 3 and the IC chip 20 at the same time, and cushioning materials (not shown) for relaxing the steps are arranged above and below the laminate. It is preferable to carry out. Although it depends on the type of cushion material, the difference in thickness between the double-sided wiring circuit board 3 and the IC chip 20 is preferably within 50 μm.

（ト）次に、図３（ｉ）及び図３（ｊ）に示すように、図３（ｈ）で示した多層板に、ソルダレジスト４０及びはんだバンプ４１を形成する。ソルダレジスト４０は、液状の感光性樹脂をスクリーン印刷し、パターンを露光した後に現像し形成する。はんだバンプ４１は、はんだペーストをパターン印刷し、リフローすることにより、ボール状に形成する。そして、図３（ｊ）に示すように、片面配線回路基板１上に形成したソルダレジスト４０に別途ＩＣチップ５０を搭載し、第１配線回路１１とＩＣ電極パット５１とを金ワイヤ５２等で接続する。以上の工程により、本発明の第１の実施の形態に係る多層配線板が得られる。   (G) Next, as shown in FIGS. 3 (i) and 3 (j), solder resist 40 and solder bumps 41 are formed on the multilayer board shown in FIG. 3 (h). The solder resist 40 is formed by screen-printing a liquid photosensitive resin, exposing the pattern, and developing the pattern. The solder bump 41 is formed into a ball shape by pattern printing of solder paste and reflowing. Then, as shown in FIG. 3 (j), an IC chip 50 is separately mounted on the solder resist 40 formed on the single-sided wiring circuit board 1, and the first wiring circuit 11 and the IC electrode pad 51 are connected by a gold wire 52 or the like. Connecting. Through the above steps, the multilayer wiring board according to the first embodiment of the present invention is obtained.

本発明の第１の実施の形態に係る多層配線板によれば、両面配線回路基板３を用いることで両面にＩＣチップ５０等の様々な部品を実装することができる。また、第１の実施の形態に係る多層配線板は、ＩＣチップ２０を両面配線回路基板３内に封止することで、封止する領域の基材の厚さを確保する必要性がなくなり、電気的機能としては意味をなさない絶縁層や回路層を設けることによる製造上の煩雑さと材料の浪費を避けることができる。   According to the multilayer wiring board according to the first embodiment of the present invention, by using the double-sided wiring circuit board 3, various components such as the IC chip 50 can be mounted on both sides. Moreover, the multilayer wiring board according to the first embodiment eliminates the need to secure the thickness of the base material in the region to be sealed by sealing the IC chip 20 in the double-sided wiring circuit board 3. By providing an insulating layer or a circuit layer that does not make sense as an electrical function, it is possible to avoid manufacturing complexity and waste of materials.

本発明の第１の実施の形態に係る多層配線板製造方法によれば、簡便且つコストがかからない工法で、高精細な部品を実装した多層配線板を製造することができる。   According to the multilayer wiring board manufacturing method according to the first embodiment of the present invention, a multilayer wiring board on which high-definition components are mounted can be manufactured by a simple and inexpensive method.

（第２の実施の形態）
（多層配線板）
本発明の第２の実施の形態に係る多層配線板は、図４に示すように、図１で示した多層配線板と比して、両面配線回路基板３がＩＣチップ２０より厚い硬質絶縁性基材３０を用いていて、両面配線回路基板３のＩＣチップ２０を内包する開口は貫通しておらず、ポケットエリアにＩＣチップ２０を内包する構造である点が異なる。他は図１に示した多層配線板と実質的に同様であるので、重複した記載を省略する。 (Second Embodiment)
(Multilayer wiring board)
As shown in FIG. 4, the multilayer wiring board according to the second embodiment of the present invention has a hard insulating property in which the double-sided wiring circuit board 3 is thicker than the IC chip 20 as compared with the multilayer wiring board shown in FIG. The difference is that the substrate 30 is used, the opening that encloses the IC chip 20 of the double-sided wiring circuit board 3 does not penetrate, and the IC chip 20 is enclosed in the pocket area. Others are substantially the same as those of the multilayer wiring board shown in FIG.

（多層配線板製造方法）
以下に、本発明の第２の実施の形態に係る多層配線板製造方法を図２、図５及び図６を参照しながら説明する。 (Multilayer wiring board manufacturing method)
A multilayer wiring board manufacturing method according to the second embodiment of the present invention will be described below with reference to FIGS.

（イ）まず、図２（ａ）に示すように、ポリイミド樹脂フィルムからなる絶縁性基材１０の片面に導電層となる銅箔１１が設けてあるＣＣＬを用意する。用意したＣＣＬはフォトリソグラフィ技術により、第１配線回路１１の回路パターンを形成する。具体的には、銅箔１１上にエッチングレジストを形成した後に、塩化第二鉄を主成分とするエッチャントを用いて、化学エッチングをすることにより、図２（ｂ）に示すような、第１配線回路１１の回路パターンを形成して、片面配線回路基板１とする。ここでは、ＣＣＬとして、２５μｍ厚のポリイミド樹脂フィルムからなる絶縁性基材１０に、１２μｍ厚の銅箔１１が張り合わされているものを使用した。また、銅のエッチャントとしては、塩化第二鉄を主成分とするものに限らず、塩化第二銅を主成分とするエッチャントを用いてもよい。   (A) First, as shown in FIG. 2A, a CCL in which a copper foil 11 serving as a conductive layer is provided on one surface of an insulating base material 10 made of a polyimide resin film is prepared. The prepared CCL forms a circuit pattern of the first wiring circuit 11 by photolithography. Specifically, after an etching resist is formed on the copper foil 11, chemical etching is performed using an etchant containing ferric chloride as a main component, whereby a first as shown in FIG. A circuit pattern of the wiring circuit 11 is formed to form a single-sided wiring circuit board 1. Here, a CCL in which a 12 μm thick copper foil 11 is bonded to an insulating base material 10 made of a 25 μm thick polyimide resin film was used. Further, the copper etchant is not limited to one containing ferric chloride as a main component, and an etchant containing cupric chloride as a main component may be used.

（ロ）次に、図２（ｃ）に示すように、絶縁性基材１０の第１配線回路１１を形成した面とは反対側の面に、接着剤層１２及び樹脂フィルム１３を加熱圧着により貼り合わせる。接着剤層１２には、２５μｍ厚のエポキシ系熱硬化性フィルム接着材を使用し、樹脂フィルム１３には、２５μｍ厚のポリイミドフィルムを使用した。加熱圧着には真空ラミネータを用い、減圧下の雰囲気中にて、接着剤層１２の硬化温度以下の温度で、０．３ＭＰａの圧力でプレスして貼りあわせた。なお、接着剤層１２は、エポキシ系の熱硬化性フィルム接着材に限定されることはなく、アクリル系などの接着材も使用できるし、熱可塑性ポリイミドなどに代表される熱可塑性接着材であってもよい。また、接着剤層１２は、必ずしもフィルム状でなくともよく、ワニス状の樹脂を塗布して用いてもよい。また、樹脂フィルム１３としては、絶縁性基材１０と同様の材料を用いることができ、紫外線（ＵＶ）照射によって接着や剥離が可能なフィルムを使用することもできる。なお、絶縁性基材１０として、熱可塑性を有する樹脂または半硬化状態の熱硬化樹脂からなる接着性を有するものを用いれば、接着剤層１２を貼り合わせる必要はない。   (B) Next, as shown in FIG. 2 (c), the adhesive layer 12 and the resin film 13 are thermocompression bonded to the surface of the insulating substrate 10 opposite to the surface on which the first wiring circuit 11 is formed. Paste together. The adhesive layer 12 was an epoxy thermosetting film adhesive having a thickness of 25 μm, and the resin film 13 was a polyimide film having a thickness of 25 μm. For thermocompression bonding, a vacuum laminator was used, and pressed and bonded at a pressure not higher than the curing temperature of the adhesive layer 12 at a pressure of 0.3 MPa in an atmosphere under reduced pressure. The adhesive layer 12 is not limited to an epoxy-based thermosetting film adhesive, and an acrylic-based adhesive can also be used, and is a thermoplastic adhesive typified by thermoplastic polyimide. May be. Moreover, the adhesive layer 12 does not necessarily have to be in the form of a film, and may be used by applying a varnish-like resin. Moreover, as the resin film 13, the material similar to the insulating base material 10 can be used, and the film which can be adhere | attached or peeled by ultraviolet-ray (UV) irradiation can also be used. Note that if the insulating base 10 is made of a thermoplastic resin or a semi-cured thermosetting resin, it is not necessary to bond the adhesive layer 12 together.

（ハ）次に、図２（ｄ）に示すように、前述の絶縁性基材１０、接着剤層１２、及び樹脂フィルム１３に、ＹＡＧレーザを用いて、直径１００μｍのビアホール１４ａを成形するとともに、第１配線回路１１には、直径３０μｍ程度の小孔１４ｂを開ロする。そして、ＣＦ4及びＯ2混合ガスによるプラズマデスミア処理を施した後に、図２（ｅ）に示すように、スクリーン印刷法により、ビアホール１４ａ及び小孔１４ｂに導電性ペーストを充填して導電性ペーストビア１５とし、樹脂フィルム１３を剥離する。このとき、印刷充填した導電性ペーストからなる導電性ペーストビア１５の先端は、剥離した樹脂フィルム１３の厚さ分だけ、接着剤層１２の表面より突出し、突起を形成している。なお、ビアホール１４ａ及び小孔１４ｂの形成のために使用するレーザは、ＹＡＧレーザの他に、炭酸ガスレーザ、エキシマレーザなどを使用することもできる。また、ドリル加工や化学的なエッチングによって、ビアホール１４ａ及び小孔１４ｂを形成してもよい。プラズマデスミア処理は、使用するガスの種類が、ＣＦ4及びＯ2の混合ガスに限定されることはなく、Ａｒなど、その他の不活性ガスを使用することもできる。また、ドライ処理ではなく、薬液を用いたウェットデスミア処理でもよい。 (C) Next, as shown in FIG. 2D, a via hole 14a having a diameter of 100 μm is formed on the insulating base material 10, the adhesive layer 12, and the resin film 13 by using a YAG laser. In the first wiring circuit 11, a small hole 14b having a diameter of about 30 μm is opened. Then, after performing a plasma desmear process using a mixed gas of CF 4 and O 2 , as shown in FIG. 2E, the conductive paste is filled in the via holes 14a and the small holes 14b by a screen printing method. Vias 15 are formed, and the resin film 13 is peeled off. At this time, the tip of the conductive paste via 15 made of the printed conductive paste protrudes from the surface of the adhesive layer 12 by the thickness of the peeled resin film 13 to form a protrusion. As a laser used for forming the via hole 14a and the small hole 14b, a carbon dioxide laser, an excimer laser, or the like can be used in addition to the YAG laser. Further, the via hole 14a and the small hole 14b may be formed by drilling or chemical etching. In the plasma desmear process, the type of gas used is not limited to the mixed gas of CF 4 and O 2 , and other inert gases such as Ar can be used. Further, instead of dry treatment, wet desmear treatment using a chemical solution may be used.

（ニ）次に、図２（ｆ）に示すように、ＩＣ電極パット２１、ＩＣ絶縁層２２、ＩＣ再配線層２３を備える厚さ１００μｍのＩＣチップ２０を用意する。そして、ＩＣチップ２０を、半導体チップ用マウンタで位置合わせして、接着剤層１２及び導電性ペーストビア１５をなす導電性ペーストの硬化温度以下で加熱し、ＩＣ再配線層２３と導電性ペーストビア１５の仮留めを行う。   (D) Next, as shown in FIG. 2F, an IC chip 20 having a thickness of 100 μm including an IC electrode pad 21, an IC insulating layer 22, and an IC rewiring layer 23 is prepared. Then, the IC chip 20 is aligned with a semiconductor chip mounter and heated below the curing temperature of the conductive paste forming the adhesive layer 12 and the conductive paste via 15, and the IC rewiring layer 23 and the conductive paste via are heated. Perform 15 temporary fixings.

（ホ）次に、図６（ａ）に示すように、厚さ２００μｍのガラスエポキシ両面板を硬質絶縁性基材３０とする両面配線回路基板３を用意する。ここで用いる両面配線回路基板３は、スルーホール３３によって両面に配置した第２配線回路３１の導通を得るスルーホールタイプである。   (E) Next, as shown in FIG. 6A, a double-sided wiring circuit board 3 having a glass epoxy double-sided board having a thickness of 200 μm as a hard insulating base material 30 is prepared. The double-sided wiring circuit board 3 used here is a through-hole type that obtains conduction of the second wiring circuit 31 arranged on both sides by the through-hole 33.

（ヘ）次に、図６（ｂ）に示すように、硬質絶縁性基材３０にルーター加工機によって深さ方向に１２０μｍのザグリ加工でポケットエリア３４を設ける。   (F) Next, as shown in FIG. 6B, a pocket area 34 is provided on the hard insulating base material 30 by a counterboring process of 120 μm in the depth direction by a router machine.

（ト）次に、図６（ｃ）に示すように、接着剤層１２で使用した接着剤と同様の接着剤を、スクリーン印刷法によってポケットエリア３４の壁面に塗布して接着剤層３５を形成する。   (G) Next, as shown in FIG. 6 (c), the adhesive similar to the adhesive used in the adhesive layer 12 is applied to the wall surface of the pocket area 34 by the screen printing method to form the adhesive layer 35. Form.

（チ）次に、図７（ｄ）に示すように、図２（ｆ）で示した積層体のＩＣチップ２０がポケットエリア３４に内包されるように位置合わせを行い、加熱することで仮留めを行う。   (H) Next, as shown in FIG. 7D, alignment is performed so that the IC chip 20 of the laminate shown in FIG. Make a clasp.

（リ）次に、図７（ｅ）に示すように、図７（ｄ）で示した積層体を、真空キュアプレス機を用いて、１ｋＰａ以下の減圧雰囲気中で加熱圧着する。このとき、接着剤層１２，３５を硬化させて、片面配線回路基板１、両面配線回路基板３、及びＩＣチップ２０との接着をする層間接着剤層６０とし、同時に、導電性ペーストビア１５をなす導電性ペーストの硬化及び合金化が行われる。なお、ここで「硬化」とは、熱硬化（架橋反応）のみならず、加熱により軟化した材料が冷えて硬化する場合も含んでいる。ここで、再配線層の一部となる片面配線回路基板１として、予め回路形成がなされた片面ＣＣＬを用い、また、層間接続に印刷充填した導電性ペーストによる導電性ペーストビア１５を使用することにより、全ての工程においてめっき工程を排除することができ、従来のビルドアップ方式に比べて、生産時間を大幅に短縮することができる。さらに、各層を構成する基材は、予め作成されているため、各工程で発生する不良品をその都度排除することができ、歩留まりの累積を避けることが可能となる。層間接続用の導電性ペーストには、例えば、特開２０００−４９４６０公報に記載されているように、層間接着材の硬化温度程度の低温で合金化する組成のものを適用することで、導電性ペースト内の金属粒子同士、また、銅の接続パッドと導電性ペースト内の金属粒子とが拡散接合し、バルクの金属やめっきによる層間接続と同等の接続信頼性を確保することができる。   (L) Next, as shown in FIG. 7E, the laminated body shown in FIG. 7D is heat-pressed in a reduced pressure atmosphere of 1 kPa or less using a vacuum curing press. At this time, the adhesive layers 12 and 35 are cured to form an interlayer adhesive layer 60 that adheres to the single-sided wiring circuit board 1, the double-sided wiring circuit board 3, and the IC chip 20, and at the same time, the conductive paste via 15 is formed. The resulting conductive paste is cured and alloyed. Here, “curing” includes not only thermal curing (crosslinking reaction) but also a case where a material softened by heating is cooled and cured. Here, as the single-sided wiring circuit board 1 to be a part of the rewiring layer, a single-sided CCL on which a circuit is formed in advance is used, and a conductive paste via 15 made of a conductive paste printed and filled in an interlayer connection is used. Thus, the plating process can be eliminated in all the processes, and the production time can be greatly reduced as compared with the conventional build-up method. Furthermore, since the base material constituting each layer is prepared in advance, defective products generated in each process can be eliminated each time, and accumulation of yield can be avoided. As the conductive paste for interlayer connection, for example, as described in JP 2000-49460 A, a paste having a composition that forms an alloy at a low temperature about the curing temperature of the interlayer adhesive is applied. The metal particles in the paste, and the copper connection pads and the metal particles in the conductive paste are diffusion-bonded to ensure connection reliability equivalent to interlayer connection by bulk metal or plating.

（ヌ）次に、図７（ｆ）及び図７（ｇ）に示すように、図７（ｅ）で示した多層板に、ソルダレジスト４０及びはんだバンプ４１を形成する。ソルダレジスト４０は、液状の感光性樹脂をスクリーン印刷し、パターンを露光した後に現像し形成する。はんだバンプ４１は、はんだペーストをパターン印刷し、リフローすることにより、ボール状に形成する。そして、図７（ｇ）に示すように、片面配線回路基板１上に形成したソルダレジスト４０に別途ＩＣチップ５０を搭載し、第１配線回路１１とＩＣ電極パット５１とを金ワイヤ５２等で接続する。以上の工程により、本発明の第２の実施の形態に係る多層配線板が得られる。   (N) Next, as shown in FIGS. 7 (f) and 7 (g), solder resists 40 and solder bumps 41 are formed on the multilayer board shown in FIG. 7 (e). The solder resist 40 is formed by screen-printing a liquid photosensitive resin, exposing the pattern, and developing the pattern. The solder bump 41 is formed into a ball shape by pattern printing of solder paste and reflowing. Then, as shown in FIG. 7G, a separate IC chip 50 is mounted on the solder resist 40 formed on the single-sided wiring circuit board 1, and the first wiring circuit 11 and the IC electrode pad 51 are connected by a gold wire 52 or the like. Connecting. Through the above steps, a multilayer wiring board according to the second embodiment of the present invention is obtained.

本発明の第２の実施の形態に係る多層配線板によれば、両面配線回路基板３を用いることで両面にＩＣチップ５０等の様々な部品を実装することができる。また、第２の実施の形態に係る多層配線板は、ＩＣチップ２０を両面配線回路基板３内に封止することで、封止する領域の基材の厚さを確保する必要性がなくなり、電気的機能としては意味をなさない絶縁層や回路層を設けることによる製造上の煩雑さと材料の浪費を避けることができる。   According to the multilayer wiring board according to the second embodiment of the present invention, various components such as the IC chip 50 can be mounted on both surfaces by using the double-sided wiring circuit board 3. Further, the multilayer wiring board according to the second embodiment eliminates the need to secure the thickness of the base material in the region to be sealed by sealing the IC chip 20 in the double-sided wiring circuit board 3. By providing an insulating layer or a circuit layer that does not make sense as an electrical function, it is possible to avoid manufacturing complexity and waste of materials.

また、第２の実施の形態に係る多層配線板によれば、ＩＣチップ２０直下の両面配線回路基板３の表層にも配線が可能となる。   In addition, according to the multilayer wiring board according to the second embodiment, wiring is also possible on the surface layer of the double-sided wiring circuit board 3 immediately below the IC chip 20.

また、第２の実施の形態に係る多層配線板によれば、両面配線回路基板３とＩＣチップ２０の間は、片面配線回路基板１で用いた接着剤層１２と同様の材料である接着剤で充填されるので、ＩＣチップ２０の安定性が高くなる。更に、ＩＣチップ２０は、層間接着剤層６０によって固着・封入されるので、ＩＣチップ２０に接触する接着材の適度な弾性により、ＩＣチップ２０に対して周囲の材料から及ぼされる熱応力などを緩和する作用が生じる。   Further, according to the multilayer wiring board according to the second embodiment, the adhesive between the double-sided wiring circuit board 3 and the IC chip 20 is the same material as the adhesive layer 12 used in the single-sided wiring circuit board 1. Therefore, the stability of the IC chip 20 is increased. Further, since the IC chip 20 is fixed and sealed by the interlayer adhesive layer 60, the thermal stress exerted on the IC chip 20 from the surrounding materials by the appropriate elasticity of the adhesive contacting the IC chip 20 is reduced. A relaxing action occurs.

本発明の第２の実施の形態に係る多層配線板製造方法によれば、簡便且つコストがかからない工法で、高精細な部品を実装した多層配線板を製造することができる。   According to the multilayer wiring board manufacturing method according to the second embodiment of the present invention, a multilayer wiring board on which high-definition components are mounted can be manufactured by a simple and inexpensive method.

（第３の実施の形態）
（多層配線板）
本発明の第３の実施の形態に係る多層配線板は、図７に示すように、図１で示した多層配線板と比して、両面配線回路基板３として所望の箇所を開口させたマザーボードとする点が異なる。他は図１に示した多層配線板と実質的に同様であるので、重複した記載を省略する。 (Third embodiment)
(Multilayer wiring board)
As shown in FIG. 7, the multilayer wiring board according to the third embodiment of the present invention has a mother board having a desired portion opened as a double-sided wiring circuit board 3 as compared with the multilayer wiring board shown in FIG. Is different. Others are substantially the same as those of the multilayer wiring board shown in FIG.

本発明の第３の実施の形態に係る多層配線板によれば、両面配線回路基板３を用いることで両面にＩＣチップ５０等の様々な部品を実装することができる。また、第３の実施の形態に係る多層配線板は、ＩＣチップ２０を両面配線回路基板３内に封止することで、封止する領域の基材の厚さを確保する必要性がなくなり、電気的機能としては意味をなさない絶縁層や回路層を設けることによる製造上の煩雑さと材料の浪費を避けることができる。   According to the multilayer wiring board according to the third embodiment of the present invention, various components such as the IC chip 50 can be mounted on both surfaces by using the double-sided wiring circuit board 3. Moreover, the multilayer wiring board according to the third embodiment eliminates the need to secure the thickness of the base material in the region to be sealed by sealing the IC chip 20 in the double-sided wiring circuit board 3, By providing an insulating layer or a circuit layer that does not make sense as an electrical function, it is possible to avoid manufacturing complexity and waste of materials.

また、第３の実施の形態に係る多層配線板によれば、両面配線回路基板３として所望の箇所を開口させたマザーボードを用いるので、設計の自由度が向上する。   In addition, according to the multilayer wiring board according to the third embodiment, since the mother board having a desired portion opened is used as the double-sided wiring circuit board 3, the degree of design freedom is improved.

（その他の実施の形態）
上記のように、本発明は実施の形態によって記載したが、この開示の一部をなす記述及び図面はこの発明を限定するものであると理解するべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかになるはずである。 (Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques should be apparent to those skilled in the art.

例えば、第２の実施の形態において、ポケットエリア３４とＩＣチップ２０の間には接着剤が充填されると記載したが、接着剤だけには限らず、エポキシ樹脂、ウレタン樹脂、及びアクリル樹脂等の絶縁性樹脂を用いることもできる。   For example, in the second embodiment, it has been described that an adhesive is filled between the pocket area 34 and the IC chip 20, but not limited to the adhesive, an epoxy resin, a urethane resin, an acrylic resin, or the like. Insulating resin can also be used.

また、第２の実施の形態において、ポケットエリア３４の壁面に接着剤層３５を形成する方法として、大気中でスクリーン印刷法によって接着剤層３５を形成するとしたが、ポケットエリア３４の隅への空気の混入を避ける方法として真空下でスクリーン印刷する印刷機を適用することもできる。また、ディスペンサーによって塗布することもできる。   In the second embodiment, as a method of forming the adhesive layer 35 on the wall surface of the pocket area 34, the adhesive layer 35 is formed by screen printing in the atmosphere. As a method for avoiding air contamination, a printing machine that performs screen printing under vacuum can be applied. It can also be applied by a dispenser.

この様に、本発明はここでは記載していない様々な実施の形態等を包含するということを理解すべきである。したがって、本発明はこの開示から妥当な特許請求の範囲の発明特定事項によってのみ限定されるものである。   Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

本発明の第１の実施の形態に係る多層配線板の模式的断面図である。1 is a schematic cross-sectional view of a multilayer wiring board according to a first embodiment of the present invention. 本発明の第１及び第２実施の形態に係る多層配線板の製造方法を示す工程断面図（その１）である。It is process sectional drawing (the 1) which shows the manufacturing method of the multilayer wiring board which concerns on 1st and 2nd embodiment of this invention. 本発明の第１実施の形態に係る多層配線板の製造方法を示す工程断面図（その２）である。It is process sectional drawing (the 2) which shows the manufacturing method of the multilayer wiring board which concerns on 1st Embodiment of this invention. 本発明の第２の実施の形態に係る多層配線板の模式的断面図である。It is a typical sectional view of a multilayer wiring board concerning a 2nd embodiment of the present invention. 本発明の第２実施の形態に係る多層配線板の製造方法を示す工程断面図（その２）である。It is process sectional drawing (the 2) which shows the manufacturing method of the multilayer wiring board which concerns on 2nd Embodiment of this invention. 本発明の第２実施の形態に係る多層配線板の製造方法を示す工程断面図（その３）である。It is process sectional drawing (the 3) which shows the manufacturing method of the multilayer wiring board which concerns on 2nd Embodiment of this invention. 本発明の第３の実施の形態に係る多層配線板の模式的断面図である。It is typical sectional drawing of the multilayer wiring board which concerns on the 3rd Embodiment of this invention. 従来のプリント配線板の構成を示す断面図（その１）である。It is sectional drawing (the 1) which shows the structure of the conventional printed wiring board. 従来のプリント配線板の構成を示す断面図（その２）である。It is sectional drawing (the 2) which shows the structure of the conventional printed wiring board. 従来のプリント配線板の構成を示す断面図（その３）である。It is sectional drawing (the 3) which shows the structure of the conventional printed wiring board. 多層の再配線層を有する従来の多層配線板の構成を示す断面図（その１）である。It is sectional drawing (the 1) which shows the structure of the conventional multilayer wiring board which has a multilayer rewiring layer. 多層の再配線層を有する従来の多層配線板の構成を示す断面図（その２）である。It is sectional drawing (the 2) which shows the structure of the conventional multilayer wiring board which has a multilayer rewiring layer.

符号の説明Explanation of symbols

１…片面配線回路基板
３…両面配線回路基板
１０…絶縁性基材
１１…第１配線回路
１２，３５…接着剤層
１３…樹脂フィルム
１４ａ…ビアホール
１４ｂ…小孔
１５…導電性ペーストビア
２０…ＩＣチップ
２１…ＩＣ電極パット
２２…ＩＣ絶縁層
２３…ＩＣ再配線層
３０…硬質絶縁性基材
３１…第２配線回路
３２…メッキ
３３…スルーホール
３４…ポケットエリア
３５…接着剤層
４０…ソルダレジスト
４１…バンプ
５０…チップ
５０…ＩＣチップ
５１…ＩＣ電極パット
５２…金ワイヤ
６０…層間接着剤層 DESCRIPTION OF SYMBOLS 1 ... Single-sided wiring circuit board 3 ... Double-sided wiring circuit board 10 ... Insulating base material 11 ... 1st wiring circuit 12, 35 ... Adhesive layer 13 ... Resin film 14a ... Via hole 14b ... Small hole 15 ... Conductive paste via 20 ... IC chip 21 ... IC electrode pad 22 ... IC insulating layer 23 ... IC rewiring layer 30 ... Hard insulating substrate 31 ... Second wiring circuit 32 ... Plating 33 ... Through hole 34 ... Pocket area 35 ... Adhesive layer 40 ... Solder Resist 41 ... Bump 50 ... Chip 50 ... IC chip 51 ... IC electrode pad 52 ... Gold wire 60 ... Interlayer adhesive layer

Claims (10)

ＩＣチップと、
絶縁性基材の片面に第１配線回路、他面側に接着剤層が配置され、前記絶縁性機材と前記接着剤層を貫通して前記第１配線回路と導通する導電性ペーストビアを有する片面配線回路基板と、
硬質絶縁性基材の両面に前記導電性ペーストビアと導通している第２配線回路が配置されており、前記硬質絶縁性基材には前記導電性ペーストビアと導通している前記ＩＣチップを内包するように開口が施された両面配線回路基板
とを備え、前記接着剤層によって前記ＩＣチップ及び前記両面配線回路基板が保持されることを特徴とする多層配線板。 IC chip,
A first wiring circuit is disposed on one side of the insulating substrate, an adhesive layer is disposed on the other side, and a conductive paste via that penetrates the insulating material and the adhesive layer and is electrically connected to the first wiring circuit is provided. A single-sided circuit board;
A second wiring circuit that is electrically connected to the conductive paste via is disposed on both surfaces of the hard insulating substrate, and the IC chip that is electrically connected to the conductive paste via is disposed on the hard insulating substrate. A multilayer wiring board comprising: a double-sided wiring circuit board having an opening so as to be enclosed, wherein the IC chip and the double-sided wiring circuit board are held by the adhesive layer. 前記両面配線回路基板は、前記ＩＣチップを内包する開口が貫通していることを特徴とする請求項１に記載の多層配線板。   The multilayer wiring board according to claim 1, wherein the double-sided wiring circuit board has an opening through which the IC chip is contained. 前記硬質絶縁性基材の厚さは、前記ＩＣチップと略同等の厚さであることを特徴とする請求項１又は２に記載の多層配線板。   3. The multilayer wiring board according to claim 1, wherein a thickness of the hard insulating substrate is substantially equal to that of the IC chip. 前記両面配線回路基板は、前記ＩＣチップを内包する開口が貫通していないポケットエリアであることを特徴とする請求項１に記載の多層配線板。   2. The multilayer wiring board according to claim 1, wherein the double-sided wiring circuit board is a pocket area through which an opening containing the IC chip does not penetrate. 前記ポケットエリアと前記ＩＣチップの間には、絶縁性樹脂が充填されていることを特徴とする請求項４に記載の多層配線板。   The multilayer wiring board according to claim 4, wherein an insulating resin is filled between the pocket area and the IC chip. 充填された前記絶縁性樹脂は、前記接着剤層と同様の材料であることを特徴とする請求項５に記載の多層配線板。   The multilayer wiring board according to claim 5, wherein the filled insulating resin is made of the same material as the adhesive layer. 絶縁性基材の片面に第１配線回路、他面側に接着剤層が配置され、前記絶縁性機材と前記接着剤層を貫通して前記第１配線回路と導通する導電性ペーストビアを有する片面配線回路基板を用意する工程と、
ＩＣチップを用意し、前記ＩＣチップと前記導電性ペーストビアの仮留めを行う工程と、
硬質絶縁性基材の両面に前記導電性ペーストビアと導通している第２配線回路が配置されており、前記硬質絶縁性基材には前記導電性ペーストビアと導通している前記ＩＣチップを内包するように開口が施された両面配線回路基板を用意する工程と、
前記両面配線回路基板の開口の位置に前記ＩＣチップを配置するように、前記両面配線回路基板を前記接着剤層に位置合わせして配置する工程と、
前記片面配線回路基板と前記両面配線回路基板を加熱加圧して多層化する工程
とを含むことを特徴とする多層配線板製造方法。 A first wiring circuit is disposed on one side of the insulating substrate, an adhesive layer is disposed on the other side, and a conductive paste via that penetrates the insulating material and the adhesive layer and is electrically connected to the first wiring circuit is provided. Preparing a single-sided wiring circuit board;
Preparing an IC chip, and temporarily fastening the IC chip and the conductive paste via;
A second wiring circuit that is electrically connected to the conductive paste via is disposed on both surfaces of the hard insulating substrate, and the IC chip that is electrically connected to the conductive paste via is disposed on the hard insulating substrate. A step of preparing a double-sided wiring circuit board having an opening so as to be included;
Placing the double-sided wiring circuit board in alignment with the adhesive layer so as to place the IC chip at the opening of the double-sided wiring circuit board;
And a step of heating and pressing the single-sided wiring circuit board and the double-sided wiring circuit board to form a multilayer. 前記両面配線回路基板を前記接着剤層に位置合わせして配置する工程は、前記両面配線回路基板の貫通していないポケットエリアである開口に前記ＩＣチップを位置合わせして配置することを特徴とする請求項７に記載の多層配線板製造方法。   The step of aligning and arranging the double-sided wiring circuit board with the adhesive layer is characterized in that the IC chip is aligned and arranged in an opening that is a pocket area that does not penetrate the double-sided wiring circuit board. The method for producing a multilayer wiring board according to claim 7. 加熱加圧して多層化する工程は、前記ポケットエリアと前記ＩＣチップの間に、絶縁性樹脂を流入させ充填することを特徴とする請求項８に記載の多層配線板製造方法。   9. The method of manufacturing a multilayer wiring board according to claim 8, wherein the step of multilayering by heating and pressurizing fills an insulating resin between the pocket area and the IC chip. 前記前記ポケットエリアと前記ＩＣチップの間に充填する絶縁性樹脂は、前記接着剤層と同様の材料であることを特徴とする請求項９に記載の多層配線板製造方法。   The method for manufacturing a multilayer wiring board according to claim 9, wherein the insulating resin filled between the pocket area and the IC chip is made of the same material as the adhesive layer.
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