JP2009151243A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a display device using a plurality of display panels using a high-frequency clock signal based on high image quality and high performance, where influence of electromagnetic wave disturbance is hardly caused by reducing unwanted radiation. <P>SOLUTION: The display device comprises a red signal display circuit 100, and a green signal display circuit and a blue signal display circuit having the same constitution, which are operated in parallel. Image data read from an SDRAM 108 according to a clock of frequency F1r is temporarily stored in a FIFO 103. The FIFO 103 reads red signal data according to a clock of frequency F2r and supplies it to the display panel 110 through a D/A converter 109. The clock frequency F1r of the red signal display circuit 100, and the corresponding clock frequency of the green signal display circuit and the blue signal display circuit are different from each other. The readout clock frequency F2r of the FIFO 103 transmitted to the display panel 110 of the red signal display circuit 100, and the corresponding clock frequency of the green signal display circuit and the blue signal display circuit are different from each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device such as a liquid crystal display device characterized by developing a video signal into a plurality of display panel operation signals.

  In a display device such as a liquid crystal display device, generally, a video signal is divided into three primary color signals corresponding to the three primary colors of light of a red signal, a green signal, and a blue signal, and these are divided into a plurality of display panel systems. Input and compose to display a color image. Such a liquid crystal display device does not directly input the input signal to the liquid crystal panel in order to develop the drive signal suitable for the operation of the liquid crystal, but (1) temporarily stores the video signal in the external memory and sets the frame frequency. It is common to perform optimization processing by frequency conversion, such as displaying faster, or (2) using a low frequency suitable for the operation of the liquid crystal panel and deploying to a plurality of wirings.

  Also, after the input image data is converted into parallel data by the serial / parallel conversion unit, the image data is temporarily stored in the first FIFO unit, and then the image data is read from the first FIFO unit at the input rate to the frame memory. In a device that performs writing and reading the image data from the frame memory at twice the above rate and stores it in the second FIFO unit, the size of the first FIFO unit is set to the image to the frame memory. Input image data can be accumulated during a period corresponding to the sum of a period required for writing data, a period required for reading image data from the frame memory a plurality of times, and a period required for the frame memory command. Technology to use a device with a size for a decoder that converts an input video signal into an image signal compatible with a liquid crystal panel is developed. Is (e.g., see Patent Document 1). As a result, it is possible to read up to two frames during a period in which one frame of image data is written to the frame memory.

  In a display device that separates a video signal into three primary color signals, processes the primary color signals with separate three circuits, inputs them to a plurality of display panel systems, and combines them to display a color image, the above 3 The two circuits were operating at the same timing and clock frequency, and there were no problems in order to simplify the design.

  However, in recent years, in the field of display devices such as liquid crystal projectors and television receivers, for example, high-definition such as high-definition and image quality improvement by adding image processing functions has been remarkable, so that the number of pixels and digital image processing functions are increased. Incorporation requires a large-scale digital storage circuit, which generally requires operation at a frequency higher than the frequency of the display video signal, increases the transfer amount of the video signal, and increases the clock frequency. Along with this, generation of large digital noise and unnecessary radiation is increasing.

  Further, in the conventional display device in which the three primary color signals are processed by three separate circuits and input to a plurality of display panel systems and combined to display a color image, the above three operations operating at the same timing and clock frequency are performed. Since the circuit operates at the same clock frequency and timing, unnecessary radiation three times that of one circuit is generated. The frequency spectrum of unnecessary radiation at this time is shown in FIG. FIG. 4 shows an unnecessary radiation spectrum when the clock frequency is 120 MHz and the frequency of the input analog signal of the display panel is 28 MHz, and 120 MHz and 28 MHz and their harmonics are observed, respectively. As shown in the figure, an unnecessary radiation spectrum having a large 120 MHz and its harmonics is shown.

  As a conventional method for countermeasures against unnecessary radiation, for example, an example of shifting the clock phase between a plurality of circuits (see, for example, Patent Document 2), a method for reducing unnecessary radiation by controlling fluctuation of the clock frequency by frequency spreading (for example, Patent Document). 3) is proposed.

Japanese Patent No. 3359270 JP 2005-144848 A JP 2005-269089 A

  However, the unnecessary radiation reduction methods described in Patent Document 2 and Patent Document 3 are not perfect. For example, in Patent Document 2, shifting the clock phase is effective in concentrating current peaks, but the frequency used is the same, and there is a limit in reducing unnecessary radiation. Further, in the case of Patent Document 3, depending on the circuit configuration system, it is necessary to perform not only clock but also data spread in the same way by performing frequency spreading, and depending on component parts (such as PLL). There is a circuit that cannot absorb changes due to fluctuation control, so it is not a perfect solution.

  In addition, the video signal is transmitted in parallel by a plurality of data lines synchronized with the clock frequency. Since a display device using a plurality of display panels operates at the same frequency at a plurality of locations in the device, there is a problem that electromagnetic interference is likely to occur in the conventional display device when the clock frequency is increased.

  The present invention has been made in view of the above points, and even when a plurality of display panels using a clock signal having a high frequency due to high image quality and high performance are used, unnecessary radiation is reduced and the influence of electromagnetic interference occurs. An object is to provide a display device that is difficult to display.

In order to achieve the above object, the present invention includes a plurality of display circuits each including at least a storage circuit for storing image data and a display panel for displaying image data read from the storage circuit. A display device that inputs different image data in parallel to a plurality of display circuits, operates the plurality of display circuits in parallel, and displays images of different colors on a plurality of display panels, respectively.
Each of the plurality of display circuits is
The input image data is written to the storage circuit at a first clock frequency and then read, control means for reading, temporary storage means for temporarily storing the image data read from the storage circuit, and image data from the temporary storage means And reading means for reading the image at a clock frequency of 2 and supplying it to the display panel to display an image, and one or both of the first clock frequency and the second clock frequency of at least one display circuit of the plurality of display circuits. Is set to a frequency different from the clock frequency corresponding to the other display circuit among the plurality of display circuits.

  According to the present invention, it is possible to reduce unnecessary radiation with respect to a specific frequency and to suppress electromagnetic interference at the specific frequency to a low level by dispersing the frequencies used as the entire display device.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of a main part of a display device according to the present invention. The display device of this embodiment includes a total of three display circuits: a red signal display circuit 100 shown in FIG. 1, and a green signal display circuit and a green signal display circuit each having the same configuration as that in FIG.

  The red signal display circuit 100 writes a first FIFO (First In First Out) 102 that reads and reads a red signal that is an input primary color signal, and a red signal that is input through the control unit 101 and reads the red signal. 2 FIFO 103, an oscillator 104 that oscillates at a predetermined frequency, frequency dividers / multipliers 105 and 106 that divide and multiply the frequency of the oscillation signal output from the oscillator 104, and a synchronization signal synchronized with the input synchronization signal A synchronous signal generator 107 for generating the input signal, an SDRAM (Synchronous Dynamic Random Access Memory) 108 to be read after the input red signal is written, a D / A converter 109 for converting the output data of the FIFO 103 into an analog signal, and D The display panel 110 displays a 16-phase analog signal output from the / A converter 109. The green signal display circuit and the blue signal display circuit have the same configuration as that in FIG. 1, but the oscillator 104 may be shared by three display circuits.

  Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. Red signal data which is a primary color signal input to the red signal display circuit 100 of FIG. 1 is, for example, image data having a quantization bit number of 10 bits, and is supplied to the FIFO 102 together with a two-phase clock of 74.25 MHz and a clock frequency of Once stored in the FIFO 102 at .25 MHz, the frequency of the oscillation signal output from the oscillator 104 is once divided to a low frequency, and then multiplied to a high frequency. The SDRAM 108 with the frequency F1r from the frequency divider / multiplier 105 is multiplied. The data is read by the clock and written to the SDRAM 108 by the clock having the frequency F1r.

  FIG. 2A shows the vertical synchronization signal of the input primary color signal and each line (LINE). Here, the input primary color signal (red signal data) is a progressive video signal having a horizontal direction of 1920 pixels and a vertical direction of 1080 pixels and a vertical synchronization signal frequency of 60 Hz (the same applies to other green signal data and blue signal data). Accordingly, an input red signal for 1080 lines is written in the SDRAM 108 in the effective period 16.0 msec in one frame period 16.6 msec, as shown in FIG. Here, the clock frequency F1r is 119 MHz.

  The control unit 101 writes the red signal data for one frame to the SDRAM 108 and controls writing and reading of the SDRAM 108 so that the written red signal data for one frame is read twice. Here, as shown in FIGS. 2B and 2C, when one line to 540 lines of red signal data are written into the SDRAM 108, one line of red signal data already written from the SDRAM 108. Reading is started at the above clock frequency F1r. Subsequently, the control unit 101 controls the SDRAM 108 to perform red signal data write control from the 541th line to the 1080th line, and at the same time, continues the red signal data read operation.

  When the first read operation of red signal data is completed, the control unit 101 continues to start the second read of red signal data as shown in FIG. Therefore, the control unit 101 performs writing once and reading twice in one vertical period (one frame period) with respect to the SDRAM 108. In this case, the data amount handled by the SDRAM 108 in one frame period is required to be three times the data amount of one frame of input red signal data (10 bits × 1920 × 1080), and this is processed by a 32-bit bus. The required number of clocks is 1944000 clocks, which is 1/32 times that number.

  When this clock is processed in one vertical period (16.6 msec), the clock frequency of the SDRAM 108 becomes 117 MHz, and when this is processed only in the effective period (16.0 msec), it becomes 122 MHz. Therefore, in order to cause the SDRAM 108 to perform a write operation once and read twice within one vertical period, the clock frequency of writing and reading of the SDRAM 108 may be 117 MHz to 122 MHz. Here, the clock frequency F1r of the SDRAM 108 in the red signal display circuit 100 is 119 MHz as described above.

  Note that in FIG. 2C, the solid hatched line indicates a change in the read line when read at the lowest clock frequency, and the dotted hatched line indicates a change in the read line when read at the highest clock frequency. . In addition, the writing of the next one frame is started in the middle of the second reading of the SDRAM 108, but the reading line and the writing write do not overlap.

  The red signal data read out twice from the SDRAM 108 as described above may be transmitted to the display panel 110 as it is, but there are restrictions on the operation of the display panel 110 and the long wiring length. For the reason, it is once written in the FIFO 103.

  The FIFO 103 frequency-divides the oscillation signal frequency output from the oscillator 104 by the frequency divider / multiplier 106 to a low frequency, and then reads the red signal data with a clock of the frequency F2r obtained by multiplying the frequency to a high frequency. / A converter 109 to output. Here, the clock frequency F2r is a transmission frequency to the display panel 110, and is set to 27 MHz, for example. The D / A converter 109 D / A converts the input red signal data into a 16-phase analog signal and supplies it to the display panel 110 to display a red image.

  The green signal display circuit and the blue signal display circuit have the same circuit configuration as that in FIG. 1. Each of the image data has a quantization bit number of 10 bits, and the green signal data and the blue signal data input together with a two-phase clock of 74.25 MHz On the other hand, the same operation is performed in parallel with the red signal display circuit 100 to display the green image and the blue image separately and simultaneously on the respective display panels. Here, in the green signal display circuit, the writing and reading frequency F1g of the above-mentioned SDRAM is selected to be 120 MHz and the sending frequency F2g to the display panel is set to 28 MHz, and in the blue signal display circuit, the writing and reading frequency F1b of the above-mentioned SDRAM is selected. The difference is that 121 MHz and the transmission frequency F2b to the display panel are selected to be 29 MHz. Table 1 summarizes the frequencies of the signal display circuits described above and compares them with the conventional example.

表１に示すように、従来は赤信号表示回路、緑信号表示回路、青信号表示回路は、いずれもＳＤＲＡＭの書き込み及び読み出し周波数（クロック周波数）が１２０ＭＨｚと同一であり、かつ、表示パネルへの送出周波数も２８ＭＨｚと同一であるのに対し、本実施の形態では、ＳＤＲＡＭの書き込み及び読み出し周波数（クロック周波数）が赤信号表示回路では１１９ＭＨｚ、緑信号表示回路では１２０ＭＨｚ、青信号表示回路では１２１ＭＨｚと互いに整数倍の関係に無い異なる周波数に設定されており、また、表示パネルへの送出周波数も赤信号表示回路では２７ＭＨｚ、緑信号表示回路では２８ＭＨｚ、青信号表示回路では２９ＭＨｚと互いに整数倍の関係に無い異なる周波数に設定されている。

As shown in Table 1, the conventional red signal display circuit, green signal display circuit, and blue signal display circuit all have the same SDRAM write and read frequency (clock frequency) of 120 MHz and are sent to the display panel. While the frequency is the same as 28 MHz, in this embodiment, the write and read frequencies (clock frequencies) of the SDRAM are 119 MHz for the red signal display circuit, 120 MHz for the green signal display circuit, and 121 MHz for the blue signal display circuit. The frequency is set to a different frequency that does not have a double relationship, and the transmission frequency to the display panel is 27 MHz for the red signal display circuit, 28 MHz for the green signal display circuit, and 29 MHz for the blue signal display circuit, which are not in an integer multiple relationship. The frequency is set.

  FIG. 3 shows an unnecessary radiation spectrum according to this embodiment. In FIG. 3, the solid lines indicate SDRAM write and read frequencies 119 MHz, 120 MHz, and 121 MHz and their harmonics, and the dotted lines indicate 27 MHz, 28 MHz, and 29 MHz and their harmonics that are sent to the display panel.

  Since the frequency and harmonic energy in the unwanted radiation spectrum in the present embodiment shown in FIG. 3 are different in the write and read frequencies of the SDRAM in the three primary color display circuits, the SDRAM shown by the solid line in FIG. As compared with the conventional unnecessary radiation spectrum in which the writing frequency and reading frequency of the three primary color display circuits are the same, the writing frequency and the reading frequency are tripled as shown by the solid line, but by dividing the frequency, the energy at each frequency is 1 / 3 (approximately 5.7 dB reduction). As described above, according to the present embodiment, the write and read frequencies of the SDRAM are made different from each other in the three primary color display circuits, so that unnecessary radiation energy can be reduced.

  In particular, in the case of a clock signal of high frequency, a rectangular wave is used because data is determined at the timing of the rising edge and falling edge of the clock signal. As a result, the clock signal includes high-order frequency components (frequency that is an integral multiple of the fundamental frequency) (here, for the sake of simplicity, frequencies of the fundamental wave, 3 times, 5 times, and 7 times are displayed). When the frequency is set differently for each of the red, green, and blue display circuits, it is necessary to prevent these higher-order frequency components from being the same.

  In the present embodiment, the data read from the SDRAM 108 is once stored in the FIFO 103, then read out at the same frequency as the transmission frequency to the display panel, and sent to the D / A converter 109. It is converted into a signal and supplied to the display panel 110. In FIG. 1, the D / A converter 109 is composed of 16 D / A converters and outputs 16-phase analog signals.

  In this case, in this embodiment, the transmission frequency to the display panel is made different from 27 MHz, 28 MHz, and 29 MHz in the three primary color display circuits. Therefore, in the unnecessary radiation spectrum in this embodiment shown by a dotted line in FIG. As shown in the frequency and harmonic energy, the frequency to the display panel indicated by the dotted line in FIG. 4 is three times that of the conventional unnecessary radiation spectrum in which the three primary color display circuits have the same 28 MHz. By dividing the frequency, energy at each frequency can be reduced.

  In the above embodiment, the SDRAM writing and reading frequencies of the three primary color signal display circuits and the sending frequency to the display panel are different, but at least one of the two primary color signal display circuits is used. It is only necessary to change the writing and reading frequencies of the SDRAM and the sending frequency to the display panel. Further, only one of the writing and reading frequencies of the SDRAM and the sending frequency to the display panel may be made different.

  In the above embodiment, an example of double speed conversion in a liquid crystal display device has been described. However, the present invention is not limited to this, and for example, a high-speed memory such as a field memory is used. In the signal processing system and digital processing system used, three signal processing systems such as the three primary color signals R, G, B or the luminance signal Y and the two kinds of color signals Pb and Pr are operated in parallel at the same timing. It can also be applied to signal processing systems.

  In the above embodiment, the example in which the digital video signal is converted into the analog signal by the D / A converter has been described. However, the analog conversion is not necessarily performed, and the signal is input to the display panel as the digital signal. The same effect can be obtained even if

It is a block diagram of one Embodiment of the principal part of the display apparatus of this invention. 2 is a timing chart for explaining the operation of FIG. 1. It is a figure which shows the unnecessary radiation spectrum in one embodiment of this invention apparatus. It is a figure which shows the unnecessary radiation spectrum in an example of the conventional display apparatus.

Explanation of symbols

100 Red signal display circuit 101 Control unit 102, 103 FIFO
104 Oscillator 105, 106 Frequency Divider / Multiplier 107 Synchronization Signal Generation Unit 108 Synchronous Dynamic Random Access Memory (SDRAM)
109 D / A converter 110 Display panel

Claims (2)

A plurality of display circuits including at least a storage circuit for storing image data and a display panel for displaying the image data read from the storage circuit are provided, and the image data different from each other are provided in the plurality of display circuits. Are displayed in parallel, and the plurality of display circuits are operated in parallel to display images of different colors on the plurality of display panels, respectively.
Each of the plurality of display circuits is
Control means for reading the input image data after writing it to the storage circuit at a first clock frequency;
Temporary storage means for temporarily storing the image data read from the storage circuit;
Reading means for reading out the image data from the temporary storage means at a second clock frequency and supplying the read data to the display panel to display an image; and the first display circuit of at least one display circuit of the plurality of display circuits. One or both of the clock frequency and the second clock frequency are set to a frequency different from the corresponding clock frequency of the other display circuit among the plurality of display circuits.   One or both of the first clock frequency and the second clock frequency of at least one display circuit of the plurality of display circuits are different from corresponding clock frequencies of other display circuits of the plurality of display circuits. 2. The display device according to claim 1, wherein the display device is set to a frequency that is not an integer multiple of each other.

Images