JP2009170456A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided that can easily suppress deterioration of characteristics of a semiconductor device due to formation of a sub-trench.
A reactive ion etching process for forming a groove in a semiconductor by removing a part of the surface of the semiconductor by reactive ion etching, and an inclination at an angle of greater than 0 ° and less than 45 ° with respect to the bottom surface of the groove. And a low-angle ion milling process in which a part of the bottom surface of the groove is removed by irradiating an ion beam from the above direction.
[Selection] Figure 6

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can easily suppress deterioration of characteristics of a semiconductor device due to formation of a sub-trench.

  In recent years, semiconductor devices such as power devices using a wide band gap semiconductor such as silicon carbide (SiC) have attracted attention from the viewpoint of low power consumption, and among them, MOSFETs (Metal Oxide Semiconductor Fields) having normally-off characteristics Effect Transistor) is being researched by various institutions.

  Currently, DiMOSFET (Double-Implanted MOSFET) is the main MOSFET, but UMOSFET (trench gate MOSFET) in which the groove formed in the semiconductor becomes the trench gate portion is superior in that it can reduce the on-resistance most. ing.

  However, UMOSFET has a fact that there are few research reports due to variations in the formation of the groove portion serving as the trench gate portion.

  Hereinafter, a conventional UMOSFET manufacturing method will be described with reference to schematic cross-sectional views of FIGS.

  First, as shown in FIG. 11, for example, n-type silicon carbide substrate 101 is prepared. Next, as shown in FIG. 12, n − type silicon carbide crystal layer 102 is formed by epitaxially growing an n − type silicon carbide crystal on the surface of n type silicon carbide substrate 101. Here, the n type impurity concentration of n − type silicon carbide crystal layer 102 is set lower than the n type impurity concentration of n type silicon carbide substrate 101.

  Next, as shown in FIG. 13, p-type silicon carbide crystal layer 103 is formed by epitaxially growing a p-type silicon carbide crystal on the surface of n − -type silicon carbide crystal layer 102.

  Next, as shown in FIG. 14, n-type silicon carbide crystal layer 104 is formed by epitaxially growing an n-type silicon carbide crystal on the surface of p-type silicon carbide crystal layer 103. Here, the n-type impurity concentration of n-type silicon carbide crystal layer 104 is set higher than the n-type impurity concentration of n − -type silicon carbide crystal layer 102.

  Thereafter, as shown in FIG. 15, a part of n-type silicon carbide crystal layer 102, p-type silicon carbide crystal layer 103 and n-type silicon carbide crystal layer 104 is removed by reactive ion etching (RIE). By doing so, the surface of n − type silicon carbide crystal layer 102 is exposed to form groove 110. Here, in the groove 110, a sub-trench 109, which is a groove shallower than the groove 110, is formed at the base portion of the side wall of the groove 110.

  Then, as shown in FIG. 16, the gate insulating film 105 is formed so as to fill the trench 110, and the gate electrode 106 is formed on the gate insulating film 105. Further, source electrode 107 is formed on the surface of n-type silicon carbide crystal layer 104, and drain electrode 108 is formed on the back surface of n-type silicon carbide substrate 101. Thus, the UMOSFET is completed.

  However, the conventional UMOSFET manufactured as described above has a problem that the high breakdown voltage characteristic of the UMOSFET is impaired because electric field concentration may occur in the sub-trench 109 portion and the dielectric breakdown may occur. .

  FIGS. 17 to 19 illustrate an example of an experiment in which a part of the surface of the silicon carbide substrate is removed by reactive ion etching.

  First, as shown in the schematic cross-sectional view of FIG. 17, a resist 202 is formed on part of the surface of silicon carbide substrate 201.

  Next, as shown in the schematic cross-sectional view of FIG. 18, a part of the surface of silicon carbide substrate 201 is removed by reactive ion etching. At this time, sub-trench 203 is formed at the periphery of the portion of silicon carbide substrate 201 protected by resist 202.

FIG. 19 shows an SEM (Scanning Electron Microscope) photograph of the sub-trench formed in the above experiment. As shown in FIG. 19, the sub-trench is formed so as to surround the periphery of the portion of the silicon carbide substrate protected by the resist.
JP 2007-242943 A

  As described above, in the production of the conventional UMOSFET, there is a problem that the high breakdown voltage characteristic of the UMOSFET is impaired because the sub-trench is formed in the groove portion to be the trench gate portion.

  Although it may be possible to prevent the formation of the sub-trench by changing the reactive ion etching conditions at the time of the groove formation to such a condition that the sub-trench is not formed, a condition that can completely prevent the formation of the sub-trench. It is very difficult to find.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily suppress deterioration in characteristics of the semiconductor device due to formation of a sub-trench.

  The present invention relates to a reactive ion etching process in which a groove is formed in a semiconductor by removing a part of the surface of the semiconductor by reactive ion etching, and an inclination of 0 ° to 45 ° with respect to the bottom surface of the groove. And a low-angle ion milling process in which a part of the bottom surface of the groove is removed by irradiating an ion beam from the above direction. With such a configuration, it is possible to easily suppress the deterioration of the characteristics of the semiconductor device due to the formation of the sub-trench.

  Here, in the method for manufacturing a semiconductor device of the present invention, after the low-angle ion milling step, a high angle in which the ion beam is irradiated from a direction inclined at an angle of 45 ° to 90 ° with respect to the bottom surface of the groove. It is preferable to include an ion milling step. In this case, the deterioration of the characteristics of the semiconductor device due to the formation of the sub-trench can be more stably suppressed.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that the aspect ratio of the groove formed by the reactive ion etching process is 1 or less. In this case, it is possible to form a suitable groove in which the angle formed between the side wall and the bottom surface of the groove is 90 ° or less.

  In the method for manufacturing a semiconductor device of the present invention, the ion beam is preferably an argon ion beam. In this case, the low-angle ion milling process and / or the high-angle ion milling process can be performed simply and efficiently.

  In the method for manufacturing a semiconductor device of the present invention, the semiconductor is preferably silicon carbide. In this case, a semiconductor device having a high withstand voltage and a low loss and excellent in heat resistance and environmental resistance can be manufactured.

  In the method for manufacturing a semiconductor device of the present invention, the semiconductor device is preferably a UMOSFET. In this case, a UMOSFET having normally-off characteristics and low on-resistance can be manufactured.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that a trench gate portion of UMOSFET is formed in the groove. In this case, a high-performance UMOSFET can be manufactured.

  In the present invention, reactive ion etching refers to an operation of performing etching using sputtering by ions and a chemical reaction of an etching gas.

  In the present invention, ion milling refers to an operation of physically performing etching by making ions collide.

  In the present invention, the UMOSFET means a MOSFET in which a groove is formed in a part of a semiconductor and a gate portion is provided in the groove.

  Furthermore, in the present invention, the trench gate portion refers to a gate portion provided in at least a part of a groove formed in a semiconductor.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can suppress easily the characteristic fall of the semiconductor device by formation of a subtrench can be provided.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

(Embodiment 1)
First, as shown in the schematic cross-sectional view of FIG. 1, for example, an n-type silicon carbide substrate 1 is prepared. Next, as shown in the schematic cross-sectional view of FIG. 2, n − type silicon carbide crystal layer 2 is formed by epitaxially growing an n − type silicon carbide crystal on the surface of n type silicon carbide substrate 1. Here, the n type impurity concentration of n − type silicon carbide crystal layer 2 is set lower than the n type impurity concentration of n type silicon carbide substrate 1.

  Next, as shown in the schematic cross-sectional view of FIG. 3, p-type silicon carbide crystal layer 3 is formed by epitaxially growing a p-type silicon carbide crystal on the surface of n − -type silicon carbide crystal layer 2.

  Next, as shown in the schematic cross-sectional view of FIG. 4, an n-type silicon carbide crystal layer 4 is formed by epitaxially growing an n-type silicon carbide crystal on the surface of the p-type silicon carbide crystal layer 3. Here, the n-type impurity concentration of n-type silicon carbide crystal layer 4 is set higher than the n-type impurity concentration of n − -type silicon carbide crystal layer 2.

  Thereafter, as shown in the schematic cross-sectional view of FIG. 5, n-type silicon carbide crystal layer 2, p-type silicon carbide crystal layer 3, and n-type silicon carbide crystal layer 4 are formed by reactive ion etching (RIE). Is removed to expose the surface of n − -type silicon carbide crystal layer 2 to form groove 5 (reactive ion etching step).

  Thereby, groove 5 has groove 5 at the root of the side wall of groove 5 (in this example, the side surfaces of n − type silicon carbide crystal layer 2, p type silicon carbide crystal layer 3 and n type silicon carbide crystal layer 4). A sub-trench 9 which is a shallower groove is formed. The steps so far are the same as the steps shown in FIGS. 11 to 15 described in the section of the background art.

  Here, the aspect ratio of the groove 5 after the reactive ion etching step (the width d of the bottom surface 5a of the groove 5 after the reactive ion etching step / the depth h of the groove 5 after the reactive ion etching step) is 1 or less. It is preferable that it is 0.8 or less. When the aspect ratio of the groove 5 after the reactive ion etching step is set to 1 or less, particularly 0.8 or less, a suitable groove in which the angle formed between the side wall of the groove 5 and the bottom surface 5a is 90 ° or less. 5 tends to be formed.

  Next, as shown in the schematic enlarged cross-sectional view of FIG. 6, the ion beam 10 is irradiated from a direction inclined at an angle α of greater than 0 ° and 45 ° or less with respect to the bottom surface 5 a of the groove 5. A part of the bottom surface 5a is removed (low-angle ion milling step). As a result, the bottom surface 5a of the groove 5 is cut, and the sub-trench 9 is filled with the n-type silicon carbide crystal layer 4 constituting the bottom surface 5a of the cut groove 5 as shown in the schematic enlarged sectional view of FIG. become.

  When the ion beam 10 is incident from a direction that does not tilt with respect to the bottom surface 5a of the groove 5 (angle α = 0 °), the bottom surface 5a of the groove 5 cannot be cut, and the bottom surface 5a of the groove 5 cannot be cut. When the ion beam 10 is incident from a direction inclined at an angle larger than 45 °, the bottom surface 5a of the groove 5 is excessively shaved and the side wall of the groove 5 (in this example, the n − -type silicon carbide crystal layer 2, p Will adhere to the side surfaces of the silicon carbide crystal layer 3 and the n-type silicon carbide crystal layer 4.

  Here, the ion beam 10 irradiated in the low-angle ion milling step is preferably an argon ion beam. When the argon ion beam is irradiated in the low-angle ion milling process, the low-angle ion milling process can be performed easily and efficiently.

  In addition, the incident angle α of the ion beam 10 irradiated to the bottom surface 5a of the groove 5 in the low-angle ion milling step is preferably 10 ° or more and 45 ° or less, and more preferably 20 ° or more and 40 ° or less. . When the incident angle α with respect to the bottom surface 5a of the groove 5 of the ion beam 10 irradiated in the low-angle ion milling process is 10 ° to 45 °, particularly 20 ° to 40 °, the sub It tends to be possible to fill the trench 9.

  Further, in the low-angle ion milling step, the n-type silicon carbide substrate 1 is not rotated and the n-type carbonization is performed so that the sub-trench 9 faces the incident direction of the ion beam 10 (the direction of the arrow in FIG. 6). It is preferable to fix the silicon substrate 1. In this case, the sub-trench 9 can be efficiently filled in the low-angle ion milling process.

  Thereafter, as shown in the schematic cross-sectional view of FIG. 8, the bottom surface 5a of the groove 5, the side wall (in this example, the n-type silicon carbide crystal layer 2, the p-type silicon carbide crystal layer 3, and the n-type silicon carbide crystal layer 4). ) And a part of the surface of the n-type silicon carbide crystal layer 4, a gate insulating film 15 is formed, and a gate electrode 6 is formed on the gate insulating film 15. In addition, source electrode 7 is formed on the surface of n-type silicon carbide crystal layer 4, and drain electrode 8 is formed on the back surface of n-type silicon carbide substrate 1. Thereby, a UMOSFET in which the portion of the groove 5 becomes a trench gate portion is manufactured.

  The UMOSFET thus obtained has a normally-off characteristic and becomes a semiconductor device with low on-resistance.

  In the present invention, the UMOSFET is formed after filling the sub-trench formed in the base portion of the side wall of the groove 5 formed by the reactive ion etching process. Therefore, in the present invention, it is possible to reduce the occurrence of the problem that the high breakdown voltage characteristic of the UMOSFET is impaired due to the dielectric breakdown due to the electric field concentration on the subtrench which has occurred in the conventional UMOSFET. Degradation of the characteristics of a semiconductor device such as a UMOSFET due to the formation of can be easily suppressed. Further, when the present invention is used for forming the trench gate portion of the UMOSFET, a higher performance UMOSFET can be obtained.

  In the above, silicon carbide is used as the semiconductor, but it goes without saying that a semiconductor other than silicon carbide may be used. In the present invention, for example, gallium nitride, diamond, zinc oxide, or aluminum nitride can be used as the semiconductor.

  Among these, in the present invention, it is preferable to use a semiconductor having a band gap energy of 2.5 eV or more, and it is particularly preferable to use silicon carbide. In this case, a semiconductor device having a high withstand voltage and a low loss and excellent in heat resistance and environmental resistance tends to be manufactured.

  In the above description, the UMOSFET is manufactured as the semiconductor device. However, it goes without saying that a semiconductor device other than the UMOSFET may be manufactured in the present invention.

(Embodiment 2)
In the present embodiment, after the low-angle ion milling step, a high-angle ion milling step of irradiating an ion beam from a direction inclined at an angle greater than 45 ° and 90 ° or less with respect to the bottom surface of the groove is performed. It is characterized by that.

  First, n-type silicon carbide substrate 1 is prepared as shown in FIG. 1, and n-type silicon carbide crystal is epitaxially grown on the surface of n-type silicon carbide substrate 1 as shown in FIG. Crystal layer 2 is formed.

  Next, a p-type silicon carbide crystal layer 3 is formed by epitaxially growing a p-type silicon carbide crystal on the surface of the n-type silicon carbide crystal layer 2 as shown in FIG. 3, and a p-type silicon carbide crystal layer 3 as shown in FIG. An n-type silicon carbide crystal layer 4 is formed by epitaxially growing an n-type silicon carbide crystal on the surface of silicon carbide crystal layer 3.

  Thereafter, as shown in FIG. 5, n-type silicon carbide crystal layer 2, p-type silicon carbide crystal layer 3 and n-type silicon carbide crystal layer 4 are partially removed by reactive ion etching. Grooves 5 are formed by exposing the surface of the crystal layer 2 (reactive ion etching step). Thereby, in the groove 5, a sub-trench 9 which is a groove shallower than the groove 5 is formed at the base portion of the side wall of the groove 5.

  Next, as shown in FIG. 6, a part of the bottom surface 5 a of the groove 5 is irradiated by irradiating the ion beam 10 from a direction inclined at an angle α of greater than 0 ° and 45 ° or less with respect to the bottom surface 5 a of the groove 5. Remove (low angle ion milling process). Thereby, bottom surface 5a of groove 5 is cut, and sub-trench 9 is filled with n-type silicon carbide crystal layer 4 constituting bottom surface 5a of groove 5 as shown in FIG. The steps so far are the same as those in the first embodiment.

  Thereafter, as shown in the schematic cross-sectional view of FIG. 9, the ion beam 13 is irradiated from the direction inclined at an angle β of 45 ° to 90 ° with respect to the bottom surface 5a of the groove 5 (high angle ion milling step). ).

  As a result, for example, as shown in the schematic cross-sectional view of FIG. 10, the sidewalls of trench 5 (in this example, n − -type silicon carbide crystal layer 2, p-type silicon carbide crystal layer 3 and n-type are formed by a low-angle ion milling process. The deposit 12 attached to the side surface of the silicon carbide crystal layer 4 can be removed. Also, by removing the bottom surface 5a of the groove 5 by etching and increasing the depth of the groove 5 by irradiation with the ion beam 13, the sub-trench 9 is removed together with the deposit 11 filling the sub-trench 9. Can do. Furthermore, the shape of the portion of the groove 5 that becomes the trench gate portion can be finely controlled.

  Here, the ion beam 13 irradiated in the high-angle ion milling process is preferably an argon ion beam. When an argon ion beam is irradiated in the high-angle ion milling process, the deposit 12 on the side wall of the groove 5 and the deposit 11 filling the sub-trench 9 can be easily and efficiently removed, and the trench gate portion. Thus, the shape of the groove 5 can be finely controlled.

  In addition, the incident angle β of the ion beam 13 irradiated to the bottom surface 5a of the groove 5 in the high-angle ion milling process is preferably 45 ° or more and 90 ° or less, and more preferably 60 ° or more and 90 ° or less. . When the incident angle β with respect to the bottom surface 5a of the groove 5 of the ion beam 13 irradiated in the high-angle ion milling process is 45 ° or more and 90 ° or less, particularly when it is 60 ° or more and 90 ° or less, the deposition is efficiently performed. There is a tendency that the object 11 can be removed.

  In this example, the deposit 12 and the deposit 11 shown in FIG. 9 are each composed of a portion of the n-type silicon carbide crystal layer 4 that forms the bottom surface 5 a of the groove 5.

  Thereafter, in the same manner as in the first embodiment, for example, as shown in FIG. 8, bottom surface 5a and side walls of trench 5 (in this example, n − -type silicon carbide crystal layer 2, p-type silicon carbide crystal layer 3 and n Gate insulating film 15 is formed so as to cover a part of the surface of n-type silicon carbide crystal layer 4 and the side surface of n-type silicon carbide crystal layer 4, and gate electrode 6 is formed on gate insulating film 15. Further, source electrode 7 is formed on the surface of n-type silicon carbide crystal layer 4, and drain electrode 8 is formed on the back surface of n-type silicon carbide substrate 1. Thereby, a UMOSFET in which the portion of the groove 5 becomes a trench gate portion is manufactured.

  As described above, by performing the high-angle ion milling step after the low-angle ion milling step, in addition to the effects described in the first embodiment, the deposits 12 and the sub-trench on the side wall of the groove 5 9 can be removed, and the shape of the groove 5 serving as the trench gate portion can be finely controlled. Therefore, the deterioration of the characteristics of the semiconductor device due to the formation of the sub-trench 9 is further stabilized. Can be deterred. Other explanations are the same as those in the first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, it is possible to provide a method of manufacturing a semiconductor device that can easily suppress the deterioration of the characteristics of the semiconductor device due to the formation of the sub-trench. Therefore, the present invention uses the trench portion as a trench gate portion. There is a possibility that it can be suitably used for manufacturing UMOSFETs.

It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is a typical expanded sectional view illustrating other part of the manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is a typical expanded sectional view illustrating other part of the manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of an example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of another example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating another part of manufacturing process of another example of the manufacturing method of the semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating other one part of the manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating other one part of the manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating other one part of the manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating other one part of the manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating other one part of the manufacturing process of an example of the manufacturing method of the conventional semiconductor device. It is typical sectional drawing illustrating a part of process of an example of the experiment which removes a part of surface of a silicon carbide substrate by reactive ion etching. It is typical sectional drawing illustrating other one part of the process of an example of the experiment which removes a part of surface of a silicon carbide substrate by reactive ion etching. It is a SEM photograph of the subtrenches formed in the experiment which removes a part of surface of a silicon carbide substrate by reactive ion etching.

Explanation of symbols

  1,101 n-type silicon carbide substrate, 2,102 n-type silicon carbide crystal layer, 3,103 p-type silicon carbide crystal layer, 4,104 n-type silicon carbide crystal layer, 5,110 groove, 5a bottom surface, 6, 106 gate electrode, 7, 107 source electrode, 8, 108 drain electrode, 15, 105 gate insulating film, 9, 109 sub-trench, 10, 13 ion beam, 11 deposit, 12 deposit

Claims (7)

A reactive ion etching step of forming a groove in the semiconductor by removing a part of the surface of the semiconductor by reactive ion etching;
A low-angle ion milling step of removing a part of the bottom surface of the groove by irradiating an ion beam from a direction inclined at an angle of greater than 0 ° and not more than 45 ° with respect to the bottom surface of the groove. Manufacturing method.   The low-angle ion milling step includes a high-angle ion milling step of irradiating an ion beam from a direction inclined at an angle greater than 45 ° and 90 ° or less with respect to the bottom surface of the groove. Item 14. A method for manufacturing a semiconductor device according to Item 1.   The method of manufacturing a semiconductor device according to claim 1, wherein an aspect ratio of the groove formed by the reactive ion etching process is 1 or less.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the ion beam is an argon ion beam.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor is silicon carbide.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a UMOSFET.   The method for manufacturing a semiconductor device according to claim 1, wherein a trench gate portion of the UMOSFET is formed in the groove.