JP2009130760A - Frequency divider and synthesizer - Google Patents

Abstract

The present invention relates to a frequency dividing circuit and an object thereof is to improve the degree of freedom in setting a fractional frequency division.
A clock input terminal, first and second flip-flop circuits to which a clock is input from the clock input terminal, a pair of program input terminals, and a first and second flip-flop circuit are connected. A combinational circuit to which signals from a pair of program input terminals are input and a clock output terminal for outputting the output of the second flip-flop circuit. The second flip-flop circuit is input, and the inverted output of the second flip-flop circuit is input to the first flip-flop circuit.
[Selection] Figure 5

Description

  The present invention relates to a frequency dividing circuit and a synthesizer, and more particularly to a frequency dividing circuit capable of variably setting a frequency dividing number and a synthesizer having such a frequency dividing circuit.

  For example, a synthesizer used for wireless communication is required to output clocks having various frequencies. In recent years, since the communicable band is subdivided, it is required that the frequency step can be set finely and at high speed. Such a synthesizer is used in, for example, an LSI for a digital television tuner.

  A typical synthesizer is a fractional N synthesizer (ΔΣPLL). In the fractional N synthesizer, a code output from a third-order mash (ΔMASH) type ΔΣ modulator is supplied to a frequency dividing circuit to variably set the frequency dividing ratio of the frequency dividing circuit. Since the output code of the third order mash ΔΣ modulator takes a value of ± 3 from the center value, the frequency dividing ratio of the frequency dividing circuit is 1 / (N−3), 1 / (N−2),. . . , 1 / (N + 2), 1 / (N + 3).

  FIG. 1 is a circuit diagram showing an example of a conventional frequency dividing circuit. The frequency dividing circuit 1 includes D flip-flops (D-FF) 11 and 12, NAND circuit 13, AND circuit 14, NOR circuit 15, inverter circuit 16, and program input terminal connected as shown in FIG. The PRG has a clock input terminal CKI, a mode control input terminal MODI, a clock output terminal CKO, and a mode control output terminal MODEO. The frequency dividing circuit 1 is also called a 2/3 frequency divider or 2/3 cell. When the logical value of the control signal input to the mode control input terminal MODI is “1”, the frequency is input to the program input terminal PRG. When the logic value of the signal to be output is “0”, a clock obtained by dividing the clock input to the clock input terminal CKI by 2 is output from the clock output terminal CKO. When the logic value is “1”, the clock input terminal CKI is input to the clock input terminal CKI. A clock obtained by dividing the input clock by 3 is output from the clock output terminal CKO. If the logical value of the control signal input to the mode control input terminal MODI is “0”, the frequency dividing number of the frequency dividing circuit 1 is set to 2 regardless of the logical value input to the program input terminal PRG. The

  FIG. 2 is a circuit diagram showing another example of a conventional frequency dividing circuit. The frequency dividing circuit 1A has a configuration in which frequency dividing circuits 1-1 to 1-3 having the same configuration as the frequency dividing circuit 1 shown in FIG.

  FIG. 3 is a timing chart for explaining the operation of the frequency dividing circuit 1A shown in FIG. In FIG. 3, CKA is a clock input to the clock input terminal CKI of the frequency dividing circuit 1-1, MA is a control signal output from the mode control output terminal MODEO of the frequency dividing circuit 1-1, and CKB is the frequency dividing circuit 1. -2 is input to the clock input terminal CKI, MB is a control signal output from the mode control output terminal MODEO of the frequency divider 1-2, and CKC is input to the clock input terminal CKI of the frequency divider 1-3. , MC is a control signal output from the mode control output terminal MODEO of the frequency divider 1-3, and CKD is a clock output from the clock output terminal CKO of the frequency divider 1-3. In FIG. 3, for convenience of explanation, the logical values of the signals PA, PB, PC input to the program input terminals PRG of the frequency dividers 1-1, 1-2, 1-3 are “1”, “0”, “0” indicates the signal timing when the frequency dividing circuit 1A performs the frequency dividing operation by 9, and the asterisk indicates the number of cycles in the frequency dividing operation by 9.

  FIG. 4 is a diagram showing the frequency dividing number of the frequency dividing circuit 1A shown in FIG. As shown in FIG. 4, the frequency dividing number N (1) of the frequency dividing circuit 1A is determined by the logical values of signals PA, PB, PC input to the program input terminals PRG of the frequency dividing circuits 1-1, 1-2, 1-3. Alternatively, when the frequency division ratio 1 / N) is determined and the frequency division number is 9, an asterisk is added to the right side of the frequency division number.

  By the way, when the fractional frequency division is performed by the third-order mash ΔΣ modulator using the frequency dividing circuit 1A, the center value of the frequency dividing number is 11 or as shown by a circle on the right side of the frequency dividing number in FIG. Only in the case of 12, fractional frequency division can be set. That is, when the center value of the frequency division number is 8 to 10 and 13 to 15, fractional frequency division cannot be set.

The 2/3 cell is proposed in Patent Document 1, for example. Various prescalers have been proposed in Patent Documents 2, 3, 4, and 5, for example.
JP 2005-508108 A JP-A-7-221633 JP 2001-44824 A JP 2006-101168 A Japanese Patent No. 3821441

  For example, when fractional frequency division is performed by a third-order mash ΔΣ modulator using a frequency divider circuit, the conventional frequency divider circuit has a problem that the degree of freedom in setting the fractional frequency division is low.

  Accordingly, an object of the present invention is to provide a frequency dividing circuit and a synthesizer in which the degree of freedom for setting the fractional frequency division is improved.

  The above problem is that a clock input terminal, first and second flip-flop circuits to which a clock from the clock input terminal is input, a pair of program input terminals, and the first and second flip-flop circuits A combinational circuit connected between the pair of program input terminals and a clock output terminal for outputting an output of the second flip-flop circuit, and an output of the first flip-flop circuit Is input to the second flip-flop circuit through the combinational circuit, and an inverted output of the second flip-flop circuit is input to the first flip-flop circuit. it can.

  The above-described problems include the frequency dividing circuit described above, a phase frequency detection circuit, a voltage controlled oscillator that outputs a clock in response to an output of the phase frequency detection circuit, and a ΔΣ to which a frequency division setting input signal is input. A modulator and a decoder for decoding the output of the ΔΣ modulator, and a clock output from a clock output terminal of the M-th frequency divider is input to the phase frequency detection circuit and the ΔΣ modulator, In the voltage controlled oscillator, the output clock is input to the clock input terminal of the first stage frequency divider, and the output of the decoder is input to the corresponding program input terminal of the first to Mth frequency dividers. Can be achieved by a synthesizer characterized by:

  According to the present invention, it is possible to realize a frequency dividing circuit and a synthesizer with an improved degree of freedom for setting the fractional frequency division.

  The frequency dividing circuit of the present invention includes a combinational circuit connected to at least a pair of program input terminals, a pair of D flip-flops connected to a clock input terminal and connected via a combinational circuit, and a D on the rear stage side of the combinational circuit. And a clock output terminal connected to the flip circuit. The frequency dividing number of the frequency dividing circuit is variably set to 2 to 4 in accordance with signals input to the pair of program input terminals. That is, a 2/3/4 cell can be realized with a relatively simple circuit configuration.

  The frequency dividing circuit may further include a mode control input terminal connected to the combinational circuit. In this case, based on a control signal input to the mode control input terminal, a mode in which the frequency dividing number of the frequency dividing circuit can be variably set to 2 to 4 according to the signal input to the program input terminal, and the program input terminal It is possible to select a mode in which the frequency division number is fixed to 2 regardless of the signal input to.

  The frequency dividing circuit may further include a mode control output terminal connected to the combinational circuit. In this case, when the frequency dividing number of the frequency dividing circuit is set to N, a signal having a predetermined logic value is output from the mode control output terminal every N cycles of the clock input to the clock input terminal.

  By connecting the frequency dividing circuits as described above in cascade, the degree of freedom in setting the fractional fraction is further improved. Therefore, the frequency dividing circuits cascaded in this way are suitable for use in a synthesizer.

  Each embodiment of the frequency divider of the present invention will be described below with reference to FIG.

  FIG. 5 is a circuit diagram showing a first embodiment of the present invention. The frequency dividing circuit 21 is connected via a combinational circuit 33-1 connected to the clock input terminal CKIN and a combinational circuit 33-1 connected to at least a pair of program input terminals PRGA and PRGB connected as shown in FIG. And a pair of D flip-flops 31 and 32 and a clock output terminal CKOUT connected to the D flip circuit 32 on the subsequent stage of the combinational circuit 33-1. The frequency dividing number of the frequency dividing circuit 21 is variably set to 2 to 4 in accordance with signals input to the pair of program input terminals PRGA and PRGB. That is, a 2/3/4 cell can be realized with a relatively simple circuit configuration.

  FIG. 6 is a circuit diagram showing an example of the combinational circuit of the first embodiment in more detail. The combinational circuit 33-1 includes a logic circuit including a NAND circuit 311, an OR circuit 312, an AND circuit 313, and an inverter circuit 314 which are connected as shown in FIG. The clock input to the clock input terminal CKIN is input to the clock terminals of the flip-flop circuits 31 and 32. The clock output from the clock output terminal CKOUT is output from the Q output terminal of the flip-flop circuit 32. The QB output terminal of the flip-flop circuit 32 feeds back a clock inverted from the clock output from the Q output terminal to the D input terminal of the flip-flop 31 via the inverter circuit 314 in the case of FIG.

  The frequency dividing number of the frequency dividing circuit 21 is set to 2 when the logical value of the signal input to the program input terminal PRGA is “0” and the logical value of the signal input to the program input terminal PRGB is “0”. When the logical value of the signal input to the program input terminal PRGA is “1” and the logical value of the signal input to the program input terminal PRGB is “0”, it is set to 3 and input to the program input terminal PRGA. It is set to 4 when the logical value of the signal is “1” and the logical value of the signal input to the program input terminal PRGB is “1”. A combination of signals in which the logical value of the signal input to the program input terminal PRGA is “0” and the logical value of the signal input to the program input terminal PRGB is “1” is prohibited.

  FIG. 7 is a circuit diagram showing a second embodiment of the present invention. In FIG. 7, the same parts as those in FIG. The frequency dividing circuit 41 further has a mode control input terminal MODIN connected to the combinational circuit 33-2. In this case, based on the control signal input to the mode control input terminal MODIN, the frequency dividing number of the frequency dividing circuit 41 can be set to 2 to 4 in accordance with the signals input to the program input terminals PRGA and PRGB. And a mode in which the frequency division number is fixed to 2 regardless of the signals input to the program input terminals PRGA and PRGB.

  FIG. 8 is a circuit diagram showing an example of the combinational circuit of the second embodiment in more detail. The combinational circuit 33-2 includes a logic circuit including a NAND circuit 311, an OR circuit 312, an AND circuit 313, an inverter circuit 315, and a NOR circuit 316 connected as shown in FIG. In this example, when the logical value of the control signal input to the mode control input terminal MODIN is “1”, the mode designation by the signals input to the program input terminals PRGA and PRGB is enabled, and the logical value is “0”. In the case of "", the mode designation by the signals input to the program input terminals PRGA and PRGB is disabled and the frequency division number is fixed at 2.

  FIG. 9 is a circuit diagram showing another example of the combinational circuit of the second embodiment in more detail. The combinational circuit 33-2 includes a logic circuit including a NAND circuit 311, an OR circuit 312, an AND circuit 313, an inverter circuit 317, and a NOR circuit 318 connected as shown in FIG.

  FIG. 10 is a circuit diagram showing still another example of the combinational circuit of the second embodiment in more detail. The combinational circuit 33-2 includes a logic circuit including a NAND circuit 311, an AND circuit 319, an OR circuit 312, an AND circuit 313, an inverter circuit 317, and a NOR circuit 318 connected as shown in FIG.

  FIG. 11 is a circuit diagram showing a third embodiment of the present invention. In FIG. 11, the same parts as those in FIG. The frequency dividing circuit 51 further has a mode control output terminal MODOUT connected to the combinational circuit 33-3. In this case, when the frequency dividing number of the frequency dividing circuit 51 is set to N, the mode control output terminal MODOUT outputs a control signal having a predetermined logic value every N cycles of the clock input to the clock input terminal CKIN. Is done. In this example, a control signal having a logical value “1” is output every N cycles of the clock input to the clock input terminal CKIN, and a signal having a logical value “0” is output at other times.

  FIG. 12 is a circuit diagram showing an example of the combinational circuit of the third embodiment in more detail. The combinational circuit 33-3 is a logic circuit including an AND circuit 301, a NAND circuit 311, an AND circuit 319, an OR circuit 312, an AND circuit 313, an inverter circuit 317, a NOR circuit 318, and a selector circuit 320 connected as shown in FIG. It consists of By providing the selector circuit 320, the signal output from the mode control output terminal MODOUT is switched between when the frequency division number is 2 or 3 and when the frequency division number is 4. In this example, in response to a signal input to the program input terminal PRGB and input to the selection input terminal S of the selector circuit 320, a signal input to one of the input terminals D0 and D1 of the selector circuit 320 is selected. Output terminal X and supplied to the mode control output terminal MODOUT.

  FIG. 13 is a circuit diagram showing a fourth embodiment of the present invention. In FIG. 13, the same parts as those in FIGS. 11 and 12 are denoted by the same reference numerals, and the description thereof is omitted. The frequency dividing circuit 51A has a configuration in which frequency dividing circuits 51-1 to 51-3 having the same configuration as the frequency dividing circuit 51 shown in FIG.

  14 and 15 are timing charts for explaining the operation of the frequency dividing circuit shown in FIG. FIG. 14 shows a case where the logical value of the signal input to the program input terminal PRGA is “0” and the logical value of the signal input to the program input terminal PRGB is “0”, and FIG. The case where the logical value of the signal input to is “1” and the logical value of the signal input to the program input terminal PRGB is “1” is shown. 14 and 15, CKA is a clock input to the clock input terminal CKIN of the frequency dividing circuit 51-1, and MA is an output of the frequency dividing circuit 51A output from the mode control output terminal MODOUT of the frequency dividing circuit 51-1. The control signal CKB is a clock input from the clock output terminal CKOUT of the frequency divider 51-1 to the clock input terminal CKIN of the frequency divider 51-2, and MB is output from the mode control output terminal MODOUT of the frequency divider 51-2. The control signal CKC input to the mode control input terminal MODIN of the frequency divider 51-1 is output from the clock output terminal CKOUT of the frequency divider 51-2 and applied to the clock input terminal CKIN of the frequency divider 51-3. The input clock, MC, is output from the mode control output terminal MODOUT of the frequency dividing circuit 51-3, and the frequency dividing circuit 51-2. Control signal input to the mode control input terminal MODIN, CKD indicates the output divided clock of the frequency divider circuit 51A is outputted from the clock output terminal CKOUT divider 51-3. In FIG. 14, the asterisk indicates the number of cycles during the divide-by-8 operation. In FIG. 15, the asterisk indicates the number of cycles during the divide-by-22 operation.

  FIG. 16 is a diagram showing the frequency division number of the frequency dividing circuit 51A shown in FIG. In FIG. 16, PRGA1 and PRGB1 are logical values of signals input to the program input terminals PRGA and PRGB of the frequency divider 51-1, and PRGA2 and PRGB2 are input to the program input terminals PRGA and PRGB of the frequency divider 51-2. The logic values PRGA3 and PRGB3 indicate the logic values of signals input to the program input terminals PRGA and PRGB of the frequency divider 51-3. As shown in FIG. 16, the frequency division number can be variably set to 8-22.

When the divider circuit 51 is cascade-connected, for example, in four stages, the frequency division number can be variably set to 16 to 46, and when the divider circuit 51 is cascade-connected, for example, in M stages (M is an integer of 3 or more). In this case, the frequency division number can be variably set to 2 ^M to (3 × 2 ^M −2). It is desirable that M = 3 or M = 4 in that the circuit configuration is relatively simple but the degree of freedom in setting the fractional frequency division is high.

For example, when fractional frequency division is performed using a frequency division circuit 51A by a third-order mash ΔΣ modulator, the center value of the frequency division number is 11 to 11, as indicated by a circle on the right side of the frequency division number in FIG. In the case of 19, fractional frequency division can be set. Thus, the degree of freedom in setting the fractional fraction is improved by cascading the frequency dividing circuits 51-1 to 51-3. Therefore, when the frequency dividing circuit 51 is cascade-connected in M stages, the center value of the frequency dividing number of the frequency dividing circuit 51A is (2 ^M +3) to (3 × 2 ^M −2−3) = (3 × 2 ^M -5).

  FIG. 17 is a circuit diagram showing a fractional N synthesizer (ΔΣPLL) having the frequency dividing circuit 51A shown in FIG. A fractional-N synthesizer (ΔΣPLL) 61 includes a third-order mash ΔΣ modulator 71 connected as shown in FIG. 17, a decoder 72, a frequency divider circuit 51A in which frequency divider circuits 51-1 to 51-3 are cascade-connected, and a charge pump. A circuit 700 and a phase frequency detector (PFD) 74 are included. The charge pump circuit 700 includes a voltage controlled oscillator (VCO), capacitors C1 and C2, resistors R, current sources I1 and I2, and switches SW1 and SW2 connected as shown in FIG.

  The clock output from the clock output terminal CKOUT of the frequency divider 51-3 is input to the PFD 74 and the ΔΣ modulator 71. A reference clock input signal is input to the PFD 73. The output of the PFD 73 is input to the VCO 73 via the charge pump circuit 700. The clock output from the VCO 73 is input to the clock input terminal CKIN of the frequency divider 51-1. The ΔΣ modulator 71 modulates the frequency division setting input signal and outputs, for example, a 4-bit signal to the decoder 72. The decoder 72 decodes the signal from the ΔΣ modulator 71 and outputs an 8-bit signal, which is input to the corresponding program input terminals PRGA and PRGB of the frequency dividing circuits 51-1 to 51-3.

  A synthesizer used for wireless communication like the fractional N synthesizer 61 is required to output clocks having various frequencies. In recent years, since the communicable band is subdivided, it is required that the frequency step can be set finely and at high speed. Such a synthesizer is used in, for example, an LSI for a digital television tuner. When the frequency dividing circuit 51A is used in such a synthesizer, as shown in FIG. 16 with a circle on the right side of the frequency dividing number, when the center value of the frequency dividing number is 11 to 19, the fractional frequency division is set. And the degree of freedom for setting fractional fractions is improved.

  In each of the above embodiments, a combinational circuit is configured with positive logic. However, it goes without saying that the combinational circuit may be configured with negative logic.

  FIG. 18 is a circuit diagram showing a first modification of the third embodiment. In FIG. 18, the same parts as those in FIG. The combinational circuit of the frequency dividing circuit 511-1 is composed of a negative logic circuit. The combinational circuit includes an OR circuit 411, an inverter circuit 412, an AND circuit 413, an OR circuit 414, an AND circuit 415, OR circuits 416 and 417, and an inverter circuit 418 connected as shown in FIG.

  FIG. 19 is a circuit diagram showing a second modification of the third embodiment. In FIG. 19, the same parts as those in FIG. The combinational circuit of the frequency dividing circuit 511-2 is composed of a negative logic circuit. The combinational circuit includes a NOR circuit 511, AND circuits 512 and 513, an OR circuit 514, an AND circuit 515, an inverter circuit 516, and a spare AND circuit 517 connected as shown in FIG.

  FIG. 20 is a circuit diagram showing a modification of the fourth embodiment. 20, parts that are the same as those in FIGS. 13 and 17 to 19 are given the same reference numerals, and descriptions thereof are omitted. The frequency dividing circuit 511A has a configuration in which the frequency dividing circuits 511-1 to 511-3 having the same configuration as the frequency dividing circuit 511-1 shown in FIG. 18 or the frequency dividing circuit 511-2 shown in FIG. . The program input terminals PRGA and PRGB of the frequency dividing circuit 511-1 are connected to the outputs of the OR circuit 611 and the AND circuit 612. Program input terminals PRGA and PRGB of the frequency dividing circuit 511-2 are connected to outputs of the OR circuit 613 and the AND circuit 614. The program input terminals PRGA and PRGB of the frequency dividing circuit 511-3 are connected to the outputs of the OR circuit 615 and the AND circuit 616. The signal input to the program terminal PRG0 is supplied to one input of the OR circuit 611 and the AND circuit 612. The signal input to the program terminal PRG1 is supplied to one input of the OR circuit 613 and the AND circuit 614. The signal input to the program terminal PRG2 is supplied to one input of the OR circuit 615 and the AND circuit 616. The signal input to the program terminal PRG3 is supplied to the other inputs of the OR circuit 611, 613, 615 and the AND circuit 612, 614, 616. In this case, the 4-bit signal input to the program terminals PRG0 to PRG3 is decoded into a 6-bit program input signal by the decoder 72 including the OR circuits 611, 613, 615 and the AND circuits 612, 614, 616 and cascade-connected. The frequency dividing number is inputted to the frequency dividing circuit 511A and the frequency dividing number is variably set.

  FIG. 21 is a timing chart for explaining the operation of the frequency dividing circuit shown in FIG. FIG. 21 shows a case where a signal PRG [4: 0] having a predetermined logic value designating frequency division by 8 is input to the program terminals PRG0 to PRG3, and CKIN1 is input to the clock input terminal CKIN of the frequency dividing circuit 511-1. An input clock, CKOUT1 is a clock output from the clock output terminal CKOUT of the frequency divider 511-1, MODOUT2 is a control signal output from the mode output terminal MODOUT of the frequency divider 511-2, and CKOUT2 is a frequency divider 511. -2 is output from the clock output terminal CKOUT, MODOUT3 is output from the mode output terminal MODOUT of the frequency divider 511-3, and CKOUT3 is output from the clock output terminal CKOUT of the frequency divider 511-3. An output frequency division clock of the frequency dividing circuit 511A is shown.

In addition, this invention also includes the invention attached to the following.
(Appendix 1) Clock input terminal,
First and second flip-flop circuits to which a clock from the clock input terminal is input;
A pair of program input terminals;
A combinational circuit connected between the first and second flip-flop circuits and receiving signals from the pair of program input terminals;
A clock output terminal for outputting the output of the second flip-flop circuit,
The output of the first flip-flop circuit is input to the second flip-flop circuit via the combinational circuit,
A frequency dividing circuit, wherein an inverted output of the second flip-flop circuit is input to the first flip-flop circuit.
(Supplementary note 2) The frequency dividing circuit according to supplementary note 1, wherein a frequency division number is variably set to 2 to 4 in accordance with the signals inputted to the pair of program input terminals.
(Supplementary Note 3) The combinational circuit sets the frequency division number to 2 when the logical value of the signal input to the pair of program input terminals is the first combination, and A logic circuit for setting the frequency division number to 3 and setting the frequency division number to 4 in the case of the third combination;
The frequency divider circuit according to Supplementary Note 1 or 2, wherein the fourth combination is prohibited.
(Supplementary Note 4) A mode control input terminal for inputting a control signal to the combinational circuit is further provided.
The combinational circuit has a mode in which the frequency division number can be set according to the signals input to the pair of program input terminals based on the control signal input to the mode control input terminals, and the pair of The frequency dividing circuit according to claim 1 or 2, further comprising a logic circuit that selects a mode in which the frequency dividing number is fixed to 2 regardless of the signal input to the program input terminal.
(Additional remark 5) It further has a mode output terminal which outputs the output signal of this combinational circuit,
The combination circuit includes a logic circuit that outputs a signal having a predetermined logic value from the mode control output terminal every N cycles of the clock when the frequency division number is set to N. The frequency divider described.
(Appendix 6) The combinational circuit is
An AND circuit having as inputs the output of the first flip-flop circuit and the output of the second flip-flop circuit;
6. The frequency dividing circuit according to claim 5, further comprising a selection circuit that selects one of the output of the first flip-flop and the output of the AND circuit.
(Appendix 7) The combinational circuit is
An OR circuit having as inputs the output of the first flip-flop circuit and the inverted output of the second flip-flop circuit;
6. The frequency dividing circuit according to claim 5, further comprising a selection circuit that selects one of the output of the first flip-flop and the output of the OR circuit.
(Supplementary note 8) The frequency divider circuit according to supplementary note 5, wherein the frequency divider circuit is cascade-connected in a plurality of stages.
(Supplementary Note 9) The clock is input to the clock input terminal of the first-stage frequency divider,
The first divided clock output from the clock output terminal of the first-stage divider circuit is input to the second-stage divider circuit, and the mode control input terminal of the first-stage divider circuit is Connected to the mode output terminal of the second stage frequency divider,
When M is an integer greater than or equal to 3, the clock output terminal of the M−1 stage divider circuit is connected to the clock input terminal of the M stage divider circuit, and the M−1 stage divider The mode control input terminal of the frequency divider is connected to the mode output terminal of the Mth frequency divider;
9. The frequency dividing circuit according to appendix 8, wherein an Mth frequency divided clock is output from the clock output terminal of the Mth frequency dividing circuit.
(Supplementary Note 10) The frequency division number of the cascade-connected frequency divider circuits is determined by a combination of logical values of the signals input to the pair of program input terminals of each of the first to Mth frequency divider circuits. The frequency-dividing circuit according to appendix 9, wherein the frequency-dividing circuit is variably set to 2 ^M to (3 × 2 ^M −2).
(Supplementary Note 11) The frequency divider circuit according to Supplementary Note 9 or 10, and
A phase frequency detection circuit;
A voltage controlled oscillator that outputs a clock in response to the output of the phase frequency detection circuit;
A ΔΣ modulator to which a frequency division setting input signal is input;
A decoder for decoding the output of the ΔΣ modulator,
The M-th divided clock output from the clock output terminal of the M-th stage dividing circuit is input to the phase frequency detection circuit and the ΔΣ modulator,
The voltage controlled oscillator outputs the clock, and the clock is input to the clock input terminal of the first-stage frequency divider circuit,
An output of the decoder is input to the corresponding program input terminal of the first to Mth frequency divider circuits.
(Supplementary Note 12) The ΔΣ modulator is a third-order mash ΔΣ modulator,
The center value of the frequency dividing number of the cascade-connected frequency dividing circuits is set to (2 ^M +3) to (3 × 2 ^M −5), and the fractional frequency division is set. Synthesizer.
(Supplementary note 13) The synthesizer according to Supplementary note 11 or 12, wherein M = 3 or M = 4.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a circuit diagram which shows an example of the conventional frequency divider circuit. It is a circuit diagram which shows the other example of the conventional frequency divider. 3 is a timing chart for explaining the operation of the frequency dividing circuit shown in FIG. 2. FIG. 3 is a diagram showing the frequency division number of the frequency dividing circuit shown in FIG. 2. 1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows an example of the combinational circuit of 1st Example in detail. It is a circuit diagram which shows 2nd Example of this invention. It is a circuit diagram which shows an example of the combinational circuit of 2nd Example in detail. It is a circuit diagram which shows the other example of the combinational circuit of 2nd Example in detail. It is a circuit diagram which shows the other example of the combinational circuit of 2nd Example in detail. It is a circuit diagram which shows 3rd Example of this invention. It is a circuit diagram which shows an example of the combinational circuit of 3rd Example in detail. It is a circuit diagram which shows 4th Example of this invention. 14 is a timing chart for explaining the operation of the frequency dividing circuit shown in FIG. 13. 14 is a timing chart for explaining the operation of the frequency dividing circuit shown in FIG. 13. It is a figure which shows the frequency division number of the frequency divider circuit shown in FIG. FIG. 14 is a circuit diagram showing a fractional N synthesizer (ΔΣPLL) having the frequency dividing circuit shown in FIG. 13. It is a circuit diagram which shows the 1st modification of 3rd Example. It is a circuit diagram which shows the 2nd modification of 3rd Example. It is a circuit diagram which shows the modification of 4th Example. FIG. 21 is a timing chart for explaining the operation of the frequency divider shown in FIG. 20. FIG.

Explanation of symbols

21, 41, 51, 51-1 to 51-3, 51A Frequency dividing circuit 31, 32 Flip-flop circuit 33-1, 33-2, 33-3 Combination circuit 71 ΔΣ modulator 72 Decoder 73 VCO
74 PFD
CKIN Clock input terminal CKOUT Clock output terminal PRGA, PRGB Program input terminal MODIN Mode control input terminal MODOUT Mode control output terminal

Claims (10)

A clock input terminal;
First and second flip-flop circuits to which a clock from the clock input terminal is input;
A pair of program input terminals;
A combinational circuit connected between the first and second flip-flop circuits and receiving signals from the pair of program input terminals;
A clock output terminal for outputting the output of the second flip-flop circuit,
The output of the first flip-flop circuit is input to the second flip-flop circuit via the combinational circuit,
A frequency dividing circuit, wherein an inverted output of the second flip-flop circuit is input to the first flip-flop circuit.   2. The frequency dividing circuit according to claim 1, wherein the frequency dividing number is variably set to 2 to 4 in accordance with the signals input to the pair of program input terminals. The combinational circuit sets the frequency division number to 2 when the logical values of the signals input to the pair of program input terminals are the first combination, and sets the frequency division number when the second combination is the second combination. And a logic circuit that sets the frequency division number to 4 in the case of the third combination,
3. The frequency dividing circuit according to claim 1, wherein the fourth combination is prohibited. A mode control input terminal for inputting a control signal to the combinational circuit;
The combinational circuit has a mode in which the frequency division number can be set according to the signals input to the pair of program input terminals based on the control signal input to the mode control input terminals, and the pair of 3. The frequency dividing circuit according to claim 1, further comprising a logic circuit that selects a mode in which the frequency dividing number is fixed to 2 regardless of the signal input to the program input terminal. A mode output terminal for outputting an output signal of the combinational circuit;
The combinational circuit includes a logic circuit that outputs a signal having a predetermined logic value from the mode control output terminal every N cycles of the clock when the frequency division number is set to N. 4. The frequency dividing circuit according to 4. 6. The frequency dividing circuit according to claim 5, wherein the frequency dividing circuit is cascade-connected in a plurality of stages. The clock is input to the clock input terminal of the first stage frequency divider,
The first divided clock output from the clock output terminal of the first-stage divider circuit is input to the second-stage divider circuit, and the mode control input terminal of the first-stage divider circuit is Connected to the mode output terminal of the second stage frequency divider,
When M is an integer greater than or equal to 3, the clock output terminal of the M−1 stage divider circuit is connected to the clock input terminal of the M stage divider circuit, and the M−1 stage divider The mode control input terminal of the frequency divider is connected to the mode output terminal of the Mth frequency divider;
7. The frequency dividing circuit according to claim 6, wherein the Mth frequency divided clock is output from the clock output terminal of the Mth frequency dividing circuit. Depending on the combination of the logical values of the signals input to the pair of program input terminals of each of the first to ^Mth frequency divider circuits, the frequency division number of the cascaded frequency divider circuits is 2 ^M to ( 8. The frequency dividing circuit according to claim 7, wherein the frequency dividing circuit is variably set to 3 × 2 ^M −2). A frequency dividing circuit according to claim 7 or 8,
A phase frequency detection circuit;
A voltage controlled oscillator that outputs a clock in response to the output of the phase frequency detection circuit;
A ΔΣ modulator to which a frequency division setting input signal is input;
A decoder for decoding the output of the ΔΣ modulator,
The M-th divided clock output from the clock output terminal of the M-th stage dividing circuit is input to the phase frequency detection circuit and the ΔΣ modulator,
The voltage controlled oscillator outputs the clock, and the clock is input to the clock input terminal of the first-stage frequency divider circuit,
An output of the decoder is input to the corresponding program input terminal of the first to Mth frequency divider circuits. The ΔΣ modulator comprises a third order mash ΔΣ modulator,
10. The center value of the frequency dividing number of the cascaded frequency dividing circuits is set to (2 ^M +3) to (3 × 2 ^M −5), and fractional frequency division is set. Synthesizer.

Images