JP2009246205A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device having excellent withstand voltage characteristics and current amplification characteristics and a method for manufacturing the semiconductor device are provided.
In RESURF-MOSFET 100 having a RESURF region 110 functioning as A field limiting region, a RESURF region 110, and ^{the n +} -type contact region 104s which functions as a contact for the source, ^{n +} -type contact which functions as a drain contact At least one of the regions 104d includes an atom having n-type conductivity and a nitrogen atom as impurities.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device using a normally-off group III nitride semiconductor and a method for manufacturing the semiconductor device.

  Compound-based wide bandgap semiconductors typified by Group III nitride semiconductors have superior characteristics compared to silicon, which is currently the mainstream semiconductor material, such as high breakdown voltage, saturated carrier mobility, and thermal conductivity. It is attracting attention as a material for high-power or high-frequency semiconductor devices in a high-temperature environment. In addition, for example, an AlGaN / GaN heterojunction field effect transistor (HFET), which is a semiconductor device using a group III nitride semiconductor, is generated by a two-dimensional electron gas at a heterostructure interface generated by a piezo electric field. It is known to have a high carrier density and electron mobility. Since this HFET has characteristics such as low on-resistance, high-speed switching characteristics, and high-temperature operation, application as a high-power switching element is expected.

  A normal AlGaN / GaN HFET is configured as a so-called normally-on type device in which a current flows even when no voltage is applied to the gate, and the current is interrupted by applying a negative voltage to the gate. However, in the power switching element, in order to ensure safety when the device is broken, current does not flow when no voltage is applied to the gate, and current flows by applying a positive voltage to the gate. Therefore, it is required to configure a transistor as a so-called normally-off type device.

  As a normally-off type transistor, there is a MOS (Metal Oxide Semiconductor) FET. In addition, in order to improve the breakdown voltage characteristics of the MOSFET, a configuration in which an electric field relaxation region is arranged between the drain and the gate is known (for example, see Non-Patent Document 1). This electric field relaxation region is also called RESURF (Reduced SURface Field) and plays a role of relaxing electric field concentration in the vicinity of the gate that occurs when the drain voltage rises when a bias voltage is not applied to the gate (off state). Have. For this reason, the MOSFET in which the RESURF region is formed (hereinafter referred to as RESURF-MOSFET) is difficult to break down, and high breakdown voltage characteristics can be obtained.

M. Kuraguchi et al., “Normally-off GaN-MISFET with well-controlled threshold voltage,” International Workshop on Nitride Semiconductors 2006 (IWS2006), Oct. 22-27, 2006, Kyoto, Japan, WeED1-4

  However, the conventional RESURF-MOSFET has a problem that a large drain current cannot be obtained because the resistance between the source and the drain is extremely high and sufficient current amplification cannot be performed. Further, in order to avoid such a problem, for example, when the sheet carrier concentration between the source and the drain is increased, the electric field concentration generated in the vicinity of the gate cannot be sufficiently relaxed, and the breakdown voltage characteristic is deteriorated. .

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device excellent in breakdown voltage characteristics and current amplification characteristics and a method for manufacturing the semiconductor device.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a channel formation region, a first doped region formed in a region in contact with the channel formation region in the channel length direction, and the upper surface on the upper side. A semiconductor layer made of a group III nitride semiconductor, having a second doped region formed in two regions sandwiching a channel forming region and the first doped region, and having a higher impurity concentration than the first doped region; An atom having an insulating film formed on the channel formation region and a gate electrode formed on the insulating film, wherein the first doped region and / or the second doped region has n-type conductivity. And nitrogen atoms as dopants.

  In the semiconductor device according to the present invention, the channel formation region has p-type conductivity, and the second doped region has n-type conductivity.

  In the above-described semiconductor device according to the present invention, the semiconductor layer is formed on the first semiconductor layer made of a group III nitride semiconductor having p-type conductivity, and on a part of the first semiconductor layer. a second semiconductor layer made of a group III nitride semiconductor having n-type conductivity, and one of the second doped regions is formed in the first semiconductor layer and the other is formed in the second semiconductor layer. The first doped region is formed in the second semiconductor layer.

  In the semiconductor device according to the present invention, the group III nitride semiconductor is any one of GaN, AlGaN, BGaN, BAlN, InGaN, AlN, and InN.

  Further, the semiconductor device according to the present invention is characterized in that the n-type conductive atom is Si, Ge, Se, S, O, or Te.

In the semiconductor device according to the present invention, the sheet carrier concentration in the first doped region is 5 × 10 ¹³ / cm ² or less.

  In the semiconductor device according to the present invention, the ratio of the nitrogen atom to the n-type conductive atom in the first doped region is 0.5 or more and 3 or less.

  In the semiconductor device according to the present invention, the depth of the second doped region from the upper surface of the semiconductor layer is not less than 30 nm and not more than 100 nm.

  In addition, a method of manufacturing a semiconductor device according to the present invention includes a preparation step of preparing a substrate having a semiconductor layer made of a group III nitride semiconductor, and a first region and a second region, which are two separated regions in the semiconductor layer. a first implantation step of implanting an n-type conductivity impurity; and a third region in the semiconductor layer sandwiched between the first region and the second region and in contact with one of the second regions And at least one of the first to third regions, and a second implantation step of implanting an n-type conductivity impurity so as to have an impurity concentration lower than that of the first and second regions. And a third implantation step of implanting nitrogen atoms.

  Further, in the above-described method for manufacturing a semiconductor device according to the present invention, the semiconductor layer includes a p-type conductive first semiconductor layer made of the group III nitride semiconductor, and a part on the first semiconductor layer. And a second semiconductor layer having n-type conductivity formed, wherein the first region is a part of the first semiconductor layer, and the second region is a part of the second semiconductor layer. And the third region is a partial region of the second semiconductor layer.

In the semiconductor device manufacturing method according to the present invention, the sheet carrier concentration in the third region is 5 × 10 ¹³ / cm ² or less.

  Further, the above-described method for manufacturing a semiconductor device according to the present invention is characterized in that the ratio of the nitrogen atom to the n-type conductive atom in the third region is not less than 0.5 and not more than 3.

  In the semiconductor device manufacturing method according to the present invention, the depth of the third region from the upper surface of the semiconductor layer is not less than 30 nm and not more than 100 nm.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a preparation step of preparing a substrate comprising a first semiconductor layer made of a group III nitride semiconductor and having p-type conductivity; A semiconductor layer forming step of forming a second semiconductor layer doped with an n-type conductivity impurity and a nitrogen atom in a portion thereof; a part of the first region of the first semiconductor layer; and the second semiconductor layer And an impurity implantation step of implanting an impurity having n-type conductivity into a part of the second region.

In the method for manufacturing a semiconductor device according to the present invention, the sheet carrier concentration of the second semiconductor layer is 5 × 10 ¹³ / cm ² or less.

  In the method of manufacturing a semiconductor device according to the present invention, the ratio of the nitrogen atom to the n-type conductive atom in the second semiconductor layer is 0.5 or more and 3 or less.

  In the method of manufacturing a semiconductor device according to the present invention, the group III nitride semiconductor is any one of GaN, AlGaN, BGaN, BAlN, InGaN, AlN, and InN.

  Further, the above-described method for manufacturing a semiconductor device according to the present invention is characterized in that the n-type conductive atom is Si, Ge, Se, S, O, or Te.

  According to the present invention described above, in the configuration including the electric field relaxation region (first doped region / third region / second semiconductor layer), the sheet resistance is reduced while keeping the sheet carrier concentration in the region where nitrogen atoms are implanted low. As a result, the resistance value can be lowered while suppressing the sheet carrier concentration between the source and the drain. As a result, it is possible to realize a semiconductor device and a method for manufacturing the semiconductor device that are excellent in breakdown voltage characteristics and current amplification characteristics.

  Embodiments of a semiconductor device and a semiconductor device manufacturing method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
First, Embodiment 1 of the present invention will be described in detail with reference to the drawings. In this embodiment, a RESURF-MOSFET 100 is taken as an example of a normally-off type semiconductor device using a group III nitride semiconductor. FIG. 1 is a cross-sectional view showing a schematic configuration of the RESURF-MOSFET 100. Note that FIG. 1 shows a schematic configuration when the RESURF-MOSFET 100 is cut along a plane perpendicular to the substrate and parallel to the gate length direction.

As shown in FIG. 1, the RESURF-MOSFET 100 includes a buffer layer 102 and a p-type semiconductor layer 103 formed on a substrate 101 such as a silicon substrate. Two spaced apart regions in the upper layer portion of the p-type semiconductor layer 103 include an n ⁺ -type contact region 104s (second doped region) functioning as a source contact and an n ⁺ -type contact region 104d (functioning as a drain contact). Second doped region). In the region in contact with the two ^{n +} -type contact region 104s and a region sandwiched 104d and the drain-side ^{n +} -type contact region 104d in the upper portion of the p-type semiconductor layer 103, the breakdown voltage characteristics of RESURF-MOSFET 100 A RESURF region 110 (first doped region) for the purpose of increasing the resistance is formed. Note that a region between the two n ⁺ -type contact regions 104s and 104d in the p-type semiconductor layer 103 functions as a channel formation region 103a. A gate insulating film 105 formed of an insulating film such as a silicon oxide film (SiO ₂ ) is formed on the p-type semiconductor layer 103 and at least on the channel formation region 103 a, and a gate insulating film 105 is further formed on the gate insulating film 105. An electrode 106 is formed. Further, a source electrode 107s is formed on the n ⁺ -type contact region 104s on the source side, and a drain electrode 107d is formed on the n ⁺ -type contact region 104d on the drain side.

In the above, in addition to the silicon substrate described above, for example, a sapphire (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a zirconium boride (ZrB ₂ ) substrate, or the like can also be applied to the substrate 101.

  The buffer layer 102 is a layer for ensuring the adhesion between the substrate 101 and the p-type semiconductor layer 103. For example, the buffer layer 102 includes a laminated film made of undoped AlGaN (aluminum gallium nitride) and gallium nitride (GaN). AlGaN / GaN film) can be applied. Moreover, the film thickness can be about 500 nm in total, for example.

The p-type semiconductor layer 103 is a layer (also referred to as a base film) made of a group III nitride semiconductor doped with a p-type impurity for threshold adjustment. In the present embodiment, GaN is used for the group III nitride semiconductor, and magnesium (Mg) is used for the p-type impurity. Further, the impurity concentration is set to about 1 × 10 ¹⁵ / cm ³ to about 5 × 10 ¹⁷ / cm ³ , and the film thickness is set to about 2 μm. However, the present invention is not limited to this, and beryllium (Be), zinc (Zn), carbon (C), or the like can be used as the p-type impurity. In this embodiment, GaN is applied as the group III nitride semiconductor. However, the present invention is not limited to this. For example, the composition is Al _0.2 Ga _0.8 N or Al _0.3 Ga _0. AlGaN such as ₇ N, BGaN such as B _0.05 Ga _0.95 N, BAlN such as B _0.03 Al _0.97 N, or indium gallium nitride ( A nitride semiconductor containing at least one of Al, Ga, In, and B as a group III element, such as InGaN), aluminum nitride (AlN), or indium nitride (InN), can be used.

The n ⁺ -type contact regions 104 s and 104 d are regions where n-type impurities are doped at a relatively high concentration, and each function as a source contact or a drain contact as described above. In this embodiment, Si ions are used as n-type impurities. However, the present invention is not limited to this, and germanium (Ge), selenium (Se), sulfur (S), oxygen (O), tellurium (Te), or the like can also be used.

  The RESURF region 110 is an electric field relaxation region doped with both n-type impurities and N ions (p-type impurities), and is formed for the purpose of improving the breakdown voltage characteristics of the RESURF-MOSFET 100 as described above. Yes. In this embodiment, Si ions are applied to the n-type impurity as a dopant in the RESURF region 110. Thereby, the sheet resistance of the RESURF region 110 according to the present embodiment is reduced, and the current amplification characteristic of the RESURF-MOSFET 100 is improved. In addition, the current amplification characteristic and the withstand voltage characteristic of the RESURF-MOSFET 100 realized by this embodiment will be described later.

As the gate insulating film 105 formed on at least the channel formation region 103a on the p-type semiconductor layer 103, an insulating film such as a silicon nitride film (SiN) is applied in addition to the above-described silicon oxide film (SiO ₂ ). You can also. Moreover, the film thickness can be about 60 nm, for example.

  The gate electrode 106 formed on the gate insulating film 105 is formed of a polysilicon film having conductivity by containing an impurity such as phosphorus (P). However, the present invention is not limited to this, and a conductive film such as gold (Au), platinum (Pt), or nickel (Ni) can also be applied.

The source electrode 107s or the drain electrode 107d has a configuration for reducing resistance between the n ⁺ -type contact region 104s or 104d and an upper wiring (not shown). For this, for example, a laminated film (Ti / Al film) made of titanium (Ti) and aluminum (Al) can be applied. However, the present invention is not limited to this, and various modifications can be made as long as it is a conductor film that can make ohmic contact with the n ⁺ -type contact regions 104s and 104d.

  Next, current amplification characteristics and breakdown voltage characteristics of the RESURF-MOSFET 100 according to the present embodiment will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram showing each resistance component in the current path of the RESURF-MOSFET 100. As shown in FIG. 2, the current path of the RESURF-MOSFET 100 includes a resistance component R _scon existing between the source electrode 107 s and the n ⁺ -type contact region 104 s and a resistance component (channel resistance) R of the channel formation region 103 a. _ch , the resistance component R _RES of the RESURF region 110, and the resistance component R _dcon existing between the n ⁺ -type contact region 104d and the drain electrode 107d are connected in series. In the current path of a normal MOSFET that does not have the RESURF region 110, the resistance component of the RESURF region 110 is removed from the resistance component.

Here, the drain current Id in the linear region and in the saturation region in a normal MOSFET is expressed by the following Equation 1 or Equation 2, respectively. Note that Formula 3 shows the capacitance C _ox of the gate insulating film (105) per unit area.

In Equation 1 and Equation 2, W _ch and L _ch are the channel width W _ch and the channel length L _ch , respectively. _μNR is the mobility in a normal MOSFET. In other words, μ _NR is the mobility after being affected by the resistance component R _scon , the channel resistance R _ch, and the resistance component R _dcon . V _{g ′} , V _th ′, and V _ds are a gate voltage, a threshold voltage, and a drain voltage, respectively. ε ₀ and ε _ox are the dielectric constant of vacuum and the relative dielectric constant of the gate insulating film (105), respectively. D _ox is the thickness of the gate insulating film (105).

On the other hand, the drain current I _{d_RES} of the RESURF-MOSFET 100 according to the present embodiment is expressed by the following Expression 4 from the resistance components shown in Expressions 1 and 2 and FIG.

In Expression 4, L _RES is the length of the RESURF region 110 in the gate length direction. R _{RES_SHEET} is a sheet resistance of the RESURF region 110.

Next, FIG. 3 shows the relationship between the sheet resistance R _{RES_SHEET} of the RESURF region 110 and the drain current I _{d_RES} of the RESURF-MOSFET 100 derived from the above equation 4. In order to derive the relationship of FIG. 3, the channel width of the gate electrode 106 was set to 200 mm, and the 600 V · 10 A class RESURF-MOSFET 100 was designed. In FIG. 3, L1 shows a relational curve when the length of the RESURF region 110 in the gate length direction is 5 μm, and L2 shows a relational curve when the length of the RESURF region 110 in the gate length direction is 10 μm. L3 indicates a relationship curve when the length of the RESURF region 110 in the gate length direction is 15 μm, L4 indicates a relationship curve when the length of the RESURF region 110 in the gate length direction is 20 μm, and L5 indicates A relationship curve is shown when the length of the RESURF region 110 in the gate length direction is 25 μm, and L6 shows a relationship curve when the length of the RESURF region 110 in the gate length direction is 30 μm. Further, in FIG. 3, the drain current Id of a normal MOSFET is indicated by a straight line L0.

As apparent from FIG. 3, when the sheet resistance R _{RES_SHEEET} of the RESURF region 110 is about 10 kΩ / cm ² or less, a drain current I _{d_RES} of about 10 A or more, which is desirable for a 600 V / 10 A class MOSFET, is _obtained . I was able to get it.

In general, the sheet resistance in a region into which impurities are implanted can be reduced by increasing the sheet carrier concentration in this region. However, if the sheet carrier concentration in the RESURF region 110 is too high, the pressure resistance characteristics of the RESURF-MOSFET 100 will be degraded. FIG. 4 shows the relationship between the sheet carrier concentration in the RESURF region 110 and the dielectric breakdown voltage of the RESURF-MOSFET 100. In deriving the relationship of FIG. 4, the length of the RESURF region in the gate length direction was set to 20 μm. In FIG. 4, L11 represents a relationship curve when the impurity concentration of the channel formation region 103a is 5 × 10 ¹⁵ / cm ³ and the thickness of the p-type semiconductor layer (p-GaN layer) 103 is 6 μm. Shows a relationship curve when the impurity concentration is 5 × 10 ¹⁵ / cm ³ and the film thickness of the p-type semiconductor layer 103 is 10 μm, and L13 is also the impurity concentration of 1 × 10 ¹⁶ / cm ³ and the p-type semiconductor layer. 103 shows a relational curve when the film thickness of 103 is 6 μm, L14 shows a relational curve when the impurity concentration is 1 × 10 ¹⁶ / cm ³ and the film thickness of the p-type semiconductor layer 103 is 10 μm, and L15 Similarly, a relationship curve is shown when the impurity concentration is 5 × 10 ¹⁶ / cm ³ and the thickness of the p-type semiconductor layer 103 is 6 μm.

As apparent from FIG. 4, the highest dielectric breakdown voltage is obtained when the sheet carrier concentration in the RESURF region 110 is about 1 × 10 ¹³ / cm ^{3, and is} about 5 × 10 ¹³ / cm ³ or less. High breakdown voltage can be obtained in the range. That is, particularly good breakdown voltage characteristics can be obtained in this range.

However, for example, when the RESURF region 110 is formed by implanting only Si ions, the sheet resistance is 1 × 10 ⁴ Ω / cm ² when the sheet carrier concentration in the RESURF region 110 is about 5 × 10 ¹³ / cm ² or less. A high value of about or higher. Therefore, in the present embodiment, N ions are implanted together with Si ions to form the RESURF region 110, thereby reducing the sheet resistance while suppressing the sheet carrier concentration in the RESURF region 110. FIG. 5 shows the relationship between the sheet carrier concentration and the sheet resistance when activation annealing is performed by implanting only Si ions, and both Si ions and N ions are implanted at a ratio of 1: 1. The relationship between the sheet carrier concentration and the sheet resistance when annealing is performed is shown. In FIG. 5, the plot “×” shows the measurement result when only Si ions are implanted, and the plot “●” shows the measurement result when both Si ions and N ions are implanted.

As apparent from FIG. 5, when only Si ions are implanted, the sheet resistance is about 1 × 10 ⁴ Ω / cm ² or more in the range where the sheet carrier concentration is about 5 × 10 ¹³ / cm ² or less. On the other hand, when both Si ions and N ions are implanted, the sheet resistance is reduced by about an order of magnitude to about 1 × 10 ³ Ω / cm ^{2 in} the same range of sheet carrier concentration. Therefore, the RESURF-MOSFET 100 having the RESURF region 110 formed by implanting both Si ions and N ions and performing activation annealing has better withstand voltage characteristics and current amplification characteristics. I understand that.

In this embodiment, the dopant of the RESURF region 110 is both N ions and n-type Si ions. However, the present invention is not limited to this. For example, the n ⁺ -type contact regions 104s and / or 104d The dopant may be both n-type Si ions and p-type N ions. Alternatively, all of these may be doped with both n-type Si ions and p-type N ions. Accordingly, since the RESURF region 110 is provided, the sheet resistance of the n ⁺ -type contact regions 104s / 104d can be reduced in the MOSFET having high breakdown voltage characteristics, and thus high current amplification characteristics can be realized. However, as apparent from FIG. 5, the drain is obtained by implanting both ions into the n ⁺ -type contact regions 104s and / or 104d having a relatively high sheet carrier concentration of about 5 × 10 ¹³ / cm ² or more. _Rather than increasing the current I _{d_RES} , the drain current I _{d_RES} is implanted by injecting both Si ions and N ions into the RESURF region 110 having a relatively low sheet carrier concentration of about 5 × 10 ¹³ / cm ² or less. In the case of increasing the sheet resistance, the sheet resistance can be reduced while keeping the sheet carrier concentration in the injected region low, so that higher breakdown voltage characteristics and current amplification characteristics can be realized.

  FIG. 5 shows a measurement result of an experiment in which the ratio of Si ions to N ions is 1 (= N ions / Si ions). However, the present invention is not limited to this, and the ratio is, for example, 0. Various changes such as about .5 to 3 can be made according to the desired sheet carrier concentration and sheet resistance. By setting this ratio to about 0.5 to 3, a good relationship between the sheet carrier concentration and the sheet resistance can be obtained.

  In the present embodiment, the depth of the RESURF region 110 is set to about 30 nm to about 100 nm. This is because if the impurity implantation depth when forming the RESURF region 110 is greater than about 100 nm, the carrier concentration per unit deposition in the RESURF region 110 decreases, and the sheet resistance of the RESURF region 110 increases. On the other hand, if it is smaller than about 30 nm, the cross-sectional area of the current path is reduced, the conductivity is decreased, and the resistance value of the RESURF region 110 is increased. Further, when the depth of impurity implantation is made smaller than about 30 nm, the acceleration energy must be set low. However, since the acceleration energy cannot be set lower than 25 keV in a normal ion implantation apparatus, the depth of impurity implantation is low. The depth of the impurity implantation is preferably about 30 nm or more because it is difficult to make the thickness smaller than about 30 nm.

  Next, a method for manufacturing the RESURF-MOSFET 100 according to the present embodiment will be described in detail with reference to the drawings. FIGS. 6A to 7C are process diagrams showing a method for manufacturing the RESURF-MOSFET 100 according to the present embodiment. In addition, the cross section of each figure respond | corresponds with the cross section shown in FIG.

  In this manufacturing method, first, for example, by using MOCVD (metal organic chemical vapor deposition), the total film thickness of undoped AlGaN and undoped GaN is, for example, about 500 nm on the substrate 101 to be processed. In this way, the buffer layer 102 (see FIG. 6A) made of a laminated film of undoped AlGaN / GaN is formed by epitaxial growth in this manner.

Subsequently, by using, for example, the MOCVD method, a GaN film doped with Mg is epitaxially grown on the buffer layer 102 so as to have a film thickness of, for example, about 2.0 μm. A p-type semiconductor layer 103 (see FIG. 6A) is formed (preparation step). At this time, the flow rate of the dopant (Mg) is controlled so that the impurity in the p-type semiconductor layer 103 is, for example, about 1 × 10 ¹⁵ / cm ³ to 5 × 10 ¹⁷ / cm ³ . Thereby, the cross-sectional structure shown in FIG. The formation of the buffer layer 102 and the p-type semiconductor layer 103 is not limited to the above-described MOCVD method, and for example, an HVPE method (halide vapor phase epitaxy method) or an MBE method (molecular beam epitaxy method) is applied. You can also.

  Next, a photoresist liquid is spin-coated on the p-type semiconductor layer 103, and this is exposed and developed to form a photoresist having openings formed along the element isolation region (photolithography process). Subsequently, using the photoresist as a mask, the p-type semiconductor layer 103 is etched to form a trench (not shown) having a depth of, for example, about 200 nm from the surface of the p-type semiconductor layer 103 (etching step). ). Thereby, the upper layer of the p-type semiconductor layer 103 is partitioned into one or more element formation regions (element isolation). Note that anisotropic dry etching such as reactive ion etching (RIE) or inductively coupled plasma RIE (ICP-RIE) can be applied to the etching. However, the present invention is not limited to this, and various element isolation techniques can be applied.

Next, after removing the photoresist on the p-type semiconductor layer 103 with, for example, acetone, the film thickness is about 1000 nm on the p-type semiconductor layer 103 by using, for example, PECVD (plasma chemical vapor deposition). A silicon oxide film is formed. Subsequently, by patterning the silicon oxide film using a photolithography process and an etching process, openings are formed on regions (first and second regions) where the n ⁺ -type contact regions 104 s and 104 d are formed in the p-type semiconductor layer 103. A mask oxide film M1 (see FIG. 6B) is formed. For example, wet etching using a hydrofluoric acid aqueous solution can be used for patterning the mask oxide film M1.

  Subsequently, after removing the photoresist on the p-type semiconductor layer 103 used in the photolithography process and the etching process with, for example, acetone, the film thickness is, for example, about 20 nm on the entire upper surface of the substrate by using, for example, PECVD. A protective film M2 (see FIG. 2B) made of a silicon oxide film is formed. Note that the mask oxide film M1 is a film for limiting a region where Si ions are implanted in a later process, and the protective film M2 reduces damage to the surface of the p-type semiconductor layer 103 when Si ions are implanted. It is a film to do.

  Subsequently, as shown in FIG. 6B, by using an existing ion implantation apparatus, Si ions are implanted while using the mask oxide film M1 as a mask, so that an implantation region 104a is implanted into the upper layer portion of the p-type semiconductor layer 103. Is formed (first implantation step).

In this embodiment, Si ions are implanted in a plurality of stages. At this time, by changing the dose amount and acceleration energy at each stage, it is possible to form the implantation region 104a in which Si ions are implanted almost uniformly from the surface of the p-type semiconductor layer 103 to a desired depth. In this embodiment, as an example, the impurity implantation is divided into four stages, and the combination of the dose amount and the acceleration energy in each stage is, for example, 3 × 10 ¹⁴ cm ⁻² and 30 KeV, 4 × 10 ¹⁴ cm ⁻² and 60 KeV, respectively. 8 × 10 ¹⁴ cm ⁻² and 120 KeV, and 1.5 × 10 ¹⁵ cm ⁻² and 160 KeV.

  When Si ions are implanted as described above, the silicon oxide film on the p-type semiconductor layer 103 is then removed by about 20 nm by wet etching using, for example, a hydrofluoric acid aqueous solution. As a result, the protective film M2 is removed and the implantation region 104a is exposed.

  Subsequently, for example, by using the same process as described above, the mask oxide film M3 (see FIG. 6C) having an opening on the region where the RESURF region 110 (third region) is formed and the entire upper surface of the substrate are protected. A film M4 (see FIG. 6C) is formed on the p-type semiconductor layer 103 with, for example, a silicon oxide film (second implantation step).

  Subsequently, as shown in FIG. 6C, the upper layer portion of the p-type semiconductor layer 103 is implanted by using the existing ion implantation apparatus while implanting Si ions and N ions while using the mask oxide film M3 as a mask. An implantation region 110a is formed in the first layer.

In this embodiment, first, N ions are implanted, and then Si ions are implanted. As conditions for implanting N ions, the dose can be set to, for example, about 7 × 10 ¹⁴ / cm ² , and the acceleration energy can be set to, for example, about 75 KeV. Further, as conditions for implanting Si ions, the dose can be about 3 × 10 ¹⁴ / cm ² and the acceleration energy can be about 45 KeV, for example. For N ions, the dose varies depending on the desired activation rate.

  When N ions and Si ions are implanted as described above, next, the mask oxide film M3 and the protective film M4 on the p-type semiconductor layer 103 are completely removed by wet etching using, for example, a hydrofluoric acid aqueous solution. Subsequently, a scattering prevention film M5 made of a silicon oxide film having a film thickness of, for example, about 500 nm is formed on the entire upper surface of the substrate by using, for example, PECVD. The scattering prevention film M5 is a film for preventing atoms constituting the p-type semiconductor layer 103, particularly N atoms, from being scattered in the subsequent annealing step.

Subsequently, the Si ion and N ions implanted in the implantation regions 104a and 110a are diffused and activated by annealing the substrate on which the anti-scattering film M5 is formed using an existing annealing apparatus (annealing step). ). As a result, as shown in FIG. 6D, the n ⁺ -type contact regions 104s and 104d and the RESURF region 110 are formed. In this case, the annealing is performed, for example, for 10 seconds in a nitrogen atmosphere in an electric furnace having a set temperature of 1200 ° C., for example.

  Next, for example, all of the scattering prevention film M5 on the p-type semiconductor layer 103 is removed by wet etching using a hydrofluoric acid aqueous solution. Subsequently, by using, for example, PECVD, a gate insulating film 105 made of a silicon oxide film having a thickness of, for example, about 60 nm is formed on the p-type semiconductor layer 103 as shown in FIG. 7A.

Thereafter, for example, by using a photolithography process and an etching process, openings for exposing the n ⁺ -type contact regions 104s and 104d are formed in the gate insulating film 105, and, for example, titanium (Ti) and aluminum (Al) are formed in the openings. A laminated film (Ti / Al film) is formed. As a result, as shown in FIG. 7B, the source electrode 107s and the drain electrode 107d are formed in ohmic contact with the n ⁺ -type contact regions 104s and 104d, respectively.

Next, by using, for example, an LPCVD (Low-Pressure CVD) method or a sputtering method, a polysilicon film 106A is formed on the entire upper surface of the substrate as shown in FIG. 7C. Subsequently, the substrate on which the polysilicon film 106A is formed is left in a thermal diffusion furnace in which POCl ₃ gas is sealed for about 20 minutes. At this time, the temperature in the thermal diffusion furnace is set to about 900 ° C. As a result, the polysilicon film 106A is doped with phosphorus (P) as an impurity, and this functions as a conductor film. As a method for doping impurities into the polysilicon film 106A, in addition to the above-described method, for example, phosphorus (P) is deposited on the polysilicon film 106A, and this is doped into the polysilicon film by thermal diffusion. Various modifications can be made.

  Subsequently, the polysilicon film 106A is patterned on the gate electrode 106 by using a photolithography process and an etching process. Thereby, the RESURF-MOSFET 100 having the cross-sectional structure as shown in FIG. 1 is manufactured.

  As described above, the RESURF-MOSFET 100 according to the present embodiment reduces the sheet resistance while keeping the sheet carrier concentration in the region where nitrogen atoms are implanted low in the configuration including the RESURF region 110 that functions as an electric field relaxation region. As a result, the resistance value can be lowered while suppressing the sheet carrier concentration between the source and the drain. As a result, it is possible to realize the RESURF-MOSFET 100 having excellent withstand voltage characteristics and current amplification characteristics.

(Embodiment 2)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, items not specifically mentioned are the same as those in the first embodiment.

  In this embodiment, a RESURF-MOSFET 200 is taken as an example of a normally-off type semiconductor device using a group III nitride semiconductor. FIG. 8 is a cross-sectional view showing a schematic configuration of the RESURF-MOSFET 200. 8 also shows a schematic configuration when the RESURF-MOSFET 200 is cut along a plane perpendicular to the substrate and parallel to the gate length direction, as in FIG.

As shown in FIG. 8, the RESURF-MOSFET 200 has the same configuration as the RESURF-MOSFET 100 shown in FIG. 1, and an n ⁻ type semiconductor layer 203 (in the drain side region on the upper surface of the p type semiconductor layer 103 (first semiconductor layer)). A second semiconductor layer), the RESURF region 210 (corresponding to the RESURF region 110) and the drain side n ⁺ -type contact region 204d (corresponding to the n ⁺ -type contact region 104d) in the upper layer portion of the n ⁻ -type semiconductor layer 203 Is formed. In addition, the gate insulating film 105 in the RESURF-MOSFET 100 is replaced with a gate insulating film 205 that covers the upper surface of the source-side p-type semiconductor layer 103 from the upper surface thereof through the side surface of the n ⁻ -type semiconductor layer 203. The gate electrode 206 extends from above the p-type semiconductor layer 103 on the source side to above the RESURF region 210 through the side surface of the n ⁻ -type semiconductor layer 203.

In the above, the n ⁻ type semiconductor layer 203 is a layer made of a group III nitride semiconductor doped with an n type impurity. In the present embodiment, GaN is used for the group III nitride semiconductor, and Si ions are used for the n-type impurity. Further, the impurity concentration is, for example, about 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ , and the film thickness is, for example, about 130 nm. However, the present invention is not limited to this, and Si, Ge, Se, S, O, Te, or the like can be applied as an n-type impurity. In this embodiment, GaN is applied as the group III nitride semiconductor. However, the present invention is not limited to this. For example, the composition is Al _0.2 Ga _0.8 N or Al _0.3 Ga _0. AlGaN such as ₇ N, BGaN such as B _0.05 Ga _0.95 N, BAlN such as B _0.03 Al _0.97 N, or indium gallium nitride ( A nitride semiconductor containing at least one of Al, Ga, In, and B as a group III element, such as InGaN), aluminum nitride (AlN), or indium nitride (InN), can be used.

  The RESURF region 210 is an electric field relaxation region doped with both n-type impurities and N ions (p-type impurities), similar to the RESURF region 110 in the first embodiment of the present invention. However, in the present embodiment, the RESURF region 210 is formed by doping n-type impurities (Si) in the film formation process, implanting N by an ion implantation method, and performing activation annealing. In the present embodiment, as in the first embodiment of the present invention, N ions and Si ions that are n-type impurities are applied as the dopant of the RESURF region 210.

The n ⁺ type contact region 204d formed in the upper layer portion of the n ⁻ type semiconductor layer 203 on the drain side has a configuration corresponding to the n ⁺ type contact region 104d in the first embodiment of the present invention. In addition, the gate insulating film 205 and the gate electrode 206 have structures corresponding to the gate insulating film 105 and the gate electrode 106 in Embodiment 1 of the present invention, respectively. Therefore, detailed description is omitted here, and touched in the description of the manufacturing method below. In addition, since the other structure is the same as that of RESURF-MOSFET 100, detailed description is abbreviate | omitted here.

  Next, a method for manufacturing the RESURF-MOSFET 200 according to the present embodiment will be described in detail with reference to the drawings. FIG. 9A to FIG. 11C are process diagrams showing this manufacturing method. In the following description, the same steps as those in the first embodiment of the present invention will be omitted by quoting the description.

  In this manufacturing method, first, the buffer layer 102 and the p-type semiconductor layer 103 are formed on the substrate 101 by using a process similar to the process described with reference to FIG. 6A in the first embodiment of the present invention. Next, by forming a trench from the upper surface of the p-type semiconductor layer 103, the upper layer of the p-type semiconductor layer 103 is partitioned into one or more element formation regions. The photoresist used at the time of element isolation is removed with, for example, acetone.

Next, a silicon oxide film having a thickness of, for example, about 1000 nm is formed on the p-type semiconductor layer 103 by using, for example, PECVD. Subsequently, by patterning the silicon oxide film using a photolithography process and an etching process, a mask oxide film M21 (having an opening on a region where the n ⁺ -type contact region 104s on the source side in the p-type semiconductor layer 103 is formed ( 9A) is formed. For patterning the mask oxide film M21, for example, wet etching using a hydrofluoric acid aqueous solution can be used.

  Subsequently, after removing the photoresist on the mask oxide film M21 used in the photolithography process and the etching process with, for example, acetone, by using, for example, PECVD, silicon having a film thickness of, for example, about 20 nm is formed on the entire upper surface of the substrate. A protective film M22 (see FIG. 9A) made of an oxide film is formed.

  Subsequently, as shown in FIG. 9A, Si ions are implanted into the source side in the upper layer portion of the p-type semiconductor layer 103 by using an existing ion implantation apparatus while using the mask oxide film M21 as a mask. An implantation region 104a is formed.

Next, after removing the mask oxide film M21 and the protective film M22 on the p-type semiconductor layer 103 by, for example, wet etching using a hydrofluoric acid-based aqueous solution, the MOCVD method is used, for example, on the p-type semiconductor layer 103. A GaN film 203A doped with Si (see FIG. 9B) is epitaxially grown so that the film thickness becomes, for example, about 130 nm. At this time, the Si concentration in the GaN film 203A is controlled to be, for example, about 6 × 10 ¹⁷ / cm ³ .

  Subsequently, a silicon oxide film having a thickness of, for example, about 300 nm is formed on the GaN film 203A by using, for example, PECVD. Subsequently, by removing the source side portion of the silicon oxide film using a photolithography process and an etching process, as shown in FIG. 9B, a mask oxide film M23 is formed only on the drain side on the GaN film 203A. Form. For patterning the mask oxide film M23, for example, wet etching using a hydrofluoric acid aqueous solution can be used.

Next, by using the mask oxide film M23 as a mask and patterning the GaN film 203A by wet etching using, for example, a hydrofluoric acid aqueous solution, as shown in FIG. An n ⁻ type semiconductor layer 203 made of an n ⁻ type GaN film is formed on the drain side, and the source side on the surface of the p type semiconductor layer 103 is exposed.

Subsequently, after removing the mask oxide film M23 on the n ⁻ type semiconductor layer 203 by wet etching using, for example, a hydrofluoric acid aqueous solution, the exposed p type semiconductor layer 103 and the n ⁻ by using, for example, PECVD. A silicon oxide film having a thickness of, for example, about 1000 nm is formed on the type semiconductor layer 203. Subsequently, by patterning the silicon oxide film using a photolithography process and an etching process, a mask oxide film M24 having an opening on a region where an n ⁺ -type contact region 204d is to be formed later (see FIG. 10A). Form. For patterning the mask oxide film M24, for example, wet etching using a hydrofluoric acid aqueous solution can be used.

  Subsequently, after removing the photoresist on the mask oxide film M24 used in the photolithography process and the etching process with, for example, acetone, the film thickness is, for example, about 20 nm on the entire upper surface of the substrate by using, for example, PECVD. A protective film M25 (see FIG. 10A) made of a silicon oxide film is formed.

Subsequently, as shown in FIG. 10A, by using an existing ion implantation apparatus, Si ions are implanted while using the mask oxide film M24 as a mask, so that an implantation region is formed in an upper layer portion of the n ⁻ type semiconductor layer 203. 204a is formed.

Next, after removing all of the mask oxide film M24 and the protective film M25 on the p-type semiconductor layer 103 and the n ⁻ -type semiconductor layer 203 by, for example, wet etching using a hydrofluoric acid-based aqueous solution, a process similar to the above is used. Then, a mask oxide film M26 (see FIG. 10B) having an opening is formed on the region where the RESURF region 210 is formed, and then the entire upper surface of the substrate is covered and the film thickness is, for example, about 20 nm. A protective film M27 (see FIG. 10B) made of an oxide film is formed.

Subsequently, as shown in FIG. 10B, N ions are implanted into the upper layer portion of the n ⁻ -type semiconductor layer 203 by using an existing ion implantation apparatus while using the mask oxide film M26 as a mask. 210a is formed. Note that since the N ion implantation method can be the same as the N ion implantation method (see FIG. 6C) in the first embodiment of the present invention, detailed description thereof is omitted here.

When N ions are implanted as described above, next, all of the mask oxide film M26 and the protective film M27 on the p-type semiconductor layer 103 and the n ⁻ -type semiconductor layer 203 are removed by wet etching using, for example, a hydrofluoric acid aqueous solution. To do. Subsequently, a scattering prevention film M28 (see FIG. 11A) made of a silicon oxide film having a thickness of, for example, about 500 nm is formed on the entire upper surface of the substrate by using, for example, PECVD.

Subsequently, by annealing the substrate on which the anti-scattering film M28 is formed using an existing annealing apparatus, Si ions and N ions implanted in the implantation regions 104a, 204a, and 210a are diffused and activated, respectively. As a result, the n ⁺ -type contact regions 104s and 204d and the RESURF region 210 are formed as shown in FIG. In this case, the annealing is performed, for example, for 10 seconds in a nitrogen atmosphere in an electric furnace having a set temperature of 1200 ° C., for example.

Next, the scattering prevention film M28 on the surface of the p-type semiconductor layer 103 and the n ⁻ -type semiconductor layer 203 is all removed by wet etching using, for example, a hydrofluoric acid aqueous solution. Subsequently, by using, for example, PECVD, the gate insulating film 205 made of a silicon oxide film having a thickness of, for example, about 60 nm is formed on the entire surface of the p-type semiconductor layer 103 and the n ⁻ -type semiconductor layer 203 (see FIG. 11B). ).

Thereafter, for example, by using a photolithography process and an etching process, the gate insulating film 205, part of the ^{region n +} -type contact region 104s in the p-type semiconductor layer 103 is formed and n ^{- n} in type semiconductor layer 203 ⁺ An opening exposing a part of the region where the mold contact region 204d is formed is formed, and for example, a Ti / Al film is formed in the opening. As a result, as shown in FIG. 11B, the source electrode 107s and the drain electrode 107d are formed in ohmic contact with the n ⁺ -type contact regions 104s and 204d, respectively.

Next, by using, for example, an LPCVD method or a sputtering method, a polysilicon film 206A is formed on the entire upper surface of the substrate as shown in FIG. Subsequently, the substrate on which the polysilicon film 206A is formed is left in a thermal diffusion furnace in which POCl ₃ gas is sealed for about 20 minutes. At this time, the temperature in the thermal diffusion furnace is set to about 900 ° C. As a result, the polysilicon film 206A is doped with phosphorus (P) as an impurity, and this functions as a conductor film. As a method for doping impurities into the polysilicon film 206A, in addition to the above-described method, for example, phosphorus (P) is deposited on the polysilicon film 206A, and this is doped into the polysilicon film 206A by thermal diffusion. Various changes, such as a method, can be made.

  Subsequently, the polysilicon film 206A is patterned on the gate electrode 206 by using a photolithography process and an etching process. Thereby, the RESURF-MOSFET 200 having the cross-sectional structure as shown in FIG. 8 is manufactured.

In the present embodiment, as in the first embodiment of the present invention, the dopant in the RESURF region 210 is both N ions and n-type Si ions. However, the present invention is not limited to this, for example, The dopant in the n ⁺ -type contact region 104s and / or 204d may be both N ions and n-type Si ions. Alternatively, all of these may be doped with both n-type Si ions and p-type N ions. Accordingly, since the RESURF region 210 is provided, the sheet resistance of the n ⁺ -type contact region 104s / 204d and / or the RESURF region 210 can be reduced in the MOSFET having a high breakdown voltage characteristic. Can be realized.

  As described above, the RESURF-MOSFET 200 according to the present embodiment has a configuration including the RESURF region 210 functioning as an electric field relaxation region, and reduces the sheet resistance while keeping the sheet carrier concentration in the region where nitrogen atoms are implanted low. As a result, the resistance value can be lowered while suppressing the sheet carrier concentration between the source and the drain. As a result, it is possible to realize the RESURF-MOSFET 100 having excellent withstand voltage characteristics and current amplification characteristics.

In the present embodiment, the n ⁻ type semiconductor layer 203 may be composed of, for example, a non-doped GaN film. In this case, the GaN film exhibits some n-type conductivity due to the influence of the residual donor. Further, when the n ⁻ type semiconductor layer 203 is composed of a non-doped GaN film, the RESURF region 210 is injected with both n-type impurities and N ions as in the RESURF region 110 in the first embodiment of the present invention. Then, it is formed by activation.

Furthermore, in the present embodiment, the GaN film 203A shaped into the n ⁻ type semiconductor layer 203 is formed by epitaxial growth in a state doped with n type impurities (for example, Si ions) using, for example, the MOCVD method. The present invention is not limited to this. For example, it may be formed by epitaxial growth in a state where n-type impurities (for example, Si ions) and N ions are doped. In this case, the RESURF region 210 in FIG. 8 is omitted, and the region in which the n ⁺ -type contact region 204d in the n ⁻ -type semiconductor layer 203 is not formed functions as the RESURF region. Further, the N ion implantation step described with reference to FIG. 10B can be omitted.

It is sectional drawing which shows the structure of RESURF-MOSFET by Embodiment 1 of this invention. It is the schematic diagram which showed each resistance component in the current path of RESURF-MOSFET by Embodiment 1 of this invention. 6 is a graph showing the relationship between the RESURF region sheet resistance derived from Equation 4 in Embodiment 1 of the present invention and the RESURF-MOSFET drain current. It is a graph which shows the relationship between the sheet carrier density | concentration of RESURF area | region and the dielectric breakdown voltage of RESURF-MOSFET by Embodiment 1 of this invention. In the first embodiment of the present invention, when the activation annealing is performed by implanting only Si ions, the relationship between the sheet carrier concentration and the sheet resistance, and both Si ions and N ions are implanted at a ratio of 1: 1. 5 is a graph showing the relationship between sheet carrier concentration and sheet resistance when activation annealing is performed. It is a process diagram which shows the manufacturing method of RESURF-MOSFET by Embodiment 1 of this invention (1). It is a process diagram which shows the manufacturing method of RESURF-MOSFET by Embodiment 1 of this invention (2). It is sectional drawing which shows the structure of RESURF-MOSFET by Embodiment 2 of this invention. It is a process diagram which shows the manufacturing method of RESURF-MOSFET by Embodiment 2 of this invention (1). It is a process figure which shows the manufacturing method of RESURF-MOSFET by Embodiment 2 of this invention (2). It is a process figure which shows the manufacturing method of RESURF-MOSFET by Embodiment 2 of this invention (3).

Explanation of symbols

100, 200 RESURF-MOSFET
101 substrate 102 buffer layer 103 p-type semiconductor layer 103a channel formation region 104a, 204a, 210a implantation region 104d n ⁺ type contact region 104s n ⁺ type contact region 105, 205 gate insulating film 106, 206 gate electrode 106A polysilicon film 107d drain Electrode 107s Source electrode 110, 210 RESURF region 110a Injection region 203 n ⁻ type semiconductor layer 203A GaN film 204d n ⁺ type contact region 206A Polysilicon film M1, M3, M21, M23, M24, M26 Mask oxide films M2, M4, M22 , M25, M27 Protective film M5, M28 Anti-scattering film

Claims (18)

A channel forming region, a first doped region formed in a region in contact with the channel forming region in the channel length direction, and two regions sandwiching the channel forming region and the first doped region on the upper surface; A second doped region having a higher impurity concentration than the doped region, and a semiconductor layer made of a group III nitride semiconductor;
An insulating film formed on the channel formation region;
A gate electrode formed on the insulating film,
The first doped region and / or the second doped region includes an n-type conductive atom and a nitrogen atom as dopants. The channel formation region has p-type conductivity,
The semiconductor device according to claim 1, wherein the second doped region has n-type conductivity. The semiconductor layer includes a first semiconductor layer made of a group III nitride semiconductor having p-type conductivity, and a group III nitride having n-type conductivity formed on a part of the first semiconductor layer. A second semiconductor layer made of a semiconductor,
One of the second doped regions is formed in the first semiconductor layer, and the other is formed in the second semiconductor layer,
The semiconductor device according to claim 1, wherein the first doped region is formed in the second semiconductor layer.   The semiconductor device according to claim 1, wherein the group III nitride semiconductor is any one of GaN, AlGaN, BGaN, BAlN, InGaN, AlN, and InN.   The semiconductor device according to claim 1, wherein the n-type conductive atom is Si, Ge, Se, S, O, or Te. The semiconductor device according to claim 1, wherein the first doped region has a sheet carrier concentration of 5 × 10 ¹³ / cm ² or less.   The semiconductor according to claim 1, wherein the first doped region has a ratio of the nitrogen atom to the atom having n-type conductivity of 0.5 or more and 3 or less. apparatus.   The semiconductor device according to claim 1, wherein the second doped region has a depth from the upper surface of the semiconductor layer of 30 nm to 100 nm. A preparation step of preparing a substrate including a semiconductor layer made of a group III nitride semiconductor;
A first implantation step of implanting n-type conductivity impurities into the first and second regions, which are two regions separated from each other in the semiconductor layer;
A third region in the semiconductor layer sandwiched between the first region and the second region and in contact with one of the second regions has an impurity concentration lower than that of the first and second regions. A second implantation step of implanting n-type conductivity impurities into
A third implantation step of implanting nitrogen atoms into at least one of the first to third regions;
A method for manufacturing a semiconductor device, comprising: The semiconductor layer is made of the group III nitride semiconductor, and includes a first semiconductor layer having p-type conductivity and a second semiconductor having n-type conductivity formed on a part of the first semiconductor layer. Made up of layers,
The first region is a partial region of the first semiconductor layer;
The second region is a partial region of the second semiconductor layer,
The method for manufacturing a semiconductor device according to claim 9, wherein the third region is a partial region of the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 9, wherein the third region has a sheet carrier concentration of 5 × 10 ¹³ / cm ² or less.   12. The semiconductor device according to claim 9, wherein the third region has a ratio of the nitrogen atom to the n-type conductive atom of 0.5 or more and 3 or less. Manufacturing method.   13. The method of manufacturing a semiconductor device according to claim 9, wherein the third region has a depth from the upper surface of the semiconductor layer of 30 nm to 100 nm. A preparation step of preparing a substrate comprising a first semiconductor layer made of a group III nitride semiconductor and having p-type conductivity;
A semiconductor layer forming step of forming a second semiconductor layer in which a part of the first semiconductor layer is doped with an impurity having n-type conductivity and a nitrogen atom;
An impurity implantation step of implanting an impurity having n-type conductivity into a part of the first region of the first semiconductor layer and a part of the second region of the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 14, wherein the second semiconductor layer has a sheet carrier concentration of 5 × 10 ¹³ / cm ² or less.   16. The method of manufacturing a semiconductor device according to claim 14, wherein the second semiconductor layer has a ratio of the nitrogen atom to the n-type conductive atom of 0.5 or more and 3 or less.   The method for manufacturing a semiconductor device according to claim 9, wherein the group III nitride semiconductor is any one of GaN, AlGaN, BGaN, BAlN, InGaN, AlN, and InN.   The method for manufacturing a semiconductor device according to claim 9, wherein the n-type conductive atom is Si, Ge, Se, S, O, or Te.

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