JP2009260219A - Method of dicing semiconductor wafer, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of dicing that sufficiently prevents a semiconductor wafer from being broken. <P>SOLUTION: The method of dicing the semiconductor wafer includes a process of coating the semiconductor wafer 1 so that projection electrodes 2 formed on one surface S1 thereof are embedded, with an insulating resin layer 3, a process of sticking a dicing tape 5 on the surface of the insulating resin layer 3 and mounting the semiconductor wafer 1 on a wafer ring 4 via the dicing tape 5, a process of grinding the reverse surface of the semiconductor wafer 1 from the side of the other surface S2 of the semiconductor wafer 1 after the mounting on the wafer ring, a process of fixing the semiconductor wafer 1 with the wafer ring 4 mounted thereon to a dicing device 40 after the reverse surface grinding, and a dicing process of cutting the semiconductor wafer 1 from the side of the other surface S2 to obtain a semiconductor chip 10 which has the projection electrode 2 on the one surface S1 and also has the one surface S1 coated with the cut insulating resin layer 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer dicing method and a semiconductor device manufacturing method.

  With recent progress in downsizing and higher functionality of electronic devices, semiconductor devices are required to be reduced in size and thickness, and to improve electrical characteristics such as compatibility with high-frequency transmission. In order to satisfy the above requirements, various studies have been made on the process of mounting a semiconductor chip on a substrate in the process of manufacturing a semiconductor device.

  Conventionally, when a semiconductor device is manufactured by mounting a semiconductor chip on a substrate, a method of connecting the semiconductor chip to the substrate by wire bonding has been mainly employed. However, in recent years, the transition to the flip chip connection method has begun. In this flip chip connection method, bump electrodes called bumps formed on a semiconductor chip are directly connected to electrodes formed on a substrate.

  Known flip-chip connection methods include metal bonding using solder, tin, etc., metal bonding using ultrasonic vibration, and method of maintaining mechanical contact using the shrinkage force of the resin. Yes. Among these methods, from the viewpoint of productivity and connection reliability, a method of metal bonding using solder, tin or the like is widely adopted. Since the method of metal bonding using solder shows particularly high connection reliability, it is adopted for mounting such as MPU (Micro Processing Unit).

  When a semiconductor chip is mounted on a substrate by a flip chip connection method, the gap between the semiconductor chip and the substrate is usually made of a resin material in order to protect the connection portion from the external environment and prevent external stress from concentrating on the connection portion. Seal and fill. As a sealing and filling method, there is known a method in which after a semiconductor chip is mounted on a substrate, a liquid resin material is injected and cured by a capillary phenomenon (see, for example, Patent Documents 1 to 3).

  Incidentally, a relatively thin semiconductor wafer having a thickness of 100 μm or less has been used in order to cope with the thinning of semiconductor devices and the multi-layer stacking of semiconductor chips. Such a semiconductor wafer is manufactured by grinding a relatively thick semiconductor wafer to a predetermined thickness by a grinding method called back grinding.

As one aspect of flip chip connection, a method of forming a resin layer for sealing (adhesive layer) in advance on the surface of a semiconductor wafer obtained by back grinding is known (for example, see Patent Documents 4 and 5). reference). In this method, both the semiconductor wafer and the resin layer provided on one surface thereof are simultaneously cut, and the separated semiconductor chip is mounted on the substrate through the resin layer.
JP 2004-349561 A Japanese Patent Laid-Open No. 2000-10082 JP 2003-142529 A JP 2001-332520 A JP 2005-28734 A

  However, a semiconductor wafer ground to a thickness of 100 μm or less by back-grinding is extremely low in mechanical strength, and therefore easily breaks before reaching the dicing process. For this reason, it is difficult to handle the semiconductor wafer. In this respect, the conventional method for manufacturing a semiconductor device has room for improvement.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor wafer dicing method that can sufficiently prevent damage to a semiconductor wafer. It is another object of the present invention to provide a method for efficiently manufacturing a semiconductor device using a semiconductor chip separated by the dicing method.

  A dicing method of a semiconductor wafer according to the present invention includes a covering step of forming an insulating resin layer on one surface of the semiconductor wafer so as to embed a plurality of protruding electrodes formed on the one surface of the semiconductor wafer, and an insulating resin layer A wafer ring mounting step for bonding the surface and a dicing tape and fixing the semiconductor wafer to the wafer ring via the dicing tape, and a back grind for grinding the semiconductor wafer from the other side of the semiconductor wafer after the wafer ring mounting step A dicing preparation process for fixing the semiconductor wafer with the wafer ring mounted thereon after the process and the back grinding process on the stage of the dicing apparatus via the insulating resin layer and the dicing tape, and from the other side of the semiconductor wafer Cut the semiconductor wafer together with the insulating resin layer, and have a protruding electrode on one side and cut it. And and a dicing step to obtain a semiconductor chip in which the one surface is covered with an insulating resin layer.

  According to the dicing method of the present invention, it is possible to shift from the back grinding process to the dicing preparation process and the dicing process while being fixed to the wafer ring. For this reason, damage of the semiconductor wafer can be sufficiently prevented in these processes. Further, after one surface of the semiconductor wafer is coated with the insulating resin layer, the semiconductor wafer is diced to obtain a plurality of semiconductor chips having the insulating resin layer on the one surface at a time. For this reason, the productivity of semiconductor chips is improved compared to the case where filling is performed using a capillary phenomenon after the connection process and the case where an insulating adhesive layer is individually formed on the surface of a separated semiconductor chip later. it can.

  Further, in the back grinding process and the dicing process, the surface of the insulating adhesive layer is in contact with the dicing tape. For this reason, it can fully prevent that the cutting waste etc. which generate | occur | produce in a back grinding process and a dicing process adhere to an insulating resin layer, and can fully suppress the performance fall of an insulating resin layer. A semiconductor device with high connection reliability can be manufactured by mounting a semiconductor chip on a substrate through an insulating resin layer in which predetermined performance is maintained.

  In the dicing step, it is preferable that the dicing pattern formed on one surface of the semiconductor wafer is recognized by an infrared camera from the other surface side of the semiconductor wafer. By recognizing the dicing pattern using the infrared camera, it is possible to accurately grasp the portion to be cut in the dicing process.

  In the covering step, it is preferable to form the insulating resin layer by bonding a film made of the insulating resin composition onto one surface of the semiconductor wafer. The insulating resin layer may be formed by coating an insulating resin composition on the surface of a substrate or a semiconductor chip, but if a film formed in advance is used, the working efficiency can be further improved.

  The insulating resin layer functions as an adhesive that seals the gap between the semiconductor chip and the substrate and adheres them in the method of the semiconductor device according to the present invention described later. From the viewpoint of efficiently manufacturing a semiconductor device with high connection reliability after the dicing step, it is preferable to use an insulating resin layer that satisfies the following conditions. That is, the insulating resin layer preferably has a visible light transmittance of 10% or more. Thus, in the step of adjusting the position of the semiconductor chip and the substrate (position adjustment step), the position of the protruding electrode of the semiconductor chip can be confirmed with a normal visible light camera or the like. Moreover, it is preferable that an insulating resin layer consists of an insulating resin composition which does not produce resin foam even if it connects at the temperature of 300 degreeC or more. As a result, in the semiconductor device obtained through the process of connecting the semiconductor chip and the substrate (connection process), bubbles remaining in the connection part are sufficiently reduced. Note that air bubbles remaining in the connection portion contribute to a decrease in connection reliability of the semiconductor device.

  Furthermore, the insulating resin layer preferably contains a polyimide resin, an epoxy resin, and a curing agent. By containing these components, the high heat resistance of the insulating resin layer can be achieved, and the insulating resin layer can be cured by heating.

  A semiconductor device manufacturing method according to the present invention includes a pick-up step of picking up a semiconductor chip obtained by the above-described semiconductor wafer dicing method together with the cut insulating resin layer, and cutting the substrate on which the semiconductor chip is to be mounted. A position adjusting step for aligning the electrodes provided on the surface of the substrate with the protruding electrodes of the semiconductor chip while holding the semiconductor chip with the insulating resin layer side facing, and after the position adjusting step, the semiconductor chip is mounted on the substrate A connection preparation step of temporarily fixing the semiconductor chip on the substrate; and a connection step of pressing the semiconductor chip against the substrate and applying heat to the substrate to mount the semiconductor chip on the substrate.

  When a sealing resin layer is formed on the surface of the semiconductor chip or the substrate before mounting the semiconductor chip on the substrate, there is room for improvement in terms of connection reliability of the semiconductor device. That is, when the resin layer is formed in advance, the properties (melt viscosity, etc.) of the resin layer may change due to heat or the like until the process of mounting the semiconductor chip on the substrate, and connection failure may occur. On the other hand, according to the method for manufacturing a semiconductor device according to the present invention, after performing the position adjustment process, the connection process is performed, so that the property of the insulating resin layer is changed by heat before the connection process. It can be suppressed sufficiently. Therefore, the insulating resin layer can sufficiently exhibit performance in the connection step, enables good connection, and manufactures a semiconductor device with high connection reliability.

  Further, if the semiconductor chip is temporarily fixed at a predetermined position on the substrate prior to the connecting step, the laminated body including the substrate, the insulating resin layer, and the semiconductor chip can be transferred to the crimping apparatus after the temporary fixing. For example, the semiconductor device can be manufactured more efficiently if the laminate is continuously conveyed to the crimping apparatus and the conveyed laminate and the substrate are continuously connected.

  ADVANTAGE OF THE INVENTION According to this invention, the dicing method of the semiconductor wafer which can fully prevent damage to a semiconductor wafer is provided. In addition, according to the present invention, there is provided a method for efficiently manufacturing a semiconductor device using a semiconductor chip separated by the dicing method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

<First Embodiment>
A semiconductor wafer dicing method and a semiconductor device manufacturing method according to the first embodiment will be described with reference to FIGS.

  First, a semiconductor wafer 1 as shown in FIG. 1 is prepared. The semiconductor wafer 1 has a circuit surface (one surface) S1 on which a circuit is formed by a semiconductor process, and a back surface (other surface) S2 that is a surface opposite to the circuit surface S1. A plurality of protruding electrodes 2 and a dicing pattern (not shown) protruding from the circuit surface S1 are formed on the circuit surface S1 of the semiconductor wafer 1.

  The thickness of the semiconductor wafer 1 is preferably 50 to 600 μm, more preferably 50 to 550 μm, and still more preferably 50 to 400 μm. If the thickness of the semiconductor wafer 1 is less than 50 μm, the semiconductor wafer 1 is likely to be damaged. On the other hand, if it exceeds 600 μm, it is difficult to manufacture a thin semiconductor device. Moreover, it is preferable that it is 1-200 micrometers, and, as for the height (t2 shown in FIG. 1) of the protruding electrode 2, it is more preferable that it is 1-100 micrometers.

  Examples of the material of the semiconductor wafer 1 include silicon and gallium arsenide. Examples of the material of the protruding electrode 2 include gold, silver, copper, nickel, indium, palladium, tin, lead, and bismuth. The protruding electrode 2 may be composed of a single metal among the above materials, or may be composed of two or more kinds of metals. The protruding electrode 2 may be a laminate of metal layers having different compositions.

  Next, as shown in FIG. 2, an insulating resin layer 3 is formed on the circuit surface S1 so as to embed a plurality of protruding electrodes 2 formed on the circuit surface S1 of the semiconductor wafer 1 (covering step). The insulating resin composition forming the insulating resin layer 3 preferably has high heat resistance and thermosetting properties. The insulating resin composition will be described in detail later.

  As a method for forming the insulating resin layer 3, a method of applying a coating liquid containing an insulating resin composition to the circuit surface S1 by spin coating or printing by spin coating or printing, and then drying, or a film A method of laminating the insulating resin composition formed in a shape on the circuit surface S1 of the semiconductor wafer 1 (laminating method) is mentioned. From the viewpoint of workability, it is preferable to employ a laminating method. The laminating method can be performed using a roll laminator, a vacuum laminator, or the like.

The thickness of the insulating resin layer 3 is preferably such that the insulating resin layer 3 can sufficiently fill the space between the semiconductor chip 10 and the substrate 14 to be mounted (see FIG. 6). Usually, the thickness of the insulating resin layer 3 (t ₃ shown in FIG. 2) is such that the height of the protruding electrode 2 (t ₂ shown in FIG. 1) and the height of the electrode 14a of the substrate 14 (t _14a shown in FIG. 6). As long as it corresponds to the total of the above, the gap between the semiconductor chip 10 and the substrate 14 can be sufficiently filled with the insulating resin composition. Specifically, the thickness of the insulating resin layer 3 is preferably 5 μm or more, and more preferably 10 μm or more. If the thickness of the insulating resin layer 3 is less than 5 μm, it tends to be difficult to form the insulating resin layer 3 by the laminating method. And bubbles are likely to occur.

  The insulating resin layer 3 preferably has a visible light transmittance of 10% or more, more preferably 15% or more, and still more preferably 20% or more. By adjusting the composition and thickness of the insulating resin layer 3 so that the visible light transmittance falls within the above range, the position of the protruding electrode 2 can be confirmed with a normal visible light camera or the like in the subsequent position adjustment step. Can do. “Visible light transmittance” here means a value obtained by measuring the transmittance of light having a wavelength of 555 nm using a commercially available spectrophotometer.

  Next, as shown in FIG. 3, a dicing tape 5 is attached to the surface S <b> 3 of the insulating resin layer 3 and the lower edge 4 a of the wafer ring 4. Thereby, the semiconductor wafer 1 is fixed to the wafer ring 4 via the insulating resin layer 3 and the dicing tape 5 (wafer ring mounting step).

  The wafer ring 4 is an annular member and functions as a fixing jig for the semiconductor wafer 1 during dicing. The wafer ring 4 has an inner diameter larger than the outer shape of the semiconductor wafer 1 and is disposed on the dicing tape 5 so as to surround the semiconductor wafer 1. Thus, the semiconductor wafer 1, the insulating resin layer 3 and the wafer ring 4 are integrated by the dicing tape 5.

  The dicing tape 5 has a base film 5a and an adhesive layer 5b formed on the surface of the base film 5a, and the adhesive layer 5b and the surface S3 of the insulating resin layer 3 are bonded. As the dicing tape 5, it is preferable to use a tape whose adhesive strength of the adhesive layer 5b is reduced by at least one of heating and ultraviolet irradiation.

  Subsequently, as shown in FIG. 4, the semiconductor wafer 1 and the wafer ring 4 are fixed via the dicing tape 5 on the stage 30 b of the grinding apparatus 30 so that the back surface (other surface) S <b> 2 of the semiconductor wafer 1 faces upward. To do. While pressing the grinding wheel 30a against the back surface S2 of the semiconductor wafer 1, the grinding wheel 30a and the stage 30b are rotated to grind the semiconductor wafer 1 (back grinding process). It is preferable to thin the semiconductor wafer 1 to a thickness of 50 to 550 μm by this grinding process. If the thickness of the semiconductor wafer 1 is less than 50 μm, the semiconductor wafer 1 is likely to be damaged, and if it exceeds 550 μm, it is difficult to manufacture a thin semiconductor device.

  After the back grinding process, the thinned semiconductor wafer 1 and wafer ring 4 are removed from the stage 30 b together with the dicing tape 5. Then, it moves to the dicing apparatus 40 shown in FIG. As shown in the figure, the semiconductor wafer 1 and the wafer ring 4 are placed on the stage 40b of the dicing apparatus 40 via the dicing tape 5 so that the back surface (the other surface) S2 of the thinned semiconductor wafer 1 faces upward. Fix (dicing preparation step).

  Then, the location (dicing pattern) which should cut | disconnect the circuit surface S1 of the semiconductor wafer 1 from the back surface S2 side with the infrared camera 12 is recognized. Then, as shown in FIG. 5, the semiconductor wafer 1 is cut together with the insulating resin layer 3 from the back surface S2 side of the semiconductor wafer 1 by the dicing blade 9 (dicing step). As the dicing blade 9, for example, a diamond blade can be used. The dicing is preferably performed while the dicing blade 9 rotating at high speed is cooled with water.

  Through the dicing process, a plurality of semiconductor chips 10 having the cut semiconductor wafer 1 and the protruding electrodes 2 provided on the circuit surface S1 are obtained. The semiconductor chip 10 is covered with the circuit surface S1 by the cut insulating resin layer 3. The size of the semiconductor chip 10 may be set as appropriate according to the application and required performance. For example, in a COF (Chip On Film) which is a mounting package such as a liquid crystal driver IC, a semiconductor chip cut into a rectangle having a width of 1 to 2 mm and a length of 10 to 25 mm by a dicing process is usually used.

  After completion of the dicing process, the semiconductor chip 10 is picked up using a pickup device (not shown) (pickup process). Before picking up the semiconductor chip 10, it is preferable to reduce the adhesive force by heating or irradiating the adhesive layer 5b.

  Subsequently, as shown in FIG. 6, the temporary fixing device 50 and the visible light camera 13 are used to align the electrode 14 a of the substrate 14 and the protruding electrode 2 of the semiconductor chip 10.

  First, the back surface S2 of the picked-up semiconductor chip 10 is attracted to the crimping head 50a. On the other hand, the substrate 14 is placed on the stage 50b with the surface on which the electrode 14a is formed facing upward. Subsequently, an alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 10 is recognized by the visible light camera 13 through the insulating resin layer 3, and an electrode 14a of the substrate 14 is formed. The alignment reference mark (not shown) on the other surface S4 is recognized by the visible light camera 13, and alignment is performed.

  After the position adjusting step, as shown in FIG. 7, the semiconductor chip 10 is temporarily fixed to the substrate 14 by pressing the semiconductor chip 10 against the substrate 14 and applying heat by using the temporary fixing device 50 (connection preparation step). ). The crimping head 50a and the stage 50b of the temporary fixing device 50 each have a built-in heater so that the surface temperature can be set to a desired temperature. The crimping head 50a is movable in the direction perpendicular to the surface of the stage 50b (in the direction of arrow V in FIG. 6).

  The temperature of the crimping head 50a and the stage 50b of the temporary fixing device 50 may be a temperature at which the insulating resin layer 3 exhibits adhesiveness and does not promote the curing reaction of the insulating resin layer 3 in the connection preparation step. For example, it is preferable to set to about 40-100 degreeC. In the connection preparation step, heating may be performed by only one of the crimping head 50a and the stage 50b, or temporary fixing may be performed only by pressing with the crimping head 50a without heating.

  After the connection preparation step, the stacked body 18 in which the substrate 14, the insulating resin layer 3, and the semiconductor chip 10 are stacked in this order is conveyed to the crimping device 60. As shown in FIG. 8, the semiconductor chip 10 is mounted on the substrate 14 by pressing the semiconductor chip 10 against the substrate 14 and applying heat using the crimping device 60 (connection process). Each of the crimping head 60a and the stage 60b of the crimping device 60 has a built-in heater so that the surface temperature can be set to a desired temperature. The crimping head 60a is movable in a direction perpendicular to the surface of the stage 60b (in the direction of arrow V in FIG. 8).

  The temperature of the crimping head 60a and the stage 60b of the crimping device 60 is such that the insulating resin layer 3 flows sufficiently so that no resin remains between the protruding electrode 2 and the electrode 14a in order to prevent poor connection in the connection process. It is preferable to set the temperature. Further, when the eutectic is formed and connected between the protruding electrode 2 and the electrode 14a, the temperature at which the insulating resin layer 3 flows sufficiently and the temperature of the connecting portion is the same as the material of the protruding electrode 2 and the material of the electrode 14a. It is preferable to set so as to exceed the crystallization temperature. For example, when the protruding electrode 2 is made of gold and the electrode 14a is tin-plated, it is preferable to heat the connecting portion so as to exceed the eutectic temperature (278 ° C.) of gold and tin. For example, it is preferable to set the pressure-bonding head 60 a to 30 to 500 ° C. and the stage 60 b to 50 to 150 ° C. The heating time is preferably 0.1 to 10 seconds, more preferably 0.1 to 5 seconds.

  Through the connecting step, the protruding electrode 2 of the semiconductor chip 10 and the electrode 14a of the substrate 14 are electrically connected. Further, the semiconductor chip 10 and the substrate 14 are bonded together by the cured product 3 a of the insulating resin layer 3 interposed between the semiconductor chip 10 and the substrate 14. As a result, the semiconductor chip 10 is mounted on the substrate 14, and the semiconductor device 100 as shown in FIG. 9 is manufactured. Subsequently, in order to further advance the curing of the insulating resin layer 3, heat treatment may be performed using a heating oven or the like.

(Insulating resin composition)
The insulating resin composition used for forming the insulating resin layer 3 in the above coating step will be described. The insulating resin composition preferably contains a thermosetting component and its curing agent.

  Examples of thermosetting components include epoxy resins, bismaleimide resins, polyamide resins, polyimide resins, triazine resins, cyanoacrylate resins, unsaturated polyester resins, melamine resins, urea resins, benzoxazine resins, polyurethane resins, polyisocyanate resins. , Furan resin, resorcinol resin, xylene resin, benzoguanamine resin, diallyl phthalate resin, silicone resin, polyvinyl butyral resin, siloxane-modified epoxy resin, siloxane-modified polyamideimide resin, acrylate resin, etc. To epoxy resin, benzoxazine resin, siloxane-modified epoxy resin, and siloxane-modified polyamideimide resin. These thermosetting components may be used individually by 1 type, and may use 2 or more types together.

  Examples of the curing agent include phenol resin, aliphatic amine, alicyclic amine, aromatic polyamine, polyamide, aliphatic acid anhydride, alicyclic acid anhydride, aromatic acid anhydride, dicyandiamide, organic acid dihydrazide, Examples thereof include boron trifluoride amine complexes, imidazoles, tertiary amines, and organic peroxides. These curing agents may be used alone or in combination of two or more.

  As a combination of the thermosetting component and the curing agent in the insulating resin layer 3, it is preferable to use an epoxy resin as the thermosetting component and a phenol resin or imidazole as the curing agent from the viewpoint of heat resistance. From the viewpoint of further improving the heat resistance, it is preferable to use a polyimide resin and an epoxy resin as the thermosetting component. In addition, by including a polyimide resin, heat resistance and adhesiveness are improved, and film forming properties of the insulating resin composition are improved.

  The insulating resin layer 3 may further contain a thermoplastic component. Examples of the thermoplastic component include polyester resin, polyether resin, polyamide resin, polyamideimide resin, polyimide resin, polyacrylate resin, polyvinyl butyral resin, polyurethane resin, phenoxy resin, polyacrylate resin, polybutadiene, acrylonitrile butadiene copolymer , Acrylonitrile butadiene rubber styrene resin (ABS), styrene butadiene copolymer (SBR), acrylic acid copolymer and the like. These thermoplastic components may be used individually by 1 type, and may use 2 or more types together. Among the above thermoplastic components, a polyimide resin and a phenoxy resin are preferable from the viewpoints of heat resistance and film formability.

  The insulating resin layer 3 may further contain a filler (inorganic fine particles) made of an inorganic compound. By blending the filler, the thermal expansion coefficient of the insulating resin layer 3 can be lowered. In addition to this, by blending a filler, the adhesiveness of the insulating resin layer 3 can be controlled, the thermal conductivity or the dicing property can be improved, or the melt viscosity can be adjusted. As fillers, alumina, aluminum nitride, boron nitride, crystalline silica or amorphous silica, mullite (composite oxide of silicon dioxide and aluminum oxide), composite oxide of silicon dioxide and titanium oxide, aluminum hydroxide, hydroxylation It is preferable to use magnesium, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, or magnesium oxide. In addition, the said filler may be used individually by 1 type, and may use 2 or more types together.

  The average particle size of the filler is preferably 0.005 to 5.0 μm, more preferably 0.005 to 2.5 μm, and still more preferably 0.005 to 2.0 μm. When a filler having an average particle size of less than 0.005 μm or more than 5.0 μm is used, the filler remains between the protruding electrode 2 and the electrode 12a as compared with the case of using a filler having an average particle size within the above range. Connection failure may occur. In addition to this, the film formability of the insulating resin composition tends to be insufficient. In addition, what is necessary is just to adjust the compounding quantity of a filler suitably according to the performance by which the insulating resin layer 3 is requested | required.

  The insulating resin layer 3 may further contain additives such as a curing accelerator, a silane coupling agent, a titanium coupling agent, an antioxidant, a leveling agent, and an ion trapping agent. These additives may be used individually by 1 type, and may use 2 or more types together. What is necessary is just to adjust the compounding quantity of an additive suitably so that the effect of each additive may express.

  As described above, the insulating resin layer 3 preferably has a visible light transmittance of 10% or more. It is preferable to set the composition of the insulating resin layer 3, the material of the filler, the particle size, etc. so that the visible light transmittance of the insulating resin layer 3 is 10% or more.

  Insulating resin layer 3 is preferably made of an insulating resin composition that does not cause foaming of resin even when connected at a temperature of 300 ° C. or higher. Bubbles remaining in the connection portion after the connection process contribute to a decrease in connection reliability of the semiconductor device. Therefore, by using an insulating resin composition that satisfies the above requirements, it is possible to suppress the generation of voids due to resin foaming, so that the connection reliability of the semiconductor device can be further improved. In addition, the presence or absence of generation | occurrence | production of the resin foam after the said heat processing can be evaluated using the apparatus of the structure similar to the crimping | compression-bonding apparatus 60 shown in FIG. First, a glass substrate (thickness 0.7 mm), an insulating resin layer (thickness 90 to 100 μm), and a glass substrate (thickness 0.15 μm) are stacked in this order on the stage 60b. A pressure-bonding head 60a having a surface temperature of 300 to 400 ° C. is pressed against the laminated body for 0.5 to 5 seconds. It can be evaluated by visually observing the presence or absence of bubbles in the insulating resin layer after curing.

  For a film made of an insulating resin composition, for example, a coating liquid containing an insulating resin is applied on a support film such as a polyethylene terephthalate (PET) film whose surface has been release-treated with silicone or the like, and then dried. Can be obtained.

  As described above, according to the first embodiment, the semiconductor wafer 1 thinned by the back grinding process can be transported to the dicing apparatus 40 while being fixed to the wafer ring 4. For this reason, damage to the semiconductor wafer 1 after the back grinding process can be sufficiently prevented.

  Further, after one surface S1 of the semiconductor wafer 1 is coated with the insulating resin layer 3, the semiconductor wafer 1 is diced, so that a plurality of semiconductor chips 10 having the insulating resin layer 3 on the one surface S1 are collectively collected. can get. For this reason, the productivity of semiconductor chips is improved compared to the case where filling is performed using a capillary phenomenon after the connection process and the case where an insulating adhesive layer is individually formed on the surface of a separated semiconductor chip later. it can.

  Further, in the back grinding process and the dicing process, the surface S3 of the insulating resin layer 3 is in contact with the adhesive layer 5b of the dicing tape 5. For this reason, in the back grinding process and the dicing process, the cutting waste and water of the semiconductor wafer 1 can be sufficiently prevented from adhering to the insulating resin layer 3, and the performance degradation of the insulating resin layer 3 can be sufficiently suppressed. As described above, by mounting the semiconductor chip 10 on the substrate 14 via the insulating resin layer 3 in which predetermined performance is maintained, good connection is possible, and the semiconductor device 100 with high connection reliability can be manufactured. .

  According to the method for manufacturing a semiconductor device according to the present embodiment, the position adjustment step and the connection preparation step are performed using the crimping head 50a set at a relatively low temperature. Curing can be sufficiently prevented. Prior to the connecting step, the semiconductor chip 10 is temporarily fixed at a predetermined position on the substrate 14 to produce the laminated body 18, so that the laminated body 18 can be transported to the crimping apparatus 60, and alignment is performed in the crimping apparatus 60. Since it is not necessary to perform the connection, an effect that the connection can be efficiently performed is achieved.

Second Embodiment
A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. Since this embodiment can be carried out in the same manner as the first embodiment up to the pick-up step, the steps after the position adjustment step will be described here.

  This embodiment is different from the first embodiment in that instead of mounting the semiconductor chip 10 on the substrate 14, the electrode 22a is mounted on the light-transmitting substrate 22 formed on the one surface S5. In addition, as the board | substrate 22 which has a light transmittance, a polyimide etc. are mentioned, for example, As the electrode 22a, the copper wiring by which the tin plating process was given to the surface is mentioned.

  As shown in FIG. 10, the visible light camera 13 is used to align the electrode 22 a of the light-transmitting substrate 22 and the protruding electrode 2 of the semiconductor chip 10 (position adjustment process). The light-transmitting substrate 22 is movable in a direction parallel to the surface of the stage 70b of the temporary fixing device 70 (in the direction of arrow H in FIG. 10) while being held by a substrate holding unit (not shown).

  First, the back surface S <b> 2 of the picked-up semiconductor chip 10 is fixed on the surface of the stage 70 b of the temporary fixing device 70. On the other hand, the substrate 22 having light transmissivity, on which the electrode 22a is formed on the one surface S5, is transported above the semiconductor chip 10 using the substrate holder. Subsequently, the alignment reference mark (not shown) formed on the circuit surface S1 of the semiconductor chip 10 is recognized by the visible light camera 13 through the insulating resin layer 3 and the light-transmitting substrate 22. The alignment reference mark (not shown) on the one surface S5 on which the electrode 22a of the substrate 22 having optical transparency is formed is recognized by the visible light camera 13, and the arrow H of the substrate 22 having optical transparency is recognized. Adjust the position of the direction. Instead of adjusting the position by moving the light-transmitting substrate 22 by the substrate holding portion, the semiconductor chip 10 is moved by the stage 70b, thereby having light transmittance with the protruding electrode 2 of the semiconductor chip 10. Position adjustment with the electrode 22a of the board | substrate 22 may be performed.

  After the position adjustment step, as shown in FIG. 11, the semiconductor chip 10 is pressed by pressing the semiconductor chip 10 against the light-transmitting substrate 22 and applying heat using the crimping head 70a of the temporary fixing device 70. Temporary fixing to the substrate 22 (connection preparation step). Each of the crimping head 70a and the stage 70b of the temporary fixing device 70 has a built-in heater so that the surface temperature can be set to a desired temperature. The crimping head 70a is movable in the direction perpendicular to the surface of the stage 70b (the direction of arrow V in FIG. 11).

  The temperature of the pressure-bonding head 70a and the stage 70b of the temporary fixing device 70 may be a temperature at which the insulating resin layer 3 exhibits adhesiveness and does not accelerate the curing reaction of the insulating resin layer 3 in the connection preparation step. For example, it is preferable to set to about 40-100 degreeC. In the connection preparation step, heating may be performed by only one of the crimping head 70a and the stage 70b, or temporary fixing may be performed only by pressurization by the crimping head 70a without heating.

  After the connection preparation step, the stacked body 19 in which the semiconductor chip 10, the insulating resin layer 3, and the substrate 22 are stacked in this order is transported to the crimping device 80 using a transporter (not shown) or the like. As shown in FIG. 12, the semiconductor chip 10 is mounted on the substrate 22 by pressing the light-transmitting substrate 22 against the semiconductor chip 10 and applying heat using the crimping device 80 (connection process). Each of the pressure-bonding head 80a and the stage 80b of the pressure-bonding apparatus 80 has a built-in heater so that the surface temperature can be set to a desired temperature. The crimping head 80a is movable in the direction perpendicular to the surface of the stage 80b (in the direction of arrow V in FIG. 12).

  The temperatures of the pressure bonding head 80a and the stage 80b of the pressure bonding apparatus 80 are temperatures at which the insulating resin layer 3 is sufficiently cured in the connection step, and the temperature of the connection portion is a eutectic of the material of the protruding electrode 2 and the material of the electrode 22a. It is preferable to set so as to exceed the temperature. For example, when the protruding electrode 2 is formed by gold plating and the electrode 22a is formed by tin plating, it is preferable to heat the connection portion so as to exceed the eutectic temperature (278 ° C.) of gold and tin. For example, it is preferable to set the pressure-bonding head 80a to 50 to 150 ° C. and the stage 80b to 300 to 500 ° C. The heating time is preferably 0.1 to 10 seconds, more preferably 0.1 to 5 seconds.

  Through the connecting step, the protruding electrode 2 of the semiconductor chip 10 and the electrode 22a of the light-transmitting substrate 22 are electrically connected. Further, the semiconductor chip 10 and the substrate 22 are bonded by the cured product 3 a of the insulating resin layer 3 interposed between the semiconductor chip 10 and the substrate 22. Thereby, the semiconductor device 200 as shown in FIG. 13 is manufactured. Subsequently, in order to further advance the curing of the insulating resin layer 3, heat treatment may be performed using a heating oven or the like.

  According to the method for manufacturing a semiconductor device according to the second embodiment, the same effects as those obtained by the method for manufacturing a semiconductor device according to the first embodiment are exhibited.

  In the method for manufacturing a semiconductor device according to the second embodiment, it is preferable to supply the light-transmitting substrate 22 by a reel-to-reel method. That is, in the semiconductor device manufacturing method according to the second embodiment, the flexible substrate 22 is continuously connected to the temporary fixing device 70 and the crimping device 80 by the reel-to-reel method in the position adjustment process, the connection preparation process, and the connection process. Preferably. As described above, the semiconductor device 200 can be more efficiently manufactured by continuously performing position adjustment, temporary fixing, and connection between the semiconductor chip 10 and the substrate 22.

It is sectional drawing which shows the semiconductor wafer which has a protruding electrode. It is sectional drawing which shows the semiconductor wafer in which the insulating resin layer was formed on the circuit surface. It is sectional drawing which shows the state which mounted | wore the wafer ring with the semiconductor wafer. It is sectional drawing which shows the state which grinds the back surface of a semiconductor wafer. It is sectional drawing which shows the state which is dicing the semiconductor wafer. It is sectional drawing which shows the state which is adjusting the position of a semiconductor chip and a board | substrate. It is sectional drawing which shows the state which is temporarily fixing a semiconductor chip and a board | substrate. It is sectional drawing which shows the state which has connected the semiconductor chip and the board | substrate. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the state which is adjusting the position of a semiconductor chip and a transparent substrate. It is sectional drawing which shows the state which is temporarily fixing a semiconductor chip and a transparent substrate. It is sectional drawing which shows the state which has connected the semiconductor chip and the transparent substrate. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Projection electrode, 3 ... Insulating resin layer, 4 ... Wafer ring, 5 ... Dicing tape, 10 ... Semiconductor chip, 12 ... Infrared camera, 13 ... Visible light camera, 14, 22 ... Substrate , 14a, 22a ... electrode, 30 ... grinding device, 40 ... dicing device, 50, 70 ... temporary fixing device, 60, 80 ... crimping device, 100, 200 ... semiconductor device, S1 ... circuit surface (one surface of semiconductor wafer 1) ), S2... Back surface (the other surface of the semiconductor wafer 1).

Claims (7)

A covering step of forming an insulating resin layer on the one surface so as to embed a plurality of protruding electrodes formed on one surface of the semiconductor wafer;
A wafer ring mounting step of bonding the surface of the insulating resin layer and a dicing tape, and fixing the semiconductor wafer to a wafer ring via the dicing tape,
After the wafer ring mounting step, a back grinding step of grinding the semiconductor wafer from the other side of the semiconductor wafer;
After the back grinding step, a dicing preparation step of fixing the semiconductor wafer with the wafer ring mounted thereon on a stage of a dicing apparatus via the insulating resin layer and the dicing tape;
Cutting the semiconductor wafer from the other surface side of the semiconductor wafer together with the insulating resin layer, having a protruding electrode on one surface, and covering the one surface with the cut insulating resin layer; A dicing step to obtain;
A semiconductor wafer dicing method comprising:   The dicing method for a semiconductor wafer according to claim 1, wherein in the dicing step, a dicing pattern formed on the one surface of the semiconductor wafer is recognized by an infrared camera from the other surface side of the semiconductor wafer.   The semiconductor wafer dicing method according to claim 1, wherein in the covering step, the insulating resin layer is formed by bonding a film made of an insulating resin composition onto one surface of the semiconductor wafer.   The semiconductor wafer dicing method according to claim 1, wherein the insulating resin layer has a visible light transmittance of 10% or more.   The said insulating resin layer is a dicing method of the semiconductor wafer as described in any one of Claims 1-4 which consists of an insulating resin composition which does not produce a resin foam even if it connects at the temperature of 300 degreeC or more.   The said insulating resin layer is a dicing method of the semiconductor wafer as described in any one of Claims 1-5 containing a polyimide resin, an epoxy resin, and a hardening | curing agent. A pickup step of picking up the semiconductor chip obtained by the semiconductor wafer dicing method according to any one of claims 1 to 6 together with the cut insulating resin layer;
An electrode provided on a surface of the substrate while holding the semiconductor chip with the cut insulating resin layer side facing the substrate on which the semiconductor chip is to be mounted; and the protruding electrode of the semiconductor chip; A position adjustment process for adjusting the position of
After the position adjustment step, a connection preparation step of temporarily fixing the semiconductor chip on the substrate;
A connecting step of mounting the semiconductor chip on the substrate by pressing the semiconductor chip against the substrate and applying heat;
A method for manufacturing a semiconductor device comprising:

Images