JP2009260856A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an error-diffused image from being considerably varied when error-diffusing low-order bits by inputting a uniform image or a smoothly varying image. <P>SOLUTION: An image processor comprises: a round-down circuit 113 that outputs a value of high-order bits resulting from rounding down the predetermined number of low-order bits of input pixel data; an integration circuit 111 that outputs a carry bit when a carry occurs by integrating the values of the predetermined number of low-order bits that are rounded down; and an addition circuit 112 that adds the carry bit to the value of the high-order bits to produce output pixel data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that converts the number of gradations of input image data into a smaller number of gradations.

  The technology that takes digitized RGB color signals as input, and transmits and displays them can separate the physical properties of the input / output devices from the image communication and correction algorithms. Widely used regardless of wireless or wired. In recent years, with the increase in the size of the display screen and the sophistication of photographing devices, it has been considered that a standard in which the gradation accuracy of RGB signals is increased from 8 bits to 10 bits is used in broadcasting and data communication.

  However, a display such as a liquid crystal display (LCD) or a plasma display (PDP) has a limit that can display a digitized color signal as an effective one depending on each physical property. Bit gradation cannot be expressed as it is.

  The accuracy of gradation that can be expressed by an LCD depends on the control of an AD converter that controls the continuous orientation of liquid crystal molecules. In PDP, gradation is expressed by light emission and non-light emission of the phosphor on the display surface, so that the number of gradations that can be displayed is smaller than that of LCD. Therefore, techniques have been developed to increase the gray scales that can be expressed in a pseudo manner using a technique called an error diffusion method and a technique called a dither method.

  The error diffusion method is to add the lower bit value (error) rounded down from a certain pixel to the adjacent pixel (diffusion) when expressing the color of the pixel expressed by a certain number of bits with a smaller number of bits. By doing so, it is a technique for preventing deterioration of the image quality of the entire screen. Usually, the pixels constituting the two-dimensional image are input from the upper side to the lower side, from the left side to the right side, and output after the error diffusion process, so that the diffusion of the truncation error has not been determined. Will be made against. As an example, Floyd-Steinberg method for diffusing an error to one adjacent pixel (Patent Document 1), Jarvis method, Stucki method for diffusing an error to two adjacent pixels, and the like are known.

  In the Floyd-Steinberg method, for example, the values (errors) of lower bits that are rounded down from the adjacent pixels A, B, and C of the previous line (upper line) and the previous pixel D (left side) of the same line. Is added to the subsequent pixel X at a constant rate (FIG. 7). In the added pixel X, the higher-order bit of the value is output, and the lower-order bit rounded down of the pixel X is added to the subsequent pixel (FIG. 8).

  The dither method is a method of selecting the round-up or truncation of the gradation value of each pixel according to the position of each pixel in the entire image. A general method is to divide the entire image into a predetermined dither table size, and round up when the value of the lower bit of each pixel is larger than the value of the corresponding part of the table, and round down when the value is smaller. Furthermore, for a moving image such as a television, the dither table to be applied for each frame is rotated, thereby rounding up time and distributing rounding errors.

  In addition, in order to reduce the increase in power consumption due to the implementation of such a method of increasing the gradation in a pseudo manner, the process of increasing the gradation only when it is detected that the luminance of the input video signal changes gently. Has also been proposed (Patent Document 2).

  FIG. 9 is a diagram showing a configuration of an error diffusion circuit 400 for realizing the error diffusion method described in FIG. 7 with a circuit. 401 to 403 are registers that hold the values of the lower bits of the pixels A, B, and C read from the line memory 200, 404 is a register that holds all the bits of the pixel D immediately before the current line, and 405 is the current pixel. This register holds all the bits of X. Reference numerals 411 to 414 denote multipliers 421 to 424 that multiply the lower bits of the pixels A, B, C, and D by 1 times, 5 times, 3 times, and 7 times to 1/16 (shift them by 4 bits toward the lower bits). Is an adder, and 431 is a lower bit truncation circuit that truncates the lower bits and outputs only the upper bits.

Thus, in order to hold the pixel value of the previous line, the line memory 200 for at least one line is required. This corresponds to a storage capacity of 1920 pixels × 10 bits × 3 colors = about 9 kB in the HDTV standard image, which is a very large scale. Therefore, as shown in FIG. 10, there is a case in which a technique for saving the circuit scale is used by sharing the line memory 200 with another image processing circuit 300 such as a noise removal processing circuit.
JP-A-10-210291 Japanese Patent Laid-Open No. 11-327497

  However, when the method of sharing the line memory 200 as shown in FIG. 10 is used, there is a problem that an accurate error diffusion method cannot be realized. The output value of each RGB color corresponding to the pixel X in FIG. 7 is a value obtained by adding the lower bits of the left and upper pixels A, B, C, and D to the value and truncating the lower bits from that value. A part of the value of the truncated lower bits is diffused to the next (right side) pixel of the same line, while the other part is diffused to the pixel of the next line. In the circuit of FIG. 9, the value of the lower bit diffused to the next line is written into the line memory 200. That is, the value of the input pixel X is not written as it is in the line memory 200, but a value obtained by adding an error to be diffused to the pixels of the next line is written.

  However, when the line memory 200 is shared with other image processing circuits 300 as shown in FIG. 10, the stored contents must not be changed. For this reason, the value of the pixel X including an error cannot be written in the storage area. As a result, it has a serious effect on a uniform image or a slowly changing image.

  As an example, let us consider a case where an 8-bit video signal that changes gradually as shown in FIG. 11 is to be reproduced with 5 bits. For the sake of simplicity, the case of one dimension (difference of error to the right pixel) is considered, but the same applies to the case of a two-dimensional image. The value of the lower half bits a to i in the left half is “3”, and the value of the lower 3 bits in the right half of the pixels j to q is “4”.

  In this case, since the error “3” of the lower 3 bits of the pixel a is added to the pixel b, the addition error becomes “6”, but does not reach “8”, and no carry occurs for the upper 5 bits. At this time, the lower 3 bits are truncated by the lower bit truncation circuit 431. This situation is the same for pixels a to i. In the pixel j, its own error “4” is added to the error “3” of the pixel i on the left side to become “7”, but similarly, it does not reach “8”, and no carry is generated for the upper 5 bits.

  However, in the pixels k to q, the error “4” is added to the error “4” of the pixel on the left side, so that the error is “8”, and the upper bit is “1” in each pixel k to q. It moves up one by one. Therefore, the upper 5 bits of the pixel output from the lower bit truncation circuit 431 are advanced by “1” near the boundary between the pixel with the error “3” and the pixel with the error “4”. After that, “1” is sequentially incremented for each pixel, and the change becomes severe, and it becomes easy to notice.

  An object of the present invention is to provide an image processing apparatus that outputs a natural image without causing a large change in an error-diffused image even in the case of a uniform image or a slowly changing image as described above. Is to provide.

In order to achieve the above object, an image processing apparatus according to a first aspect of the present invention provides a predetermined number of bits representing pixel values of pixels arranged in each line of an input image composed of a plurality of lines. Is converted to output pixel data having a number of bits smaller than the predetermined number of bits, and the pixel values of a plurality of pixels arranged in one line are output. A cut-out circuit for receiving input pixel data representing the order of arrangement in the line, and outputting a value of upper bits obtained by truncating a predetermined number of lower bits; A first error is made up of an integration circuit that integrates and outputs a carry bit when a carry occurs, and an adder circuit that adds the carry bit to the value of the upper bit to generate the output pixel data. Characterized in that it comprises a spreading circuit.
According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the integration circuit is configured to calculate a value of a lower bit of input pixel data representing pixel values of a plurality of pixels arranged in the one line. Following the integration, one or more predetermined values are added, and then the lower-order bit values of the input pixel data representing the pixel values of a plurality of pixels arranged in the next line are integrated. .
According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, the uniform determination circuit that outputs a detection signal when detecting that the pixel value of the input image changes gently, and A second error diffusion circuit for generating the output pixel data by performing processing different from that of the first error diffusion circuit, and the first error diffusion when the uniform determination circuit outputs a detection signal. The output pixel data generated by the circuit is output, and at other times, the output pixel data generated by the second error diffusion circuit is output.
According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, a line memory capable of storing input pixel data for one line, and an input pixel representing a pixel value of a pixel arranged in the first line Another image processing circuit that receives input of data, performs processing on the input pixel data to generate processed input pixel data, and writes the input pixel data to the line memory, and the second error diffusion circuit includes the second error diffusion circuit, The input pixel data representing the pixel value of the pixel arranged in the first line is received, and the pixel value of the pixel arranged in the line immediately before the first line already written in the line memory is inputted. The processed input pixel data to be represented is read out, and output pixel data representing the pixel values of the pixels arranged in the first line is generated.

  According to the present invention, it is possible to realize natural reproducibility for a uniform image or a slowly changing image with a small-scale circuit while maintaining the advantage of saving the circuit scale by sharing one line memory. it can.

  In the present invention, it is determined whether or not the input image is a partially uniform image or a slowly changing image, and the error diffusion method is switched between the error accumulation method and the regular error diffusion method. .

  A conventional Floyd-Steinberg method or the like is used as an error diffusion method in the case where it is determined that it is not uniform. However, the line memory necessary for diffusion of the cut-off error in the vertical direction of the image is shared with other functional parts, and the calculated cumulative error is not recorded there. That is, only reading is performed. On the other hand, the uniform error diffusion method is used as the error diffusion method when it is determined that the pattern is uniform. This is provided with a counter for accumulating the value of the lower bit as the error part, and every time the value exceeds the round-down range, the pixel value is rounded up and rounded down regularly, and rounded-up pixels are arranged.

  All the steps caused by the conventional error diffusion method have not been eliminated, but are only dispersed. Therefore, in order to maintain the uniform and smooth appearance of the image, it is placed after the error diffusion processing unit. A dither processing portion may be provided. In that case, the rotation angle of the dither table is changed for each place so that the period does not match the regular error diffusion processing part.

<Example>
FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to an embodiment of the present invention. The image post-processing device 100 receives input pixel data having a predetermined number of bits representing pixel values (tone values of each color, color difference values, etc.) of pixels arranged in each line. Output pixel data having a smaller number of bits is output. Specifically, for example, input pixel data having a luminance value of 10 bits for each color of RGB is input, and output pixel data having a luminance value of 6 bits for each color of RGB is output.

  An image processing apparatus 100 shown in FIG. 1 receives first 10-bit RGB image data, performs uniform error diffusion, and outputs 7-bit RGB image data. The first error diffusion circuit 110 outputs 10-bit RGB data. A second error diffusion circuit 120 that inputs image data and performs error diffusion by the Floyd-Steinberg method and outputs 7-bit RGB image data. The input image data is a uniform image or an image that changes gradually. Uniformity determination circuit 130 for determining whether or not the output data of first error diffusion circuit 110 and output image data of second error diffusion circuit 120 are selected according to the determination result of uniformity determination circuit 130 The selector 140 and the 7-bit RGB output image data of the selector 140 are subjected to dither processing and each 6-bit RGB image data Comprising a dither processing circuit 15 to be output. Reference numeral 200 denotes a line memory, which supplies pixel values for one line of an input image to the second error diffusion circuit 120 and is used for processing in another image processing circuit 300.

  In the example shown in FIG. 1, input pixel data is written in the line memory 200 as it is. Then, another image processing circuit 300 reads the input pixel data from the line memory 200, performs various processes, and writes the processed input pixel data to the line memory 200. The second error diffusion circuit 120 reads out the processed input pixel data in order to perform error diffusion from the pixels of the previous line. As another image processing circuit 300, for example, a noise reduction processing circuit can be provided.

  A configuration example of the first error diffusion circuit 110 is shown in FIG. Since the circuits for RGB are the same, the case of one color image data will be described as a representative. The first error diffusion circuit 110 includes a counter 111, an adder 112, and a truncation circuit 113 that outputs the upper 7 bits from the input 10 bits and truncates the lower 3 bits. The counter 111 includes a register 111A and an adder 111B. The counter 111 accumulates the lower 3 bits of the input image data, and when the count value reaches “8”, it overflows and generates a carry bit. The adder 112 adds “1” to the value of the upper 7 bits. The upper 7 bits are incremented by “1”.

  FIG. 3 is an explanatory diagram in one dimension when the slowly changing line images a to q are input to the first error diffusion circuit 110 and processed. It is assumed that the lower 3 bits of the pixels a to i are “3”, and the lower 3 bits of the pixels j to q are “4”.

  If the lower 3 bits of the pixels a to c are added, it becomes “9” (= 3 + 3 + 3) at the time of the pixel c, and therefore the value of the upper 7 bits of the pixel c is incremented by “1” due to overflow. The value of the counter 111 is “1”.

  Further, if the lower 3 bits of the pixels d to f are added, it becomes “10” (= 1 + 3 + 3 + 3) at the time of the pixel f. At this time, the value of the upper 7 bits of the pixel f is incremented by “1” due to the overflow. . The value of the counter 111 is “2”.

  Further, if the lower 3 bits of the pixels g to h are added, it becomes “8” (= 2 + 3 + 3) at the time of the pixel f. At this time, the value of the upper 7 bits of the pixel h is incremented by “1” due to overflow. . The value of the counter 111 is “0”.

  Further, when the lower 3 bits of the pixels i to k are added, it becomes “11” (= 0 + 3 + 4 + 4) at the time of the pixel k. At this time, the value of the upper 7 bits of the pixel k is incremented by “1” due to overflow. . The value of the counter 111 is “3”.

  Similarly, in the case of a uniform image in which the value of the lower 3 bits is continuous at “3”, changes to “4” in the middle, and continues at “4”, 1 pixel every 2 to 4 pixels This is an image change in which “1” is added to the upper 7 bits. As a result, when the image is completely uniform, rounded-up pixels are regularly arranged, so that the gradation is kept constant throughout the image, and the uniform appearance is seen from a distance. Can keep.

  FIG. 4 is an explanatory diagram in the case of a two-dimensional uniform image. The white square part has a lower 3 bit error value of “3”, and the halftone dot square part has the same error value of “4”. The numerical value is the value of the counter 111 at the pixel. In the example of FIG. 4, the value of the counter 111 at the time when the error accumulation up to the last pixel of one line (the rightmost pixel in FIG. 4) is completed is kept as it is, and the first of the next line is maintained. The error of the image (the leftmost pixel in the figure) and the subsequent image error are integrated. In the pixel region where the error is “3”, the upper 7 bits are incremented by “1” for the pixels of the counter 111 whose values are “0”, “1”, “2”, and “3”. In the pixel area where the error is “4”, the upper 7 bits are incremented by “1” in the pixels where the value of the counter 111 is “0”, “1”, and “2”.

  By the way, as shown in FIG. 5, when the number of pixels in one line is a multiple of 8 (1 in FIG. 5), the values of the counters 111 are arranged in the same vertical value, and the upper 7 bits are repeated by “1”. The rising pixels are arranged vertically. In the white square part whose lower 3 bits are “3”, the square part of the halftone dot whose count values are “0”, “1”, “2”, “3” are vertically arranged, and whose lower 4 bits are “3”. In this case, the count value “0” is moved up vertically, and vertical stripes appear there, causing image degradation.

  Therefore, when the number of pixels in one line is a multiple of 8, as shown in FIG. 6, a predetermined value (“3” or “4” in the example of FIG. That is, the lower 3 bits (error) of the last pixel of the line are added. In this case, the predetermined value may be added to the counter 111 described in FIG. 2 for each timing of the last pixel in the line. As a result, it is possible to avoid pixels in which the upper 7 bits are moved up by “1” vertically.

  In the above example, the case where only error diffusion in one line is performed has been described. However, as shown in FIG. 7, it is also possible to perform error diffusion from the pixels on the previous line together. Specifically, for example, as shown in FIG. 10, the values of the lower bits of the pixels A, B, and C in the previous line are read into the registers 401, 402, and 403, and multiplied by an appropriate coefficient. The added value can be supplied to the first error diffusion circuit 110 in FIG. 2 as an error diffused from the pixel on the previous line. Then, in the first error diffusion circuit 110 of FIG. 2, the value output from the register 111A is multiplied by an appropriate coefficient, and added to the error diffused from the pixel on the previous line, and then added. It is possible to supply to the vessel 111B.

  The second error diffusion circuit 120 has the same configuration as the error diffusion circuit 400 described with reference to the Floyd-Steinberg method in FIG. 10, and a truncation error at each pixel is set to a constant ratio to the right and lower pixels of the pixel. Disperse with. However, a new pixel value obtained by adding an error from another pixel is not written back to the line memory 200 shared with the other image processing circuit 300.

  The uniformity determination circuit 130 determines whether the image is a uniform image or an image that changes gradually using the input RGB image data. As the uniform determination circuit 130, for example, a difference between an average value of, for example, two pixels in front of the pixel and an average value of two pixels in the rear is taken, and the difference between the average values falls within a predetermined threshold range. If there is, it can be determined that there is uniformity, and if not, a circuit that operates to determine that there is no uniformity can be used. As an example of this, for example, there is one that detects only in the horizontal direction described in Patent Document 2 (FIG. 3), but in addition, one that detects in the horizontal and vertical directions (FIG. 5). A thing by movement (FIG. 12) etc. can also be used.

It is a block diagram which shows the structure of the image processing apparatus of the Example of this invention. FIG. 2 is a block diagram showing a configuration of a first error diffusion circuit constituting the image processing apparatus of FIG. 1. FIG. 3 is an operation explanatory diagram of the first error diffusion circuit of FIG. 2. FIG. 3 is a map diagram of count values of a counter at each pixel of a two-dimensional image when the first error diffusion circuit of FIG. 2 is used. FIG. 3 is a map diagram of the count value of the counter at each pixel when one line of pixels of the two-dimensional image when the first error diffusion circuit of FIG. 2 is used is an integer multiple of 8; It is the map figure which improved the fault of FIG. It is explanatory drawing of an error diffusion method. It is explanatory drawing of an error diffusion method. It is a block diagram which shows the structure of the conventional error diffusion circuit. It is a block diagram which shows the structure of another conventional error diffusion circuit. It is explanatory drawing of error diffusion when a uniformity image is input.

Explanation of symbols

100: Image processing device 110: First error diffusion circuit, 111: Counter, 111A: Register, 111B, 112: Adder, 113: Truncation circuit 120: Second error diffusion circuit 130: Uniformity determination circuit 140: Selector 150: Dither processing circuit 200: Line memory 300: Other image processing circuit 400: Error diffusion circuit, 401-405: Register, 411-414: Multiplier, 421-424: Adder, 431: Lower bit truncation circuit

Claims (4)

Input pixel data having a predetermined number of bits representing pixel values of pixels arranged in each line of an input image composed of a plurality of lines, an output having a number of bits smaller than the predetermined number of bits An image processing apparatus that converts to pixel data and outputs the data,
The input pixel data representing the pixel values of a plurality of pixels arranged in one line is received in the order of arrangement in the line, and a high-order bit value obtained by discarding a predetermined number of low-order bits is output. Discard circuit,
An integration circuit that integrates the values of the predetermined number of lower bits rounded down and outputs a carry bit when a carry occurs;
An image processing apparatus comprising: a first error diffusion circuit including an addition circuit that adds the carry bit to the value of the upper bit to generate the output pixel data.   The integration circuit adds one or more predetermined values following the integration of lower bit values of input pixel data representing pixel values of a plurality of pixels arranged in the one line, and then The image processing apparatus according to claim 1, wherein values of lower bits of input pixel data representing pixel values of a plurality of pixels arranged in a line are integrated. A uniform determination circuit that outputs a detection signal when it is detected that the pixel value of the input image changes gently;
A second error diffusion circuit that performs processing different from that of the first error diffusion circuit to generate the output pixel data;
Output pixel data generated by the first error diffusion circuit when the uniform determination circuit outputs a detection signal, and output pixel data generated by the second error diffusion circuit at other times. The image processing apparatus according to claim 1, wherein the image processing apparatus outputs the image. A line memory capable of storing input pixel data for one line;
Other image processing that receives input pixel data representing pixel values of pixels arranged on the first line, performs processing on the input pixel data to generate processed input pixel data, and writes the input pixel data to the line memory And further including a circuit,
The second error diffusion circuit receives input pixel data representing pixel values of pixels arranged in the first line and immediately before the first line already written in the line memory. 4. The processed input pixel data representing a pixel value of a pixel arranged in a line is read, and output pixel data representing a pixel value of a pixel arranged in the first line is generated. Image processing apparatus.

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