JP2009267739A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce distortion that a composite image has owing to fast movement of a subject when the images having a wide dynamic range imaged by performing exposures a plurality of times are subjected to the composition. <P>SOLUTION: A timing generator 50 and a vertical scanning circuit 60 as a driving control means generate two long-time exposures L1 and L2 before and after a short-time exposure S and a very-short-time exposure V to expose respective pixels of a pixel matrix portion 10A for a plurality of kinds of exposure periods in order. An image processing portion 70 acquires pixel signals of exposure results of the respective exposure periods read out of the pixel matrix portion 10A, and composits image data with a wide dynamic range of L image data obtained by averaging exposure results of the two long-time exposures L1 and L2, and S image data as a result of the short-time exposure S and V image data as a result of the very-short-time exposure V. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that extracts and outputs an electrical signal corresponding to the amount of received light from a plurality of pixels arranged in a matrix, and particularly has a function of synthesizing image data having a wide dynamic range by a plurality of exposures. The present invention relates to a solid-state imaging device including

  As is well known, in a solid-state imaging device such as a CMOS solid-state imaging device, each pixel forming a matrix is sequentially driven, and a pixel signal is read from each pixel. In the most basic configuration, the operation of reading out pixel signals from all pixels is repeated every frame (vertical scanning period) having a fixed time length. In such a configuration, focusing on one pixel, one frame, which is a period from the previous pixel signal readout to the current pixel signal readout, is the exposure time, and the signal value of the pixel signal read this time is within the exposure period. This reflects the amount of light received by the pixel.

  When the exposure time is changed long and short, the gradient of the signal value of the pixel signal with respect to the exposure time increases depending on the intensity of light received by the pixel (= illuminance of the subject). Therefore, it is preferable to adjust the exposure time according to the illuminance of the subject, such as shortening the exposure time when the subject is bright and increasing the exposure time when the subject is dark. However, when the illuminance range of the subject is wide, it is difficult to obtain an image signal that accurately represents the brightness of each part of the subject by imaging with one type of exposure time. Therefore, a technique for performing multiple exposures with different exposure times and synthesizing image data with a wide dynamic range using a plurality of types of image signals obtained by each exposure (hereinafter referred to as “multiple exposure” for the sake of convenience) has been proposed. Yes.

FIG. 8 shows an example of an imaging sequence by this multiple exposure technique. In this example, focusing on one pixel, a long exposure L, a short exposure S, and an extremely short exposure V are sequentially performed in one frame, and a pixel signal that is an exposure result of these three types of exposure periods is represented in a pixel matrix. Have gained from. Thus, by multiplying each pixel signal obtained in each exposure period by a gain proportional to the reciprocal of the length of each exposure period, for example, image data having a wide dynamic range is synthesized. be able to.
A technique for obtaining image data having a wide dynamic range by performing a plurality of exposures is disclosed in Patent Document 1, although it is for a CCD solid-state imaging device.
JP 2002-27328 A

  By the way, when multiple exposures as shown in FIG. 8 are performed, the difference between the imaging timing by the long exposure L and the imaging timings by the short exposure S and the extremely short exposure V becomes large, so that the subject is in the horizontal direction. However, there is a problem that distortion of an image to be synthesized increases when moving at high speed.

  Hereinafter, this problem will be described with reference to FIGS. 9 (a) and 9 (b). In this example, the subject has a circular shape, and its light and dark distribution is concentric, the central circular region is the brightest, the outer annular region is the second brightest, and the outermost region The toric region is the darkest.

  When a plurality of exposures shown in FIG. 8 are performed in a state where the subject is stationary, and the exposure results are combined, a composite image illustrated in FIG. 9A is obtained. In this composite image, the outer annular region is the darkest part that is included in an image obtained by long exposure L (hereinafter referred to as L image). In addition, the annular region inside the annular portion is a part that is slightly bright and included in an image obtained by the short-time exposure S (hereinafter referred to as S image). The central circular region is a very bright portion that is included in an image (hereinafter referred to as a V image) obtained by the short-time exposure S. In such a state where the subject is stationary, a composite image without distortion is obtained when imaging is performed by multiple exposures and the exposure results are combined.

  However, when the subject is moving at high speed and the subject is imaged by multiple exposures and the exposure results are combined, the combined image is greatly distorted in the moving direction of the subject. FIG. 9B illustrates a composite image obtained when the subject moves at high speed in the horizontal direction (arrow direction). When multiple exposures as shown in FIG. 8 are performed, the timing at which the S image is taken by the short exposure S is greatly delayed from the timing at which the L image is taken by the long exposure L, and the V image is obtained by the extremely short exposure V. The timing to be taken is further delayed. For this reason, in the composite image, the S image moves to a position shifted in the moving direction of the subject (in this example, the direction from left to right) than the L image, and the V image further moves in the moving direction of the subject. There is a problem that the composite image is greatly distorted with respect to the subject by moving to a shifted position.

  The present invention has been made in view of the circumstances described above, and in the case of compositing an image having a wide dynamic range by performing imaging with multiple exposures, distortion generated in the composite image when the subject moves at high speed. An object of the present invention is to provide a solid-state imaging device that can be reduced.

  According to the present invention, a pixel matrix portion formed by arranging a plurality of pixels in a matrix and two long exposure periods before and after a short exposure period are generated, and a plurality of pixels are provided for each pixel of the pixel matrix portion. Drive control means for sequentially performing exposures of different types of exposure periods and reading out pixel signals that are exposure results of each exposure period, and pixel signals that are exposure results of each exposure period read from the pixel matrix unit Obtained and image data from a combined value of each pixel signal that is an exposure result of two long exposure periods and a pixel signal that is an exposure result of a short exposure period between the two long exposure periods And a solid-state imaging device.

  According to this invention, long-time exposure is performed before and after short-time exposure, and a composite value of pixel signals that are the exposure results of these two long-time exposures, and pixels that are the exposure results of short-time exposure between them. A wide dynamic range image signal is synthesized from the signal. Accordingly, the difference between the imaging timing due to the long exposure and the imaging timing due to the short exposure is reduced, and distortion generated in the composite image when the subject moves at high speed can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a CMOS solid-state imaging device according to an embodiment of the present invention. In this CMOS solid-state imaging device, the pixel matrix unit 10A is formed by arranging the pixels 10 in a matrix.

  FIG. 2 shows a configuration example of one pixel 10 in the pixel matrix unit 10A. As shown in FIG. 2, one pixel 10 includes a PD (Photo Diode) 101, a transfer transistor 102 that is a MOS transistor, a reset transistor 103, an amplification transistor 104, and a row selection transistor 105. It is comprised by. Each of these elements is formed on a p-type semiconductor substrate. In FIG. 2, the cross-sectional structure of the PD 101, the transfer transistor 102, and the reset transistor 103 is illustrated, and the amplification transistor 104 and the row selection transistor 105 are illustrated using circuit symbols.

  In FIG. 2, a PD 101 is a photoelectric conversion element that is formed by forming a buried layer of low-concentration n-type impurities on a p-type semiconductor substrate and generates a signal charge corresponding to the amount of received light. The transfer transistor 102 has a source connected to the PD 101 and a drain FD (Floating Diffusion) 102d. The transfer transistor 102 transfers the signal charge accumulated in the PD 101 to the FD 102d when a transfer pulse TXi is applied to the gate. The reset transistor 103 has a source connected to the power supply VDD and a drain FD102d. The reset transistor 103 resets the FD 102d to the potential of the power supply VDD when a reset pulse RTi is given to the gate. The amplification transistor 104 has a drain connected to the power supply VDD and a gate connected to the FD 102d. The row selection transistor 105 is interposed between the source of the amplification transistor 104 and the column signal line 11, and a row selection pulse SLi is given to the gate. These amplifying transistor 104 and row selection transistor 105 serve as a readout circuit that reads out a voltage corresponding to the electric charge accumulated in FD 102d to column signal line 11 when row selection pulse SLi is applied.

  As shown in FIG. 1, a plurality of pixels 10 having the same configuration are connected to the column signal line 11, and a constant current source serving as a load for the amplification transistor 104 of each pixel 10 is connected (not shown). . Further, a CDS (Correlated Double Sampling) circuit is connected to each column signal line 11. The column CDS unit 20 in FIG. 1 is an aggregate of CDS circuits provided for each column signal line 11. Each CDS circuit samples a voltage read to each column signal line 11 of the pixel matrix unit 10A at each timing when the sampling pulses φr and φs are supplied from the timing generator 50, detects a difference, and outputs an analog pixel signal respectively. Output. The column ADC unit 30 is an aggregate of ADCs (Analog to Digital Converters) provided for each column of the pixels 10 in the pixel matrix unit 10A. Each ADC converts an analog pixel signal output from each CDS circuit into a digital pixel signal under the control of the timing generator 50. The horizontal scanning circuit 40 is a shift register having the same number of stages as the number of columns of the pixel matrix unit 10A. Under the control of the timing generator 50, the horizontal scanning circuit 40 repeats the operation of taking in one row of digital pixel signals output from the column ADC unit 30 and transferring them serially to the image processing unit 70 for each horizontal scanning period.

  The vertical scanning circuit 60 controls the row selection pulse SLi (i = 1 to n), the reset pulse RTi (i = 1 to n), and the transfer pulse TXi (i = i =) for each row of the pixel matrix unit 10A under the control of the timing generator 50. 1 to n). The timing generator 50 is a circuit that generates signals for timing control of each part of the CMOS solid-state imaging device, such as the vertical scanning circuit 60, the column CDS unit 20, the column ADC unit 30, and the horizontal scanning circuit 40. In the present embodiment, the timing generator 50 and the vertical scanning circuit 60 sequentially select each row of the pixel matrix unit 10A for each horizontal scanning period, and output a row selection pulse SLi to each pixel 10 in the selected i-th row. At the same time, the reset pulse RTi and the transfer pulse TXi are sequentially output and function as drive control means for outputting the sampling pulses φr and φs at the respective timings before and after the transfer pulse TXi. Further, in the present embodiment, the timing generator 50 and the vertical scanning circuit 60 as the drive control means generate two long exposure periods before and after the short exposure period, and each of the pixel matrix unit 10A. The pixel 10 is caused to sequentially perform exposures of a plurality of types of exposure periods, and to read out pixel signals that are exposure results of the exposure periods. The specific configuration will be described later.

  The image processing unit 70 is a device that processes digital pixel signals supplied via the horizontal scanning circuit 40 and synthesizes image data for one screen for each frame. In the present embodiment, exposure is performed a plurality of times within one frame period, and a plurality of types of digital pixel signals having different exposure periods are obtained for each pixel. The image processing unit 70 synthesizes image data having a wide dynamic range using each digital pixel signal obtained in different exposure periods. The image data synthesized by the image processing unit 70 is displayed on a monitor (not shown) or recorded on a recording medium such as an HD (hard disk) (not shown).

  The U / I (user interface) unit 80 includes a display device such as a liquid crystal display panel and various operators such as push buttons. The U / I unit 80 displays various guidance information related to the operation of the CMOS solid-state imaging device, and plays a role of acquiring various information related to imaging conditions and the like from the user via the operation element. The control unit 90 is a device that controls each unit of the CMOS solid-state imaging device in accordance with an instruction from the user acquired via the U / I unit 80.

  FIG. 3 is a block diagram showing specific configurations of the timing generator 50 and the vertical scanning circuit 60. As shown in FIG. 3, the timing generator 50 includes a clock counter 52, a line counter 53, a pulse generator 55, and an enable pulse generator 56.

  The clock counter 52 and the line counter 53 perform a frame switching control and a horizontal scanning period switching control within the frame, and manage information indicating the current time. In the present embodiment, the frame is divided into m horizontal scanning periods that are larger than the number n of rows of the pixel matrix unit 10A. Each horizontal scanning period constituting one frame is specified by line numbers from No. 1 to No. m. Each horizontal scanning period has a time length in which an analog pixel signal for one row is read from the pixel matrix unit 10 </ b> A, digitized, and serially transferred to the image processing unit 70.

  In the present embodiment, the time of one horizontal scanning period is counted by counting clocks having a constant frequency. The clock counter 52 in FIG. 3 performs this clock counting. The count value of the clock counter 52 is used as information indicating the relative time within the horizontal scanning period.

  The clock counter 52 outputs the line clock φH every time it finishes counting the clocks for one horizontal scanning period. The line counter 53 counts this line clock φH. The line counter 53 initializes the count value every time m line clocks φH are counted. Therefore, the count value of the line counter 53 always indicates the line number of the current horizontal scanning period.

  The pulse generator 55 is a circuit that generates a reset pulse RTG and a transfer pulse TXG that are the basis of the reset pulse RTi and the transfer pulse TXi supplied to each row of the pixel matrix unit 10A. In addition to the reset pulse and the transfer pulse, the pulse generator 55 supplies sampling pulses φr and φs for causing the column CDS unit 20 to perform correlated double sampling, and the column ADC unit 30 applies A to the sampling pulse φr and φs. A sampling pulse for performing / D conversion and a shift clock for causing the horizontal scanning circuit 40 to perform serial transfer are generated. The control unit 90 gives information specifying the count value of the clock counter 52 corresponding to the timing of the rising edge and the falling edge of each pulse and the generation start timing of the shift clock to the pulse generator 55. The pulse generator 55 At the timing indicated by this information, each pulse is raised or lowered, or generation of a shift clock is started.

  The enable pulse generator 56 generates two types of enable pulses ENa and ENb having a pulse width for one horizontal scanning period. The enable pulse ENa is a pulse for instructing reading of a pixel signal. The enable pulse ENb is a pulse for instructing erasure of the accumulated charge in the PD 101 of the pixel 10. The control unit 90 instructs each line number of each horizontal scanning period for generating the enable pulses ENa and ENb in the frame to the enable pulse generator 56, and the enable pulse generator 56 Enable pulses ENa and ENb are generated in each numbered horizontal scanning period.

  The vertical scanning circuit 60 includes shift registers 61 and 62 each having the same number of stages as the number n of rows of the pixel matrix unit 10A, and AND-OR gates 63 and 64 provided for each row of the pixel matrix unit 10A. . The line clock φH output from the clock counter 52 of the timing generator 50 is applied to the clock terminals of the flip-flops forming the stages of the shift registers 61 and 62. The enable pulse ENa output from the enable pulse generator 56 is output to the first data input terminal of the shift register 61, and the enable pulse ENb output from the enable pulse generator 56 is output to the first data input terminal of the shift register 62. Given. The shift register 61 sequentially shifts the enable pulse ENa to the subsequent stage by the line clock φH, and the shift register 62 sequentially shifts the enable pulse ENb to the subsequent stage by the line clock φH.

  Each stage i of the shift register 61 supplies the enable pulse ENa coming from the previous stage to the AND-OR gates 63 and 64 corresponding to the i-th row of the pixel matrix unit 10A as the enable pulse ENai. The enable pulse ENai is supplied to the AND-OR gates 63 and 64, and is also supplied as a row selection pulse SLi to each pixel 10 in the i-th row of the pixel matrix unit 10A. Each stage i of the shift register 62 supplies the enable pulse ENb coming from the previous stage to the AND-OR gates 63 and 64 corresponding to the i-th row of the pixel matrix unit 10A as the enable pulse ENbi.

  The AND-OR gate 63 corresponding to the i-th row of the pixel matrix unit 10A calculates the logical product of the enable pulse ENai and the reset pulse RTG and the logical product of the enable pulse ENbi and the reset pulse RTG, Is output as a reset pulse RTi. The AND-OR gate 64 corresponding to the i-th row of the pixel matrix unit 10A obtains a logical product of the enable pulse ENai and the transfer pulse TXG and a logical product of the enable pulse ENbi and the transfer pulse TXG, and performs a logical sum of both logical products. Is output as a transfer pulse TXi.

  While the enable pulse ENai is generated, the AND-OR gate 63 corresponding to the i-th row of the pixel matrix unit 10A selects the reset pulse RTG output from the pulse generator 55, and the AND-OR gate 64 transmits the transfer pulse TXG. Are supplied to the pixels 10 in the i-th row of the pixel matrix unit 10A as reset pulses RTi and transfer pulses TXi, respectively. The enable pulse ENai is supplied as a row selection pulse SLi to each pixel 10 in the i-th row of the pixel matrix unit 10A. Accordingly, in each pixel 10 in the i-th row of the pixel matrix unit 10A, the voltage of the FD 102d is read out to the column signal line 11, and the pixel signal is read out.

On the other hand, while the enable pulse ENbi is generated, the AND-OR gate 63 corresponding to the i-th row of the pixel matrix unit 10A selects the reset pulse RTG output from the pulse generator 55, and the AND-OR gate 64 performs the transfer. The pulse TXG is selected and supplied to each pixel 10 in the i-th row of the pixel matrix unit 10A as the reset pulse RTi and the transfer pulse TXi. In this case, the row selection pulse SLi is not supplied to each pixel 10 in the i-th row of the pixel matrix unit 10A. Therefore, in each pixel 10 in the i-th row of the pixel matrix portion 10A, the accumulated charge in the PD 101 is erased.
The above is the details of the configuration of the CMOS solid-state imaging device according to the present embodiment.

  Next, the operation of this embodiment will be described. When it is necessary to acquire an image signal having a wide dynamic range, in this embodiment, a plurality of exposures shown in FIG. 4A are performed for each frame. That is, paying attention to one pixel 10 in the pixel matrix portion 10A, in the present embodiment, the short exposure S and the extremely short exposure V are positioned at the center of the frame within one frame, and the same exposure time is set before and after that. The long exposures L1 and L2 are positioned, and these four types of exposure are sequentially performed.

  FIG. 4B illustrates a specific imaging sequence for performing such multiple exposure. In FIG. 4B, the stripes arranged in the vertical direction indicate a state of reading pixel signals and a state of erasing accumulated charges in each row of the pixel matrix portion 10A.

  More specifically, in each horizontal scanning period labeled R in FIG. 4B (hereinafter, horizontal scanning period R), as shown in FIG. 4C, the row selection pulse SLi is set to the active level. During this time, the reset pulse RTi and the transfer pulse TXi are sequentially generated, and the sampling clocks φr and φs are supplied to the column CDS unit 20 at each timing before and after the transfer pulse TXi, and the analog pixels in the i-th row of the pixel matrix unit 10A. A signal is read out. Further, although not shown, conversion of the analog pixel signal into a digital pixel signal by the column ADC unit 30 and serial transfer of the digital pixel signal to the image processing unit 70 by the horizontal scanning circuit 40 are performed.

  In each horizontal scanning period labeled r in FIG. 4B (hereinafter, horizontal scanning period r), as shown in FIG. 4D, the row selection pulse SLi is set to an inactive level and reset. A pulse RTi and a transfer pulse TXi are sequentially generated. During this horizontal scanning period, the pixel signal is not read, and only the charge accumulated in the PD 101 in each pixel 10 in the i-th row of the pixel matrix unit 10A is erased.

  Focusing on one row, in a certain frame, the generation timing of the transfer pulse TXi in the last horizontal scanning period R of the immediately preceding frame is the start point of the long exposure L1, and the transfer pulse TXi in the subsequent horizontal scanning period R. Is the end point of the long-time exposure L1. The generation timing of the transfer pulse TXi in the horizontal scanning period r after the long exposure L1 is the start point of the short exposure S, and the generation timing of the transfer pulse TXi in the subsequent horizontal scanning period R is the short exposure. This is the end point of S. Further, the generation timing of the transfer pulse TXi in the horizontal scanning period r after the short exposure S is the start point of the extremely short exposure V, and the generation timing of the transfer pulse TXi in the horizontal scanning period R immediately thereafter is the extreme. It is the end point of the short exposure V and the start point of the long exposure L2. The generation timing of the transfer pulse TXi in the horizontal scanning period R after the horizontal scanning period R is the end point of the long exposure L2 and at the same time the start point of the long exposure L1 in the next frame.

  The enable pulse generator 56 in the timing generator 50 sends the enable pulse ENa to the shift register 61 so that pixel signals in each row i of the pixel matrix unit 10A are read in each horizontal scanning period R shown in FIG. Supply. Further, in each of these horizontal scanning periods R, the pulse generator 55 generates sampling clocks φr and φs, sampling pulses for performing A / D conversion, and a shift clock for serial transfer. Further, the enable pulse generator 56 supplies the enable pulse ENb to the shift register 62 so that the accumulated charge in each row i of the pixel matrix unit 10A is erased in each horizontal scanning period r shown in FIG. 4B. .

  Thus, in each horizontal scanning period R including the end point of the long exposure L1, a digital pixel signal for one row as a result of the long exposure L1 is generated in the column ADC unit 30, and image processing is performed via the horizontal scanning circuit 40. Serially transferred to the unit 70. The same applies to the short exposure S, the very short exposure V, and the last long exposure L2, and in each horizontal scanning period R including the end point of each exposure period, the digital pixel signal for one row as the exposure result. Are generated in the column ADC unit 30 and serially transferred to the image processing unit 70 via the horizontal scanning circuit 40.

  Then, the image processing unit 70 synthesizes image data having a wide dynamic range according to the procedure shown in FIG. First, L1 image data that is a set of digital pixel signals obtained by the long-time exposure L1 at the beginning of the frame, and L2 image data that is a set of digital pixel signals obtained by the last long-time exposure L2 of the frame. L image data averaged between the same pixels is generated. Next, from this L image data, S image data that is a set of digital pixel signals obtained by short-time exposure S, and V image data that is a set of digital pixel signals obtained by extremely short-time exposure V Synthesizes image data with a wide dynamic range.

  Various methods of combining can be considered. When the relationship between the exposure time and the pixel signal value is linear, the following combining method can be implemented. In FIG. 6, the horizontal axis represents exposure time, and the vertical axis represents pixel signal values of L image data, S image data, and V image data. Further, tL is the exposure time of the long exposures L1 and L2, tS is the exposure time of the short exposure S, and tV is the exposure time of the extremely short exposure V. Further, th0 is a saturation value of the digital pixel signal output from the column ADC unit 30.

  As described above, the gradient of the pixel signal value with respect to the exposure time increases depending on the intensity of light received by the pixel 10, that is, the illuminance of the subject. In the orthogonal coordinate system composed of the exposure time axis and the pixel signal value axis shown in FIG. 6, the gradient of the straight line connecting the origin (0, 0) and the point (tL, th0) is the pixel signal value at the long exposure L1 or L2. This corresponds to the upper limit of the illuminance of a saturated subject. Further, the slope of the straight line connecting the origin (0, 0) and the point (tS, th0) corresponds to the upper limit value of the illuminance of the subject whose pixel signal value is saturated in the short exposure S. In this synthesis method, a pixel signal value th1 of a point corresponding to the exposure time tS on the straight line connecting the origin (0, 0) and the point (tL, th0) is obtained, and this pixel signal value th1 is obtained by the short-time exposure S. Of the pixel signal values of the obtained S image data, the lower limit value is adopted as the pixel value of the composite image. Further, the pixel signal value th2 of the point corresponding to the exposure time tV on the straight line connecting the origin (0, 0) and the point (tS, th0) is obtained, and this pixel signal value th2 is obtained by the extremely short time exposure V. The lower limit value of the pixel signal value of the V image data to be adopted as the pixel value of the composite image. Then, using the saturation value th0 and the lower limit values th1 and th2, the pixel signal value of the composite image is determined from the L image data, the S image data, and the V image data as follows.

  First, when the pixel signal value of the L image data of a certain pixel is less than the saturation value th0, the image processing unit 70 multiplies the pixel signal value by the weighting factor A / tL to obtain the pixel signal value of the composite image. And Here, A is a constant. When the pixel signal value of the L image data of a certain pixel reaches the saturation value th0, the pixel signal value of the S image data is smaller than the saturation value th0, and is equal to or greater than the lower limit value th1, the image processing unit 70 The pixel signal value of the S image data multiplied by the weighting factor A / tS is used as the pixel signal value of the composite image. When the pixel signal value of the S image data has reached the saturation value th0, the pixel signal value of the V image data is smaller than the saturation value th0, and is equal to or greater than the lower limit value th2, the image processing unit 70 The pixel signal value of the composite image is obtained by multiplying the pixel signal value of the data by the weighting factor A / tV. By performing the processing as described above, image data of a composite image having a wide dynamic range can be obtained.

  FIG. 7 illustrates the effects of this embodiment. In this embodiment, a plurality of exposures as shown in FIG. 4A are performed, two long exposures L1 and L2 are performed at the beginning and end of the frame, and an average of these exposure results Used as L image data as a result of time exposure. For this reason, there is less deviation between the substantial imaging timing of the L image data and the imaging timing of the S image data and the V image data. For this reason, even when the subject moves at high speed, in the composite image, as illustrated in FIG. 7, the positional deviation of the S image and the V image from the L image can be reduced, and the distortion of the composite image with respect to the subject can be reduced. There is an effect that can be done.

Although one embodiment of the present invention has been described above, other embodiments are conceivable for the present invention. For example:
(1) In the above embodiment, the short-time exposure S and the very short-time exposure V are arranged between the two long-time exposures L1 and L2, but only one of them may be arranged.
(2) In the above embodiment, the exposure times of the long exposures L1 and L2 performed at the beginning and the end of the frame are set to the same length, but these exposure times may be set to different lengths. In this case, if the exposure times of the long exposures L1 and L2 are tL1 and tL2, for example, the pixel signal value of the L1 image data is multiplied by the weighting factor A / tL1, and the pixel signal value of the L2 image data is weighted. What is necessary is just to synthesize | combine L image data by adding what multiplied the coefficient A / tL2.
(3) In the above embodiment, a CMOS solid-state imaging device is shown as an example of the solid-state imaging device according to the present invention. However, the present invention can also be applied to other solid-state imaging devices such as a CCD solid-state imaging device.

It is a block diagram which shows the structure of the CMOS solid-state imaging device which is one Embodiment of this invention. It is a figure showing an example of composition of pixel 10 in the embodiment. 2 is a block diagram showing a configuration example of a timing generator 50 and a vertical scanning circuit 60 in the same embodiment. FIG. It is a figure which illustrates the multiple exposure performed in the same embodiment, and the imaging sequence for performing this multiple exposure. It is a figure which shows the synthetic | combination procedure of the image data performed in the embodiment. It is a figure explaining the method of calculating | requiring the pixel signal value of a synthesized image from L image data, S image data, and V image data in the embodiment. It is a figure which illustrates the synthesized image obtained when the to-be-photographed subject is imaged in the embodiment. It is a figure which shows the example of multiple exposure. It is a figure which illustrates the synthesized image at the time of imaging by the multiple exposure about the to-be-moved subject.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pixel, 11 ... Column signal line, 10A ... Pixel matrix part, 20 ... Column CDS part, 30 ... Column ADC part, 40 ... Horizontal scanning circuit, 50 ... Timing generator, 60 ... Vertical Scanning circuit 70... Image processing unit 80... U / I unit 90... Control unit 52... Clock counter 53 53 Line counter 56. 61, 62 ... shift register, 63, 64 ... AND-OR gate.

Claims (1)

A pixel matrix portion formed by arranging a plurality of pixels in a matrix,
Two long exposure periods are generated before and after a short exposure period to cause each pixel of the pixel matrix unit to sequentially perform exposure for a plurality of types of exposure periods, and the exposure results for each exposure period. Drive control means for reading out pixel signals;
A pixel signal that is an exposure result of each exposure period read from the pixel matrix unit is acquired, and a combined value of each pixel signal that is an exposure result of two long exposure periods and the two long exposure periods A solid-state imaging device comprising: an image processing unit that synthesizes image data from a pixel signal that is an exposure result of a short exposure period.

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