JP2009272596A - Solid-state imaging device, method of manufacturing the same, and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable curtailment in numbers of manufacturing steps and improvement in characteristic of pixel in a solid-state imaging device. <P>SOLUTION: The solid-state imaging device has a first element separating unit 43 having a pixel portion 23, a peripheral circuit 24, and an STI structure formed on the semiconductor substrate 22 of the peripheral circuit 24; and a second element separating unit 45 having the STI structure, formed on the semiconductor substrate 22 of the pixel portion 23, with a shallower embedded portion inside the semiconductor substrate 22 than that inside the semiconductor substrate 22 of the first element separating unit 43, and with the same height of the surface as that of the first element separating unit 43. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus including the solid-state imaging device.

  Solid-state imaging devices are roughly classified into an amplification-type solid-state imaging device typified by a CMOS (Complementary Metal Oxide Semiconductor) image sensor and a charge transfer type solid-state imaging device typified by a CCD (Charge Coupled Device) image sensor. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped mobile phone or a PDA (Personal Digital Assistant), a CMOS image sensor is often used from the viewpoint of low power supply voltage and power consumption. .

  In the CMOS solid-state imaging device, a configuration using an STI (Shallow Trench Isolation) structure of the same configuration is known for both the pixel unit and the peripheral circuit unit as the element isolation unit. In addition, a CMOS solid-state imaging device is also known in which a diffusion layer is used as an element separation portion of a pixel portion (see Patent Documents 1 and 2). FIG. 27 shows an example of a CMOS solid-state imaging device in which an element isolation unit using a diffusion layer is configured.

  As illustrated in FIG. 27, the solid-state imaging device 101 includes a pixel unit 103 in which a plurality of pixels are arranged on a semiconductor substrate 102 and a peripheral circuit unit 104 including a logic circuit formed around the pixel unit 103. It consists of In the pixel portion 103, a plurality of unit pixels 110 including a photodiode (PD) 107 serving as a photoelectric conversion element and a plurality of pixel transistors 108 are two-dimensionally arranged. In FIG. 27, the pixel transistor 108 is shown as a representative, and the pixel transistor 108 includes a source / drain region 109 and a gate insulating film and a gate electrode (not shown). A multilayer wiring layer 114 in which a multilayer wiring 113 is formed via an interlayer insulating film 112 is formed above the pixel 110, and an on-chip color filter 115 and an on-chip microlens 116 are formed thereon. Although not shown, a multilayer wiring layer in which multilayer wiring is formed is also formed in the peripheral circuit portion 104 via an interlayer insulating film.

  In the pixel unit 103, the element isolation unit 121 includes a p + diffusion layer 122 formed by ion implantation in the semiconductor substrate 102 and an insulating layer 123 made of a silicon oxide film thereon. Although the insulating layer 123 is partially embedded in the substrate 102, the embedded depth h1 is set to 50 nm or less, and the total thickness is set to about 50 nm to 150 nm. On the other hand, in the peripheral circuit unit 104, the element isolation unit 125 has a STI structure in which a groove 126 is formed in the semiconductor substrate 102 and an insulating layer 127 made of a silicon oxide film is embedded in the groove 126. The embedded depth h2 embedded in the substrate 102 of the insulating layer 127 is about 200 nm to 300 nm, and the protruding height h3 protruding to the substrate surface is sufficiently larger than the protruding height h4 of the insulating layer 123 of the pixel portion 103. Low.

In addition, Patent Document 3 discloses an example of an element isolation part of a pixel part, and an example of an element isolation part of a DRAM of Patent Document 4.
JP 2005-347325 A JP 2006-24786 A JP 2005-191262 A JP 2007-288137 A

  As the element separation unit of the solid-state imaging device, in the former pixel unit and the peripheral circuit unit described above, the configuration using the STI structure of the same structure has a problem that white spots increase. That is, since the STI element isolation portion in the pixel portion is formed deep in the semiconductor substrate, similar to the STI isolation portion in the peripheral circuit portion, the influence of stress and damage on the photodiode increases and white spots increase. become. In order to suppress this white spot, pinning (that is, hole accumulation) at the end of the STI element isolation portion must be strengthened. Since pinning enhancement, that is, hole accumulation enhancement, performs p-type ion implantation, the area of the n-type region constituting the photodiode is reduced accordingly, and the saturation signal amount is reduced. Therefore, the enhancement of pinning has a trade-off relationship with the decrease of the saturation signal amount.

As an improvement measure, there is a configuration of the element isolation portion 121 including the latter (see the configuration of FIG. 27) p + diffusion layer 122 and the insulating layer 123 thereon. However, in this case, there is a problem that the number of processes increases due to the incorporation of the STI structure element isolation portion 125 of the peripheral circuit portion 104. Further, as shown in FIGS. 28A and 28B, in the element isolation portion 121 of the pixel portion, the protruding height h4 of the insulating layer 123 is large. Therefore, in the step of forming the gate electrode 131 [131A, 131B, 131C] of each pixel transistor, There has been a problem that polysilicon residue 133a and the like are generated. That is, as shown in FIG. 19B, when a polysilicon film 133 is formed on the entire surface and then patterned using a lithography technique and an etching technique, a conductive polysilicon residue 133a is formed on the sidewall of the insulating layer 123 having a large step. Is likely to occur. If the polysilicon residue 133a is generated, the adjacent gate electrodes 131 may be short-circuited, or the imaging characteristics may be adversely affected as a defect.
28A and 28B, 131A represents a gate electrode of a transfer transistor, 131B represents a gate electrode of a reset transistor, and 131C represents a gate electrode of an amplification transistor. Reference numeral 134 denotes an n + source / drain region.

  Further, in the configuration of FIG. 27, since the protrusion height h4 is larger than the substrate of the insulating layer that constitutes the element isolation portion of the pixel portion, the distance L1 between the photodiode and the on-chip microlens is easily increased accordingly, It is disadvantageous for efficiency.

In view of the above, the present invention provides a solid-state imaging device capable of reducing the number of manufacturing steps and improving pixel characteristics, and a manufacturing method thereof.
Moreover, this invention provides the electronic device provided with this solid-state image sensor.

  A solid-state imaging device according to the present invention includes a pixel unit, a peripheral circuit unit, a first element isolation unit having an STI structure formed on a semiconductor substrate of the peripheral circuit unit, and an STI structure formed on the semiconductor substrate of the pixel unit. And a second element isolation part. The second element isolation portion of the pixel portion has a shallower portion embedded in the semiconductor substrate than the portion embedded in the semiconductor substrate of the first element isolation portion, and has the same surface height as the first element isolation portion. A second element isolation portion having an STI structure.

  In the solid-state imaging device of the present invention, the portion embedded in the semiconductor substrate of the second element isolation portion of the pixel portion is shallower than the portion embedded in the semiconductor substrate of the first element isolation portion of the peripheral circuit portion. The effects of stress and damage to the can be suppressed. Since the surface height of the second element isolation portion of the pixel portion is made lower than the surface height of the first element isolation portion of the peripheral circuit portion, in the processing of the gate electrode after the formation of the element isolation portion, No electrode material remains on the sidewall. Since the surface height of the second element isolation portion of the pixel portion is made the same as the surface height of the first element isolation portion of the peripheral circuit portion, the increase in process due to the difference in the STI structure of the first and second element isolation portions is minimized. Can be suppressed.

  The method for manufacturing a solid-state imaging device according to the present invention includes a first groove in a portion where an element isolation portion of a peripheral circuit portion of a semiconductor substrate is to be formed, and a first groove in a portion where an element isolation portion of a pixel portion is to be formed. Forming a second shallower groove, forming the insulating layer including the first and second grooves, and isolating the first element by polishing the insulating layer to have the same surface height And forming a second element isolation portion.

  In the manufacturing method of the solid-state imaging device of the present invention, the insulating layer is formed in the first groove on the peripheral circuit portion side and the second groove on the pixel portion side shallower than this, and the insulating layer is polished in the same process, The surface heights of the insulating layers serving as the first and second element isolation portions are the same. As a result, an increase in the number of processes due to the difference in the STI structure between the first and second element isolation portions can be minimized. Since the surface height of the second element isolation portion of the pixel portion is made lower than the surface height of the first element isolation portion of the peripheral circuit portion, in the processing of the gate electrode after the formation of the element isolation portion, No electrode material remains on the sidewall. Since the second groove on the pixel portion side is formed shallower than the first groove on the peripheral circuit portion side, the influence of stress and damage to the photoelectric conversion element by the second element separation portion can be suppressed.

  An electronic apparatus according to the present invention includes a solid-state imaging device, an optical system that guides incident light to a photoelectric conversion element of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device. The solid-state imaging device includes a pixel portion, a peripheral circuit portion, a first element isolation portion having an STI structure formed on a semiconductor substrate of the peripheral circuit portion, and a second having an STI structure formed on the semiconductor substrate of the pixel portion. And an element isolation part. The second element isolation portion of the pixel portion has a shallower portion embedded in the semiconductor substrate than the portion embedded in the semiconductor substrate of the first element isolation portion, and has the same surface height as the first element isolation portion. It has a configuration.

  In the electronic device of the present invention, in the solid-state imaging device, the portion embedded in the second element isolation semiconductor substrate of the pixel portion is shallower than the portion embedded in the semiconductor substrate of the first element isolation portion of the peripheral circuit portion. Thereby, the influence of the stress and damage to the photoelectric conversion element by the second element separation unit can be suppressed. Since the surface height of the second element isolation portion of the pixel portion is made lower than the surface height of the first element isolation portion of the peripheral circuit portion, in the processing of the gate electrode after the formation of the element isolation portion, No electrode material remains on the sidewall. Since the surface height of the second element isolation portion of the pixel portion is made the same as the surface height of the first element isolation portion of the peripheral circuit portion, the increase in process due to the difference in the STI structure of the first and second element isolation portions is minimized. Can be suppressed.

  According to the present invention, it is possible to reduce processes and improve pixel characteristics.

  Embodiments of the present invention will be described below with reference to the drawings.

  The solid-state imaging device according to the embodiment of the present invention is characterized by the configuration of the element separation unit in the pixel unit and the peripheral circuit unit.

  FIG. 1 shows a schematic configuration of an example of a solid-state imaging device applied to the present invention, that is, a CMOS solid-state imaging device. The solid-state imaging device 1 of this example includes a pixel unit (so-called imaging region) 3 in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged in a semiconductor substrate 11, for example, a silicon substrate, a peripheral circuit unit, It is comprised. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by four transistors, for example, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor. In addition, for example, the selection transistor may be omitted and the transistor may be configured with three transistors. Since the equivalent circuit of these unit pixels is the same as usual, detailed description is omitted.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 generates a clock signal and a control signal as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows, and is a photoelectric conversion element of each pixel 2 through the vertical signal line 9, for example, a photodiode. A pixel signal based on the signal charge generated according to the amount of received light is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and signals output from the pixels 2 for one row are generated from black reference pixels (formed around the effective pixel region) for each pixel column. The signal processing such as noise removal is performed by the signal. That is, the column signal processing circuit 5 performs signal processing such as CDS for removing fixed pattern noise unique to the pixel 2 and signal amplification. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10.

  In this example, since the surface irradiation type solid-state imaging device is used, a multilayer wiring layer is formed above the surface side of the substrate on which the pixel unit 3 and the peripheral circuit unit are formed, with an interlayer insulating film interposed therebetween. In the pixel unit 3, an on-chip color filter is formed on the multilayer wiring layer via a planarizing film, and an on-chip microlens is further formed thereon. A light-shielding film is formed in a region other than the pixel portion in the imaging region, more specifically, in the peripheral circuit portion and other region other than the photodiode (so-called light receiving portion) in the imaging region. This light shielding film can be formed by, for example, the uppermost wiring layer of the multilayer wiring layer.

  As will be described later, in the back-illuminated solid-state imaging device, there is no multilayer wiring layer on the back surface on the light incident surface (so-called light receiving surface) side. The multilayer wiring layer is formed on the surface side opposite to the light receiving surface.

  And although the structure of the solid-state imaging device concerning this Embodiment, especially the element isolation | separation part is applied to the above-mentioned CMOS solid-state imaging device, it is not restricted to this example.

[First Embodiment of Solid-State Imaging Device]
FIG. 2 shows a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a configuration diagram showing a main part of a pixel portion (so-called imaging region) 23 and a peripheral circuit portion 24 formed on a semiconductor substrate 22, for example, a silicon substrate. The solid-state imaging device 21 according to the present embodiment includes a pixel unit 23 in which a plurality of pixels are arranged on a semiconductor substrate 22, and a peripheral circuit unit 24 formed of, for example, a logic circuit around the pixel unit 23. It consists of

  In the pixel unit 23, a plurality of unit pixels 25 each including a photodiode (PD) 26 serving as a photoelectric conversion element and a plurality of pixel transistors 27 are two-dimensionally arranged. In FIG. 2, a plurality of pixel transistors are representatively shown as one pixel transistor 27, and the pixel transistor 27 includes a source / drain region 28, a gate insulating film (not shown), and a gate electrode. A multilayer wiring layer 33 in which a multilayer wiring 32 is formed via an interlayer insulating film 31 is formed above the pixel 25, and an on-chip color filter 34 and an on-chip microlens 35 are formed thereon. In the peripheral circuit unit 24, a logic circuit made of, for example, a CMOS transistor (not shown) is formed, and similarly, a multilayer wiring layer in which a multilayer wiring is formed via the interlayer insulating film 31 is formed.

  The solid-state imaging device 21 of this example uses electrons as signal charges. As shown in FIG. 3, the photodiode 26 includes a p-type semiconductor well region 36 of the first conductivity type of the semiconductor substrate 22, an n-type charge storage region 37 of the second conductivity type, and an insulating film 39 on the surface thereof. For example, a p + semiconductor region (so-called hole accumulation layer) 38 for suppressing dark current is formed near the interface with the silicon oxide film.

  In the present embodiment, the first element isolation portion 43 having the STI structure is formed by embedding the insulating layer 42 in the groove 41 formed perpendicular to the semiconductor substrate 22 for element isolation in the peripheral circuit portion 24. . In the pixel portion 23, a second element isolation portion 45 having an STI structure is formed by embedding an insulating layer 42 in a groove 44 formed perpendicularly to the semiconductor substrate 22 for element isolation. The first element isolation portion 43 of the peripheral circuit portion 24 has a buried depth h5 of the portion embedded in the semiconductor substrate of the insulating layer 42 of about 200 nm to 300 nm, and the surface of the portion protruding from the surface of the semiconductor substrate 22. , Ie, the protruding height is about 0 to 40 nm. The embedding depth h <b> 5 is a depth from the surface of the semiconductor substrate 22 below the insulating film 39. The protrusion height h6 is a protrusion height from the surface of the semiconductor substrate 22 below the insulating film 39.

  On the other hand, the second element isolation portion 45 of the pixel portion 23 is formed such that the embedded depth h7 of the portion embedded in the semiconductor substrate of the insulating layer 42 is shallower than the embedded depth h5 on the peripheral circuit portion 24 side. Further, the height of the surface of the portion of the insulating layer 42 protruding from the surface of the semiconductor substrate 22, that is, the protruding height h8 is the same as the protruding height h6 on the peripheral circuit portion 24 side. It is formed to become. The protrusion height h8 of the second element isolation part 45 can be about 0 nm to 40 nm, the embedding depth h7 can be about 50 nm to 160 nm, and the total thickness h9 can be about 70 nm to 200 nm.

  On the peripheral circuit part 24 side, the protrusion height h6 of the first element isolation part 43 is required to be about 0 nm to 40 nm due to restrictions of a normal MOS structure. On the pixel part 24 side, the protrusion height h8 of the second element isolation part 45 is set to about 0 nm to 40 nm in accordance with the protrusion height h6 on the peripheral circuit part 24 side. The total thickness h9 of the second element isolation part 45 is required to be about 70 nm to 200 nm as described above due to pixel characteristic restrictions.

  The total thickness h9 of the second element isolation portion 45 of the pixel portion 23 provides element isolation, and even if a wiring is formed on the insulating layer 42, no parasitic MOS transistor is formed. The thickness is not affected by stress and damage.

  That is, when the protrusion height h8 is 0 nm to 40 nm, as described later, no polysilicon remains on the protrusion side wall from the substrate surface of the second element isolation portion 45 when the gate electrode is processed with polysilicon. This can prevent a short circuit between the gate electrodes. If h8 protrudes from 40 nm, polysilicon residue is likely to be generated on the side wall of the protrusion. If the embedding depth h7 is shallower than 50 nm, a parasitic MOS transistor is easily formed when a wiring is formed on the element isolation portion 45. If h7 is deeper than 160 nm, the photodiode 26 is likely to be stressed and damaged, which causes white spots. If the total thickness h9 is not in the range of 70 nm to 200 nm, element isolation as the element isolation unit 45 is obtained, and generation of white spots is suppressed.

  Here, the protrusion heights h6 and h8 of the first element isolation portion and the second element isolation portion are defined as the same protrusion height if the protrusion height is within the range of processing variation based on manufacturing processing accuracy. To do. That is, the film thickness of the nitride film mask in the trench processing is generally about 200 nm of nitride film, and the in-plane variation of the wafer is about ± 10%. Polishing variation due to CMP (chemical mechanical polishing) is also about ± 20 to 30 nm. Therefore, even if it is devised so that the protrusion heights h8 and h6 are the same in the pixel portion 23 and the peripheral circuit portion 24, the pixel portion 23 and the peripheral circuit portion 24 may vary by about 20 to 30 nm. When the pixel portion and the peripheral circuit portion are compared with each other in the chip surface by observing strictly, even if the protrusion height is not completely the same, the difference between the protrusion heights h8 and h6 in the pixel portion and the peripheral circuit portion. Needless to say, if it falls within 30 nm, it falls within the category of “same height” in the present invention.

  According to the solid-state imaging device 21 according to the first embodiment, both the second element isolation unit 45 of the pixel unit 23 and the first element isolation unit 43 of the peripheral circuit unit 24 have the STI structure, and the respective insulating layers 42. The protrusion heights h6 and h8 from the surface of the semiconductor substrate 22 are the same. With this configuration, steps such as embedding the insulating layer 42 and planarization of the insulating layer 42 can be performed at the same time during manufacturing, so that the number of steps can be reduced.

  In the second element isolation portion 45 of the pixel portion 23, the protrusion height h8 on the substrate is as low as 0 nm to 40 nm, similar to the protrusion height h6 of the first element isolation portion 43 of the peripheral circuit portion 24. For this reason, when the polysilicon film is patterned in the step of forming the gate electrode of the pixel transistor, the patterning is performed with high accuracy, and the polysilicon remains on the side wall of the portion where the second element isolation portion 45 protrudes from the substrate. There is no. Therefore, a short circuit failure between the pixel transistors due to the polysilicon residue is avoided.

  In the pixel portion 23, the second element isolation portion 45 is formed with an STI structure, and the embedded depth h 7 of the portion embedded in the semiconductor substrate 22 of the second element isolation portion 45 is the STI structure of the peripheral circuit portion 24. The first element isolation portion 43 is formed to be shallower than the embedding depth h5 in the semiconductor substrate 22. That is, the embedding depth h7 of the second element isolation unit 45 of the pixel unit 23 is set to 50 nm to 160 nm. This embedding depth h7 does not give stress or damage to the photodiode 26. That is, since the depth of the groove 44 is shallow, the generation of defects is suppressed. For this reason, generation of electrons for generating white spots at the interface between the second element isolation unit 45 and the photodiode 26 is suppressed. Therefore, the leakage of electrons from the interface with the second element isolation unit 45 to the photodiode 26 is suppressed, and the generation of white spots in the photodiode 26 based on this can be suppressed.

  In addition, since the total thickness h9 of the second element isolation portion 45 of the pixel portion 23 is about 70 nm to 200 nm, sufficient element isolation characteristics can be obtained. Further, even if the wiring extends on the second element isolation portion 45, the parasitic MOS transistor is not formed.

  Further, since the separation characteristics can be ensured even if the p-type ion concentration at the end (lateral end) of the second element isolation portion 45 of the pixel portion 23 is low, the configuration having the conventional diffusion layer isolation portion shown in FIG. This is advantageous for reading the transfer transistor. Although the p-type region is not shown, the p-type region is formed in a separation part beside the transfer transistor of the pixel.

  Since the protrusion height h8 of the second element isolation portion 45 of the pixel portion 23 is the same as the protrusion height h6 of the first element isolation portion 43 of the peripheral circuit portion 24, the photodiode 26 and the on-chip microlens 35 are reduced. The distance L2 between the two is shorter than the distance L1 in FIG. For this reason, the light collection efficiency to the photodiode 26 is improved, and the sensitivity is improved.

  Thus, according to the configuration of the solid-state imaging device according to the first embodiment, the number of steps in the manufacturing process can be reduced, and after-image characteristics, saturation signal amounts, prevention of short-circuits between pixel transistors, etc. Can be improved. Further, in the gate electrode processing using the polysilicon film, no polysilicon residue is generated on the side wall of the portion of the insulating film 42 that constitutes the second element isolation portion 45 on the pixel portion 23 side that protrudes on the substrate. Thereby, gate electrode processing becomes easy and the yield of manufacture can be improved.

[Second Embodiment of Solid-State Imaging Device]
FIG. 4 shows a solid-state imaging device according to the second embodiment of the present invention. FIG. 4 is a cross-sectional view showing only a main part including the photodiode 26 of the pixel portion 23 and the second element isolation portion 45 adjacent thereto. In the solid-state imaging device 48 according to the present embodiment, a p-type semiconductor layer 49 is formed at least in a region in contact with the photodiode 26 in the second element isolation unit 45 of the pixel unit 23. In other words, the insulating layer 42 of the second element isolation part 45 is formed to extend on the side surface and part of the lower surface that are in contact with the photodiode 26. Note that the p-type semiconductor layer 49 may be formed over the entire lower surface of the side surface of the portion embedded in the semiconductor substrate 22 of the insulating layer 42 as indicated by a chain line. The p-type semiconductor layer 49 can be formed by impurity ion implantation, for example.

The p-type semiconductor layer 49 can be formed by performing ion implantation after the formation of the trench when forming the STI structure, or by ion implantation from above the insulating layer 42 after forming the STI structure. It can also be formed. When forming the p-type semiconductor layer 49 by ion implantation after forming the insulating layer 42, if the depth of the insulating layer 42 is too deep, it may be difficult for p-type impurities to enter properly regardless of the angle of ion implantation. Arise. In order to avoid this, it is desirable to form the insulating layer 42 so that the depth of the insulating layer 42 is shallow and slightly tapered, that is, the width becomes narrower as it goes downward.
Other configurations are the same as those described with reference to FIGS.

  According to the solid-state imaging device 48 according to the second embodiment, the p-type semiconductor layer 49 is formed near the interface between the insulating layer 42 and the photodiode 26 in the second element isolation unit 45 of the pixel unit 23. Furthermore, generation of electrons at the element isolation interface can be suppressed, and generation of white spots at the photodiode 26 can be suppressed. In addition, the same effects as described in the first embodiment can be obtained.

[Third Embodiment of Solid-State Imaging Device]
FIG. 5 shows a solid-state imaging device according to the third embodiment of the present invention. FIG. 5 is a cross-sectional view showing only a main part including the photodiode 26 of the pixel part 23 and the second element isolation part 45 adjacent thereto. The solid-state imaging device 51 according to the present embodiment has a configuration in which the p-type semiconductor layer 52 is further formed under the insulating layer 42 in the second element isolation portion 45 of the pixel portion 23 and also serves as diffusion layer isolation. 5, a p-type semiconductor layer 49 is formed at least in the vicinity of the interface between the photodiode 26 and the insulating layer 42 as in FIG. The p-type semiconductor layer 49 may be omitted.
Other configurations are the same as those described in FIG. 2, FIG. 3, and FIG.

  According to the solid-state imaging device 51 according to the third embodiment, the p-type semiconductor layer 52 for further diffusion layer isolation is formed below the insulating layer 42 in the second element isolation unit 45 of the pixel unit 23. Therefore, the element isolation of the second element isolation unit 45 of the pixel unit 23 is further improved by combining this diffusion layer isolation. In addition, the same effects as described in the first and second embodiments can be obtained.

[Fourth Embodiment of Solid-State Imaging Device]
FIG. 6 shows a solid-state imaging device according to the fourth embodiment of the present invention. FIG. 6 is a cross-sectional view showing only the main part including the photodiode 26 of the pixel part 23 and the second element isolation part 45 adjacent thereto. In the solid-state imaging device 54 according to the present embodiment, in the pixel unit 23, the second element isolation unit 45 having a shallower STI structure than the peripheral circuit unit 24 side is formed as in the above example. The part is extended so as to enter the lower surface of the second element isolation part 45. A p-type semiconductor layer 49 similar to that shown in FIG. 4 can be formed in the vicinity of the interface between the second element isolation portion 45 and the photodiode 26 at least. The p-type semiconductor layer 49 may be omitted. Further, as described with reference to FIG. 5, the p-type semiconductor layer 52 used for the diffusion layer element isolation can be formed under the insulating layer 42 of the second element isolation part 45.
Other configurations are the same as those described in the first and second embodiments, and therefore, a duplicate description is omitted.

According to the solid-state imaging device 54 according to the fourth embodiment, the photodiode 26 is formed so as to extend partly so as to enter the lower surface of the second element isolation portion 45, so that the area of the photodiode 26 is increased. can. Increasing the area of the photodiode contributes to an increase in saturation signal amount and an improvement in sensitivity.
In addition, the same effects as described in the first, second, and third embodiments can be obtained.

[Fifth Embodiment of Solid-State Imaging Device]
FIG. 7 shows a solid-state imaging device according to the fifth embodiment of the present invention. FIG. 7 is a cross-sectional view showing only essential parts including the photo 26 of the pixel portion 23, the pixel transistor 27, the second element isolation portion 45 adjacent thereto, and the first element isolation portion 43 of the peripheral circuit portion 24. In the solid-state imaging device 55 according to the present embodiment, the first element isolation portion 43 having the STI structure of the peripheral circuit portion 24 is formed deep in the vertical direction in the semiconductor substrate 22 as described above. Further, the second element isolation part 45 of the STI structure of the pixel part 23 is formed shallower than the first element isolation part 43 in the direction perpendicular to the semiconductor substrate 22. The heights h8 and h6 protruding from the surface of the semiconductor substrate 22 of the insulating layer 42 of the first element isolation portion 43 and the insulating layer 42 of the second element isolation portion 45 are the same height.

  In the present embodiment, in particular, a bird's beak-like insulating portion 42 a extending from the insulating layer 42 is provided in a portion of the first element separating portion 43 and the second element separating portion 45 that is in contact with the surface of the semiconductor substrate 22. That is, the shoulder portions of the first element isolation portion 43 and the second element isolation portion 45 in contact with the semiconductor substrate surface of the insulating layer 42 are bird's beak-like insulating portions 42a, and the shoulder portions have a thick film thickness. Covered with. In addition, since the insulating portion 42a has a bird's beak shape, the curvature of the insulating film 42 at the shoulder portion is gentle.

  In the present embodiment, as will be described later, the side walls are formed by side wall thermal oxidation of the grooves 41 and 44 before embedding the insulating film 42 of silicon oxide in the grooves 41 and 44, and the upper and lower portions of the grooves 41 and 44 are formed. The corner is rounded. In addition, a bird's beak-like insulating portion 42a is formed in a corner portion (so-called shoulder portion) above the grooves 41 and 44.

  Note that as the sidewall film, an insulating film other than the thermal oxide film, for example, a plasma oxide film, a plasma oxynitride film, or the like formed by an insulating process such as a plasma oxidation process or a plasma oxynitride process can also be used.

Further, in the second element isolation portion 45 in the pixel portion 23, an impurity injection region for suppressing dark current, that is, a p-type semiconductor layer 49 is formed from the interface with the semiconductor substrate 22 to a part on the surface side of the semiconductor substrate 22. Is done. That is, the p-type semiconductor layer extends from the bottom and side surfaces of the insulating layer 42 embedded in the second element isolation portion 45 partially in the lateral direction to the semiconductor substrate surface along the bird's beak-like insulating portion 42a. 49 is formed. In the pixel transistor 27, the gate electrode 56 is formed so as to straddle the protruding surface protruding from the surface of the second element isolation portion 45.
The other configuration is the same as that described in the first embodiment, and a duplicate description is omitted.

  According to the solid-state imaging device 55 according to the fifth embodiment, the bird's beak-like insulating portion 42a is formed at the upper corner portion (shoulder portion) of the groove 44 of the second element isolation portion 45 of the STI structure in the pixel portion 23. . That is, as shown in FIG. 8, since it has the bird's beak-like insulating portion 42a, the divot 59 that occurs in the element isolation portion 45 of the normal STI structure shown in FIG. 10 is suppressed.

  In the pixel transistor 27, the end portion of the gate electrode 56 is usually formed across the element isolation portion. In the present embodiment, the thickness t1 of the insulating layer 42 in the upper corner portion of the groove 44 is thick, and the curvature of the upper corner portion is gentle and the stress is relieved, so that the upper corner of the groove 44 is reduced. Electric field concentration on the part is alleviated. The relaxation of the electric field concentration increases the threshold voltage Vth at the upper corner portion, and can suppress the generation of the parasitic channel component 57 at the edge portion of the pixel transistor 27 and the second element isolation portion 45 shown in FIG. Since the parasitic channel component 57 is suppressed, the leakage current between the source S and the drain D is suppressed, and random noise can be reduced. Since the edge portion has a relatively poor oxide film quality compared to the central portion, random noise can be reduced. Since the divot 59 is suppressed, the hump in the Id (drain current) -Vg (gate voltage) characteristic of the pixel transistor 27 can be reduced.

  Since the insulating layer 42 of the first element isolation unit 43 of the peripheral circuit unit 24 has the same configuration as that of the insulating layer 42 of the second element isolation unit 45 of the pixel unit 23, the MOS transistor of the peripheral circuit unit 24 also has Id. There is an effect of reducing hump in the -Vg characteristic.

  Further, in the second element isolation portion 45 of the pixel portion 23, since the curvature of the upper corner portion of the groove 44 is gentle, the stress applied to the upper corner portion is reduced. As a result, dark current and white spots caused by the floating diffusion (FD) portion of the pixel can be improved. Junction leakage at the floating diffusion portion is suppressed.

  In the second element isolation portion 45 of the STI structure of the pixel portion 23, a p-type semiconductor layer 49 is provided around the STI structure in order to improve dark current and white spots. In the present embodiment, the p-type semiconductor layer 49 is formed from the side wall of the trench 44 to the surface side of the semiconductor substrate, that is, the p-type semiconductor layer 49 from the active region side such as a photodiode or a pixel transistor. Thus, since the p-type semiconductor layer 49 can be set also on the active region side above the trench 44, the degree of freedom for further improving the dark current and the white point is increased.

Since the p-type semiconductor layer 49 is formed on the active region side above the trench 44, the parasitic channel component can be further reduced in the pixel transistor. In combination with the above divot improvement, the random noise can be improved synergistically.
In addition, the same effects as described in the first embodiment can be obtained.

[First Embodiment of Manufacturing Method]
Next, a first embodiment of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this example, the present invention is applied to the manufacture of the solid-state imaging device according to the second embodiment shown in FIG.

  First, as shown in FIG. 11A, a thin insulating film 39 having a required thickness is formed on one main surface of the semiconductor substrate 22, and the etching rate of the insulating film 39 having the required thickness is increased on the insulating film 39. Different insulating films 61 are formed. As the insulating film 39, for example, a silicon oxide film can be used. As the insulating film 61, for example, a silicon nitride film formed by low pressure CVD having a film thickness of about 100 nm can be used. A photoresist film is deposited on the insulating film 61. This photoresist film is exposed through an optical mask having a required pattern and developed to form a resist mask 63 having an opening 62 only in a portion where an element isolation portion on the peripheral circuit portion 24 side is to be formed. The pixel portion 23 side is covered with an entire resist mask 63 having no opening.

  Next, as shown in FIG. 11B, the insulating films 61 and 39 on the peripheral circuit portion 24 side are selectively removed by etching through the resist mask 63, and the semiconductor substrate 22 is selectively removed by etching to a required depth. Thus, the groove 41 is formed. As described above, the groove 41 is formed as a deep groove of about 200 nm to 300 nm.

  Next, as shown in FIG. 12C, after removing the resist mask 63, a new photoresist film is deposited. The photoresist film is exposed and developed through an optical mask having a required pattern to form a resist mask 65 having an opening 64 only in a portion where the pixel portion 23 side element separation portion is to be formed. The peripheral circuit portion 24 side is covered with an entire resist mask 65 having no opening.

  Next, as shown in FIG. 12D, the insulating films 61 and 49 on the pixel portion 23 side are selectively removed by etching through the resist mask 65, and the semiconductor substrate 22 is selectively removed by etching to a required depth. A groove 44 is formed. As described above, the groove 44 is formed as a shallow groove of about 50 nm to 160 nm. Actually, a groove having a thickness of about 40 nm to 150 nm is first formed by an etching process, and then light etching is performed, so that a final finished size becomes 50 nm to 160 nm as described above.

Next, as shown in FIG. 13E, the resist mask 65 is removed.
The deep groove 41 on the peripheral circuit portion 24 side is formed first, and then the shallow groove 44 on the pixel portion 23 side is formed. On the contrary, the shallow groove 44 on the pixel portion 23 side is formed first, and then, A deep groove 41 on the peripheral circuit portion 24 side may be formed.

  Next, for example, in the step of FIG. 13F, the p-type semiconductor layer 49 may be formed on the inner wall surface of the groove 44 by ion implantation. The p-type semiconductor layer 49 can also be formed by ion implantation after the element isolation portion is completely formed. Further, the first p-type impurity is ion-implanted in the step of FIG. 13F, and after the element isolation portion is completely formed, the second p-type impurity is ion-implanted. The semiconductor layer 49 can also be formed.

  In this example, as shown in FIG. 13F, a photoresist film is deposited on the entire surface. This photoresist film is exposed through an optical mask having a required pattern and developed to form a resist mask 67 only on the peripheral circuit portion 24 side. Then, the p-type impurity 60 is ion-implanted into the entire surface of the pixel portion 23 using an insulating film 61 on the pixel portion 23 side, for example, a silicon nitride film as a hard mask. The p-type impurity 60 is not ion-implanted into the portion of the substrate 22 where the insulating film 61 serving as a hard mask is formed, and the opening 61a is ion-implanted into the portion of the substrate 22 where the insulating film 61 is formed, that is, the inner wall surface of the groove 44. . Thus, the p-type semiconductor layer 49 is formed on the inner wall surface of the groove 44, that is, the entire inner wall surface including the inner surface and the bottom surface. This ion implantation is performed by rotational implantation. Note that the p-type semiconductor layer 49 can be formed only on the inner surface of the groove on the side in contact with the photodiode by another method of ion implantation.

  Since the trench 44 is formed, the p-type impurity is ion-implanted to form the p-type semiconductor layer 49. However, there is a possibility that the concentration of the p-type impurity to be ion-implanted can be reduced, and the charge Qs per unit area can be reduced. There is also an advantage to improve.

  Next, as shown in FIG. 14G, after removing the resist mask 67, an insulating layer 42 is deposited on the entire surface of the substrate by, for example, a CVD method so as to be embedded in the grooves 41 and 44, respectively. As the insulating layer 42, for example, a silicon oxide film can be used.

  Next, as shown in FIG. 14H, in the polishing of the insulating layer 42 in a later step, a portion of the surface having a rough surface roughness density is partially etched away so that the entire surface can be uniformly polished. If there is a difference in density of the unevenness on the surface, uneven polishing occurs when the entire surface is polished simultaneously. For this reason, a portion where the uneven density is rough is slightly etched in the step of FIG. 14H.

  Next, as shown in FIG. 15I, the surface of the insulating layer 42 is flatly polished. At this time, polishing stops on the surface of the insulating film 61. Thereafter, polishing is performed so that the protruding heights h6 and h8 of the insulating layer 42 are about 0 nm to 40 nm, in this example about 40 nm. At this time, it is a little thicker, and it is adjusted to 0 nm to 40 nm including work such as cleaning after polishing. For the polishing, for example, a CMP (Chemical Mechanical Polishing) method can be used.

  Next, as shown in FIG. 15J, the insulating film 61 is selectively removed by etching. As a result, the protruding heights h8 and h6 of the pixel unit 23 and the peripheral circuit unit 24 are the same (h8 = h6), and the first element isolation unit 43 having a deep STI structure is formed in the peripheral circuit unit 24. In the portion 23, a second element isolation portion 45 having an STI structure shallower than the first element isolation portion 43 is formed.

  In the subsequent process, the photodiode 26 and the pixel transistor 27 are formed, and the multilayer wiring layer 33 is formed thereon. Further, an on-chip color filter 34 and an on-chip microlens 35 are formed on the multilayer wiring layer 33 through a planarizing film to obtain a target MOS type solid-state imaging device 48.

  Note that the photodiode 26 may be formed before the step of forming the first element isolation portion 43 and the second element isolation portion 45.

[Second Embodiment of Manufacturing Method]
Next, a second embodiment of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this example, the present invention is applied to the manufacture of the solid-state imaging device according to the second embodiment shown in FIG.

  First, as shown in FIG. 16A, a thin insulating film 39 having a required thickness is formed on one main surface of the semiconductor substrate 22, and the etching rate of the insulating film 39 having the required thickness is increased on the insulating film 39. Different insulating films 61 are formed. As the insulating film 39, for example, a silicon oxide film can be used. As the insulating film 61, for example, a silicon nitride film by a low pressure CVD method having a film thickness of about 100 nm can be used. A photoresist film is deposited on the insulating film 61. The photoresist film is exposed through an optical mask having a required pattern and developed to form a resist mask 73 having openings 71 and 72 in portions where the element isolation portions on the pixel portion 23 and peripheral circuit portion 24 sides are to be formed. Form.

  Next, as shown in FIG. 16B, the insulating films 61 and 39 on the pixel portion 23 side and the peripheral circuit portion 24 side are selectively removed by etching through the resist mask 73, and the semiconductor substrate 22 is further removed to a required depth. The groove 44 and the groove 41a are formed by selectively etching away. As described above, the groove 44 is formed as a shallow groove of about 50 nm to 160 nm. Further, since the groove 41 a on the peripheral circuit portion 24 side is formed at the same time as the groove 44 on the pixel portion 23 side, it is formed as a groove having the same depth as the groove 44.

  Next, as shown in FIG. 17C, after removing the resist mask 73, a new photoresist film is deposited. This photoresist film is exposed through an optical mask having a required pattern and developed to form a resist mask 74 only on the pixel portion 23 side. That is, the resist mask 74 is not formed on the peripheral circuit portion 24 side, and the entire area on the pixel portion 23 side is covered with the resist mask 74. The deep groove 41 is formed by further etching away the groove 41a on the peripheral circuit portion 24 side through the resist mask 74. The groove 41 is formed as a groove having a depth of about 200 nm to 300 nm as described above.

  Next, as shown in FIG. 17D, the resist mask 74 is removed.

  Next, for example, in the step of FIG. 18E, the p-type semiconductor layer 49 may be formed on the inner wall surface of the groove 44 by ion implantation. The p-type semiconductor layer 49 can also be formed by ion implantation after the element isolation portion is completely formed. Further, the first p-type impurity is ion-implanted in the step of FIG. 18E, and after the element isolation portion is completely formed, the second p-type impurity is ion-implanted. The semiconductor layer 49 can also be formed.

  In this example, next, as shown in FIG. 18E, after removing the resist mask 74, a new photoresist film is deposited. This photoresist film is exposed through an optical mask having a required pattern and developed to form a resist mask 76 only on the peripheral circuit portion 24 side. Then, the p-type impurity 60 is ion-implanted into the entire surface of the pixel portion 23 using an insulating film 61 on the pixel portion 23 side, for example, a silicon nitride film as a hard mask. The p-type impurity 60 is not ion-implanted into the portion of the substrate 22 where the insulating film 61 serving as a hard mask is formed, but is ion-implanted into the portion of the substrate 22 where the opening 61 a is formed, that is, the inner wall surface of the groove 44. Thus, the p-type semiconductor layer 49 is formed on the inner wall surface of the groove 44, that is, the entire inner wall surface including the inner surface and the bottom surface. This ion implantation is performed by rotational implantation. Note that the p-type semiconductor layer 49 can be formed only on the inner surface of the groove on the side in contact with the photodiode by another method of ion implantation.

  Since the subsequent steps from FIG. 18F to FIG. 20 are the same as the steps from FIG. 14G to FIG. 15J described above, the same reference numerals are given to the portions corresponding to FIG. To do.

  After this step, the photodiode 26 and the pixel transistor 27 are formed as described above, and the multilayer wiring layer 33 is formed thereon. Further, an on-chip color filter 34 and an on-chip microlens 35 are formed on the multilayer wiring layer 33 through a planarizing film to obtain a target MOS type solid-state imaging device 48.

  Note that the photodiode 26 may be formed before the step of forming the first element isolation portion 43 and the second element isolation portion 45.

  According to the manufacturing method of the solid-state imaging device according to the first and second embodiments described above, after forming the groove 44 and the groove 41 on the pixel unit 23 and the peripheral circuit unit 24 side, Deposition and polishing by a CMP method are performed to form second and first element isolation portions 45 and 43 of the pixel portion 23 and the peripheral circuit portion 24. Therefore, the number of manufacturing process steps can be reduced. Further, the protruding heights of the first and second element isolation parts 45 and 43 are the same, and the depth of the second element isolation part 45 on the pixel part 23 side is the same as the first element isolation part 43 on the peripheral circuit part 24 side. It is formed shallower. Thereby, as described above, a solid-state imaging device having improved pixel characteristics such as afterimage characteristics, saturation signal amount, and the like can be manufactured.

[Third Embodiment of Manufacturing Method]
Next, a third embodiment of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this example, the present invention is applied to the manufacture of the solid-state imaging device 55 according to the fifth embodiment shown in FIG.

  In the manufacturing method according to the third embodiment, as shown in FIG. 21A, first, a shallow groove is formed in the pixel portion 23 by using the steps up to FIGS. 11A to 13E or the steps up to FIGS. 16A to 17D. 44 and the deep groove 41 are formed in the peripheral circuit portion 24, respectively. In the state of FIG. 21A, a thin insulating film 39 made of, for example, a silicon oxide film and an insulating film 61 made of, for example, a silicon nitride film are formed on the surface of the semiconductor substrate 22 where the grooves 44 and 41 are not formed.

  Next, as shown in FIG. 21B, the width of the insulating film 61 is selectively narrowed. For example, the exposed surface of the insulating film 61 made of a silicon nitride film is selectively removed by a required thickness using a chemical solution such as hot phosphoric acid, and narrowed from the initial width d1 to the width d2. The width d3 to be removed can be about 2 nm to 15 nm. If it is less than 2 nm, the effect of the present invention cannot be obtained. When the width d3 is increased, the region where the gate oxide film at the edge of the active layer region becomes thicker increases, and the effective gate width of the transistor becomes narrower. In the 90 nm generation, the minimum active layer width is desired to be about 120 nm. When the width d3 is set to 15 nm or more, the minimum effective active layer width is about 120-15 × 2 = 90 nm, and the driving force of the transistor having the minimum active layer width is deteriorated by about 10%. Since the speed performance is affected, the maximum amount of d3 is about 15 nm.

  Next, as shown in FIG. 22C, thermal oxidation is performed from the side walls of the grooves 41 and 44 to the substrate surface side using the insulating film 61 made of silicon nitride as a mask. Side wall oxidation of the so-called grooves 41 and 44 is performed. A thermal oxide film 71 is formed on the side walls of the grooves 41 and 44 by this thermal oxidation treatment. Since this thermal oxidation is selective oxidation of the surface not covered with the insulating film 61 by the silicon nitride film, as shown in FIG. 24, a so-called bird's beak-like shape in which the oxide film swells at the upper corner portions of the grooves 41 and 44 is formed. A thermal oxide film 71a is formed. The bird's beak-like thermal oxide film 71a corresponds to the bird's beak-like insulating layer 42a shown in FIG. By this selective oxidation, the surface of the thermal oxide film in contact with the silicon semiconductor substrate 22 in the upper corner portions of the grooves 41 and 44 becomes a gently rounded curved surface. At the same time, the lower corners of the grooves 41 and 44 are also rounded thermal oxide films.

  As the sidewall film from the sidewalls of the grooves 41 and 44 to the substrate surface, in addition to the thermal oxide film, a plasma oxide film, a plasma acid formed by a selective insulating process such as a plasma oxidation process or a plasma oxynitriding process is used. A nitride film or the like may be used. These plasma oxidation and plasma oxynitridation are selectively performed using the insulating film 61 made of a silicon nitride film as a mask.

  Next, as shown in FIG. 22D, with the peripheral circuit portion 24 side covered with a resist mask, p-type impurities 60 are ion-implanted using the insulating film 61 made of silicon nitride as a mask to form the pixel portion 23 groove 44. A p-type semiconductor layer 49 is formed on the inner wall surface. As shown in FIG. 25, the p-type semiconductor layer 49 is formed so as to extend laterally from the upper corner portion together with the inner surface and the bottom surface of the groove 44. That is, the p-type semiconductor layer 49 is formed extending to the surface of the semiconductor substrate 22 that is not covered with the insulating film 61. The process of FIG. 22D corresponds to the process of FIGS. 13F and 18E described above.

  The subsequent steps are the same as the steps shown in FIGS. 14G to 15J and FIGS. 18F to 19H and FIG. As shown in FIG. 23, the protrusion heights h8 and h6 of the pixel portion 23 and the peripheral circuit portion 24 are the same, and the first element isolation portion 43 having a deep STI structure is formed in the peripheral circuit portion 24. In the portion 23, a second element isolation portion 45 having a shallow STI structure is formed. At this time, although the insulating layer 42 is embedded in the grooves 41 and 44 in the first and second element isolation parts 43 and 45, a bird's beak-like insulating part 42 a is provided at the upper corner part of the grooves 41 and 44. In the second element isolation part 45 on the pixel part 23 side, a p-type semiconductor layer 49 that surrounds the element isolation part 45 and extends laterally from the upper corner part of the partial groove 44 is formed.

  In the subsequent process, the photodiode 26 and the pixel transistor 27 are formed, and the multilayer wiring layer 33 is formed thereon. Further, an on-chip color filter 34 and an on-chip microlens 35 are formed on the multilayer wiring layer 33 through a planarizing film to obtain a target MOS type solid-state imaging device 55.

  According to the method of manufacturing the solid-state imaging device according to the third embodiment, after forming the grooves 41 and 44, the width of the insulating film 61 made of the silicon nitride film is narrowed in the process of FIG. 41 and 44 are subjected to side wall oxidation. That is, the oxide film 71 is formed by oxidizing the side walls of the trenches 41 and 44 using the narrowed insulating film 61 as a mask. By this selective oxidation, an oxide film 71a having a bird's beak shape in which the oxide film is raised is formed at the corner portion above the groove. This oxide film 71a corresponds to the bird's beak-like insulating layer 42a of FIG. Then, since the first and second element isolation parts 43 and 45 are formed by embedding the insulating layer 42 in the grooves 41 and 44, divots generated in the element isolation part having a normal STI structure can be reduced.

  Since the divot can be suppressed, in the pixel transistor or the MOS transistor in the peripheral circuit portion, although the film quality is inferior to that of the gate oxide film in the central portion, the poor quality of the insulating layer in the isolation edge portion can be improved. By eliminating the divot, parasitic channel components can be reduced and random noise can be reduced.

  Further, the side wall oxidation can round the upper and lower corner portions of the grooves 41 and 44. A surface with a gentle curvature is formed at the upper corner of the groove. Thereby, the stress of the upper corner part in the element isolation parts 43 and 45 of the STI structure can be reduced. In the pixel portion, dark current and white spots caused by the floating diffusion (FD) portion of the pixel can be improved.

  In order to suppress dark current and white spots in the step of FIG. 22D, the p-type semiconductor layer 49 is formed by ion implantation. At this time, the p-type semiconductor layer 49 is formed from the trench sidewall to the lateral direction of the substrate surface. . Since the p-type semiconductor layer 49 is formed so as to extend in the lateral direction on the surface of the upper portion of the trench 44 on the active region side, the degree of freedom for further improving the dark current and the white point can be increased.

  Since the p-type semiconductor layer 49 is formed so as to extend from the upper part of the groove to the substrate surface side, the concentration of the p-type semiconductor layer 49 at the edge part of the upper part of the groove is increased. Thereby, for example, the parasitic channel component of the edge portion in contact with the element isolation portion of the pixel transistor shown in FIG. 9 can be further reduced. Together with the improvement of the divot, the random noise can be improved synergistically.

  In addition, the same effects as described in the method for manufacturing the solid-state imaging device according to the first and second embodiments can be obtained.

The present invention can be applied to both a front-illuminated solid-state imaging device and a back-illuminated solid-state imaging device. As described above, the CMOS solid-state imaging device can be applied to the front side irradiation type in which light is incident from the multilayer wiring layer side and the back side irradiation type in which light is incident from the back surface of the substrate opposite to the multilayer wiring layer.
The solid-state imaging device according to the present invention can be applied to a linear image sensor or the like in addition to the above-described area image sensor.

  The solid-state imaging device according to the present invention can be applied to electronic devices such as a camera equipped with a solid-state imaging device, a portable device with a camera, and other devices equipped with a solid-state imaging device.

  FIG. 26 shows an embodiment applied to a camera as an example of the electronic apparatus of the present invention. The camera 80 according to the present embodiment includes an optical system (optical lens) 81, a solid-state imaging device 82, and a signal processing circuit 83. As the solid-state imaging device 82, any one of the above-described embodiments is applied. The optical system 81 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device. Thereby, signal charges are accumulated in the photoelectric conversion element of the solid-state imaging device 82 for a certain period. The signal processing circuit 83 performs various signal processing on the output signal of the solid-state imaging device 82 and outputs the processed signal. The camera 80 according to the present embodiment includes a camera module in which an optical system 81, a solid-state imaging device 82, and a signal processing circuit 83 are modularized.

The present invention can constitute the camera shown in FIG. 26 or a camera-equipped portable device such as a mobile phone provided with a camera module.
Furthermore, the configuration of FIG. 26 can be configured as a module having an imaging function in which the optical system 81, the solid-state imaging device 82, and the signal processing circuit 83 are modularized, a so-called imaging function module. The present invention can constitute an electronic apparatus provided with such an imaging function module.

  According to the electronic device according to this embodiment, the pixel characteristics of the solid-state imaging device are excellent, high image quality is obtained, and a high-performance electronic device can be provided.

  In the above example, the case where the present invention is applied to a solid-state imaging device in which a plurality of unit pixels each including one photodiode and a plurality of pixel transistors are arranged has been described. However, the solid-state imaging device of the present invention can also be applied to a solid-state imaging device in which a plurality of so-called shared pixels including a plurality of transistors and transfer transistors and one other pixel transistor are arranged.

It is a block diagram which shows an example of the solid-state imaging device to which this invention is applied. It is a schematic block diagram of the principal part of the solid-state imaging device which concerns on 1st Embodiment of this invention. It is an expanded sectional view of a photoelectric conversion element. It is a schematic block diagram of the principal part of the solid-state imaging device which concerns on 2nd Embodiment of this invention. It is a schematic block diagram of the principal part of the solid-state imaging device which concerns on 3rd Embodiment of this invention. It is a schematic block diagram of the principal part of the solid-state imaging device which concerns on 4th Embodiment of this invention. It is a schematic block diagram of the principal part of the solid-state imaging device which concerns on 5th Embodiment of this invention. It is an expanded sectional view of the element isolation part of the STI structure of the pixel part which concerns on 5th Embodiment. It is a schematic plan view of the pixel transistor used for description of the fifth embodiment. It is an expanded sectional view of the STI element isolation | separation part for a comparison. 1A and 1B are manufacturing process diagrams (part 1) illustrating a first embodiment of a method for manufacturing a solid-state imaging device according to the present invention. C and D are manufacturing process diagrams (part 2) illustrating the first embodiment of the method of manufacturing the solid-state imaging device according to the present invention. E and F are manufacturing process diagrams (part 3) illustrating the first embodiment of the method of manufacturing the solid-state imaging device according to the present invention. G and H are manufacturing process diagrams (part 4) illustrating the first embodiment of the method of manufacturing the solid-state imaging device according to the present invention. I and J are manufacturing process diagrams (part 5) illustrating the first embodiment of the method of manufacturing the solid-state imaging device according to the present invention. FIGS. 9A and 9B are manufacturing process diagrams (part 1) illustrating a second embodiment of a method for manufacturing a solid-state imaging device according to the present invention. FIGS. C and D are manufacturing process diagrams (part 2) illustrating the second embodiment of the method of manufacturing the solid-state imaging device according to the present invention. E and F are manufacturing process diagrams (part 3) illustrating the second embodiment of the method of manufacturing the solid-state imaging device according to the present invention. G and H are manufacturing process diagrams (part 4) showing the second embodiment of the method of manufacturing the solid-state imaging device according to the present invention. It is a manufacturing process figure (the 5) which shows 2nd Embodiment of the manufacturing method of the solid-state imaging device which concerns on this invention. A and B are manufacturing process diagrams (part 1) showing a third embodiment of the method of manufacturing the solid-state imaging device according to the present invention. C and D are manufacturing process diagrams (part 2) illustrating the third embodiment of the method of manufacturing the solid-state imaging device according to the present invention. It is a manufacturing process figure (the 3) which shows 3rd Embodiment of the manufacturing method of the solid-state imaging device which concerns on this invention. FIG. 22C is an enlarged cross-sectional view of FIG. 22C. FIG. 22D is an enlarged cross-sectional view of FIG. 22D. It is a schematic block diagram at the time of applying the electronic device which concerns on this invention to a camera. It is a schematic block diagram of the solid-state imaging device concerning a prior art example. A and B are a plan view of a pixel and a cross-sectional view taken along the line AA for explaining a conventional problem.

Explanation of symbols

  1 ..Solid-state imaging device, 21, 48, 51, 54, 55 ..Solid-state imaging device, 22 ..Semiconductor substrate, 23 ..Pixel unit, 24 ..Peripheral circuit unit, 25. Photoelectric conversion element 27... Pixel transistor 41, 44... Groove, 42.. Insulating layer 43.. First element isolation part 45.. Second element isolation part 31.・ Multi-layer wiring, 33 ..Multi-layer wiring layer, 34 .. On-chip color filter, 35 ..On-chip microlens, 49 ..p-type semiconductor layer, 52 ..p-type semiconductor layer, 71. ··Electronics

Claims (19)

A pixel portion;
A peripheral circuit section;
A first element isolation part having an STI structure formed on a semiconductor substrate of the peripheral circuit part;
The portion formed in the semiconductor substrate of the pixel portion and embedded in the semiconductor substrate is shallower than the portion embedded in the semiconductor substrate of the first element isolation portion, and the surface height is the same as that of the first element isolation portion. A solid-state imaging device having a second element isolation unit having the same STI structure. The solid-state imaging device according to claim 1, further comprising an impurity implantation region formed at an interface contacting the photoelectric conversion element of the second element isolation unit and the pixel unit. The solid-state imaging device according to claim 2, wherein a protrusion height from the substrate surface of the first element isolation part and the second element isolation part is 0 to 40 nm. The depth of the portion embedded in the semiconductor substrate of the second element isolation part is 50 nm to 160 nm,
The solid-state imaging device according to claim 3, wherein a total thickness of the second element separation unit is 70 nm to 200 nm. The solid-state imaging device according to claim 1, wherein a part of the photoelectric conversion element extends below the second element separation unit. 2. The solid-state imaging device according to claim 1, further comprising: a bird's beak-like insulating portion at a portion of the first element separation portion and the second element separation portion that are in contact with a surface of the semiconductor substrate. The solid-state imaging device according to claim 6, further comprising an impurity implantation region for suppressing dark current from an interface between the second element isolation portion and the semiconductor substrate to a part on a surface side of the semiconductor substrate. Forming a first groove in a portion of the peripheral circuit portion of the semiconductor substrate where the element isolation portion is to be formed and a second groove shallower than the first groove in a portion of the pixel portion where the element isolation portion is to be formed; When,
Forming an insulating layer including in the first and second grooves;
Polishing the insulating layer to form a first element isolation part and a second element isolation part having the same surface height. A method for manufacturing a solid-state imaging device. In the chemical mechanical polishing step,
The method for manufacturing a solid-state imaging device according to claim 8, wherein the insulating layer is polished so that a protruding height of the first element isolation part and the second element isolation part from the substrate is 0 to 40 nm. The depth of the insulating layer in the groove is 50 nm to 160 nm,
The method for manufacturing a solid-state imaging device according to claim 9, wherein the second groove is formed so that a total thickness of the insulating layer is 70 nm to 200 nm. Forming the first groove or the second groove;
The method for manufacturing a solid-state imaging device according to claim 8, further comprising: forming the second groove or the first groove. Forming first and second grooves of the same depth by a simultaneous etching process;
The method for manufacturing a solid-state imaging device according to claim 8, further comprising a step of forming a first groove deeper than the second groove by etching. After the step of forming the first groove and the second groove using the nitride film as a mask,
Reducing the width of the mask;
Oxidation treatment or oxynitridation treatment is performed through the narrowed mask, and an oxide film or an oxynitride film is formed on the inner surfaces of the first groove and the second groove and on the surface of the semiconductor substrate where the mask is not formed. The method for manufacturing a solid-state imaging device according to claim 8, further comprising a forming step. After the step of forming the oxide film,
Introducing a required impurity through the mask and forming an impurity implantation region for dark current suppression from the interface between the second element isolation part and the semiconductor substrate to a part of the surface side of the semiconductor substrate; A method for manufacturing a solid-state imaging device according to claim 13. A solid-state imaging device;
An optical system for guiding incident light to the photoelectric conversion element of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device;
The solid-state imaging device
A pixel portion;
A peripheral circuit section;
A first element isolation part having an STI structure formed on a semiconductor substrate of the peripheral circuit part;
A portion formed in the semiconductor substrate of the pixel portion and embedded in the semiconductor substrate is shallower than a portion embedded in the semiconductor substrate of the first element isolation portion, and a surface height is the same as that of the first isolation element portion. A second element isolation portion having the same STI structure. The electronic device according to claim 15, further comprising: an impurity implantation region formed near an interface in contact with the photoelectric conversion element of the pixel unit and the second element separation unit in the solid-state imaging device. The electronic apparatus according to claim 16, wherein a part of the photoelectric conversion element in the solid-state imaging device is extended below the second element separation unit. The electronic device according to claim 15, further comprising: a bird's beak-like insulating portion in a portion of the solid-state imaging device in contact with the surface of the semiconductor substrate of the first element separation portion and the second element separation portion. 19. The electronic device according to claim 18, further comprising: an impurity implantation region for suppressing dark current from an interface between the second element isolation unit and the semiconductor substrate in the solid-state imaging device to a part on a surface side of the semiconductor substrate.

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