JP2009283819A - Semiconductor device producing method, semiconductor device, electrooptical device, and electronic apparatus - Google Patents

Abstract

A manufacturing method and device configuration capable of improving characteristics in a three-dimensional semiconductor device are provided.
A step of forming a plug electrode (15) including carbon nanotubes on a first semiconductor film (9), and a step of forming an interlayer insulating film (16, 18) around the formed plug electrode (15). Smoothing the surface of the interlayer insulating film to expose the top of the plug electrode (15); forming an amorphous second semiconductor film on the top of the interlayer insulating film and the plug electrode; (2) A step of supplying energy to the semiconductor film to cause the plug electrode (15) exposed to function as a catalyst to crystallize the amorphous second semiconductor film to obtain a crystallized second semiconductor film (23).
[Selection] Figure 7

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a plurality of semiconductor films are stacked, a semiconductor device, and the like, and more particularly, to an invention that uses carbon nanotubes as plug electrodes that connect a lower semiconductor film and an upper semiconductor film. is there.

In the electro-optical device such as a liquid crystal device or an organic EL (E lectro L uminescence) device, as a transistor for pixel driving, or a thin film transistor as a drive circuit for driving the panel (TFT: T hin F ilm T ransistor) is used It has been.

  Since these devices have the merit that an inexpensive substrate having low heat resistance can be used by being manufactured by a low temperature process, various thin film transistor manufacturing methods using a low temperature process have been developed.

In particular, the technique described in Patent Document 1 below by the present inventors is a low-temperature semiconductor device having a three-dimensional structure in which a plurality of semiconductor films (semiconductor devices) are stacked (hereinafter also referred to as “three-dimensional semiconductor device”). It is an effective method of forming by a process. According to the invention, in addition to the merit of using the low temperature process, the merit of the three-dimensional semiconductor device such as the reduction of wiring delay and the reduction of the chip area of the semiconductor device can be enjoyed.
JP 2006-310741 A

  However, as will be described in detail later in the embodiment of the present specification, when the upper semiconductor film which is indispensable in the low temperature process is crystallized by laser irradiation, the upper semiconductor film and the lower semiconductor film are connected. As a result, the plug electrode metal diffuses into the semiconductor film, which hinders crystallization of the upper semiconductor film and may deteriorate transistor characteristics. In addition, silicide with volume expansion is formed between the plug electrode and the silicon constituting the upper semiconductor film, and a change in the volume causes voids and increases the contact resistance.

  Accordingly, an object of the present invention is to provide a manufacturing method and a device configuration that can improve the characteristics of a three-dimensional semiconductor device.

  (1-1) In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plurality of semiconductor films are stacked, and includes carbon nanotubes on the first semiconductor film. A step of forming a plug electrode, a step of forming an interlayer insulating film around the formed plug electrode, a step of smoothing the surface of the interlayer insulating film to expose the top of the plug electrode, and the interlayer insulating film and the plug electrode Forming an amorphous second semiconductor film on the top of the first semiconductor film, and supplying the energy to the amorphous second semiconductor film so that the exposed plug electrode functions as a catalyst to form an amorphous second semiconductor film And crystallization step.

  This invention has been conceived by the present inventor based on the discovery that when an amorphous semiconductor film is brought into contact with carbon nanotubes and energy is applied, the amorphous semiconductor film crystallizes. Since the structure of the carbon nanotube after crystallization of the semiconductor film is not changed, the carbon nanotube is considered to function as a so-called catalyst in the present invention. According to the present invention, in manufacturing a three-dimensional semiconductor device having a three-dimensional structure in which a plurality of semiconductor films are stacked, a plug electrode made of carbon nanotubes is formed on the first semiconductor film, and the plug electrode made of carbon nanotubes An amorphous second semiconductor film is formed in contact with. If energy is supplied to the amorphous second semiconductor film in this state, the carbon nanotubes function as a catalyst, and the amorphous second semiconductor film is crystallized to function as a functional film such as a transistor. Is possible.

  According to the present invention, since the carbon nanotube only functions as a catalyst, the problem that the carbon nanotube diffuses into the semiconductor film and inhibits crystallization of the semiconductor film does not occur. Further, according to the present invention, since the compound with the composition of the semiconductor film is not generated by using the carbon nanotube, the volume of the semiconductor film is not changed, and the semiconductor film is increased in accordance with the increase in contact resistance. The problem of characteristic deterioration does not occur.

(1-2) The semiconductor device of the present invention formed by the above manufacturing method is formed around the first semiconductor film, the plug electrode formed of the carbon nanotube formed on the first semiconductor film, and the periphery of the electrode. And a second semiconductor film formed on the interlayer insulating film and connected to the plug electrode, and the second semiconductor film is crystallized by causing the plug electrode to function as a catalyst. It is characterized by that.
In the semiconductor device of this invention, if the crystal structure of the second semiconductor film is analyzed, it can be confirmed that the second semiconductor film is crystallized by the function of the carbon nanotubes forming the plug electrode as a catalyst. .

Specifically, the present invention can include the following aspects.
(1-3) First, in the method for manufacturing a semiconductor device of the present invention, a step of forming a metal layer for growing carbon nanotubes on the first semiconductor film, and a high-frequency plasma is applied to the metal layer to cause nuclei in the metal layer. It is preferable to include a step of forming and a step of growing a carbon nanotube from the metal layer to form a plug electrode.

  According to this invention, when high frequency plasma is applied, nuclei are formed in the metal layer by the energy, and the structure of carbon nanotubes grows from the nuclei of the metal layer by maintaining the atmosphere in which the carbon nanotubes are grown. A plug electrode having conductivity is formed.

(1-4) Here, the metal layer is preferably a metal selected from the group consisting of nickel, cobalt, and iron.
Such a metal is a metal that has been identified as a metal that forms a nucleus capable of growing carbon nanotubes.

The present invention can preferably include the following steps and configurations.
(2-1) First, the manufacturing method of the present invention includes a step of forming an amorphous first semiconductor film on a translucent substrate before a step of forming a plug electrode on the first semiconductor film. After the step of forming the plug electrode, energy is supplied to the amorphous first semiconductor film from the back side of the light-transmitting substrate so that the plug electrode in contact with the first semiconductor film functions as a catalyst. A step of crystallizing the crystalline first semiconductor film can be provided.

  According to this invention, since the translucent substrate is used, the plug is formed by supplying energy from the back surface of the translucent substrate after forming the amorphous first semiconductor film and forming the plug electrode. The amorphous first semiconductor film can be crystallized by using the electrode as a catalyst. Therefore, even in the lowermost semiconductor film, the semiconductor film can be crystallized by using the carbon nanotube as a catalyst.

(2-2) In the semiconductor device of the present invention formed by the above manufacturing method, the first semiconductor film is crystallized by using the plug electrode as a catalyst.
According to this invention, when the crystal structure of the first semiconductor film is analyzed, it can be confirmed that the first semiconductor film is crystallized by the function of the carbon nanotube forming the plug electrode as a catalyst.
(2-3) In the semiconductor device formed according to the present invention, when the first semiconductor film is crystallized using the catalytic function of the carbon nanotube, the main crystal plane orientation of the first semiconductor film and the second semiconductor The main crystal plane orientation of the film is the same.
Since the semiconductor film is crystallized by utilizing the catalytic function of the plug electrode formed of the same carbon nanotube, the crystal plane orientation which is the crystal structure becomes the same.

(1/2) Here, the energy for crystallizing the first and / or second semiconductor film is preferably supplied by irradiating with laser light.
This invention is based on the fact that it has been confirmed that by irradiating laser light, the plug electrode of the carbon nanotube functions as a catalyst and the semiconductor film in contact with the plug electrode can be crystallized.

(3) In the present invention, after the step of crystallizing the second semiconductor film, it is possible to stack three or more semiconductor films connected to the plug electrode by repeating the above semiconductor device manufacturing method one or more times. It is.
Since the second semiconductor film formed on the first semiconductor film can be crystallized by applying the semiconductor device manufacturing method, a plug electrode is further formed on the crystallized second semiconductor film. As described above, if the semiconductor device manufacturing method is repeated a plurality of times, a semiconductor film having three or more layers can be formed.

(4) In this invention, the process of forming the semiconductor device containing each semiconductor film can be included.
The purpose is to apply a conventional technique to each semiconductor film and to individually manufacture a semiconductor device. Which semiconductor film is formed on the semiconductor device is arbitrary, whether the semiconductor device is formed only on the second semiconductor film, the semiconductor device is formed only on the first semiconductor film, or on both semiconductor films. A semiconductor device may be formed.

  (5) The present invention is also a semiconductor device manufactured by the method for manufacturing a semiconductor device described above, or an electro-optical device or an electronic apparatus having the semiconductor device described above.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.
In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.

(Definition)
Some terms in this specification are defined as follows.
“Semiconductor film”: refers to a film containing a semiconductor element as a main component and includes not only a crystallized semiconductor but also an amorphous semiconductor before crystallizing. As the “semiconductor”, silicon (Si) is exemplified in the following embodiments, but other semiconductor elements such as germanium may be used as long as they can be crystallized by the catalytic function of the carbon nanotube.

  “Carbon nanotube”: A fine tube formed from carbon. Usually, a hexagonal, pentagonal, and heptagonal polygonal mesh structure is provided, but the structure is not limited. This includes the case of a composite having conductivity by including organic molecules or the like inside the tube. There are armchair type with metallic properties and zigzag type / spiral type with semiconductor properties. It does not matter whether it is a single wall (single layer) type or a multi wall (multilayer) type. The case where a predetermined molecule, for example, an organic molecule is contained inside is also included.

  “Plug electrode” means a columnar electrode that connects a lower semiconductor film and an upper semiconductor film or metal layer.

  “Smoothing”: treatment for smoothing the surface of the insulating film, and includes polishing by applying a CMP (Chemical Mechanical Polishing) method, etching back, etc.

  “Energy”: Power given to crystallize the semiconductor film, including the case where it is applied not only by laser irradiation but also by supply of heat or electromagnetic waves.

  “Metal layer”: a metal element that has been confirmed to grow carbon nanotubes, and includes nickel, cobalt, or iron. However, any element that can grow carbon nanotubes is applicable to the present invention without being limited to metals.

  “Semiconductor device”: refers to an element for realizing a predetermined function of a semiconductor film, and examples thereof include a functional element configured using a thin film such as a thin film transistor (TFT) or a thin film diode.

  “Function as a catalyst”: A function that causes a physical or chemical effect on another composition without being physically or chemically changed by itself.

  “Electro-optical device”: A general device equipped with an electro-optical element that emits light by electrical action or changes the state of light from the outside. Both the device that emits light and the device that controls the passage of light from the outside. including. Examples of the electro-optical element include a liquid crystal element, an electrophoretic element, an EL (electroluminescence) element, and an electron-emitting element that emits light by applying electrons generated by applying an electric field to a light-emitting plate.

  “Electronic device”: A general device that exhibits a certain function by a combination of a plurality of elements or circuits, and includes, for example, an electro-optical device and a memory. Here, the electronic device can include one or more circuit boards. The configuration is not particularly limited, but for example, a mobile phone, a wristwatch, a personal computer, an IC card, a video camera, a head mounted display, a rear type or a front type projector, a fax machine with a display function, a digital camera finder, a mobile phone Type TV, DSP device, PDA, electronic notebook, electric bulletin board, display for public notice, etc.

(Principle explanation)
As described in the above definition, the carbon nanotube is a fine tube having a diameter of 0.4 to 100 nm, for example, obtained by forming a network structure in which carbon atoms have a predetermined shape. The inventor of the present application discovered that an amorphous semiconductor film can be crystallized by bringing an amorphous semiconductor film into contact with the carbon nanotubes and applying energy. Since this crystallization does not cause a physical or chemical change in the carbon nanotube, it can be said that the carbon nanotube functions as a catalyst.

  The reason why carbon nanotubes can crystallize a semiconductor film can be considered as follows, for example. When the lattice constant of the polygonal structure of carbon atoms constituting the carbon nanotube is slightly different from the lattice constant in the crystal of the semiconductor film, this lattice constant mismatch makes it strong against the semiconductor film that grows the crystal with the carbon nanotube as the nucleus. Tensile stress will be generated. When such a tensile stress is generated, the energy required for crystallization of the semiconductor film may be reduced due to the free energy, and in such a case, an amorphous (solid or liquid phase) semiconductor It is conceivable that the crystallization of the film proceeds easily.

  For example, in the case where the semiconductor film is silicon, the lattice constant of a diamond-type crystal of silicon is 0.543 nm. On the other hand, a carbon nanotube called an armchair type has a polygonal lattice constant composed of carbon atoms of 0.2454 nm. At this time, if silicon is crystal-grown like heteroepitaxy at a pitch twice the lattice constant of the armchair carbon nanotube, it is considered that there is a lattice mismatch of about 9.6%. If there is such a lattice mismatch, it is considered that a strong tensile stress is introduced into the silicon crystal that grows, and this crystallization promotes crystallization.

  Carbon nanotubes are easy to insert organic molecules into the structure, and become very stable once organic molecules having a size close to the inner diameter of the nanotubes are inserted. It has been reported that by inserting organic molecules, carriers are supplied from the inserted organic molecules to the nanotubes, and the electrical conductivity can be controlled.

  Hereinafter, Embodiment 1 exemplifies a manufacturing method in which a plug electrode made of carbon nanotubes is formed on a first semiconductor film, and the plug electrode functions as a catalyst to crystallize an amorphous second semiconductor film. Further, Embodiment 2 exemplifies a manufacturing method in which a first semiconductor film is formed on a light-transmitting substrate, carbon nanotubes are formed, and then the carbon nanotubes are functioned as a catalyst to crystallize the first semiconductor film.

(Embodiment 1)
Embodiment 1 relates to a method for manufacturing a semiconductor device in which a plug electrode formed on a first semiconductor film functions as a catalyst, and a second semiconductor film is crystallized.
1 to 6 are manufacturing process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. The first method for manufacturing a semiconductor device according to the first embodiment includes the following steps.

1) a step of forming a first semiconductor device 10 including the first semiconductor film 9 (FIG. 1);
2) a step of forming a plug electrode 15 of carbon nanotubes on the first semiconductor film 9 (FIG. 2);
3) Step of forming an interlayer insulating film 16 around the formed plug electrode 15 (FIG. 3A),
4) Smoothing the surface of the interlayer insulating film 16 to expose the top of the plug electrode 15 (FIG. 3B),
5) A step of forming an amorphous second semiconductor film 22 on top of the interlayer insulating film 16 and the plug electrode 15 (FIGS. 3C to 5),
6) A step of crystallizing the amorphous second semiconductor film 22 by supplying energy to the amorphous second semiconductor film 22 to cause the exposed plug electrode 15 to function as a catalyst (FIG. 6).
This will be described in detail below.

(First semiconductor device forming step)
First, the first semiconductor device is formed by applying a conventional lithography method or the like. An example of the first semiconductor device is a thin film transistor (TFT). This semiconductor device forming step is optional, and if it is not necessary to provide a semiconductor device using the first semiconductor film on the lower layer side, the steps after the formation of the first semiconductor film are unnecessary.
As shown in FIG. 1A, amorphous silicon is deposited on a predetermined substrate (glass substrate, quartz glass substrate) 1 to form an amorphous silicon film. The thickness of the amorphous silicon film is arbitrary. As the forming method, various CVD (chemical vapor deposition, C hemical V apor D eposition) method, a sputtering method, an evaporation method can be applied. For example, using the LPCVD (L ow P ressure C hemical V apor D eposition) process, silane at a substrate temperature of 545 ℃ (SiH ₄₎ may be deposited amorphous silicon film of approximately 50nm by introducing gas .

  Optionally, a base insulating film may be formed between the substrate 1 and the amorphous silicon film. This base insulating film is made of, for example, a silicon oxide film and can be formed by a plasma CVD method.

Next, the amorphous silicon film is separated from other elements to form island-like first semiconductor films 3 for one semiconductor device. For example, a photoresist film is formed on an amorphous silicon film, and exposed and developed to leave the photoresist film in an island shape. Next, an island-shaped silicon film is formed by dry etching using the remaining photoresist film as a mask. Thereafter, the remaining photoresist film is removed by ashing. A series of steps from formation of the photoresist, exposure / development and resist removal is referred to as “patterning”. Such a separation method is called a mesa separation method. Besides the mesa isolation method, it is possible to apply such LOCOS (Loc al O xidation of S ilicon) method or trench isolation method.

Next, as shown in FIG. 1B, a gate insulating film 5 is formed over the first semiconductor film 3. The film thickness of the gate insulating film 5 is arbitrary. As a method for forming the gate insulating film 5, various insulating film forming methods such as a thermal oxidation method and a CVD method can be applied. For example, the surface of the first semiconductor film 3 is subjected to predetermined conditions, for example, using a mixed gas of oxygen and krypton Kr (gas volume ratio, oxygen O ₂ : Kr = 3: 97), pressure 1 torr, power 3 kW, substrate temperature 400 By performing plasma oxidation under the condition of ° C., the gate insulating film 5 made of silicon oxide having a thickness of about 5 nm can be formed.

  Next, as shown in FIG. 1C, a gate electrode 7 is formed on the gate insulating film 5, and impurity ions are implanted (doped) into the first semiconductor film 3 using the gate electrode 7 as a mask. A drain region 9 is formed. The gate electrode 7 can have a single-layer structure or a multi-layer structure using tantalum (Ta), tantalum nitride (TaN), or the like as an electrode material. The gate electrode 7 is formed by uniformly forming a metal film by vapor deposition or sputtering, and then patterning the metal film using photolithography. Next, source / drain regions 9 which are high concentration impurity regions are formed by implanting impurity ions. The first semiconductor film 3 between the source and drain regions 9 becomes a channel region. The impurity ions to be implanted are n-type impurities (for example, phosphorus) when an n-channel TFT is formed, and p-type impurities (for example, boron) when a p-channel TFT is formed. Inject. Note that impurities such as threshold adjustment impurities may be implanted in addition to the impurities forming the source and drain regions.

Note that when the impurity concentration by introducing the impurity ions after forming the sidewall to the gate electrode to form a different region in the semiconductor film, the LDD (L ightly D oped D rain ) current leakage preventing structure such as a structure A semiconductor device having the same may be formed.

Optionally, a silicide film 6 is formed on the source / drain region 9. For example, a nickel (Ni) film is deposited on the first semiconductor film 3 by a sputtering method, and heat treatment is performed, thereby forming nickel silicide at the contact portion between the nickel film and the first semiconductor film 3 made of silicon. This silicide film 6 is formed to reduce contact resistance. It is preferable to remove the unreacted Ni film.
Through the above steps, the first semiconductor device 10 that is a thin film transistor is formed.

(Plug electrode formation process)
Next, the plug electrode 15 is formed on the first semiconductor film.
First, as shown in FIG. 2A, a metal layer 11 is formed at a position where a plug electrode is to be disposed with respect to the source / drain region 9 and the gate electrode 7.

  The metal layer 11 is a catalyst layer for growing carbon nanotubes, and nickel is exemplified as the metal material. The thickness of the metal layer 11 is sufficient as long as it can be a nucleus for forming carbon nanotubes. As a method for forming the metal layer 11, various metal film forming methods can be applied. For example, under the conditions of a substrate temperature of 200 ° C., an argon gas of 100%, and a pressure of 15 mtorr, a nickel film is formed to about 8 nm by applying a sputtering method with a power of 1 kW.

  After the formation of the metal layer, patterning is performed to pattern the layer in the carbon nanotube formation region. That is, the pattern of the metal layer 11 is formed on the silicide film 6 on the source / drain region 9 and the plug electrode installation position on the gate electrode 7. However, it is not necessary to form all the electrodes with carbon nanotubes. For example, only one or both of the source and drain electrodes may be carbon nanotube plug electrodes, and the gate may be a plug electrode made of a normal metal material. More specifically, the metal layer 11 to be a contact region of the plug electrode is formed by patterning to a diameter necessary for the growth of the carbon nanotube, for example, 1 μm. As an etching solution for patterning, for example, a mixed acid of nitric acid (65%): sulfuric acid (98%): acetic acid: water in a ratio of 5: 5: 2: 28 can be used at room temperature.

  Next, as shown in FIG. 2B, high-frequency plasma is applied to form nuclei in the metal layer 11. The high frequency plasma is applied under predetermined conditions suitable for the growth of carbon nanotubes. For example, using a high-frequency plasma CVD apparatus, the high-frequency plasma 13 is applied for a predetermined time under the conditions of a substrate temperature of 400 ° C., an ammonia atmosphere, a pressure of 0.64 torr, and an applied power of 90 W. By this treatment, the metal layer 11 is converted to have nanometer-sized island-like nuclei.

  If nickel silicide nuclei capable of forming carbon nanotubes directly on the surface of the silicide film 6 are formed, this step is unnecessary. Further, when carbon nanotubes can be grown without applying high frequency plasma to the metal layer, it is not necessary to apply high frequency plasma.

Next, as shown in FIG. 2C, carbon nanotubes are grown in a predetermined atmosphere to form plug electrodes 15. It is known that carbon nanotubes can be grown by a CVD method using a gas containing carbon atoms (for example, methane). For example, PECVD (P lasma- e nhanced P hysical V apor D eposition) introducing a predetermined concentration of methane and hydrogen gas in the apparatus (e.g. methane 10 sccm, hydrogen 100 sccm), pressure 0.9 Torr, under the conditions of applied power 50 W 20 By maintaining for a minute, it is possible to grow carbon nanotubes to a certain height. At this time, the ambient temperature is about 400 ° C. The growth conditions and growth time can be determined by the required length of the plug electrode 15. Organic molecules may be inserted into the carbon nanotubes during the growth process. In addition, a carbon nanotube may be formed by applying a laser evaporation method.

(Interlayer insulation film formation process)
In this embodiment, as will be described below, the plug electrode 15 connected to the gate electrode 7 and the drain region 9 among the three plug electrodes 15 is connected to the wiring 17 and the plug connected to the source region 9 is connected. The description will be made assuming that the electrode 15 is connected to the upper second semiconductor film. However, plug electrodes for other gate electrodes and drain electrodes may be connected to the upper second semiconductor film. An arbitrary electrode connection structure may be selected depending on the wiring structure between the upper and lower semiconductor devices.

First, as shown in FIG. 3A, an interlayer insulating film 16 is formed around the plug electrode 15. The thickness of the interlayer insulating film 16 depends on the height of the plug electrode 15, but is thick enough to sufficiently insulate the upper and lower semiconductor films and does not increase the smoothing time. The thickness is within the range. As a method for forming the interlayer insulating film 16, a normal insulating film forming method can be applied. For example, the plug electrodes 15 at a predetermined condition to form an interlayer insulating film to a thickness enough to hide all using TEOS (t etra e th o xy s ilane).

  Next, as shown in FIG. 3B, the surface of the interlayer insulating film 16 is smoothed by a predetermined method. Various smoothing methods are conceivable. For example, a polishing method such as a CMP method and an etching method are conceivable. For example, when applying the CMP method, the polishing load, the rotation speed of the surface plate, the rotation speed of the head, the method of selecting and supplying the slurry, the condition and frequency of conditioning, etc. are appropriately set as control parameters of the CMP apparatus, and the interlayer Smooth the surface of the insulating film. It is sufficient to polish to such an extent that the surface of the plug electrode 15 is exposed. Preferably, in order to reliably bring out the surface of the carbon nanotube, an ashing method using oxygen or the like may be applied to remove the carbon nanotube residue.

  Next, as shown in FIG. 3C, a wiring 17 is formed so as to be in contact with the exposed plug electrode 15. A normal metal wiring forming method can be applied to the wiring 17. For example, after forming a metal layer such as aluminum, patterning is performed by a photolithography method based on the wiring pattern to form the wiring 17 for the plug electrode 15 connected to the gate electrode 7 and the drain region 9.

  Then, as shown in FIG. 4A, carbon nanotubes are grown again for the plug electrode 15 connected to the source region 9. The growth conditions are as described above.

  Next, as shown in FIG. 4B, an interlayer insulating film 18 is formed around the plug electrode 15 connected to the source region 9. The formation of the interlayer insulating film 18 is the same as that of the lower interlayer insulating film 16. That is, the interlayer insulating film 18 is formed using TEOS to such a thickness that the plug electrodes 15 are completely hidden under predetermined conditions.

(Smoothing process)
Next, as shown in FIG. 5A, the surface of the interlayer insulating film 18 is smoothed to expose the top of the plug electrode 15. Various smoothing methods such as a polishing method and an etching method are conceivable. For example, by applying a CMP method, polishing is performed until the top of the plug electrode 15 is visible. Details of the CMP method are as described above. As described above, the ashing method can be applied.

(Second semiconductor film forming step)
Next, as shown in FIG. 5B, an amorphous second semiconductor film 22 is formed on the smoothed interlayer insulating film 18 and the exposed tops of the plug electrodes 15. The thickness of the tragic second semiconductor film 22 is formed to a thickness that can function as a functional film of the thin film transistor. As a method for forming the amorphous second semiconductor film 22, various CVD methods, sputtering methods, and vapor deposition methods are applicable. For example, LPCVD (L ow P ressure C hemical V apor D eposition) process when using, under conditions to be introduced at 30sccm concentrations Si ₂ H ₆ gas at a substrate temperature of 425 ° C., 250 nm approximately amorphous silicon A film can be deposited.

(Second semiconductor film crystallization process)
Next, as shown in FIG. 6A, energy is supplied to the amorphous second semiconductor film 22 so that the plug electrode 15 functions as a catalyst to crystallize the second semiconductor film. As an energy source to be applied, various methods such as heating and light irradiation are conceivable. In order to crystallize a semiconductor film in a specific region, it is preferable to irradiate a laser beam. The intensity of the applied laser beam is set to a level necessary for crystallization of the semiconductor film. For example, when an excimer laser with a wavelength of 308 nm is used, irradiation is performed with an intensity of 1.5 J / cm ² .

  By this laser light irradiation, as shown in FIG. 6B, a crystal grows in an amorphous semiconductor film with the carbon atom structure at the top of the plug electrode 15 as a nucleus, and has a grain size of, for example, 5 μm or more. A crystallized second semiconductor film 23 having a single crystal can be formed.

(Second semiconductor device forming step)
Next, as shown in FIG. 7, a second semiconductor device 20 using the second semiconductor film 23 as a functional layer is formed. An example of the second semiconductor device is a thin film transistor (TFT). The second semiconductor device forming process is an optional process, and is an unnecessary process when it is not necessary to form a semiconductor device.

  As a specific manufacturing method of the second semiconductor device 20, various conventional semiconductor device manufacturing methods can be applied. For example, the gate insulating film 26 and the gate electrode 27 are formed on the second semiconductor film 23, and impurity ions are introduced into the second semiconductor film 23 using the gate electrode 27 as a mask to form the source / drain regions 29. The lower layer of the gate electrode 27 becomes a channel region. A silicide layer is formed on the source / drain region 29 by forming a nickel layer on the source / drain region 29 and applying heat treatment as necessary. Thus, the second semiconductor device 20 is formed.

Further, in the same manner as the manufacturing method applied to the first semiconductor device 10, an interlayer insulating film 30 is formed, and contact holes 31 are formed at the electrode formation positions of the source / drain regions 29 and the gate electrode 27 of the second semiconductor device 20. Then, a metal layer is formed and then patterned. By this process, the wiring 32 connected to the source / drain region 29 and the gate electrode 27 of the second semiconductor device 20 is formed. A protective layer 33 is formed on the interlayer insulating film 30 and the wiring 32 as necessary.
The three-dimensional semiconductor device 100 is manufactured by the above processing.

As described above, the first embodiment has the following advantages.
1) According to the first embodiment, since the carbon nanotube functions as a catalyst, it is possible to greatly promote the crystallization of the second semiconductor film as compared with the case of performing simple annealing.

  2) According to the first embodiment, since the carbon nanotubes constituting the plug electrode do not easily react with atoms (silicon) in the semiconductor film, a semiconductor compound (silicide) is not formed. No change in volume due to the occurrence of the above. For this reason, characteristic deterioration of the semiconductor film can be suppressed, and an increase in contact resistance between the plug electrode and the semiconductor film can be suppressed.

  3) According to the first embodiment, the carbon nanotube forming the plug electrode can be grown at a relatively low temperature, that is, a low temperature range of about 400 ° C., so that the semiconductor film in the lower layer is thermally grown in the process of forming the plug electrode. There is no possibility of adverse effects, and it is suitable as connection electrodes for the upper and lower layers of the three-dimensional semiconductor device.

  4) According to the first embodiment, the carbon nanotube forming the plug electrode has a very high melting point as compared with the metal material, and is therefore physically stable by heat during the process, and the electrode structure in the semiconductor film It is possible to prevent the material from diffusing and inhibiting crystallization.

  5) According to the first embodiment, the carbon nanotube forming the plug electrode has a very high thermal conductivity as compared with the metal material, so that it is surrounded by the interlayer insulating film or the semiconductor film, and is easy to store heat. It is also possible to function as a heat sink that dissipates heat from the inside of the semiconductor device.

  6) According to the first embodiment, the carbon nanotube forming the plug electrode has a very low electrical conductivity compared to the metal material, so that the amount of heat generated by the current flowing through the plug electrode is insignificant and the heat is reduced. It is possible to suppress the generation of heat itself inside the three-dimensional semiconductor device that is easy to measure.

  7) According to the first embodiment, since carbon nanotubes are grown by the CVD method after applying high frequency plasma to the metal layer 11 to form nuclei, the desired height can be easily and quickly. The plug electrode 15 can be formed.

(Embodiment 2)
The second embodiment relates to a method for manufacturing a semiconductor device in which a first semiconductor film on the lower layer side is also crystallized by using carbon nanotubes as a catalyst.

  Since the details of the layer structure and the manufacturing process in the second embodiment are the same as those in the first embodiment, the same steps and structures are denoted by the same reference numerals, and the description thereof is omitted.

  8 and 9 are cross-sectional views illustrating a manufacturing process for explaining the method of manufacturing the semiconductor device according to the first embodiment. The second method for manufacturing a semiconductor device according to the second embodiment includes the following steps.

1) a step of forming an amorphous first semiconductor film 2 on a translucent substrate 1a (FIG. 8A);
2) a step of forming the plug electrode 15 on the amorphous first semiconductor film 2 (FIGS. 8B and 8C);
3) Step of forming the gate insulating film 4 (FIG. 8D),
4) Step of crystallizing the amorphous first semiconductor film 2 by supplying energy from the back surface side of the translucent substrate 1a (FIGS. 8E and 9A),
5) First semiconductor device formation step (FIG. 9C).
This will be described in detail below.

(Amorphous first semiconductor film forming step)
First, as shown in FIG. 8A, an amorphous first semiconductor film 2 is formed on a translucent substrate 1a. The light-transmitting substrate 1a is desirably a substrate that has resistance to heat and mechanical resistance to handling in a semiconductor process and has a minimum attenuation rate of transmitted light. For example, a glass substrate or a quartz glass substrate can be used. The thickness of the translucent substrate 1a is determined in consideration of the light attenuation factor in addition to the heat resistance and durability.

Amorphous silicon is deposited on the translucent substrate 1a. The thickness of the amorphous silicon film is arbitrary. As the forming method, various CVD methods, sputtering methods, and vapor deposition methods can be applied. For example, an amorphous silicon film of about 50 nm can be deposited by introducing silane (SiH ₄ ) gas at a substrate temperature of 545 ° C. using LPCVD.

  Optionally, a base insulating film may be formed between the substrate 1 and the amorphous silicon film. This base insulating film is made of, for example, a silicon oxide film and can be formed by a plasma CVD method.

  Next, the amorphous silicon film is separated from other elements. For example, by applying a photolithography method, the amorphous silicon film is patterned to leave the island-shaped amorphous first semiconductor film 2. A LOCOS method, a trench isolation method, or the like may be applied.

(Plug electrode formation process)
Next, as shown in FIG. 8B, the metal layer 11 is formed in an island shape over the amorphous first semiconductor film. The material, thickness, and formation method of the metal layer are the same as those in the first embodiment. Optionally, high frequency plasma may be applied as described above to form nuclei in the metal layer 11. A silicide film may be formed on the first semiconductor film 2.

  Next, as shown in FIG. 8C, carbon nanotubes are grown in a predetermined atmosphere to form plug electrodes 15. The method of forming the carbon nanotube is the same as that in the first embodiment.

(Gate insulation film formation process)
Next, as shown in FIG. 8D, the gate insulating film 4 is formed when the carbon nanotubes are slightly grown. The method for forming the gate insulating film is the same as that in the first embodiment.

  In the case where the semiconductor device is not formed using the first semiconductor film, it is not necessary to perform this process, but after forming an interlayer insulating film to protect the plug electrode 15, laser irradiation described later is performed. It is preferable to do.

(First semiconductor film crystallization process)
Next, as shown in FIG. 8E, energy is supplied from the back surface side of the translucent substrate 1a so that the plug electrode 15 that is in contact with the first semiconductor film 2 functions as a catalyst, thereby forming an amorphous first semiconductor. The film 2 is crystallized. As an energy source to be applied, various methods such as heating and light irradiation are conceivable. In order to crystallize a semiconductor film in a specific region, it is preferable to irradiate the laser beam 8. The intensity of the applied laser beam is set to a level necessary for crystallization of the semiconductor film. For example, when an excimer laser with a wavelength of 308 nm is used, irradiation is performed with an intensity of 1.5 J / cm ² . By this process, crystallization of the first semiconductor film 2 is promoted using the plug electrode 15 in contact with the amorphous first semiconductor film 2 as a nucleus, and crystallized with a single crystal having a grain size of, for example, 5 μm or more. The first semiconductor film 3 can be formed (FIG. 9A).

(First semiconductor device forming step)
In this embodiment, in order to protect the plug electrode 15 formed of carbon nanotubes in the crystallization process of the first semiconductor film, two-stage plug electrode growth is performed in the following process. That is, after the plug electrode 15 is grown to the extent necessary for crystallization of the first semiconductor film (FIG. 8C), the gate insulating film 4 is once formed to protect the plug electrode 15 (FIG. 8D )) After the crystallization of the first semiconductor film (FIG. 8E, FIG. 9A), the plug electrode is grown again. Therefore, in addition to the first semiconductor device forming step, the method includes a gate insulating film smoothing step and a plug electrode re-forming step formed of carbon nanotubes. However, when it is not necessary to protect the carbon nanotubes, the smoothing process of the gate insulating film (FIG. 9C) and the plug electrode re-forming process (FIG. 9D) are unnecessary.

  First, as shown in FIG. 9B, a gate electrode 7 is formed on the gate insulating film 4, and impurity ions are introduced into the first semiconductor film 3 using the gate electrode 7 as a mask to form source / drain regions 9. The lower layer of the gate electrode 7 becomes a channel region. A silicide layer is formed on the source / drain region 9 by forming a nickel layer on the source / drain region 9 and performing heat treatment as necessary. Thus, the first semiconductor device 10 is formed.

  Next, as shown in FIG. 9C, the surface of the gate insulating film 4 is smoothed to expose the top of the plug electrode 15. Various smoothing methods such as a polishing method and an etching method are conceivable. For example, by applying a CMP method, polishing is performed until the top of the plug electrode 15 is visible. Details of the CMP method are as described above. As described above, the ashing method can be applied.

  Next, as shown in FIG. 9D, the exposed plug electrode 15 is further grown. After the plug electrode 15 is grown to a required height, an interlayer insulating film forming step, a smoothing step, a second semiconductor film forming step, a second semiconductor film crystallization step, etc. are performed as in the first embodiment. Thus, the second semiconductor device may be formed.

  As described above, according to the second embodiment, the laser light is irradiated from the back side of the translucent substrate, so that the plug electrode 15 formed of carbon nanotubes functions as a catalyst to crystallize the lower first semiconductor film 2. Can be promoted.

  According to the second embodiment, the lower first semiconductor film 2 is also crystallized by utilizing the catalytic function of the carbon nanotubes in the same manner as the upper second semiconductor film 23. Therefore, the main crystal plane orientation of the first semiconductor film and the first It is possible to make the main crystal plane orientation of the two semiconductor films the same. Therefore, the characteristics of the semiconductor film can be made uniform in the upper and lower layers. By repeating this process, it is possible to provide a three-dimensional semiconductor device including a semiconductor device having uniform characteristics.

(Embodiment 3)
Embodiment 3 of the present invention relates to an electro-optical device and an electronic apparatus including the three-dimensional semiconductor device manufactured by the manufacturing method of the above-described embodiment.

  FIG. 10 illustrates an example of an electronic device using an electro-optical device. FIG. 10A shows an application example to a mobile phone, and FIG. 10B shows an application example to a video camera. FIG. 10C illustrates an example of application to a television (TV), and FIG. 10D illustrates an example of application to a roll-up television.

  The three-dimensional semiconductor device manufactured by the manufacturing method of the above embodiment is used for, for example, an electro-optical device (display unit). Examples of electronic devices including the electro-optical device will be described below.

  As shown in FIG. 10A, the cellular phone 530 includes an antenna portion 531, an audio output portion 532, an audio input portion 533, an operation portion 534, and an electro-optical device (display portion) 500. The semiconductor device of the present invention can be incorporated in this electronic apparatus.

  As shown in FIG. 10B, the video camera 540 includes an image receiving unit 541, an operation unit 542, an audio input unit 543, and an electro-optical device (display unit) 500. The semiconductor device of the present invention can be incorporated in this electronic apparatus.

As shown in FIG. 10C, the television 550 includes an electro-optical device (display unit) 500. The semiconductor device of the present invention can be incorporated in this electronic apparatus.
Note that the semiconductor device of the present invention can also be incorporated in a monitor device (electro-optical device) used in a personal computer or the like.

  As shown in FIG. 10D, the roll-up television 560 includes an electro-optical device (display unit) 500. The semiconductor device of the present invention can be incorporated in this electronic apparatus.

  In addition to the above, the electronic apparatus having the electro-optical device includes a fax machine with a display function, a digital camera finder, a portable TV, an electronic notebook, an electric bulletin board, a display for advertisements, and the like.

(Modification)
The present invention is not limited to the above-described embodiment, and can be variously modified and applied. That is, the examples and application examples described through the above embodiment can be used in appropriate combination according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above embodiment. Is not to be done. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

  For example, in the above embodiment, the semiconductor device (thin film transistor) is formed for both the first semiconductor film and the second semiconductor film. However, the present invention is not limited to this. The lower semiconductor device and the upper semiconductor device may be of different types (for example, a thin film transistor and a diode).

  A semiconductor device may be formed only on one of the first semiconductor film and the second semiconductor film. For example, when a semiconductor device is formed only on the upper second semiconductor film, the lower first semiconductor film can function as a growth base, an electrode, and a heat sink of a plug electrode formed of carbon nanotubes. .

  Furthermore, in the above-described embodiment, a three-dimensional semiconductor device including three or more layers of semiconductor films is provided by repeating the semiconductor device manufacturing method after the second semiconductor film crystallization step or the second semiconductor device formation step. Is possible. Specifically, the method for manufacturing the semiconductor device can be repeated a plurality of times such that a plug electrode 15 is further formed on the crystallized second semiconductor film 23.

4A and 4B are cross-sectional views of a manufacturing process according to the first embodiment of the present invention, where FIG. 5A is a first semiconductor film forming process, FIG. 5B is a gate insulating film forming process, and FIG. It is manufacturing process sectional drawing of Embodiment 1 which concerns on this invention, (A) is an electrode layer formation process, (B) is a high frequency plasma supply (nucleation formation) process, (C) is a plug electrode formation process. It is manufacturing process sectional drawing of Embodiment 1 which concerns on this invention, (A) is an interlayer insulation film formation process, (B) is a smoothing process, (C) is a wiring formation process. It is a manufacturing process sectional view of Embodiment 1 concerning the present invention, (A) is a plug electrode re-formation process, (B) is an interlayer insulation film formation process. It is a manufacturing process sectional view of Embodiment 1 concerning the present invention, (A) is a smoothing process and (B) is the 2nd semiconductor film formation process. FIG. 4 is a manufacturing process cross-sectional view of the first embodiment according to the present invention, in which (A) is a second semiconductor film crystallization process and (B) is a second semiconductor film after crystallization. It is manufacturing process sectional drawing of Embodiment 1 which concerns on this invention, and sectional drawing of the manufactured three-dimensional semiconductor device. It is manufacturing process sectional drawing of Embodiment 2 which concerns on this invention, (A) is a 1st semiconductor film formation process, (B) is an electrode layer formation process, (C) is a plug electrode formation process, (D) is gate insulation. A film forming process, (D) is a first semiconductor film crystallization process. It is manufacturing process sectional drawing of Embodiment 2 which concerns on this invention, (A) is 1st semiconductor film sectional drawing after crystallization, (B) is a 1st semiconductor device formation process, (C) is a smoothing process, ( D) is a plug electrode re-forming step. It is an illustration of the electronic device which concerns on Embodiment 3, (A) is a mobile telephone, (B) is a wristwatch, (C) is a portable information processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 1a ... Translucent substrate, 2 ... Amorphous first semiconductor film, 3 ... Crystallized first semiconductor film, 4 ... Gate insulating film, 5 ... Gate insulating film, 6 ... Silicide film, 7 ... Gate Electrode, 9 ... Source / drain region, 10 ... First semiconductor device, 11 ... Metal layer, 15 ... Plug electrode, 16 ... Interlayer insulating film, 17 ... Wiring, 18 ... Interlayer insulating film, 20 ... Second semiconductor device, 22 ... Amorphous second semiconductor film, 23 ... Crystallized second semiconductor film, 26 ... Gate insulating film, 27 ... Gate electrode, 29 ... Source / drain region, 30 ... Interlayer insulating film, 32 ... Wiring, 33 ... Protective layer 530: Cellular phone, 531 ... Antenna unit, 532 ... Audio output unit, 533 ... Audio input unit, 534 ... Operation unit, 540 ... Video camera, 541 ... Image receiving unit, 542 ... Operation unit, 543 ... Audio input unit, 550 ... TV, 560 ... Roll-up Equation television

Claims (13)

A method of manufacturing a semiconductor device in which a plurality of semiconductor films are stacked,
Forming a plug electrode comprising carbon nanotubes on the first semiconductor film;
Forming an interlayer insulating film around the formed plug electrode;
Smoothing the surface of the interlayer insulating film to expose the top of the plug electrode; and
Forming an amorphous second semiconductor film on top of the interlayer insulating film and the plug electrode;
Supplying the energy to the amorphous second semiconductor film to cause the plug electrode exposed to function as a catalyst to crystallize the amorphous second semiconductor film;
A method for manufacturing a semiconductor device, comprising: Forming a metal layer for growing the carbon nanotubes on the first semiconductor film;
Applying high frequency plasma to the metal layer to form nuclei in the metal layer;
Growing the carbon nanotubes from the metal layer to form the plug electrode;
A method for manufacturing a semiconductor device according to claim 1. The metal layer is a metal selected from the group consisting of nickel, cobalt, and iron.
A method for manufacturing a semiconductor device according to claim 2. Before the step of forming a plug electrode on the first semiconductor film,
Forming an amorphous first semiconductor film on a translucent substrate;
After the step of forming the plug electrode,
Energy is supplied to the amorphous first semiconductor film from the back side of the translucent substrate so that the plug electrode in contact with the first semiconductor film functions as a catalyst, and the amorphous first semiconductor film is formed. Comprising the step of crystallizing,
A method for manufacturing a semiconductor device according to claim 1. The main crystal plane orientation of the first semiconductor film is the same as the main crystal plane orientation of the second semiconductor film;
A method for manufacturing a semiconductor device according to claim 4. The energy is supplied by irradiating a laser beam.
A method for manufacturing a semiconductor device according to claim 1. After the step of crystallizing the second semiconductor film, the semiconductor device manufacturing method according to claim 1 is repeated one or more times to stack three or more semiconductor films connected to the plug electrode.
A method for manufacturing a semiconductor device. Forming a semiconductor device including each of the semiconductor films,
A method for manufacturing a semiconductor device according to claim 1. A first semiconductor film;
A plug electrode formed of carbon nanotubes formed on the first semiconductor film;
An interlayer insulating film formed around the electrode;
A second semiconductor film formed on the interlayer insulating film and connected to the plug electrode,
The semiconductor device, wherein the second semiconductor film is crystallized by using the plug electrode as a catalyst. The first semiconductor film is crystallized by using the plug electrode as a catalyst;
The semiconductor device according to claim 9. The main crystal plane orientation of the first semiconductor film is the same as the main crystal plane orientation of the second semiconductor film;
The semiconductor device according to claim 10.   An electro-optical device comprising the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, or the semiconductor device according to any one of claims 9 to 11.   An electronic apparatus comprising the semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, or the semiconductor device according to any one of claims 9 to 11.

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