JP2009290032A - Evaluation analysis system and probe card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an evaluation test system which securely regenerates a non-conformance found out in a reliability evaluation test of a semiconductor device when the non-conformance of the semiconductor device is analyzed, whereby the non-conformance of a semiconductor device found out in a reliability evaluation test is exactly analyzed. <P>SOLUTION: The evaluation test system includes a reliability evaluation test device 100a to generate reliability evaluation signals applied to a semiconductor device, and an analysis device 100b to analyze an abnormal site of the semiconductor device generated by application of the reliability evaluation signals to the semiconductor device. The reliability evaluation test device and the analysis device are electrically connected to the semiconductor device through a common connection jig (probe card) 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an evaluation analysis system and a probe card, and more particularly to a reliability evaluation test apparatus for performing a reliability evaluation test of a semiconductor device in an analysis apparatus such as a weak light emission analysis apparatus used for failure analysis of a semiconductor device such as a system LSI. And a probe card used in such an evaluation analysis system.

  The semiconductor device is formed through a wafer forming process and a package forming process.

  This wafer forming process is roughly composed of repetition of processing steps such as film formation, exposure, and etching. In the process of performing these processes, various processes are performed on the silicon wafer in a clean room where very fine foreign matter (dust) is not generated. However, in these steps, silicon scraps and artificial dust are generated due to the processing, and these may adhere to the wafer during the processing in the step.

  Semiconductor elements and wirings constituting the semiconductor device are processed and formed in units of 1 μm or less, and foreign matters (dust) adhering to the wafer are short-circuited between metal wirings, Via high resistance connection (that is, upper layer wiring and lower layer wiring). The contact hole connecting the terminal and the I / O terminal due to a short circuit or electrostatic breakdown.

  Therefore, a reliability evaluation test is conventionally performed on a semiconductor device, and FIG. 6A is a diagram illustrating a schematic configuration of a conventional reliability evaluation test apparatus.

  A reliability evaluation apparatus 10 shown in FIG. 6A includes a probe card (not shown) having a probe needle 13a for inputting a signal to the LSI semiconductor device 12 and taking out the signal from the semiconductor device 12. And a signal generator 11 for generating a reliability evaluation signal. The probe needle 13a is connected to the signal generator 11 via a signal wiring 13, and a reliability evaluation signal generated by the apparatus 11 is input to the semiconductor device 12 via the probe needle 13a, and the semiconductor A signal generated by the device 12 is supplied to the signal generator 11 via the probe needle 13a.

  In such a reliability evaluation device 10, for example, when evaluating reliability against latch-up, the signal generation device 11 generates a reliability evaluation signal that induces latch-up, and this signal is transmitted via the probe needle 13 a. Applied to the semiconductor device 12. In this state, the semiconductor device is evaluated based on the leakage current.

  As a result of the reliability evaluation, when a defect of the semiconductor device is detected, the cause of the defect is further analyzed.

  FIG. 6B is a diagram illustrating a schematic configuration of an analysis apparatus that analyzes a cause of a defect in a semiconductor device.

  The analysis apparatus 20 includes a probe card (not shown) having a probe needle 23a for applying a reliability evaluation signal for inducing latch-up or the like to the semiconductor device 22, and a transparent member for mounting the semiconductor device 22. A stage 21 comprising: a microscope 25 for aligning a probe needle 23a disposed on the upper side of the stage 21 with respect to the semiconductor device; and a lower side of the stage 21 for photographing the back side of the semiconductor device And a rear camera 24. The analysis apparatus 20 is connected via the probe needle 23 a and the signal wiring 23, and a power supply unit (not shown) that supplies a power supply voltage to the semiconductor device 22 and image data obtained by the rear camera 24. And an analysis processing unit (not shown) for analyzing and specifying a defective part of the semiconductor device based on the above.

  In such an analysis apparatus 20, the semiconductor device 22 placed on the stage 21 is aligned with the probe needle 23 using the alignment microscope 25, and then the semiconductor device is interposed via the probe needle 23a. A power supply voltage is applied to 22, and in this state, an image of the back side of the semiconductor device is taken by the back camera 24. When a light emitting point appears in the image obtained by this imaging, for example, it can be determined that the current is concentrated due to the occurrence of latch-up or leakage current at the light emitting point.

  An emission microscope (weak light emission analysis) apparatus or the like is used as a method for analyzing the cause of failure by the light emission point of such a semiconductor device.

  Such a semiconductor device failure analysis method using an emission microscope is disclosed in, for example, Patent Document 1, Patent Document 2, and Non-Patent Document 1.

  This emission microscope is a microscope that captures, with high sensitivity, extremely weak light caused by hot carriers generated when an electric field is concentrated at an abnormal location inside a semiconductor device, and extremely weak light in the infrared region caused by latch-up. .

  In this emission microscope, a weak current flowing through a semiconductor device is detected as a weak luminescence image by an ultra-sensitive camera. In other words, in an emission microscope, a weak emission image and an image obtained by an optical microscope (an optical microscope image) are taken with the same high-sensitivity camera, and two images are superimposed on an external control monitor, thereby causing a minute leak. It is possible to specify the current location, the disconnection of the wiring, and the short location.

  In recent technology, with the development of miniaturization process and lowering of drive voltage, the metal wiring has become multi-layered, which increases the thickness of the metal layer. From the upper surface of the wafer, the gate polysilicon of the transistor and the wiring metal The current situation is that the pattern has disappeared. For this reason, the light emission image in the layer in which the transistor is constructed cannot be confirmed.

Therefore, recently, failure analysis from the backside of the wafer, which analyzes the failure of the semiconductor device, has become mainstream by irradiating the wafer with the infrared laser from the backside of the wafer and capturing the emission image in the semiconductor device from the backside of the wafer. .
JP 2001-203248 A Japanese Patent Laid-Open No. 2001-24042 Development of Simple Emission Microscope Analysis Equipment Effortless Microscopy for Semiconductors Users Masanobu Terayama Masato Kadota Ricoh Tectronic 30 p. 113-P. 119 DECEMBER, 2004

  However, such an analysis device (weak light emitting device) is used for a semiconductor device in which a defect occurs for the first time when a defect actually occurs in the semiconductor device.

  That is, when a defect such as current leakage occurs in the semiconductor device, first, the symptom of the defect (malfunction or the like) and the reproducibility of the defect are confirmed by a reliability evaluation test apparatus other than the analysis apparatus.

  Then, the semiconductor device is brought to the analysis device while maintaining the confirmed state of the semiconductor device, and the analysis device reproduces the defect of the semiconductor device, for example, the failure of the semiconductor device is generated. Perform analysis to identify the location.

  However, a semiconductor device analyzer is different from the reliability evaluation test device in various factors such as the length of wiring to a jig (eg, probe card) for inputting / outputting signals to / from the semiconductor device. Therefore, the wiring resistance value and the like are different. For this reason, in the analysis apparatus for semiconductor devices, the leakage current value due to changes in the wiring resistance value and the like is different from that in the reliability evaluation test apparatus, and this causes a problem that has occurred in the reliability evaluation test apparatus. It cannot be reproduced.

  As described above, the failure of the semiconductor data that has occurred in the reliability evaluation test device cannot be reproduced by the analysis device, which means that the failure analysis cannot be correctly performed by the analysis device. There is a problem that the failure of the semiconductor device cannot be analyzed correctly.

  The present invention has been made to solve the above-described conventional problems, and the defects found in the reliability evaluation test of the semiconductor device can be reliably reproduced during the failure analysis of the semiconductor device. An object of the present invention is to obtain an evaluation test system capable of correctly analyzing a failure of a semiconductor device found in a reliability evaluation test and a probe card used in such an evaluation test system.

  An evaluation analysis system according to the present invention is an evaluation analysis system that performs a reliability evaluation test of a semiconductor device and analyzes an abnormal portion of the semiconductor device that has occurred during the reliability evaluation test, and is applied to the semiconductor device A reliability evaluation test apparatus for generating a reliability evaluation signal; an analysis apparatus for analyzing an abnormal portion of the semiconductor device caused by application of the reliability evaluation signal to the semiconductor device; and the semiconductor device electrically connected And a connection jig for applying the reliability evaluation signal to the semiconductor device and taking out a signal generated in the semiconductor device, thereby achieving the above object. .

  The present invention provides the evaluation analysis system, wherein the semiconductor device is a chip state device having an electrode pad to which a bonding wire is connected, which is formed in each chip region of a semiconductor wafer. Preferably, the probe card has a contact needle for making contact with the electrode pad of the state device, and is electrically connected to the chip state device by contact between the contact needle and the electrode pad.

  The present invention provides the evaluation analysis system, wherein the semiconductor device is a package state device having an external terminal formed by mounting a semiconductor chip cut out from a semiconductor wafer in a package, and the connection jig includes the package state. A device mounting portion for mounting a device; and a contact piece disposed on the device mounting portion for contacting an external terminal of the packaged device, the contact piece and the external terminal It is preferable that the package socket be electrically connected to the package state device by contact with the package state device.

  In the evaluation analysis system according to the present invention, the package state device is preferably a resin mold package formed by resin-sealing the semiconductor chip.

  According to the present invention, in the evaluation analysis system, the semiconductor device to be subjected to the reliability evaluation test includes a chip state device having an electrode pad to which a bonding wire is connected, and a semiconductor formed in each chip region of the semiconductor wafer. A semiconductor device of any type of a package state device having an external terminal formed by mounting a semiconductor chip cut out from a wafer in a package, and the connection jig is to make electrical connection with the chip state device. It is preferable to have a probing portion and a socket portion for making electrical connection with the package state device.

  According to the present invention, in the evaluation analysis system, the probing unit includes a contact needle for contacting the electrode pad of the chip state device, and the tip state device and the electrode pad are brought into contact with the chip state device. Electrically connected, the socket portion is a device placement portion for placing the package state device, and a contact disposed on the device placement portion for contacting an external terminal of the package state device It is preferable that the device is electrically connected to the package state device by contact between the contact piece and the external terminal.

  According to the present invention, in the above-described evaluation analysis system, the connection jig arranges a plurality of probe needles on a card substrate having first and second openings so that tips of the probe needles are located in the first opening. It is preferable that the socket portion is configured by disposing a package mounting portion on which the package is mounted so as to configure the probing portion and surround the second opening on the card substrate.

  In the evaluation analysis system, the present invention includes a back camera disposed on the back side of the connection jig, and the back camera includes a transparent support substrate that supports the chip state device on the back surface of the chip state device. Preferably, the package state device is photographed through the second opening of the card substrate.

  In the evaluation analysis system, the present invention includes a laser light source that is disposed on the back surface side of the connection jig and outputs laser light, and the laser light source supports the chip state device on the back surface of the chip state device. It is preferable to irradiate a laser beam through the transparent support substrate and to irradiate the back surface of the package state device through the second opening of the card substrate.

  In the evaluation analysis system, the present invention includes an alignment microscope that is disposed on the surface side of the connection jig and aligns the tip of the probe needle with the electrode pad of the chip state device. The microscope preferably forms an enlarged image of the surface of the chip state device through the first opening of the card substrate.

  In the evaluation analysis system according to the present invention, the connection jig is configured such that the probe needle of the probing part is connected to the tip state device from a non-contact position where the probe needle of the probing part does not contact the electrode pad of the tip state device. It is preferable to have a support mechanism that slidably supports the connection jig so as to move to a contact position that contacts the electrode pad.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the reliability evaluation test apparatus generates an electrostatic withstand voltage evaluation signal for performing a reliability evaluation test with respect to electrostatic withstand voltage.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the reliability evaluation test apparatus generates a latch-up evaluation signal for performing a reliability evaluation test for latch-up.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the reliability evaluation test apparatus generates an electromagnetic wave resistance evaluation signal for performing a reliability evaluation test against electromagnetic noise.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the analysis apparatus analyzes an abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied based on a leakage current of the semiconductor device.

  In the evaluation analysis system according to the present invention, the analysis apparatus analyzes an abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied based on a light emission image appearing on the back surface or the front surface of the semiconductor device. It is preferable.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the analysis apparatus performs a backside weak light emission analysis on the semiconductor device.

  According to the present invention, in the evaluation analysis system, the analysis apparatus includes image data indicating a light emission image of the semiconductor device before applying the reliability evaluation test signal, and a semiconductor device after applying the reliability evaluation test signal. A storage device that stores image data indicating a light emission image of the semiconductor device, image data indicating a light emission image of the semiconductor device before application of the reliability evaluation test signal, and a semiconductor device after application of the reliability evaluation test signal It is preferable to have a data comparison device that compares the image data indicating the light emission image.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the analysis apparatus includes a back camera that captures a back surface of the semiconductor device, and acquires image data indicating a light emission image of the semiconductor device by the back camera.

  According to the present invention, in the evaluation analysis system, before the reliability evaluation test signal is applied to the semiconductor device, a weak emission image of the back surface of the semiconductor device is captured by the back camera, and is captured by the back camera. The obtained image data is preferably stored in the storage device.

  In the evaluation analysis system, the present invention records the weak emission image of the back surface of the semiconductor device captured by the back camera after applying the reliability evaluation test signal to the semiconductor device, and is recorded in the recording device, Before applying the reliability evaluation test signal to the semiconductor device, it is preferable to compare it with a weak emission image of the back surface of the semiconductor device taken by the back camera.

  In the evaluation analysis system, the analysis apparatus includes an image output device that displays an image based on image data, and image data obtained by imaging the back surface of the semiconductor device with the back camera. It is preferable to have an image output determination device that determines whether or not to output to the image output device.

  According to the present invention, in the evaluation analysis system, the image output determination device has a characteristic value of the semiconductor device after the reliability evaluation test signal is applied to the semiconductor device, and the reliability evaluation test signal is converted to the semiconductor device. Switching the display state of the image displayed on the image output device so that the abnormal portion of the semiconductor data is analyzed based on the emission image when the reference value is larger than a reference value set before application to preferable.

  In the evaluation analysis system according to the aspect of the invention, it is preferable that the analysis apparatus analyzes an abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied based on a leakage current of the semiconductor device and a light emission image thereof. .

  A probe card according to the present invention is a probe card for exchanging signals with a semiconductor device, and is a chip state having electrode pads formed in each chip region of a semiconductor wafer to which bonding wires are connected A probing section for electrical connection with the device, and a package socket section for electrical connection with a package state device having external terminals formed by mounting a semiconductor chip cut out from the semiconductor wafer in the package So that the above object is achieved.

  In the probe card according to the present invention, the probing portion is provided corresponding to a plurality of electrode pads of the chip state device, and has a plurality of probe needles that are brought into contact with the electrode pads. It is preferable to directly input and output signals to the chip state device.

  According to the present invention, in the probe card, the package socket unit includes a package mounting unit on which the package state device is mounted, and a contact disposed on the package mounting unit for contacting an external terminal of the package state device. It is preferable that an electrical signal is applied to the package state device via the contact piece.

  According to the present invention, in the probe card, the probing portion is disposed on a card substrate having first and second openings so that a tip is located in the first opening, and the probe pad is used as an electrode pad of the chip state device. A connecting portion that has a plurality of probe needles for contact and applies an electrical signal to the chip state device via the probe needle, and the package socket portion has the second opening on the card substrate. A package mounting portion disposed so as to surround and to which the package state device is mounted; and a contact piece disposed on the package mounting portion for contacting an external terminal of the package state device. It is preferable that the connection portion applies an electrical signal to the package state device.

  According to the present invention, in the probe card, the probing unit is configured so that the laser beam for analysis emitted from the laser light source disposed on the upper side of the card substrate is the chip state device disposed on the lower side of the card substrate. It is preferable that the first opening of the card substrate is disposed so that the upper surface is irradiated.

  According to the present invention, in the probe card, the package socket unit is configured such that the analysis laser beam emitted from a laser light source disposed on the lower side of the card substrate is disposed on the upper side of the card substrate. It is preferable that the second opening of the card substrate is arranged so that the lower surface of the card substrate is irradiated.

  The operation of the present invention will be described below.

  In the present invention, a reliability evaluation test apparatus for generating a reliability evaluation signal to be applied to a semiconductor device, and an analysis apparatus for analyzing an abnormal part of the semiconductor device caused by the application of the reliability evaluation signal to the semiconductor device; The reliability evaluation test apparatus and the analysis apparatus are electrically connected to the semiconductor device with a common connection jig, so that the reliability evaluation test of the semiconductor device is performed and the analysis of the semiconductor device is performed. In some cases, a signal for reliability evaluation test (ESD / latch-up) can be applied to the semiconductor device using the same connection jig. As a result, the defects found in the reliability evaluation test of the semiconductor device can be reliably reproduced during the failure analysis of the semiconductor device (semiconductor device). As a result, the defect of the semiconductor device found in the reliability evaluation test Can be analyzed correctly.

  Further, in the present invention, the connection jig has a configuration including a probing portion for making electrical connection with the chip state device and a socket portion for making electrical connection with the package state device. A semiconductor device to be subjected to the reliability evaluation test includes a chip state device having an electrode pad connected to a bonding wire formed in each chip region of the semiconductor wafer, and a semiconductor chip cut out from the semiconductor wafer. It is possible to correctly analyze a defect of a semiconductor device found in a reliability evaluation test, regardless of which type of semiconductor device is a packaged state device having external terminals.

  According to the present invention, the probing is performed by arranging the connecting jig on a card substrate having first and second openings so that a plurality of probe needles are positioned in the first opening. And the socket portion is configured by disposing a package mounting portion on which the package is mounted so as to surround the second opening on the card substrate. By arranging a camera for imaging the semiconductor device on the side or the back side, it is possible to take an image of the front or back surface of the chip state device or to take an image of the front or back surface of the package state device. Further, by arranging a laser light source for outputting laser light on the front surface side or back surface side of the card substrate, laser light is irradiated on the front surface or back surface of the chip state device or on the front surface or back surface of the package state device. This makes it easier to detect a light emission image on the front surface side or the back surface side of the semiconductor device with a camera.

  In the present invention, the evaluation analysis system further includes an alignment microscope that is arranged on the surface side of the connection jig and aligns the tip of the probe needle with the electrode pad of the chip state device. Therefore, alignment between the probe needle and the electrode pad of the chip state device can be performed accurately and easily.

  Further, in the present invention, the connecting jig is configured such that the probe needle of the probing part is connected to the electrode pad of the chip state device from a non-contact position where the probe needle of the probing part does not contact the electrode pad of the chip state device. Since the support mechanism for slidably supporting the connection jig is provided so as to move to the contact position where the connection jig is in contact with the semiconductor device, the contact between the connection jig and the semiconductor device can be easily performed.

  In the present invention, the reliability evaluation test apparatus generates an electrostatic withstand voltage evaluation signal for performing a reliability evaluation test with respect to electrostatic withstand voltage. Failure (defect occurrence) can be analyzed.

  In the present invention, by generating a latch-up evaluation signal for performing a reliability evaluation test for latch-up in the reliability evaluation test apparatus, a latch-up resistance evaluation test for a semiconductor device and a failure due to latch-up (problem) Analysis).

  In the present invention, the above-described reliability evaluation test apparatus generates an electromagnetic wave resistance evaluation signal for performing a reliability evaluation test for electromagnetic wave noise, so that an electromagnetic wave resistance evaluation test for a semiconductor device and a failure due to electromagnetic noise (problem occurrence) ) Analysis can be performed.

  In the present invention, since the abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied is analyzed based on the light emission image appearing on the back surface or the front surface of the semiconductor device, the semiconductor device before the reliability evaluation test is analyzed. The defect portion can be easily identified by comparing the light emission image of the semiconductor device with the light emission image of the semiconductor device after the reliability evaluation test.

  In the present invention, an image output device that displays an image based on image data, and whether to output image data obtained by imaging the back surface of the semiconductor device by the back camera to the image output device. Since the image output determination device for determination is provided, only the light emission image of the defective semiconductor device is displayed on the image output device, so that time and work required for failure analysis can be reduced.

  In the present invention, the semiconductor device that has been subjected to the reliability evaluation test and has a high risk of occurrence of a failure is displayed with a display state of a luminescent image displayed on the image output device as an abnormal portion of the semiconductor data. Since switching is performed so that the analysis is performed, it is possible to efficiently analyze the defect of the semiconductor device.

  In this invention, since the abnormal part of the semiconductor device to which the reliability evaluation test signal is applied is analyzed based on the leakage current of the semiconductor device and its emission image, the failure analysis of the semiconductor device is performed with higher accuracy. Can do.

  As described above, according to the present invention, the reliability evaluation test apparatus and the analysis apparatus that were originally separate apparatuses are provided in one system, and the reliability evaluation test apparatus and the analysis apparatus include a semiconductor device. Since the connection jig for making the electrical connection to is made common, it is no longer possible that the analysis device cannot reproduce the defective portion of the semiconductor data that has occurred in the reliability evaluation test device. As a result, the defects found in the reliability evaluation test of the semiconductor device can be reliably reproduced during the failure analysis of the semiconductor device, and the semiconductor device failure found in the reliability evaluation test is correctly analyzed. can do.

  In addition, according to the present invention, a probe card is connected to a chip state device having an electrode pad to which a bonding wire is connected, which is formed in each chip region of a semiconductor wafer, and a semiconductor. Since the semiconductor chip cut out from the wafer is mounted on a package and has a package socket portion for electrical connection with a package state device having external terminals, the reliability evaluation test target Regardless of whether the resulting semiconductor device is a chip state device or a package state device, electrical contact can be made. For this reason, by using this probe card as a connection jig for making electrical connection with the semiconductor device shared by the reliability evaluation test apparatus and the analysis apparatus, the semiconductor device found in the reliability evaluation test is used. It becomes possible to correctly analyze the defect.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a schematic configuration of an evaluation analysis system according to Embodiment 1 of the present invention.

  The evaluation analysis system 100 according to the first embodiment is an evaluation analysis system that performs a reliability evaluation test of a semiconductor device and analyzes an abnormal part of the semiconductor device generated during the reliability evaluation test.

  The evaluation analysis system 100 includes a reliability evaluation test apparatus 100a that generates a reliability evaluation test signal (hereinafter also referred to as a reliability test signal), and an internal generated in the semiconductor device after the application of the reliability test signal. A device analysis apparatus 100b for analyzing the semiconductor device based on the signal, and configured to be electrically connected to the semiconductor device. The reliability test signal is applied to the semiconductor device 112 and generated in the semiconductor device. And a connecting instrument (probe card) 120 for taking out a signal. The evaluation analysis system 100 also includes a switch unit 111 that connects the device analysis apparatus 100b to a signal path that connects the probe card 120 and the reliability evaluation test apparatus 100a.

  Here, the probe card 120 mounts a chip state device 112 having electrode pads 112a formed on each chip region of a semiconductor wafer to which bonding wires are connected, and a semiconductor chip cut out from the semiconductor wafer in a package. The probe card is applicable to any package state device 129 having an external terminal 129a.

  FIG. 2 is a perspective view for explaining a probe card in the evaluation analysis system 100 of the first embodiment.

  The probe card 120 is formed on the card substrate 121 and is disposed on the card substrate 121 and has a probing portion 120a having a probe needle 122 that is brought into contact with an electrode pad (bonding pad) 112a of the chip state device. And a package socket portion 120b for mounting the state device 129 to be electrically connected.

  Here, the card substrate 121 has a first opening 122a and a second opening 128a. The probe card unit 120a is arranged on the card substrate 121 so that the tip is located in the first opening 122a, and has a plurality of probe needles 122 for contacting the electrode pads 112a of the chip state device. Yes. The package socket portion 120b is disposed on the card substrate 121 so as to surround the second opening 128a, and is disposed on the inner surface of the package mounting portion 128 and the package mounting portion 128 on which the package state device 129 is mounted. And a contact piece 128b for making contact with the external terminal 129a of the package state device, and a terminal structure for applying an electrical signal to the package state device 129 through the contact piece 128b. The probe card 121 has a card side input / output unit 123 that is disposed on one end side of the card substrate 121 and connects the probe card 121 to an external device. The probe needles 122 of the probing section 120a and the contact pieces 128b corresponding to the probe needles 122 are electrically connected by a wiring layer printed on the substrate.

  FIG. 3 is a schematic diagram for explaining the evaluation analysis system 100 of the first embodiment in more detail, and particularly shows specific configurations of the reliability evaluation test apparatus 100a and the device analysis apparatus 100b.

  The evaluation analysis system 100 is arranged on the back surface side of the stage 140a, and the laser beam L is irradiated on the back surface side of the chip state device 112 in contact with the probe needle, or the package mounted on the package socket. A light irradiation unit (laser light source) 108 that emits laser light is provided so that the laser beam L is irradiated on the back side of the state device 129. The light irradiation unit 108 irradiates the laser light L on the surface side of the chip state device that is in contact with the probe needle, or the laser light L on the surface side of the package state device attached to the package socket. May be arranged on the upper side of the probe card.

  Here, the reliability evaluation test apparatus 100a includes a latch-up evaluation unit 102a that generates a latch-up evaluation signal for performing reliability evaluation for latch-up as a reliability evaluation test signal, and a reliability evaluation test signal as It has a signal generation unit 102 including an electrostatic withstand voltage evaluation unit 102b that generates an electrostatic withstand voltage evaluation signal for performing reliability evaluation with respect to electrostatic withstand voltage. However, the test signal generator 100a may include only one of the latch-up evaluation unit 102a and the electrostatic withstand voltage evaluation unit 102b. Further, the signal generation unit 102 may include a resistance evaluation unit that generates an electromagnetic wave resistance evaluation test signal for performing a reliability evaluation test against electromagnetic wave noise.

  The device analysis unit 100b analyzes the state of the semiconductor device after application of the reliability test signal based on the leakage current of the semiconductor device 112 or 129, and based on the emission image of the semiconductor device, the reliability The failure of the semiconductor device after the application of the property test signal is analyzed. That is, the device analysis unit 110b analyzes a defect of the semiconductor device after the application of the reliability test signal based on the leakage current of the semiconductor device and the light emission image thereof. Here, the analysis based on the emission image is a backside weak emission analysis.

  Further, the device analysis unit 100b includes a storage device 103 that stores image data of the semiconductor device before application of the reliability test signal and image data of the semiconductor device after application of the reliability test signal; A data comparison unit 104 compares the image data of the semiconductor device before the application of the reliability test signal with the image data of the semiconductor device after the application of the reliability test signal. The device analysis apparatus 100b includes an imaging camera unit 106 that images the back surface of the semiconductor device, an image output apparatus 101 that displays a captured image based on image data from the imaging camera 106, and the imaging camera 106. It has an image output determination device 105 that monitors the flow of video data to the image output device 101 and controls image display on the image output device 101. Further, the device analysis unit 100b includes an LSI tester 110 that outputs a test signal to the semiconductor device 112 or 129 and tests a defect of the semiconductor device based on an output signal corresponding to the test signal from the semiconductor device. .

  The evaluation analysis system 100 further includes an alignment microscope 107 that is disposed on the surface side of the probe card and aligns the tip of the probe needle with the electrode pad of the chip state device. Is to form an enlarged image of the surface of the chip state device through the first opening of the card substrate.

  In addition, the evaluation analysis system 100 is configured so that the probe card has a probe needle of the probing part that is not contacted with the electrode pad of the chip state device from a non-contact position where the probe needle of the probing part contacts the electrode pad of the chip state device. A support mechanism 140 that slidably supports the probe card so as to move to the contact position is provided.

  The image output device 101, the storage device 103, the image output determination unit 105, the data comparison unit 104, and the LSI tester 110 are connected via one data bus. This data bus is connected to the probe card 120. Are connected through a switch 111 that is opened and closed by a control signal Sc. The signal generator 120 is directly connected to the probe card 120. Here, the switch 111 is opened and closed so that the reliability evaluation test signal from the signal generator 120 is not applied to other circuit parts other than the probe card.

  Next, the operation will be described.

  FIG. 4 is a diagram illustrating a procedure for performing an evaluation analysis of a semiconductor device using the evaluation analysis system of the first embodiment.

  First, at the same time as the start Ps of the analysis process, it is determined whether the semiconductor device that is the object of evaluation analysis (sample) is in a chip state or a package state (PKG state) (procedure P1).

  Next, as a result of this determination, when the semiconductor device is a device (chip state device) in a state of being built in each chip region of the wafer, the probe card and the semiconductor device 112 are detected by the probing unit 120a of the probe card 120. Is brought into electrical contact (procedure P2a). As a result, the reliability evaluation test apparatus 100a and the analysis apparatus 100b can apply a test signal to the semiconductor device 112 that is a sample, and can extract the internal signal from the semiconductor device 112.

  Subsequently, the reliability evaluation test apparatus 100a, for example, applies a leakage current between predetermined electrode pads in the semiconductor device before applying a reliability evaluation test signal such as a latch-up signal for inducing latch-up to the semiconductor device. Is measured (procedure P3).

  Further, the measured current value before evaluation is stored in the storage device 103 such as a magnetic disk (procedure P4). At this time, not only the leakage current value but also the data of the light emission image of the semiconductor device is stored in the storage device. In addition, a reliability evaluation threshold value serving as a reference is input to the data comparison unit 104 in advance.

  Thereafter, the reliability evaluation test apparatus 100a applies a reliability evaluation signal to the semiconductor device 112 while imaging the back surface of the semiconductor device with the back surface camera 106 in the device analysis apparatus 100b (procedure P5). A reliability test evaluation signal such as an ESD (electrostatic withstand voltage) evaluation signal or a latch-up evaluation signal is input from the reliability evaluation test apparatus to the semiconductor device through a probe card.

  After the input, the light emission image on the back surface side of the semiconductor device and the current value flowing through the semiconductor device are stored in the storage device. That is, the current value D1 such as the leakage current and the image data of the light emission image obtained after application of the reliability evaluation signal (after evaluation) are stored in the storage device 103 such as a magnetic disk (procedure P6).

  Thereafter, the data comparison unit 104 compares the current value before evaluation stored in the storage device 103 with the current value after evaluation (procedure P7). As a result of the comparison of the current values, when the difference value between the two current values is smaller than a certain threshold value, the evaluation is completed (procedure Pe). At this time, before the evaluation is completed, an image of the semiconductor device photographed by the rear camera may be displayed on the image output apparatus 101 to confirm whether there is a light emitting portion (procedure P8a).

  On the other hand, as a result of the comparison of the current values, when the difference value between the two current values is greater than or equal to a certain threshold value, the device analysis apparatus 100b supplies an operating current to the semiconductor device, and in this state, the back camera 106 takes a picture. The emitted light image is displayed on the image output apparatus 101 (procedure P8). The semiconductor device is analyzed based on the light emission image displayed on the image output apparatus 101 to identify the failure location (procedure P9). Further, the analysis result is fed back to the design of the semiconductor device (procedure P10).

  When the evaluation analysis of one sample is completed in this way, the evaluation analysis is performed on the next sample.

  When it is determined in step P1 that the semiconductor device is a package state device, the semiconductor package is mounted on the package socket portion 120b of the probe card, and the steps P2 to P10 are performed as in the chip state device. Thus, the evaluation analysis of the semiconductor device is performed.

  FIG. 5 is a diagram for explaining the data comparison process shown in FIG. 4 in detail.

  In this data comparison process, the data comparison unit 104 compares the pre-evaluation data Da and the post-evaluation data Db. Here, the pre-evaluation data Da is data on a leakage current value or light emission image of the semiconductor device before the reliability evaluation test signal is applied to the semiconductor device. For example, the pre-evaluation current value is a leakage current value before the evaluation. Da1 and evaluation signal input image data Da2 which is image data of a light emission image before evaluation are included. Further, the post-evaluation data Db is data of a leakage current value and a light emission image of the semiconductor device after the reliability evaluation test signal is applied to the semiconductor device. For example, the post-evaluation current value Db1 that is the leakage current value after the evaluation. And evaluation signal input image data Db2 which is image data of a light emission image after evaluation. In the data comparison process, a reliability evaluation threshold value Dth such as a leak current value determined in advance for the semiconductor device is used.

  Hereinafter, specific comparison processing will be described.

  First, in the data comparison unit 104, a light emission image and a current value before input (before evaluation) of an external signal, which is a reliability evaluation test signal, and a light emission image and a current value after input of an external signal (after evaluation), respectively. Based on the reliability evaluation threshold value Dth that is compared and input in advance, it is determined whether or not the leakage current value and the luminescent image are abnormal.

  For example, the pre-evaluation current value Da1 and the post-evaluation current value Db1 are compared, and a first determination is made as to whether or not the difference value is greater than a predetermined reference value. Thereafter, when the difference value is not larger than the predetermined reference value, it is determined that the leakage current after evaluation is small (normal current value). In this case, the leak current value is displayed (procedure P74a), and the light emission image is displayed on the image output device 101 by the image output determination unit 105 (procedure P74b). Thereafter, the evaluation is completed (procedure Pe).

  On the other hand, the pre-evaluation current value Da1 and the post-evaluation current value Db1 are compared, a first determination is made as to whether or not the difference value is greater than a predetermined reference value, and the difference value is greater than the predetermined reference value. In this case, a second determination is made as to whether or not the post-evaluation current value Db1 is greater than the evaluation threshold value Dth. When the post-evaluation current value Db1 is larger than the evaluation threshold value Dth, the data comparison unit determines that the current value is abnormal. As described above, when it is determined that the leakage current after evaluation is large (abnormal current value), the semiconductor device is analyzed in the device analysis apparatus 100b (procedure P72). Specifically, inside the analysis apparatus, a light emission image before evaluation is displayed on the image output apparatus 101 (procedure P75a), and further, a light emission image after evaluation is superimposed on this light emission image before evaluation (procedure P75b). . Thus, by specifying the position of the light emission image that newly appears after the evaluation, it is possible to find a portion where the leakage current has increased.

  Thereafter, the leakage current value is displayed (procedure P76a), and the light emission image is displayed on the image output unit 101 by the image display control unit 105 (procedure P76b).

  The current value may be displayed regardless of the threshold value.

  Hereinafter, the effect of the evaluation analysis system according to the first embodiment having such a configuration will be described.

  In recent semiconductor devices, the miniaturization process has become mainstream, the metal wiring has become multi-layered, and analysis from the chip surface has become difficult. In addition, the reliability test evaluation and analysis device are completely different devices, and the analysis device uses the analysis device after a semiconductor device failure occurs, and timely results are obtained. Absent.

  In addition, since the reliability evaluation test apparatus and the analysis apparatus for semiconductor devices are completely different apparatuses, if an attempt is made to reproduce a failure (leakage current failure, etc.) that occurred during the reliability evaluation test with the analysis apparatus, the semiconductor device Depending on the difference in the device environment such as the length of the wiring that gives the signal to the device, there is a problem that the reliability of the failure is low.

  In the present invention, as described in Embodiment 1 above, a configuration capable of performing a reliability evaluation test and analysis of a semiconductor device in one system is constructed, and image data and current values before and after evaluation are compared. By doing so, the configuration for making electrical connection with the semiconductor device during the reliability evaluation test and the analysis, for example, the wiring length between the probe card and each device becomes the same, and the reliability evaluation It is possible to eliminate the problem that defects appearing at the time of testing cannot be reproduced at the time of analysis, thereby obtaining the effect of shortening the development period and analysis time. In other words, in the first embodiment, when a failure of the conductor device occurs during the test while performing the reliability evaluation test in the same system, the failure can be analyzed. The time required for analysis can be greatly reduced.

  As described above, in the first embodiment, the reliability evaluation test apparatus 100a that generates the reliability evaluation signal to be applied to the semiconductor device and the abnormal portion of the semiconductor device that is generated by the application of the reliability evaluation signal to the semiconductor device are detected. The analysis apparatus 100b for analysis is provided, and the reliability evaluation test apparatus and the analysis apparatus are electrically connected to the semiconductor device by a common connection jig (probe card) 120. Therefore, the reliability evaluation of the semiconductor device is performed. A signal for reliability evaluation test (ESD / latch-up) can be applied to the semiconductor device using the same connection jig in the case of performing the test and in the case of analyzing the semiconductor device. As a result, the defects found in the reliability evaluation test of the semiconductor device can be reliably reproduced during the failure analysis of the semiconductor device (semiconductor device). As a result, the defect of the semiconductor device found in the reliability evaluation test Can be analyzed correctly.

  Hereinafter, further effects in the present embodiment will be described.

  In the first embodiment, the connection jig includes a probing portion 120a for making electrical connection with the chip state device 112 and a socket portion 120b for making electrical connection with the package state device 129. Therefore, the semiconductor device to be subjected to the reliability evaluation test is a chip state device having an electrode pad to which a bonding wire is connected formed in each chip region of the semiconductor wafer, and a semiconductor cut out from the semiconductor wafer Any type of semiconductor device, which is a package state device having an external terminal formed by mounting a chip on a package, can correctly analyze a failure of the semiconductor device found in the reliability evaluation test.

  In the first embodiment, the connecting jig (probe card) 120 is placed on the card substrate 121 having the first and second openings 120a and 120b, and a plurality of probe needles 122 are arranged at the tips thereof. The probing portion 120a is arranged so as to be positioned in the opening, and a package mounting portion 128 on which the package is mounted is disposed on the card substrate so as to surround the second opening. Since the structure is configured as 120b, by arranging a camera for imaging the semiconductor device on the front surface side or the back surface side of the card substrate, an image of the front surface or the back surface of the chip state device can be captured, or the front surface of the package state device Alternatively, an image on the back surface can be taken. Further, by arranging a laser light source for outputting laser light on the front surface side or back surface side of the card substrate, laser light is irradiated on the front surface or back surface of the chip state device or on the front surface or back surface of the package state device. This makes it easier to detect a light emission image on the front surface side or the back surface side of the semiconductor device with a camera.

  In addition, when the semiconductor device to be tested is a mold package product (package state device), the package device product can be mounted on the socket on which the mold package can be mounted with the bottom surface of the socket and the probe card substrate cut out. Therefore, the backside weak light emission analysis can be performed even in the mold package product. Further, by adjusting the mounting position of the probe card with respect to the support mechanism 140 by shifting back and forth, the light emission image on the lower surface of the package state device can be taken with a microscope disposed below the probe card.

  In the first embodiment, in the evaluation analysis system 100, the alignment microscope 107 is disposed on the surface side of the connection jig, and aligns the tip of the probe needle with the electrode pad of the chip state device. Therefore, alignment between the probe needle and the electrode pad of the chip state device can be performed accurately and easily.

  Further, in the first embodiment, the probe of the probing part is connected to the electrode pad of the chip state device from a non-contact position where the probe needle of the probing part does not contact the electrode pad of the chip state device. Since the support mechanism 140 that slidably supports the connection jig is provided so as to move to a contact position that contacts the contact jig, the contact between the connection jig and the semiconductor device can be easily performed.

  In the first embodiment, the reliability evaluation test apparatus 100a generates an electrostatic withstand voltage evaluation signal for performing a reliability evaluation test with respect to the electrostatic withstand voltage. It is possible to analyze a failure (occurrence of failure) due to electrostatic breakdown.

  In the first embodiment, the reliability evaluation test apparatus 100a generates a latch-up evaluation signal for performing a reliability evaluation test for latch-up, thereby enabling a latch-up resistance evaluation test and latch-up for a semiconductor device. It is possible to analyze the failure (occurrence of failure) due to

  In the first embodiment, the reliability evaluation test apparatus 100a generates an electromagnetic wave resistance evaluation signal for performing a reliability evaluation test with respect to electromagnetic wave noise. Failure (defect occurrence) can be analyzed.

  Further, in the first embodiment, since the abnormal part of the semiconductor device to which the reliability evaluation test signal is applied is analyzed based on the light emission image appearing on the back surface or the front surface of the semiconductor device, before the reliability evaluation test, By comparing the luminescent image of the semiconductor device with the luminescent image of the semiconductor device after the reliability evaluation test, it is possible to easily identify the defective portion.

  In the first embodiment, the image output device 101 that displays an image based on the image data and the image data obtained by imaging the back surface of the semiconductor device by the back camera are output to the image output device. Since the image output determination apparatus 105 for determining whether or not the image output apparatus 101 is included, the image output apparatus 101 displays only the emission image of the defective semiconductor device, thereby reducing the time and work required for the defect analysis. Can do.

  In the first embodiment, the semiconductor device that has been subjected to the reliability evaluation test and has a high risk of occurrence of a defect is displayed with the display state of the luminescent image displayed on the image output apparatus 101 as the semiconductor data. By switching so that the abnormal part analysis is performed, it is possible to efficiently analyze the defect of the semiconductor device.

  Further, in the first embodiment, since the abnormal part of the semiconductor device to which the reliability evaluation test signal is applied is analyzed based on the leakage current of the semiconductor device and the light emission image thereof, the failure analysis of the semiconductor device can be performed with higher accuracy. It can be performed.

  In the above embodiment, since the LSI tester is provided in addition to the reliability evaluation test apparatus, the LSI tester can also be used for the reliability evaluation test.

  For example, an operation test pattern is applied from an LSI tester to a semiconductor device, and an output signal pattern from the semiconductor device is determined. At this time, data from the head data of the test pattern to the place where the error part is found in the output signal pattern is repeatedly applied to the semiconductor device. In this way, by repeatedly applying the test pattern head data to the error occurrence position data to the semiconductor device, malfunctions in the semiconductor device occur continuously, whereby the emission image of the semiconductor device can be confirmed. It is also possible to perform a failure analysis by comparing the light emission image that appears in this way with a normal light emission image of the semiconductor device.

  In the first embodiment, the evaluation analysis system includes an LSI tester in addition to the reliability evaluation test apparatus. However, the evaluation analysis system is an LSI tester instead of the reliability evaluation test apparatus. May be provided.

  In the first embodiment, the probe card as the connection jig includes both the probing part and the socket part. However, the probe card has only one of the probing part and the socket part. Also good.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. It is understood that the patent documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  The present invention relates to a defect found in a reliability evaluation test of a semiconductor device in the field of a device for performing a reliability evaluation test of a semiconductor device such as a system LSI or an analysis device such as a weak light emission analysis device used for failure analysis of a semiconductor device. , An evaluation test system that can be reliably reproduced in the failure analysis of the semiconductor device and can correctly analyze the failure of the semiconductor device found in the reliability evaluation test, and a probe card used in such an evaluation analysis system The development period and analysis time of a semiconductor device can be shortened.

FIG. 1 is a diagram showing a schematic configuration of a test analysis system according to Embodiment 1 of the present invention. FIG. 2 is a perspective view for explaining a probe card used in the test analysis system of the first embodiment. FIG. 3 is a schematic diagram for explaining the test analysis system 100 of the first embodiment in more detail, and particularly shows specific configurations of the reliability evaluation test apparatus 100a and the device analysis apparatus 100b. FIG. 4 is a diagram for explaining the evaluation analysis procedure of the semiconductor device using the evaluation analysis system of the first embodiment. FIG. 5 is a diagram for explaining the evaluation analysis system of the first embodiment, and shows the data comparison process shown in FIG. 4 in detail. FIG. 6 is a diagram for explaining a conventional reliability evaluation test apparatus (FIG. 6A) and a conventional analysis apparatus (FIG. 6B).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Evaluation analysis system 100a Reliability evaluation test apparatus 100b Device analysis apparatus 101 Image output apparatus 102 Reliability evaluation signal generation apparatus 103 Memory | storage device 104 Data comparison part 105 Image output determination part 106 Back camera 107 Positioning microscope 108 Laser light source 110 LSI Tester 111 Switch 112 Chip state device 120 Probe card 120a Probing part 120b Package socket part 120c Wafer stage 121 Card substrate 122a First opening 128 Package mounting part 128a Second opening 128b Contact piece 129 Package state device 129a External terminal 140 Card Support mechanism

Claims (30)

An evaluation analysis system for performing a reliability evaluation test of a semiconductor device and analyzing an abnormal part of the semiconductor device generated during the reliability evaluation test,
A reliability evaluation test apparatus for generating a reliability evaluation signal to be applied to the semiconductor device;
An analysis apparatus for analyzing an abnormal portion of the semiconductor device caused by application of the reliability evaluation signal to the semiconductor device;
An evaluation analysis system comprising a connection jig configured to be electrically connected to the semiconductor device, for applying the reliability evaluation signal to the semiconductor device, and for extracting a signal generated in the semiconductor device. The semiconductor device is a chip state device having electrode pads to which bonding wires are connected, formed in each chip region of a semiconductor wafer,
The connecting jig is
2. The probe card according to claim 1, further comprising a contact needle for contacting the electrode pad of the chip state device, wherein the probe card is electrically connected to the chip state device by contact between the contact needle and the electrode pad. Evaluation analysis system. The semiconductor device is a package state device having an external terminal formed by mounting a semiconductor chip cut out from a semiconductor wafer in a package,
The connecting jig is
A device mounting portion for mounting the package state device; and a contact piece disposed on the device mounting portion for contacting an external terminal of the package state device. The evaluation analysis system according to claim 1 which is a package socket electrically connected to said package state device by contact with an external terminal.   The evaluation analysis system according to claim 3, wherein the package state device is a resin mold package formed by resin-sealing the semiconductor chip. The semiconductor device to be subjected to the reliability evaluation test includes a chip state device formed in each chip region of the semiconductor wafer and having an electrode pad to which a bonding wire is connected, and a semiconductor chip cut out from the semiconductor wafer in a package. It is a semiconductor device of any type of packaged state device having external terminals,
The connecting jig is
A probing section for making electrical connection with the chip state device;
The evaluation analysis system according to claim 1, further comprising a socket portion for establishing electrical connection with the package state device. The probing part has a contact needle for making contact with the electrode pad of the chip state device, and is electrically connected to the chip state device by contact between the contact needle and the electrode pad;
The socket portion includes a device placement portion for placing the package state device, and a contact piece disposed on the device placement portion for contacting an external terminal of the package state device, The evaluation analysis system according to claim 5, wherein the evaluation analysis system is electrically connected to the package state device by contact between the contact piece and the external terminal. The connecting jig is
A plurality of probe needles are arranged on a card substrate having first and second openings so that tips of the probe needles are located in the first opening to constitute the probing section, and The evaluation analysis system according to claim 6, wherein the socket portion is configured by arranging a package mounting portion on which the package is mounted so as to surround the second opening. A rear camera disposed on the back side of the connecting jig;
The back camera is configured to photograph the back surface of the chip state device through a transparent support substrate that supports the chip state device, and photograph the package state device through a second opening of the card substrate. The evaluation analysis system according to 7. A laser light source arranged on the back side of the connecting jig and outputting a laser beam;
The laser light source irradiates the back surface of the chip state device with laser light through a transparent support substrate that supports the chip state device, and the back surface of the package state device through the second opening of the card substrate. 9. The evaluation analysis system according to claim 8, wherein the laser beam is irradiated. An alignment microscope disposed on the surface side of the connection jig, for aligning the tip of the probe needle with the electrode pad of the chip state device;
The evaluation analysis system according to claim 9, wherein the alignment microscope forms an enlarged image of the surface of the chip state device through the first opening of the card substrate.   The connecting jig moves from a non-contact position where the probe needle of the probing part does not contact the electrode pad of the tip state device to a contact position where the probe needle of the probing part contacts the electrode pad of the tip state device The evaluation analysis system according to claim 5, further comprising a support mechanism that slidably supports the connection jig.   The evaluation analysis system according to claim 1, wherein the reliability evaluation test apparatus generates an electrostatic withstand voltage evaluation signal for performing a reliability evaluation test with respect to electrostatic withstand voltage.   The evaluation analysis system according to claim 1, wherein the reliability evaluation test apparatus generates a latch-up evaluation signal for performing a reliability evaluation test for latch-up.   The evaluation analysis system according to claim 1, wherein the reliability evaluation test device generates an electromagnetic wave resistance evaluation signal for performing a reliability evaluation test against electromagnetic noise.   The evaluation analysis system according to claim 1, wherein the analysis apparatus analyzes an abnormal part of the semiconductor device to which the reliability evaluation test signal is applied based on a leakage current of the semiconductor device.   2. The evaluation analysis system according to claim 1, wherein the analysis apparatus analyzes an abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied, based on a light emission image appearing on a back surface or a front surface of the semiconductor device.   The evaluation analysis system according to claim 16, wherein the analysis apparatus performs backside weak light emission analysis on the semiconductor device. The analysis device includes:
A storage device for storing image data indicating a light emission image of the semiconductor device before applying the reliability evaluation test signal, and image data indicating a light emission image of the semiconductor device after applying the reliability evaluation test signal;
A data comparison device for comparing image data indicating a light emission image of a semiconductor device before application of the reliability evaluation test signal and image data indicating a light emission image of the semiconductor device after application of the reliability evaluation test signal; The evaluation analysis system according to claim 17. The analysis device includes:
The evaluation analysis system according to claim 18, further comprising a rear surface camera that captures an image of the rear surface of the semiconductor device, wherein image data indicating a light emission image of the semiconductor device is acquired by the rear surface camera.   Before applying the reliability evaluation test signal to the semiconductor device, a weak light emission image of the back surface of the semiconductor device is captured by the back camera, and image data obtained by capturing the image by the back camera is stored in the storage device. The evaluation analysis system according to claim 19, wherein the evaluation analysis system is stored in.   A weak luminescence image of the back surface of the semiconductor device captured by the back camera after applying the reliability evaluation test signal to the semiconductor device is recorded in the recording device, and the reliability evaluation test signal is recorded in the semiconductor device 21. The evaluation analysis system according to claim 20, wherein the evaluation analysis system is compared with a weak emission image of the back surface of the semiconductor device imaged by the back camera before application. The analysis device includes:
An image output device for displaying an image based on image data;
The evaluation analysis system according to claim 19, further comprising: an image output determination device that determines whether or not image data obtained by imaging the back surface of the semiconductor device with the back camera is output to the image output device. The image output determination device includes:
When the characteristic value of the semiconductor device after applying the reliability evaluation test signal to the semiconductor device is larger than a reference value set before applying the reliability evaluation test signal to the semiconductor device, the image 23. The evaluation analysis system according to claim 22, wherein the display state of an image displayed on the output device is switched so that an abnormal part of the semiconductor data is analyzed based on the light emission image.   2. The evaluation analysis system according to claim 1, wherein the analysis apparatus analyzes an abnormal portion of the semiconductor device to which the reliability evaluation test signal is applied based on a leakage current of the semiconductor device and a light emission image thereof. A probe card for exchanging signals with a semiconductor device,
A probing unit for making electrical connection with a chip state device having an electrode pad to which a bonding wire is connected, formed in each chip region of the semiconductor wafer;
A probe card having a package socket portion for electrically connecting to a package state device having an external terminal, which is formed by mounting a semiconductor chip cut out from a semiconductor wafer in a package. The probing section is
A plurality of probe needles provided corresponding to the plurality of electrode pads of the chip state device and in contact with the electrode pads, wherein signals are directly input / output to / from the chip state device by the probe needles. Item 26. The probe card according to Item 25. The package socket part is
A package mounting portion on which the package state device is mounted;
A contact piece disposed on the package mounting portion for contacting an external terminal of the package state device;
The probe card according to claim 25, wherein an electric signal is applied to the package state device through the contact piece. The probing unit is disposed on a card substrate having first and second openings so that a tip is located in the first opening, and a plurality of probe needles for contacting the electrode pads of the chip state device are provided. A connecting portion for applying an electrical signal to the tip state device through the probe needle,
The package socket portion is disposed on the card substrate so as to surround the second opening, and a package mounting portion on which the package state device is mounted, and an outside of the package state device disposed on the package mounting portion. 26. The probe card according to claim 25, wherein the probe card is a connection portion that has a contact piece for contacting a terminal and applies an electrical signal to the package state device through the contact piece.   The probing unit is configured so that an analysis laser beam emitted from a laser light source disposed on the upper side of the card substrate is irradiated on an upper surface of the chip state device disposed on the lower side of the card substrate. The probe card according to claim 28, wherein the first opening of the substrate is arranged.   The package socket portion is configured such that the analysis laser light emitted from the laser light source disposed on the lower side of the card substrate is irradiated to the lower surface of the package state device disposed on the upper side of the card substrate. The probe card according to claim 28, wherein the second opening of the card substrate is arranged.

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