JP2009296312A - Semiconductor device and solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a selector where the number of transistors, the number of control wiring lines and the number of serial pMOSs can be reduced in a balanced manner. <P>SOLUTION: A first transistor part 402, having one pMOS first transistor 401 and a second transistor part 404, having M-1 nMOS second transistors 403 constitute a switch cell SW and are arranged in M pairs, in parallel. An arrangement stage of the first transistor 401 is made different in each group, and the second transistors 403 are arranged in the remaining stage in each group. Each input and output of a pair of each of transistor parts 402 and 404 are connected in common. In each switching cell SW, one of an input and an output is made each another signal input, and the other is connected in common to be a signal output. Respective gates of the same stage are connected in common to be set as a control wiring, irrespective of pMOS and nMOS. Only one of M control wiring lines is set as active L, and the rest M-1 control wiring lines are set inactive H, to thereby select and output only one among the input signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a solid-state imaging device. More specifically, a semiconductor having a signal selection function for selecting and outputting any one of a plurality of signals, or conversely, selecting and outputting one signal to any of a plurality of output destinations. The present invention relates to a device and a solid-state imaging device using the signal selection function.

  In various electronic devices and semiconductor devices such as an image processing device, an image pickup device, and a solid-state image pickup device, one of a plurality of signals is selected to be one output, or vice versa. A signal selection circuit that selects and outputs one of the systems may be used.

  As a signal selection circuit, for example, a pair of complementary switches (transfer gates and transmission gates) in which a p-channel type MOS transistor (pMOS) and an n-channel type MOS transistor (nMOS) are connected in parallel are connected between input and output. (See, for example, Patent Documents 1 to 3). A bipolar transistor may be used instead of the MOS transistor.

JP-A-10-93069 JP-A-11-166863 JP-A 63-107222

  As is apparent from the mechanisms described in Patent Documents 1 to 3, each complementary switch (pMOS and nMOS) is controlled separately by a pair of selection control signals in a complementary relationship.

  In the mechanism described in Patent Document 3, a first signal selection circuit is configured by a combination of a plurality of complementary switches, and a second signal selection circuit is configured by a combination of a plurality of complementary switches on the output side. (Hereinafter referred to as a multi-stage signal selection circuit), different signals are input to the first signal selection circuit, and the output of the second signal selection circuit is transmitted to one signal line. .

  However, in a signal selection circuit having a configuration in which complementary switches are arranged in parallel and controlled separately (hereinafter referred to simply as a signal selection circuit having a simple configuration), each complementary switch is controlled individually by a pair of selection control signals in a complementary relationship. Therefore, when the number of signal inputs corresponding to the signal selection circuit having a simple configuration increases, there is a problem that the number of control wirings increases.

  For example, when considering the M input-1 output type, the number of control wirings is 2 × M, and when a large number of signal selection circuits are connected to the control wirings, the control wirings need to be thickened. Considering the circumstances of wiring layout, the number of control wirings should be reduced as much as possible.

  For example, as shown in FIG. 1 of Patent Document 3, it is conceivable to logically invert one of a pair in a complementary relationship with an inverter (hereinafter referred to as an improved configuration signal selection circuit). More transistors are used for the inverter.

  In the mechanism described in Patent Document 3, since the signal selection circuits are cascaded, the ratio of the number of transistors and the number of control wirings to the number of signal inputs can be reduced to less than 2 × M. However, in the mechanism described in Patent Document 3, a plurality of signal selection circuits are connected in cascade between signal inputs and outputs, so that MOSs are naturally connected in cascade. A p-channel MOS transistor has a drawback that it is several times slower than an n-channel MOS transistor. This also applies to the case where a bipolar transistor is used instead of the MOS transistor, and the PNP transistor is slower than the NPN transistor. Therefore, when the number of cascade stages increases, the number of serial pMOSs (or the number of serial PNPs: the same applies hereinafter) increases, and it becomes difficult to transmit signals to the signal lines at high speed.

  As described above, there is still a difficulty in any one of the control wiring, the number of transistors, and the number of series pMOS in the relationship with the number of signal inputs to which one signal selection circuit corresponds, and the signal selection circuit in which all are solved. There is no actual situation. There is a need for a new signal selection circuit that is further improved in view of any of control wiring, the number of transistors, and the number of series pMOS. If there is a new signal selection circuit, the range of selection of the signal selection circuit in accordance with the intended use is expanded.

  The present invention has been made in view of the above circumstances, and in relation to the number of signal inputs to which one signal selection circuit corresponds, any one of various conventional mechanisms, the control wiring, the number of transistors, the series It is an object of the present invention to provide a mechanism capable of further improving from at least one viewpoint of the number of pMOSs and widening the selection range of a signal selection circuit in accordance with a use application.

  One embodiment of a semiconductor device according to the present invention includes a first transistor portion having one first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type. −1 ″ (M is a positive integer of 3 or more) cascaded second transistor units. Then, M pairs are arranged in parallel by pairs of the first transistor portion and the second transistor portion.

  The signal selection function is activated with such a configuration. For example, a pair of a first transistor portion and a second transistor portion is used as a switch cell, and each input / output is connected in common. One input / output of each switch cell is used as a separate signal input, and the other is connected in common to provide a signal output.

  An active level for turning on the first transistor is input to the control input terminal of the first transistor for any one of the M sets of the first transistor portion and the second transistor portion. At this time, the first transistor An active level for turning on each second transistor is also input to the control input terminals of all the second transistors of the set to which the group belongs. For each of the other groups to which the first transistor does not belong, an inactive level for turning off the first transistor is input to the control input terminal of the first transistor, and control of at least one second transistor is performed. An inactive level for turning off the second transistor is also input to the input terminal. By adopting such a mechanism, a signal selection function of M input-1 output type, or conversely, 1 input-M output type, can be realized by M × M transistors and M control wirings.

  The number of control signal lines is reduced as compared with a signal selection circuit having a simple configuration. The number of transistors is smaller than that of an improved signal selection circuit using an inverter.

  In particular, when the MOS configuration is used, the first transistor is a pMOS and the second transistor is an nMOS, and when the bipolar configuration is used, the first transistor is preferably a PNP transistor and the second transistor is an NPN transistor. If the first transistor is a pMOS or PNP transistor, the number of series pMOS and the number of series PNPs can be reliably made one regardless of the number of inputs M. Therefore, in comparison with a case where a plurality of 2-input-1 output-type signal selection circuits are arranged by using a multi-stage signal selection circuit having a mechanism described in Patent Document 3 and corresponding to three or more inputs, the series is compared. The number of pMOSs and the number of series PNPs are surely reduced.

  Such a signal selection circuit can also be used in a multi-stage configuration. In that case, in view of the number of transistors, the signal selection circuit should be a 3-input-1 output type and combined with a 2-input-1 output type signal selection circuit composed of two complementary switches to form a multi-stage configuration. Good. In particular, it is preferable that the signal selection circuit of the 3-input-1 output type is arranged on the lowermost stage side.

  According to one aspect of the present invention, a new signal selection function that is improved with respect to any one of various conventional mechanisms from the viewpoint of at least one of control wiring, the number of transistors, and the number of series pMOSs (the number of PNPs). Can provide.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When distinguishing each functional element by embodiment or modification, it is described with an uppercase English reference, such as A, B, C,... This reference is omitted. The same applies to the drawings.

<Semiconductor device: Basic configuration>
1 to 1D are diagrams for explaining the basic configuration of the semiconductor device of this embodiment. Here, FIG. 1 and FIG. 1A are diagrams showing the basic configuration of the semiconductor device 400 of this embodiment. FIG. 1B is a diagram for explaining a control signal for controlling the semiconductor device 400 of this embodiment. FIG. 1C is a diagram showing semiconductor devices 400X and 400Y of first and second comparative examples with respect to the semiconductor device 400 of the present embodiment. FIG. 1D is a diagram showing a semiconductor device 400Z of a third comparative example with respect to the semiconductor device 400 of the present embodiment.

  As shown in FIG. 1, the semiconductor device 400A of the first example has a first conductivity type (first conductivity type) such as a pMOS (p channel type MOS transistor) and a PNP transistor (PNP type bipolar transistor). A first transistor portion 402 having one transistor 401 and a second conductivity type (first transistor) different from the first conductivity type such as an nMOS (n-channel MOS transistor) or an NPN transistor (NPN bipolar transistor). The second transistor unit 404 includes (M−1) (second conductivity type) second transistors 403 connected in cascade (M is a positive integer of 3 or more). In the semiconductor device 400A, the first transistor unit 402 and the second transistor unit 404 are paired and arranged in M sets in parallel.

  In the figure, an example is shown in which a pMOS is used for the first transistor and an nMOS is used for the second transistor. The second transistor section 404 in which “M−1” nMOS second transistors 403 are cascade-connected exhibits nMOS properties as a whole and has a complementary relationship with the pMOS first transistor 401. In the case of a bipolar transistor, the first transistor may be replaced with a PNP transistor, and the second transistor may be replaced with an NPN transistor.

  Note that the first conductivity type and the second conductivity type are in a complementary relationship, and the conductivity type may be reversed. For example, as shown in FIG. 1A, the semiconductor device 400B of the second example includes a first transistor unit 402 having one first transistor of a first conductivity type such as an nMOS or an NPN transistor, and a pMOS or PNP transistor. A second transistor unit 404 is provided in which “M−1” (M is a positive integer of 3 or more) second transistors of a second conductivity type different from the first conductivity type are cascade-connected. In the semiconductor device 400B, the first transistor portion 402 and the second transistor portion 404 are paired and arranged in M sets in parallel.

  In the figure, an example in which nMOS is used for the first transistor and pMOS is used for the second transistor is shown. The second transistor section 404 in which “M−1” pMOS second transistors 403 are cascade-connected exhibits pMOS characteristics as a whole and has a complementary relationship with the nMOS first transistor 401. In the case of a bipolar transistor, the first transistor may be replaced with an NPN type transistor and the second transistor may be replaced with a PNP type transistor.

  Control input terminals (MOS gates and bipolar bases) of the transistors 401 and 403 are connected to control input terminals 400CNT1 and 400CNT2 to which control signals for controlling on / off of the transistors 401 and 403 are input.

  The input terminal of the first transistor 401 of each first transistor section 402 is individually connected to each signal input terminal 400IN1. The output terminal of the first transistor 401 of each first transistor section 402 is individually connected to each signal output terminal 400OUT1 selected by the first transistor section 402.

  The input terminal of the second transistor 403 closest to the signal input side of each second transistor section 404 is individually connected to each signal input terminal 400IN2. The output terminal of the second transistor 403 closest to the signal output side of each second transistor section 404 is individually connected to each output terminal 400OUT2 for signals selected by the second transistor section 404.

  As a usage form of the semiconductor device 400 having such a configuration, a signal selection function of selecting any one of the signals input to the input terminals 400IN1 and 400IN2 and outputting the selected signal from the output terminals 400OUT1 and 400OUT2 can be considered. The connection mode of the control input terminals 400CNT1, 400CNT2, the input terminals 400IN1, 400IN2, and the output terminals 400OUT1, 400OUT2 at this time is as follows.

  First, the input terminals 400IN1 and 400IN2 of the same set are connected so that the same signal is input in common to the first transistor portion 402 and the second transistor portion 404 that form a pair. All sets of output terminals 400OUT1 and 400OUT2 are connected in common so that signals selected by the first transistor portions 402_k and the second transistor portions 404_k are transmitted to the subsequent stage side in one system.

  As a result, the switch cell SW_K of the paired first transistor portion 402_k and second transistor portion 404_k functions as a complementary switch (CMOS switch) in which the first transistor 401 and the second transistor 403 are complementarily connected. . These are further connected in parallel in M sets, so that the semiconductor device 400 functions as an M input-1 output type signal selection circuit (M input selector) of the control input terminals 400CNT1_k and 400CNT2_k. Connect as follows:

  That is, an active level for turning on the first transistor 401 is input to the control input terminal 400CNT1_k of the first transistor 401 for any one of the M first transistor portions 402 and the second transistor portions 404. In some cases, an active level for turning on each second transistor 403 is also input to the control input terminals 400CNT2_ * (* is other than k) of all the k sets of second transistors 403 to which the first transistor 401 belongs. For each of the other groups to which the first transistor 401 does not belong, an inactive level for turning off the first transistor 401 is input to the control input terminal 400CNT1_ * (* is other than k) of the first transistor 401, and at least An inactive level that turns off the second transistor 403 is also input to the control input terminal 400CNT2_ * (* may include k) of one second transistor 403.

  For this reason, the control input terminal 400CNT1_k of the first transistor 401 to which the active level of each set is input is different from each of the second transistor portions 404 of the other sets to which the first transistor 401 does not belong. The control input terminal 400CNT2_k of one second transistor 403 is connected.

  As an example, as shown in the drawing, the arrangement stages j of the first transistors 401 of the first transistor sections 402 in each set are arranged differently. In the second transistor unit 404 paired with the first transistor unit 402, “M−1” second transistors 403 are arranged in the remaining stage where the first transistor 401 is not arranged.

  In this state, a simple connection method is to connect the control input terminal 400CNT1_k of the first transistor 401 and the control input terminal 400CNT2_k of the second transistor 403 in the same stage so as to penetrate all the sets. . Hereinafter, the k sets of the j-stage transistors 401 and 403 are denoted as a first transistor 401_k, j and a second transistor 403_k, j, respectively. The same applies to each input / output terminal. In this way, a total of M × M transistors 401 and 403 can be controlled by M control wirings.

  For example, the control input terminal 400CNT1_1 of the first transistor 401_1,1 in the first stage of the set is commonly connected to the control input terminals 400CNT2_k of all the k second transistors 403_k, 1 except the one set. The control input terminals 400CNT1_1 of the two sets of first transistors 401_2 and 2 in the second stage are commonly connected to the control input terminals 400CNT2_k of all the k sets of the second transistors 403_k and 2 except the two sets. Similarly, the control input terminal 400CNT1_1 of the j-th first transistor 401_j, j in the j group is connected in common with the control input terminal 400CNT2_k of all the k second transistors 403_k, j except for the j group. To do.

  In such a configuration, nMOS (or pMOS) is cascaded for each group. The combination of pMOS and nMOS is different in relation to each set. Pairs of the first transistor portion 402 and the second transistor portion 404 are arranged in parallel by the number M of inputs. Regardless of the conductivity type of the transistor, a control signal is commonly input to the control input terminal (gate) of each stage of each set of transistors. The control signal is set to the active level for the first transistor 401 not connected in cascade, and the active level at this time is input as the control signal for the second transistor 403 connected in another group. As a result, a signal selection operation is performed.

  In the figure, in view of the ease of drawing and actual wiring layout, the arrangement stages of the first transistors 401 are different for each set so that the M control wirings CN are wired in a straight line, and the second transistors 403 are left behind. This is not essential, although it is shown to be placed on the stage. The arrangement stage of the first transistor 401 and the second transistor 403 is not limited to the illustrated one as long as the connection relation of the control wiring to each transistor is maintained so as to perform a signal selection operation described later. In such a modification of the arrangement stage, the arrangement stage of the first transistor 401 is substantially different for each set, and the second transistor 403 is arranged in the remaining stage and is input to the first transistor 401 not connected in cascade. It is assumed that the active level of the control signal to be set is an inactive level for the second transistor 403 connected in cascade. Ultimately, one set of first transistors 401 is connected (or connectable) to any one of the different second transistors 403 of each of the other sets of second transistor sections 404 and each control input terminal 400CNT. Therefore, the active level of the control signal input to the control input terminal 400CNT of the first transistor 401 may be input to the control input terminal 400CNT of the second transistor 403 of another set as an inactive level.

  FIG. 1B shows how control signals are applied in the semiconductor devices 400A and 400B shown in FIGS. 1 and 1A. It is assumed that a signal input to k sets is input k. In the case of pMOS, the active level is to set the gate (control input terminal) to L (low), and the inactive level is to set the gate to H (high). In the case of the semiconductor device 400A of the first example, As shown in FIG. 1B (1), an active L control signal XCN_k is used. On the other hand, in the case of an nMOS, the active level is to set the gate to H, and the inactive level to set the gate to L. In the case of the semiconductor device 400B of the second example, as shown in FIG. , Active H control signal CN_k is used.

  In the case of the semiconductor device 400A of the first example, as can be seen from FIG. 1B (1), when the control input terminal 400CNT1_j of the j sets of the first transistors 401_j, j is active L, all the other sets of the first transistors 401_. The control input terminal 400CNT1_ * of *, * (* is other than j) becomes inactive H. This inactive H becomes active H for the control input terminal 400CNT2_j, * of each of the j sets of second transistors 403_j, *. As a result, in the j group, the first transistor 401_j, j of the first transistor portion 402_j is turned on, and all the second transistors 401_j, * of the second transistor portion 402_j are turned on. On the other hand, the first transistor portion 402 and the second transistor 403 are all turned off except for j sets. As a result, only signals (input j) input to j sets are selected and output. Only one of the M control wirings is set to active L (potential low), and the remaining “M−1” control wirings are set to inactive H (potential high), thereby enabling signal selection.

  In the case of the semiconductor device 400B of the second example, as can be seen from FIG. 1B (2), when the control input terminal 400CNT1_j of the j sets of the first transistors 401_j, j is active H, all the other sets of the first transistors 401_. The control input terminal 400CNT1_ * of *, * (* is other than j) becomes inactive L. This inactive L becomes active L for the control input terminal 400CNT2_j, * of each of the j sets of the second transistors 403_j, *. As a result, in the j group, the first transistor 401_j, j of the first transistor portion 402_j is turned on, and all the second transistors 401_j, * of the second transistor portion 402_j are turned on. On the other hand, the first transistor portion 402 and the second transistor 403 are all turned off except for j sets. As a result, only signals (input j) input to j sets are selected and output. Only one of the M control wirings is set to active H (potential high), and the remaining “M−1” control wirings are set to inactive L (potential low), thereby enabling signal selection.

  As described above, the semiconductor devices 400A and 400B according to the present embodiment adopt the connection configuration in the configuration and use as described above, so that the M input-1 output type signal selection circuit includes M control wirings. In addition, it is realized by M × M transistors. In addition, in the semiconductor device 400 of the present embodiment, there is an advantage that a transmission gate (details will be described later) using both nMOS and pMOS is equivalently configured and can enjoy its properties.

  Here, when comparing the semiconductor device 400A of the first example using the pMOS for the first transistor 401 and the semiconductor device 400B of the second example using the nMOS for the first transistor 401, the semiconductor device 400A is: Regardless of the number of inputs M, if the number of series pMOS is one, it can be said that the number of control wires and the number of series pMOS can be reduced in a balanced manner. There is no difference in the number of control wirings and the number of transistors, but in the semiconductor device 400B of the second example, there is a disadvantage that the pMOS second transistor 403 is connected in series in the second transistor unit 404. That is, when comparing a pMOS and an nMOS, the pMOS is generally several times slower than the nMOS. Therefore, in the second example semiconductor device 400B in which the pMOSs are connected in series, the output change with respect to the input change is slower and the signal delay becomes larger than the first example semiconductor device 400A.

<Comparative example>
As shown in FIG. 1C (1), in the semiconductor device 400X of the first comparative example, the first transistor 401 (one of pMOS and nMOS: here pMOS) and the second transistor 403 (the other of pMOS and nMOS: here In this case, M complementary switches 408 are connected in parallel to function as an M input-1 output type signal selection circuit 500X. The complementary connection means that the first transistor 401 and the second transistor 403 are connected in parallel so as to complement each other.

  As a result, the semiconductor device 400X has M transfer gates having a CMOS configuration that function as an analog switch in which the first transistor 401 and the second transistor 403 are connected in parallel in a CMOS type. A transfer gate having a CMOS structure is also called a transmission gate or a transmission switch.

  The active L control signal XCN_k is input to each gate of the first transistor 401 of the pMOS, and the active H control signal CN_k is input to the gate of each of the second transistors 403 of the nMOS. The active L control signal XCN_k and the active H control signal CN_k are in a logically inverted (complementary) relationship. The semiconductor device 400X functioning as the M input-1 output type signal selection circuit 500X is controlled by 2 × M control wirings. Control signals having a complementary relationship such as a pair of control signals CN_k and XCN_k are also referred to as complementary control signals hereinafter.

  When the gate of the first transistor 401 is active L and the gate of the second transistor 403 is active H, both of the transmission gates, that is, the CMOS switches are turned on to output the input data as they are.

  The analog switch may be a transistor switch composed of only one of nMOS and pMOS. In this case, there are problems of on-resistance and threshold voltage Vth although the number of elements is small. In addition, although related to the threshold voltage Vth, when used as a switch for digital data, the nMOS can pass the L level but cannot pass the H level, and the pMOS can pass the H level but cannot pass the L level. appear. Therefore, although the number of transistors increases, a transmission gate that functions as an ideal switch that can pass both the L level and the H level by connecting nMOS and pMOS in parallel in a complementary connection form is employed. As a result, in the semiconductor device 400X of the first comparative example, 2 × M control wirings and 2 × M transistors are required to obtain an M input-1 output type signal selection circuit.

  When comparing the semiconductor devices 400A and 400B of the present embodiment with the semiconductor device 400X of the first comparative example, the number of transistors is smaller in the semiconductor device 400X, but the number of control wirings is larger in the semiconductor device 400X. For example, as described later, a solid-state imaging device (CMOS sensor) can be considered as a usage mode of the selector. In this case, the total number of inputs N is assumed to be several hundred to several thousand, and on the other hand, about three or six. If a selector having the same number of inputs is used, a very large number of selectors are controlled by the same control wiring. When a large number of selectors are connected to the control wiring, it is necessary to make the control wiring thick, and the number of control wirings should be reduced as much as possible due to layout circumstances. From this point of view, it is considered that the present embodiment having a smaller number of control wirings is more advantageous.

  As a mechanism for reducing the number of control wirings, a modification in which the active L control signal and the active H control signal have a logic inversion (complementary relationship) relationship can be considered. For example, as shown in FIG. 1C (2), the semiconductor device 400Y of the second comparative example has inverters 409 on the gate side of the pMOS first transistor 401 to which an active L control signal is input. Each inverter 409 receives an active H control signal in common with the gate of the paired nMOS second transistor 403. Although not shown, an inverter 409 is provided on each gate side of the nMOS second transistor 403 to which an active H control signal is input, and is active in common with the gate of the pMOS first transistor 401 paired with each inverter 409. An L control signal may be input.

  As described above, in the semiconductor device 400Y of the second comparative example functioning as the M input-1 output type signal selection circuit 500Y, one of the active H control signal and the active L control signal is logically inverted by the inverter 409. By generating (complementary relationship), the corresponding signal is generated by itself. By doing so, the M input-1 output type signal selection circuit can be controlled by M control wirings.

  However, in this case, the semiconductor device 400Y is larger than the semiconductor device 400X of the first comparative example by the additional amount of the inverter 409. For example, if a CMOS inverter in which a pMOS 409p and an nMOS 409n are cascade-connected as shown in the figure is used as the configuration of the inverter 409, two transistors are required in the inverter 409 portion, and in the case of M inputs, 2 × M Additional transistors are used. As a result, in the semiconductor device 400Y of the second comparative example, M control wirings and 4 × M transistors are required to make an M input-1 output type signal selection circuit.

  When the semiconductor devices 400A and 400B of the present embodiment and the semiconductor device 400Y of the second comparative example are compared, the number of control wirings is the same, but the number of transistors is larger in the semiconductor device 400Y. Is advantageous.

  Further, as another mechanism for reducing the number of control wirings, as in the semiconductor device 400Z_1 of the third comparative example (first example) shown in FIG. 1D (1), two complementary switches 408 are connected in parallel. It is also conceivable to arrange 2 ^ (K-1) 1-output type signal selection circuits (2-input selector 502V) in multiple stages to form a 2 ^ K input-1 output-type signal selection circuit 500Z_1. Further, as in the semiconductor device 400Z_2 of the third comparative example (second example) shown in FIG. 1D (2), a predetermined number of 2-input selectors 502V are omitted at a predetermined stage, and a signal is sent to the lower 2-input selector 502V. By adopting the form of direct input, it is possible to cope with the M input-1 output type signal selection circuit 500Z_2 having an arbitrary number of inputs M not limited to 2 ^ K.

  In the 2-input selector 502V, the gates of the pMOS and the nMOS are connected in common with the other complementary switch 408. In the same stage, these gates are connected in common. In each stage, a pair of control signals CN_k and XCN_k having a complementary relationship are commonly input to the 2-input selector 502V.

  Although not shown, in FIGS. 1D (1) and (2), similarly to FIG. 1A (2), an inverter 409 is provided, and one of the complementary control signals is logically inverted to generate the other. Is also possible.

  In the semiconductor device 400Z of the third comparative example, it is estimated that the number of control wirings is approximately the same as or less than that of the semiconductor devices 400A and 400B of the present embodiment, regardless of the number of inputs M. On the other hand, with three inputs, the number of transistors is larger than that of the semiconductor devices 400A and 400B of the present embodiment. With 4 inputs or more, the number of transistors is smaller than that of the semiconductor devices 400A and 400B of the present embodiment. However, in the semiconductor device 400Z of the third comparative example, there is a disadvantage that the pMOSs are connected in series regardless of the number M of inputs. This is a phenomenon similar to the semiconductor device 400B of the second example of the present embodiment. Therefore, the semiconductor device 400Z of the third comparative example has a larger delay than the semiconductor device 400A of the first example of this embodiment regardless of the number of inputs M.

<Signal selection circuit: basic configuration>
2 to 2C are diagrams illustrating the basic configuration of the signal selection circuit according to the present embodiment. The signal selection circuit 500 of the present embodiment uses the mechanism of the semiconductor devices 400A and 400B of the present embodiment described above to preliminarily determine the connection mode of the terminals of each transistor and the connection relationship with the input / output terminals of signals. It is specially configured for use. This is a configuration suitable for providing to the market as a so-called selector integrated circuit.

  It is also possible to provide an integrated circuit (signal selection circuit) for a selector with each input / output terminal of the semiconductor device 400 usable as the above-described M input-1 output type signal selection circuit. In this case, however, the number of terminals is naturally increased, and the user side is inconvenient and the terminal cost is increased such as pattern layout. As a countermeasure, the signal selection circuit 500 according to the present embodiment has a mechanism in which only the minimum input / output terminals necessary for the M input-1 output type signal selection circuit are provided to the user in advance.

  A signal selection circuit 500A of the first example shown in FIG. 2 corresponds to the semiconductor device 400A of the first example, and a signal selection circuit 500B of the second example shown in FIG. 2A corresponds to the semiconductor device 400B of the second example. To do. The signal selection circuits 500A and 500B have M signal input terminals 500IN_k to which signals are input from the outside, one signal output terminal 500OUT, and M control input terminals 500CNT_k.

  The input terminal 400IN1_k of the first transistor portion 402_k and the input terminal 400IN2_k of the second transistor portion 404_k are commonly connected to the signal input terminal 500IN_k. The input k is input as a signal to the signal input terminal 500IN_k. All sets of output terminals 400OUT1_k and 400OUT2_k are connected in common to the signal output terminal 500OUT, from which one of the inputs k selected by the signal selection circuits 500A and 500B is output.

  The first transistors 401 of the first transistor section 402 of each set are arranged at different stage positions (j stages). In the second transistor unit 404 paired with the first transistor unit 402, “M−1” second transistors 403 are arranged in the remaining stages where the first transistor 401 is not arranged. The gate of the first transistor 401 and the gate of the second transistor 403 in the same stage are connected in common so as to penetrate all sets, and are connected to the control input terminal 500CNT_k.

  Accordingly, the gates of the first transistors 401_j, j to which the active levels of the respective sets are input are connected to the second transistor portions 404_ * (except j) of other sets to which the first transistors 401_j, j do not belong. Are connected to the control input terminal 500CNT_j in common with the gate of any one of the different second transistors 403 _ *, * (excluding j, j).

  As a whole, M input-1 output type signal selection circuits 500A, 500B for controlling a total of M × M transistors 401, 403 by M control wirings are configured. Since the operation of the signal selection circuits 500A and 500B of this embodiment is the same as that in the case where the semiconductor devices 400A and 400B of this embodiment are used as signal selection circuits, description thereof is omitted here. Instead, a specific configuration will be shown and described below.

  The semiconductor devices 400A and 400B of the present embodiment are used as the signal selection circuit 500, and the signal selection circuits 500A and 500B of the present embodiment are used and configured as an M input-1 output type (so-called multiplexer). Not limited to. Like a general signal selection circuit (selector circuit), it can be used and configured as a 1-input-M-output type (so-called demultiplexer) in which the input / output of signals is reversed. Variations are also within the scope of this embodiment. For example, the third example signal selection circuit 500C shown in FIG. 2B reverses the input / output of the first example signal selection circuit 500A, and the fourth example signal selection circuit 500D shown in FIG. 2C is the second example signal selection circuit 500B. The input / output of is reversed. Since the signal is transmitted between the input and output when the transistor is turned on, it is possible to cope with the circuit without any special change when using the MOS, and in the signal transmission direction when using the bipolar transistor. In combination, the emitter and collector of the transistor may be disposed.

<3-input selector: basic>
3 to 3B show a 3-input-1-output type signal selection circuit 500 (a 3-input-1 output-type input selector 502, hereinafter referred to as 3-input selector 502A), which is a first specific example of the signal selection circuit 500 of this embodiment. FIG. Here, FIG. 3 is a diagram showing a circuit configuration of the three-input selector 502A of the present embodiment. FIG. 3A is a diagram showing a selector group in which a plurality of (three in the figure) three-input selectors 502A of this embodiment are arranged in one dimension. FIG. 3B is a diagram illustrating a control signal for controlling the 3-input selector 502A of the present embodiment.

  As shown in FIG. 3, in the three-input selector 502A, a first transistor portion 402_1 having one pMOS first transistor 401_1,1 and two nMOS second transistors 403_1,2, 403_1,3 are cascade-connected. The second transistor portion 404_1 is provided. The sources of the first transistors 401_1,1 and the drains of the second transistors 403_1,2 are commonly connected to a signal input terminal 500IN_1 to which the input 1 is input.

  The three-input selector 502A further includes a first transistor portion 402_2 having one pMOS first transistor 401_2,2 and a second transistor portion in which two nMOS second transistors 403_2,1, 403_2,3 are cascade-connected. 404_2 is provided. The sources of the first transistors 401_2 and 2 and the drains of the second transistors 403_2 and 1 are commonly connected to a signal input terminal 500IN_2 to which the input 2 is input.

  The three-input selector 502A further includes a first transistor portion 402_3 having one pMOS first transistor 401_3,3 and a second transistor portion in which two nMOS second transistors 403_3,1,403_3,2 are connected in cascade. 404_3. The source of the first transistor 401_3,3 and the drain of the second transistor 403_3,1 are commonly connected to the signal input terminal 500IN_3 to which the input 3 is input.

  The drain of the first transistor 401_1,1, the source of the second transistor 403_1,3, the drain of the first transistor 401_2,2, the source of the second transistor 403_2,3, the drain of the first transistor 401_3,3, the second transistor 403_3, The two sources are connected in common to the signal output terminal 500OUT.

  The gates of the first transistors 401_1,1 and the gates of the second transistors 403_2,1, 403_3,1 are commonly connected to the control input terminal 500CNT_1 to which the control signal XA is input. The gates of the first transistors 401_2, 2 and the gates of the second transistors 403_1, 2, 403_3, 2 are commonly connected to the control input terminal 500CNT_2 to which the control signal XB is input. The gates of the first transistors 401_3, 3 and the gates of the second transistors 403_1, 3, 403_2, 3 are commonly connected to the control input terminal 500CNT_3 to which the control signal XC is input.

  As shown in FIG. 3A, in a selector group in which a plurality of three-input selectors 502A are arranged one-dimensionally, control signals XA, XB, and XC are connected so as to be commonly used by the three-input selectors 502A_1, 502A_2, and 502A_3. The

  The control signals XA, XB, and XC are all active L for the first transistors 401_1, 1, 401_2, 2, 401_3, and 3 of the pMOS, but are inactive L for the second transistors 403 of the nMOS. Therefore, as shown in FIG. 3B, when the control signal XA is L and the control signals XB and XC are H, the input 1 is selected and output from the signal output terminal 500OUT. When the control signal XB is L and the control signals XA and XC are H, the input 2 is selected and output from the signal output terminal 500OUT. When the control signal XC is L and the control signals XA and XB are H, the input 3 is selected and output from the signal output terminal 500OUT. Only one of the three control signals XA, XB, and XC is set to a low potential, and the remaining two are set to a high potential to select one of the inputs 1, 2, and 3, and the signal output terminal 500OUT Is output.

<Comparison of 3-input selector>
4 to 4F are diagrams for explaining a comparison between the 3-input selector 502A of this embodiment and the comparative example. Here, FIG. 4 is a diagram showing a circuit configuration of the three-input selector 502W of the first comparative example. FIG. 4A is a diagram showing a circuit configuration of the 3-input selector 502X of the second comparative example. FIG. 4B is a diagram showing a circuit configuration of the 3-input selector 502Y of the third comparative example. FIG. 4C is a diagram showing a circuit configuration of the 3-input selector 502Z of the fourth comparative example. FIG. 4D is a diagram showing a selector group in which a plurality of three-input selectors 502W of the first comparative example are arranged one-dimensionally. 4E and 4F are diagrams summarizing the effects of the three-input selector 502A of this embodiment in comparison with the comparative example.

  A three-input selector 502W of the first comparative example shown in FIG. 4 is based on the idea shown in FIG. 1C (1), and includes three complementary switches 408_1, 408_2, and 408_3. The complementary switches 408_1, 408_2, and 408_3 are individually connected to the corresponding signal input terminals 500IN_1, 500IN_2, and 500IN_3 on the input sides, and the output sides are commonly connected to the signal output terminal 500OUT. Control signals A, B, and C are input to the nMOS first transistors 401_1, 401_2, and 401_3, respectively, and control signals XA, XB, and XC are input to the pMOS second transistors 403_1, 403_2, and 403_3, respectively. Is done. Control signals A, B, C and control signals XA, XB, XC are in a complementary relationship.

  As shown in FIG. 4D, in a selector group in which a plurality of three-input selectors 502W of the first comparative example are arranged one-dimensionally, control signals XA, XB, XC and control signals XA, XB, XC are respectively three-input selectors 502W_1. , 502W_2 and 502W_3 are connected to be used in common. Six control wirings extend along the arrangement direction of the three-input selector 502W.

  As shown in FIG. 4E, the three-input selector 502W has six control wirings (hereinafter also referred to as CN number), six transistors (hereinafter also referred to as TR number), and six control wirings. Will increase.

  The 3-input selector 502X of the second comparative example shown in FIG. 4A is based on the idea shown in FIG. 1C (2), and is one of the complementary control signals (control signal XA) with respect to the 3-input selector 502X of the first comparative example. , XB, and XC, inverters 409_1, 409_2, and 409_3 (CMOS inverters) in which pMOS 409p and nMOS 409n are connected in cascade are added to the gate sides of the pMOS second transistors 403_1, 403_2, and 403_3, respectively. , 409_2, and 409_3 receive control signals A, B, and C, which are the other of the complementary control signals, in common with the gates of the paired nMOS first transistors 401_1, 401_2, and 401_3, respectively, and control signals XA, XB , XC is generated separately.

  As shown in FIG. 4E, the three-input selector 502X generates the control signals XA, XB, and XC by inverting (complementary) the control signals A, B, and C by the inverter 409, so that the first comparison Although the number of control wirings is reduced to three, which is half of the three-input selector 502W in the example, the number of transistors is increased by six because of the three inverters 409 (TR number = 2) and becomes twelve. The number will increase.

  In the three-input selector 502Y of the third comparative example shown in FIG. 4B, two one-input selectors 502V each having two complementary switches 408_1 and 408_2 connected in parallel are arranged in two stages. In the first-stage 2-input selector 502V_1, one input terminal is connected to the signal input terminal 500IN_1 to which the input 1 is input, and the other input terminal is connected to the signal input terminal 500IN_2 to which the input 2 is input. The second-stage 2-input selector 502V_2 has one input terminal connected to the output of the first-stage 2-input selector 502V_1, and the other input terminal connected to the signal input terminal 500IN_3 to which the input 3 is input. Is connected to the signal output terminal 500OUT.

  In the two-input selectors 502V_1 and 502V_2, the gates of the pMOS and the nMOS are connected in common between the complementary switches 408_1 and 408_2, respectively. The control signal A and the control signal XA that are complementary to each other are input to the first-stage 2-input selector 502V_1. The control signal D and the control signal XD having a complementary relationship are input to the second-stage 2-input selector 502V_2.

  As shown in FIG. 4E, the three-input selector 502Y has four control wires, eight transistors, and a large number of control wires. In addition, there is a maximum of two stages of pMOS between the input and output (when input 1 or input 2 is selected), resulting in a large delay.

  A three-input selector 502Z of the fourth comparative example shown in FIG. 4C has inverters 409_1 and 409_2 (CMOS inverters) added based on the three-input selector 502Y of the third comparative example. The inverter 409_1 receives the control signal A as an input and generates a control signal XA. The inverter 409_2 receives the control signal D as an input and generates a control signal XD.

  As shown in FIG. 4E, the three-input selector 502Z generates the control signals XA and XD by inversion of the control signals A and D by the inverter 409 (complementary relationship). Although the number of control wirings can be reduced to two, which is half that of the selector 502Y, the number of transistors is increased by 4 because of the two inverters 409 (TR number = 2), and the number of transistors increases. End up. In addition, also in this case, a maximum of two stages of pMOS are provided between the input and the output (when input 1 or input 2 is selected), and the delay becomes large.

  Thus, in the three-input selectors 502W to 502Z of the first to fourth comparative examples, either the number of transistors increases or the number of control wirings increases.

  On the other hand, in the three-input selector 502A of this embodiment, as shown in FIG. 4E, the number of control wirings is three and the number of transistors is nine. When the number of control wirings needs to be 3 or less, the number of transistors can be minimized, and when the number of transistors needs to be 9 or less, the number of control wirings can be minimized. It can be seen that the three-input selector 502A of this embodiment can reduce the number of control wirings and the number of transistors in a more balanced manner than the first to fourth comparative examples. Further, in the three-input selector 502A of this embodiment, the number of serial pMOSs is one, and the output change with respect to the input change is fast. The number of transistors, the number of control wires, and the number of series pMOSs can be reduced in a balanced manner, which is a new choice of signal selection circuit (selector). In addition, precharging or the like is not necessary. It is possible to realize a three-input selector that can reduce the number of control wirings and the number of transistors in a balanced manner, and further reduce the number of series pMOS, and a selector group in which a plurality of three-input selectors are arranged in one dimension.

<3-input selector: first modification>
FIG. 5 shows a plurality of three-input / one-output type signal selection circuits 500 (hereinafter referred to as three-input selectors 502B of the first modification) which are a second specific example of the signal selection circuit 500 of the present embodiment. FIG.

  Each of the three-input selectors 502B_k of the first modified example includes inverters 509_1, 509_2, and 509_3 (CMOS inverters) in which a pMOS 509p and an nMOS 509n are cascade-connected based on the above-described three-input selector 502A. Each inverter 509_1 receives a control signal A in common and generates a control signal XA_k separately. Each inverter 509_2 receives the control signal B in common and generates a control signal XB_k separately. Each inverter 509_3 receives a control signal C in common and generates a control signal XC_k separately.

  The control node of each three-input selector 502B_k is driven by a common control signal A, B, C, although it is different from the control signals XA_1, XB_1, XC_1, control signals XA_2, XB_2, XC_2, and control signals XA_3, XB_3, XC_3, Each of the three control signals XA_1, XB_1, XC_1, control signals XA_2, XB_2, XC_2, and control signals XA_3, XB_3, XC_3 behave similarly. The signal selection operation is not much different from the 3-input selector 502A.

  However, in each of the three-input selectors 502B_k, the number of transistors increases by six due to three inverters 509_k (TR number = 2) to 18 and the number of transistors increases. Although it is inferior to the basic configuration of the three-input selector 502A in terms of the balance between the number of control wirings and the number of transistors, the number of control wirings can be reduced at least as compared with the first and third comparative examples, and the number of series pMOSs is surely set to "1" it can. It can be said that the number of control wirings and the number of series pMOSs can be reduced in a balanced manner.

<3-input selector: second modification>
6 to 6B illustrate a 3-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 3-input selector 502C of the second modified example) which is a third specific example of the signal selection circuit 500 of the present embodiment. FIG. Here, FIG. 6 is a diagram showing a circuit configuration of the three-input selector 502C. FIG. 6A is a diagram showing a selector group in which a plurality of (three in the figure) three-input selectors 502C according to the second modification are arranged in one dimension. FIG. 6B is a diagram for explaining a control signal for controlling the 3-input selector 502C of the second modified example.

  The 3-input selector 502C of the second modification is obtained by reversing the use of pMOS and nMOS for the first transistor 401 and the second transistor 403 with respect to the 3-input selector 502A.

  As shown in FIG. 6, in the three-input selector 502C, a first transistor section 402_1 having one nMOS first transistor 401_1,1 and two pMOS second transistors 403_1, 2, 403_1, 3 are connected in cascade. The second transistor portion 404_1 is provided. The sources of the first transistors 401_1,1 and the drains of the second transistors 403_1,2 are commonly connected to a signal input terminal 500IN_1 to which the input 1 is input.

  The 3-input selector 502C further includes a first transistor portion 402_2 having one nMOS first transistor 401_2,2 and a second transistor portion in which two pMOS second transistors 403_2,1, 403_2,3 are cascade-connected. 404_2 is provided. The sources of the first transistors 401_2 and 2 and the drains of the second transistors 403_2 and 1 are commonly connected to a signal input terminal 500IN_2 to which the input 2 is input.

  The three-input selector 502C further includes a first transistor portion 402_3 having one nMOS first transistor 401_3,3 and a second transistor portion in which two pMOS second transistors 403_3,1,403_3,2 are cascade-connected. 404_3. The source of the first transistor 401_3,3 and the drain of the second transistor 403_3,1 are commonly connected to the signal input terminal 500IN_3 to which the input 3 is input.

  The drain of the first transistor 401_1,1, the source of the second transistor 403_1,3, the drain of the first transistor 401_2,2, the source of the second transistor 403_2,3, the drain of the first transistor 401_3,3, the second transistor 403_3, The two sources are connected in common to the signal output terminal 500OUT.

  The gates of the first transistors 401_1,1 and the gates of the second transistors 403_2,1, 403_3,1 are commonly connected to the control input terminal 500CNT_1 to which the control signal A is input. The gates of the first transistors 401_2, 2 and the gates of the second transistors 403_1, 2, 403_3, 2 are commonly connected to the control input terminal 500CNT_1 to which the control signal B is input. The gates of the first transistors 401_3, 3 and the gates of the second transistors 403_1, 3, 403_2, 3 are commonly connected to a control input terminal 500CNT_1 to which a control signal C is input.

  As shown in FIG. 6A, in a selector group in which a plurality of three-input selectors 502C are arranged one-dimensionally, control signals A, B, and C are connected so as to be commonly used by the three-input selectors 502C_1, 502C_2, and 502C_3. The

  The control signals A, B, and C are all active H for the nMOS first transistors 401_1, 1, 401_2, 2, 401_3, 3 but inactive H for the second transistors 403 of the pMOS. For this reason, as shown in FIG. 6B, when the control signal A is H and the control signals B and C are L, the input 1 is selected and output from the signal output terminal 500OUT. When the control signal B is H and the control signals A and C are L, the input 2 is selected and output from the signal output terminal 500OUT. When the control signal C is H and the control signals A and B are L, the input 3 is selected and output from the signal output terminal 500OUT. Only one of the three control signals A, B, and C is set to potential high, and the other two are set to potential low to select one of the inputs 1, 2, and 3, and the signal output terminal 500OUT Is output.

  The 3-input selector 502C of the second modified example reverses the use of the pMOS and nMOS for the first transistor 401 and the second transistor 403 with respect to the 3-input selector 502A, but the handling of the control signal level is also reversed. There is no big difference in the basic signal selection operation. The number of control wires is three and the number of transistors is nine, which is the same as the three-input selector 502A. Compared with the first to fourth comparative examples, the three-input selector 502C has the number of control wires and the number of transistors. Can be reduced in a well-balanced manner, and precharging or the like need not be performed.

  However, regardless of which input is selected, there are two stages of pMOS between the input and the output, resulting in a large delay. The change in output with respect to the change in input is slower than that in the three-input selector 502A.

  Although not shown, a modified configuration similar to that of the first modified example based on the three-input selector 502A can be adopted on the basis of the three-input selector 502C. Even in such a modification, the number of control wirings can be reduced at least as compared with the first and third comparative examples.

<4-input selector: basic>
7 and 7A are diagrams for explaining a 4-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 4-input selector 502D in the first example), which is a fourth specific example of the signal selection circuit 500 of the present embodiment. It is. Here, FIG. 7 is a diagram illustrating a circuit configuration of the 4-input selector 502D of the first example. FIG. 7A is a diagram illustrating a control signal for controlling the 4-input selector 502D of the first example.

  In order to support four inputs, the four-input selector 502D has four pairs of the first transistor portion 402_k and the second transistor portion 404_k, and three nMOS second transistors 403_k, j are cascaded in each second transistor portion 404_k. Connected. The concept of the connection mode of the gate, source, and drain is the same as that of the semiconductor device 400A, the signal selection circuit 500A, and the three-input selector 502A. For example, the gate of the fourth transistor 401_4,4 in the fourth set to which the input 4 is input and the gate of the second transistor 403_1,4,403_2,4,403_3,4 are connected to the control input terminal 500CNT_4 to which the control signal XD is input. Connected in common.

  The control signals XA, XB, XC, and XD are all active L for the first transistors 401_1, 1, 401_2, 2, 401_3, 3, 401_4, 4 of the pMOS, but for the second transistors 403 of the nMOS. Inactive L. Therefore, as shown in FIG. 7A, when the control signal XA is L and the control signals XB, XC, and XD are H, the input 1 is selected and output from the signal output terminal 500OUT. When the control signal XB is L and the control signals XA, XC, and XD are H, the input 2 is selected and output from the signal output terminal 500OUT. When the control signal XC is L and the control signals XA, XB, and XD are H, the input 3 is selected and output from the signal output terminal 500OUT. When the control signal XD is L and the control signals XA, XB, and XC are H, the input 4 is selected and output from the signal output terminal 500OUT. Only one of the four control signals XA, XB, XC, and XD is set to potential low, and the remaining three are set to potential high to select one of inputs 1, 2, 3, and 4. The operation of outputting from the signal output terminal 500OUT is performed.

<Comparison of 4-input selector>
FIG. 7B is a diagram illustrating a comparison between the 4-input selector 502D of the first example and the comparative example. The operational effects of the 4-input selector 502D are collectively shown in comparison with the comparative example.

  Although illustration is omitted, each comparative example has the following configuration. The four-input selector of the first comparative example is of the concept shown in FIG. 1C (1), like the three-input selector 502W of the first comparative example, and has a configuration including four complementary switches 408. Each complementary switch 408 is controlled by a pair of control signals A, B, C, D and control signals XA, XB, XC, XD. In the 4-input selector of the first comparative example, in comparison with the 3-input selector 502Y, two control wirings are added to 8 (= 2 × 4), and one complementary switch 408 is added. Increases by two to eight.

  The 4-input selector of the second comparative example is based on the idea shown in FIG. 1C (2), like the 3-input selector 502X of the second comparative example, and is based on the 4-input selector of the first comparative example. A CMOS inverter is added, and the other complementary control signal (control signals XA, XB, XC, and XD) is generated for each CMOS inverter based on one of the complementary control signals (control signals A, B, C, and D). The four-input selector of the second comparative example is reduced to four half the number of control wirings compared to the four-input selector of the first comparative example, but the number of transistors is four CMOS inverters (TR number = 2). For this reason, the number of transistors increases by 8 to 16 and the number of transistors increases.

  The 4-input selector of the third comparative example is based on the same idea as the 3-input selector 502Y of the third comparative example. Two 2-input selectors 502V are arranged in the first stage, and one 2-input selector 502V is installed. It is arranged at the second stage. In the first stage, inputs 1, 2, 3, and 4 are individually input to the input terminals, and the outputs of the first-stage 2-input selector 502V are used as the second stage inputs. The first and second stages are controlled by different complementary control signals (control signals A and XA and control signals D and XD). The four-input selector of the third comparative example has four control wirings in comparison with the three-input selector 502Y, but the number of transistors increases by four because one 2-input selector 502V is added. It will be 12 pieces. Also, two stages of pMOS are inserted between the input and the output.

  The 4-input selector of the fourth comparative example has the same idea as the 3-input selector 502Z of the fourth comparative example, and two CMOS inverters are added based on the 4-input selector of the third comparative example. The inverter generates the other of the complementary control signals (control signals XA and XD) based on one of the complementary control signals (control signals A and D). The 4-input selector of the fourth comparative example is reduced to two half the number of control wirings compared to the 4-input selector of the third comparative example, but two CMOS inverters (TR number = 2) are added. Therefore, the number of transistors is increased by 4 to 16 transistors.

  The four-input selector 502D of the first example has four control wires, sixteen transistors, and one serial pMOS, which is equivalent to the second comparative example. However, in comparison with the first comparative example, the number of control wirings can be reduced, and in comparison with the third and fourth comparative examples, the output change with respect to the input change is fast. Considering that the number of series pMOS is one, it can be said that the number of control wires and the number of series pMOS can be reduced in a balanced manner.

<< Selector using prime factorization: basic >>
In configuring the signal selection circuit 500, the input number M is primed into a form of multiplication of a prime number M_k (k is a positive integer of 1 or more) such as “M = M_1 × M_2 × M_3 ×. The M_k input-1 output type signal selection circuit 500 may be hierarchized (multi-stage configuration). In a stage where a plurality of M_k input-1 output type signal selection circuits 500 are arranged in parallel, a configuration in which control signals are supplied in common reduces the number of control wirings as a whole and enjoys the advantages of wiring layout It is. A specific configuration will be shown and described below.

<6-input selector: basic>
8 to 8C are diagrams for explaining a 6-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 6-input selector 502E) which is a fifth specific example of the signal selection circuit 500 of the present embodiment. Here, FIG. 8 is a circuit block diagram of the 6-input selector 502E of the present embodiment. FIG. 8A is a diagram showing a circuit configuration of the 6-input selector 502E of the present embodiment. FIG. 8B is a diagram showing a selector group in which a plurality of (three in the figure) six-input selectors 502E of this embodiment are arranged in one dimension. FIG. 8C is a diagram illustrating a control signal for controlling the 6-input selector 502E of the present embodiment.

  If 6 is prime factorized, it becomes “2 × 3”. Therefore, any one of the three-input selectors 502A to 502C of this embodiment is used for “3” and combined with the two-input selector 502V to form a two-stage hierarchy. Thus, the 6-input selector 502E can be configured. There are two possible ways of arranging each stage to support 6 inputs: “2 inputs → 3 inputs” and “3 inputs → 2 inputs”.

  In the 6-input selector 502Ea of the first example shown in FIGS. 8A and 8A, three 2-input selectors 502V_1, 502V_2, and 502V_3 are arranged in the first stage, and a 3-input selector 502A that receives the outputs thereof. Is arranged in the second row. The control signal D and the control signal XD having a complementary relationship are commonly supplied to the two-stage selectors 502V_1, 502V_2, and 502V_3 in the first stage. In the illustrated example, in the first stage, when the control signal D is H and the control signal XD is L, the inputs 1, 3 and 5 are selected, and when the control signal D is L and the control signal XD is H, the input 2 , 4 and 6 are selected. One of input 1 and input 2 is selected by 2-input selector 502V_1, one of input 3 and input 4 is selected by 2-input selector 502V_2, and one of input 5 and input 6 is selected by 2-input selector 502V_3 Is selected. One of the three signals selected by the three two-input selectors 502V_1, 502V_2, and 502V_3 is selected by the three-input selector 502A.

  In the 6-input selector 502Eb of the second example shown in FIG. 8 (2), two 3-input selectors 502A_1 and 502A_2 are arranged in the first stage, and the 2-input selector 502V that receives the outputs is arranged in the second stage. It is arranged. The active L control signals XA, XB, and XC for the pMOS are commonly supplied to the first three-input selectors 502A_1 and 502A_2. One of input 1, input 2, and input 3 is selected by the three-input selector 502A_1, and one of input 4, input 5, and input 6 is selected by the three-input selector 502A_2. Then, one of the two signals selected by the two three-input selectors 502A_1 and 502A_2 is selected by the two-input selector 502V. In the configuration in which “3” enters the first stage, the number of transistors increases because two 3-input selectors 502A of the present embodiment are used. The first example is more advantageous because it has a smaller number of transistors.

  As shown in FIG. 8B, in a selector group in which a plurality of 6-input selectors 502Ea are arranged one-dimensionally, the control signals D and XD related to the first stage and the control signals XA, XB and XC related to the second stage are the 6-input selectors 502Ea_1. , 502Ea_2 and 502Ea_3 are connected so as to be used in common.

  As shown in FIG. 8C, when the control signal XA is L and the control signals XB and XC are H, either the input 1 or 2 is selected. When the control signal D is H, the input 1 is selected and the control signal is selected. If XD is H, input 2 is selected and output from the signal output terminal 500OUT. When the control signal XB is L and the control signals XA and XC are H, either the input 3 or 4 is selected. However, if the control signal D is H, the input 3 is selected, and if the control signal XD is H, the input is selected. 4 is selected and output from the signal output terminal 500OUT. When the control signal XC is L and the control signals XA and XB are H, either the input 5 or 6 is selected. However, if the control signal D is H, the input 5 is selected, and if the control signal XD is H, the input is selected. 6 is selected and output from the signal output terminal 500OUT. Only one of the three control signals XA, XB, and XC is set to the potential low and the other two are set to the potential high, and only one of the control signals D and XD is set to the potential high and the other is set to the other. Is set to a low potential, and only one of the inputs 1, 2, 3, 4, 5, 6 is selected and output from the signal output terminal 500OUT.

<Comparison of 6-input selector>
8D and 8E are diagrams for explaining a comparison between the 6-input selector 502Ea of the first example of this embodiment and the comparative example. The effects of the 6-input selector 502Ea are shown in comparison with the comparative example.

  Although illustration is omitted, each comparative example has the following configuration. The 6-input selector of the first comparative example is based on the idea shown in FIG. 1C (1), similarly to the 3-input selector 502W of the first comparative example, and has a configuration including six complementary switches 408. Each complementary switch 408 is controlled by a pair of an active high control signal for nMOS and an active low control signal for pMOS. The number of control wirings is 12 (= 2 × 6), and the number of transistors is 12 (= 2 × 6).

  The 6-input selector of the second comparative example is based on the idea shown in FIG. 1C (2), similar to the 3-input selector 502X of the second comparative example. Based on the 6-input selector of the first comparative example, A CMOS inverter is added, and each CMOS inverter generates the other complementary control signal separately based on one of the complementary control signals. In the 6-input selector of the second comparative example, the number of control wirings is reduced to 6 which is half that of the 6-input selector of the first comparative example, but the number of transistors is 6 CMOS inverters (TR number = 2). For this reason, the number of transistors increases by 12 to 24, and the number of transistors increases.

  The 6-input selector of the third comparative example is based on the same idea as the 3-input selector 502X of the third comparative example. For example, two 2-input selectors 502V are installed in the first stage and two 2-input selectors 502V are installed. In the second stage, one 2-input selector 502V is arranged in the third stage. In the first stage, inputs 1, 2, 3, and 4 are individually input to the input terminals, and the outputs of the first-stage 2-input selector 502V are supplied to the two inputs of one 2-input selector 502V in the second stage. Input to the end. Inputs 5 and 6 are separately input to the other two-input selector 502V in the second stage. In the third stage, each output of the second-stage 2-input selector 502V is input to two input terminals. Since the six-input selector of the third comparative example has a three-stage configuration, three sets of complementary control signals are used, and the number of control wirings is six (= 2 × 3), and five two-input selectors 502V (the number of TRs = Since 4) is used, the number of transistors is 20. In addition, there are three stages of pMOS between the input and output.

  The 6-input selector of the fourth comparative example is based on the same idea as the 3-input selector 502Z of the fourth comparative example. Three CMOS inverters are added based on the 6-input selector of the third comparative example. Based on one of the complementary control signals, the other of the complementary control signals is generated separately. The 6-input selector of the fourth comparative example is reduced to half the number of control wirings with respect to the 6-input selector of the third comparative example, but three CMOS inverters (TR number = 2) are added. Therefore, the number of transistors increases by 6 to 26.

  The 6-input selector 502Ea of the first example of the present embodiment has three 2-input selectors 502V (CN number = 2, TR number = 4) arranged in the first stage, and one 3-input selector 502A (CN number = 3). , TR number = 9) is arranged in the second stage. Therefore, the number of control wirings is 5, the number of transistors is 21 (= 3 × 4 + 9), and the number of series pMOSs is 2. When the number of control wirings needs to be 5 or less, the number of transistors can be minimized, and when the number of transistors needs to be 21 or less, the number of control wirings can be minimized. It can be seen that the 6-input selector 502E of this embodiment can reduce the number of control wirings and the number of transistors in a more balanced manner than the first to fourth comparative examples. There is no need to precharge. The 6-input selector 502E of this embodiment is a new option in the 6-input selector, although there is a difficulty that the change in output is slow because the number of serial pMOS is two.

<9-input selector: basic>
FIG. 9 is a circuit block diagram of a 9-input / 1-output type signal selection circuit 500 (hereinafter referred to as 9-input selector 502F), which is a sixth specific example of the signal selection circuit 500 of the present embodiment.

  If 9 is factored, it becomes “3 × 3”, so that any of the 3-input selectors 502A to 502C of this embodiment can be arranged in two stages to form the 9-input selector 502F.

  The arrangement of each stage to support 9 inputs is one of “3 inputs → 3 inputs”. For example, three three-input selectors 502A_1, 502A_2, and 502A_3 are arranged in the first stage, and a three-input selector 502A_4 that receives their outputs is arranged in the second stage. Control signals XD, XE, and XF are commonly supplied to the first-stage three-input selectors 502A_1, 502A_2, and 502A_3. Control signals XA, XB, and XC are supplied to the second-stage three-input selector 502A_4.

  One of the three inputs of each group is selected by the three first-stage three-input selectors 502A_1, 502A_2, and 502A_3, and the second-stage three-input selector 502A_4 selects the first-stage three-input selectors 502A_1, 502A_2, One of the three signals selected in 502A_3 is selected. For example, only one of the inputs 1, 2, and 3 is selected by the 3-input selector 502A_1, only one of the inputs 4, 5, and 6 is selected by the 3-input selector 502A_2, and input by the 3-input selector 502A_3 Only one of 7, 8, and 9 is selected. Then, one of the three signals selected by the three three-input selectors 502A_1, 502A_2, and 502A_3 is selected by the three-input selector 502A_4.

  Only one of the three control signals XA, XB, and XC is set to the potential low and the other two are set to the potential high, and only one of the three control signals XD, XE, and XF is set. By setting the potential low and the remaining two potential high, only one of the inputs 1 to 9 is selected and output from the signal output terminal 500OUT.

<Comparison of 9-input selector>
FIG. 9A is a diagram illustrating a comparison between the 9-input selector 502F of this embodiment and the comparative example. The effects of the 9-input selector 502F are collectively shown in comparison with the comparative example.

  Although illustration is omitted, each comparative example has the following configuration. The 9-input selector of the first comparative example is based on the idea shown in FIG. 1C (1), similarly to the 3-input selector 502W of the first comparative example, and each of the nine complementary switches 408 is an active L for the pMOS. The control is performed by a pair of the control signal and the active H control signal for the nMOS. The 9-input selector of the first comparative example has 18 control lines (= 2 × 9) and 18 transistors (= 2 × 9).

  The 9-input selector of the second comparative example is based on the idea shown in FIG. 1C (2), similar to the 3-input selector 502X of the second comparative example, and is based on the 9-input selector of the first comparative example. A CMOS inverter is added, and each CMOS inverter generates the other complementary control signal separately based on one of the complementary control signals. In the 9-input selector of the second comparative example, the number of control wirings is reduced to 9 which is half that of the 9-input selector of the first comparative example, but the number of transistors is 9 CMOS inverters (TR number = 2). Therefore, the number of transistors increases to 18 to 36, and the number of transistors increases.

  The 9-input selector of the third comparative example is based on the same idea as the 3-input selector 502X of the third comparative example. For example, four 2-input selectors 502V are placed in the first stage and two 2-input selectors 502V are installed. In the second stage, one 2-input selector 502V is arranged in the third stage, and one 2-input selector 502V is arranged in the fourth stage. Only one of the inputs 1 to 8 is selected up to the third stage, and separation from the remaining inputs 9 is performed at the fourth stage. Therefore, in the first stage, eight inputs 1 to 8 are individually input to the input terminals, and the outputs of the four two-input selectors 502V in the first stage are input to the two two-input selectors 502V in the second stage. Each input of Each output of the second-stage 2-input selector 502V is input to the third-stage 2-input selector 502V, and the third-stage output is used as one input of the fourth-stage 2-input selector 502V. The remaining input 9 is input to the other of the four-stage 2-input selector 502V. Since the 9-input selector of the third comparative example has a 4-stage configuration, 4 sets of complementary control signals are used, the number of control wirings is 8 (= 2 × 4), and 8 2-input selectors 502V (the number of TRs = Since 4) is used, the number of transistors is 32. In addition, there are four stages of pMOS between the input and output.

  The 9-input selector of the fourth comparative example is based on the same idea as the 3-input selector 502Z of the fourth comparative example. Based on the 9-input selector of the third comparative example, four CMOS inverters are added to each CMOS. The inverter generates the other of the complementary control signals separately based on one of the complementary control signals. The 9-input selector of the fourth comparative example reduces the number of control wirings to four, which is half of the 9-input selector of the third comparative example, but adds four CMOS inverters (TR number = 2). As a result, the number of transistors increases by 8 to 40.

  The 9-input selector 502F of the present embodiment uses four 3-input selectors 502A (CN number = 3, TR number = 9), and three are arranged in the first stage and one is arranged in the second stage. Therefore, the number of control wirings is 6 (= 3 × 2), the number of transistors is 36 (= 9 × 4), and the number of serial pMOSs is 2. When the number of control wirings needs to be 6 or less, the number of transistors can be minimized, and when the number of transistors needs to be 36 or less, the number of control wirings can be minimized. It can be seen that the 9-input selector 502F of this embodiment can reduce the number of control wirings, the number of transistors, and the number of series pMOSs in a more balanced manner than the first to fourth comparative examples. There is no need to precharge. The 9-input selector 502F of this embodiment is a new option in the 9-input selector, although there are drawbacks that the number of serial pMOSs is 2 and the change in output is slow.

  Although not shown, even when the 3 ^ K input selector (K is 3 or more) is configured by combining only the 3-input selector 502A, the same effect can be obtained in comparison with the comparative examples of the same idea.

<12-input selector: basic>
FIG. 10 is a circuit block diagram of a 12-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 12-input selector 502G), which is a seventh specific example of the signal selection circuit 500 of the present embodiment.

  If 12 is prime factorized, it becomes “2 × 2 × 3”. The arrangement of each stage is “2 inputs → 2 inputs → 3 inputs”, “2 inputs → 3 inputs → 2 inputs”, “3 inputs”. There are three possible ways: → 2 input → 2 input. Any of the three-input selectors 502A to 502C of the present embodiment is used for the portion “3”. The configuration of “2 inputs → 2 inputs → 3 inputs” is a configuration in which a 3-input selector is further arranged on the output of the 4-input selector configured by “2 inputs → 2 inputs”. The configuration of “2 inputs → 3 inputs → 2 inputs” and “3 inputs → 2 inputs → 2 inputs” is further added to the output of the 6 input selector configured by “2 inputs → 3 inputs” or “3 inputs → 2 inputs”. It has a configuration in which a two-input selector is arranged. In the configuration where “3” enters the first stage, four of the three-input selectors 502A to 502C of the present embodiment are used, and in the configuration where “3” enters the second stage, the 3-input selector 502A of the present embodiment. Since any two of .about.502C are used, the number of transistors increases.

  Therefore, in this embodiment, a configuration of “2 inputs → 2 inputs → 3 inputs” is employed. The 12-input selector 502G of this embodiment shown in FIG. 10 has six 2-input selectors 502V arranged in the first stage, three 2-input selectors 502V arranged in the second stage, and one 3-input selector 502A. Arranged on the third stage. This can be regarded as a configuration in which six 2-input selectors 502V_4 to 502V_9 are arranged on the input side of the 6-input selector 502Ea of the first example of the present embodiment.

  The control signal E and the control signal XE having a complementary relationship are commonly supplied to the first-stage 2-input selectors 502V_4 to 502V_9. One of input 1 and input 2 is selected by 2-input selector 502V_4, one of input 3 and input 4 is selected by 2-input selector 502V_5, and one of input 5 and input 6 is selected by 2-input selector 502V_6 Is selected. One of input 7 and input 8 is selected by 2-input selector 502V_7, one of input 9 and input 10 is selected by 2-input selector 502V_8, and one of input 11 and input 12 is selected by 2-input selector 502V_9. Is selected.

  These six selection results in the first stage are further input to the 6-input selector 502Ea of the first example of the present embodiment, so that only one of the inputs 1 to 12 is selected. Only one of the three control signals XA, XB, and XC is set to the potential low and the other two are set to the potential high, and only one of the control signals D and XD is set to the potential high and the other is set to the other. , And only one of the inputs 1 to 12 is selected by setting only one of the control signals E and XE to the potential high and the other to the potential low, and the signal output terminal 500OUT Is output.

<Comparison of 12-input selector>
FIG. 10A is a diagram illustrating a comparison between the 12-input selector 502G of this embodiment and the comparative example. The operational effects of the 12-input selector 502G are collectively shown in comparison with the comparative example.

  Although illustration is omitted, each comparative example has the following configuration. The 12-input selector of the first comparative example is based on the idea shown in FIG. 1C (1), similar to the 3-input selector 502W of the first comparative example, and each of the 12 complementary switches 408 has 12 sets of complementary control. It is the structure controlled by a signal. The 12-input selector of the first comparative example has 24 (= 2 × 12) control wires and 24 (= 2 × 12) transistors.

  The 12-input selector of the second comparative example is based on the idea shown in FIG. 1C (2), similar to the 3-input selector 502X of the second comparative example, and is based on the 12-input selector of the first comparative example. A CMOS inverter is added, and each CMOS inverter generates the other complementary control signal separately based on one of the complementary control signals. In the 12-input selector of the second comparative example, the number of control wirings is reduced to 12 which is half that of the 12-input selector of the first comparative example, but the number of transistors is 12 CMOS inverters (TR number = 2). Therefore, the number of transistors increases by 24 to 48, which increases the number of transistors.

  The 12-input selector of the third comparative example is based on the same idea as the 3-input selector 502X of the third comparative example, and is composed of, for example, a combination of an 8-input selector and a 2-input selector 502V configured by a combination of 2-input selectors 502V. Each output of the selected 4-input selector is further selected by the 2-input selector 502V. As an example, four 2-input selectors 502V for the 8-input selector are in the first stage, two 2-input selectors 502V for the 8-input selector and each for the 4-input selector are in the second stage, and for the 8-input selector. One 2-input selector 502V is arranged in the third stage for the 4-input selector, and one 2-input selector 502V is arranged in the fourth stage. Since the 12-input selector of the third comparative example has a 4-stage configuration, 4 sets of complementary control signals are used, the number of control wirings is 8 (= 2 × 4), and 11 2-input selectors 502V (the number of TRs) = 4) is used, the number of transistors is 44. In addition, there are four stages of pMOS between the input and output.

  The 12-input selector of the fourth comparative example has the same idea as the 3-input selector 502Z of the fourth comparative example. Based on the 12-input selector of the third comparative example, four CMOS inverters are added to each CMOS. The inverter generates the other of the complementary control signals separately based on one of the complementary control signals. The 12-input selector of the fourth comparative example reduces the number of control wirings to four, which is half of the 12-input selector of the third comparative example, but adds four CMOS inverters (TR number = 2). As a result, the number of transistors increases by eight to 52.

  In the 12-input selector 502G of the present embodiment, six 2-input selectors 502V (CN number = 2, TR number = 4) in the first stage and three 2-input selectors 502V (CN number = 2) in the second stage. (TR number = 4) and one 3-input selector 502A (CN number = 3, TR number = 9) in the third stage, the number of control wires is seven, and the number of transistors is 45 ( = 4 × 6 + 4 × 3 + 9), and the number of series pMOS is three. It can be seen that the 12-input selector 502G can reduce the number of control wirings, the number of transistors, and the number of series pMOSs in a balanced manner. There is no need to precharge. The 12-input selector 502G of this embodiment is a new option in the 12-input selector, although there are difficulties that the change in output is slow because the number of series pMOS is three.

<< Selector using prime factorization with correction >>
In configuring the signal selection circuit 500, when the input number M is a prime number, an appropriate numerical value α is added and a prime number M_k (k is a positive number of 1 or more, such as “M + α = M_1 × M_2 × M_3 ×...”). The M_k input-1 output type sub-selector can be hierarchized (in a multistage configuration). The basic configuration of the selector using prime factorization is the same except that an appropriate numerical value α is added to M. A specific configuration will be shown and described below.

<5-input selector: basic>
FIG. 11 is a circuit block diagram of a 5-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 5-input selector 502H), which is an eighth specific example of the signal selection circuit 500 of the present embodiment.

  By adding α = 1 to the 6-input type, the mechanism of the 6-input selector 502E is used. Any of the three-input selectors 502A to 502C of the present embodiment is used for the portion “3”. Then, α = 1 is unused.

  In the 5-input selector 502Ha of the first example shown in FIG. 11A, the first-stage 2-input selector 502V_3 is removed and the second-stage 3-input selector 502A is based on the first-input 6-input selector 502Ea. Input 5 is directly input to the third input terminal. In this example, the two-input selector 502V_3 is not used for α = 1.

  In the 5-input selector 502Hb of the second example shown in FIG. 11 (2), one 3-input selector 502A_2 at the first stage is replaced with a 2-input selector 502V_2 based on the 6-input selector 502Eb of the second example. In this example, the three-input selector 502A_2 is unused for α = 1.

  Since both use two 2-input selectors 502V and one 3-input selector 502A, the number of transistors is the same, but in the second example, control signals E and XE for the 2-input selector 502V are used in the first stage. Each control wiring for the control signals XA, XB, and XC for the 3-input selector 502A is required, and the number of control wirings is increased. The first example in which only the same type of input selector is arranged in each stage is advantageous because the number of control wirings is small.

  In the second example, it can be considered that only one input selector of the same type is arranged in each stage by making unused one input terminal of one three-input selector 502A_2 in the first stage. However, in this case, as in the case of the 6-input selector 502Eb, since two 3-input selectors 502A are used in the first stage, the number of transistors is increased, and the first example is advantageous because the number of transistors is smaller.

<Comparison of 5-input selectors>
FIG. 11A is a diagram illustrating a comparison between the 5-input selector 502Ha of the first example of this embodiment and the comparative example. The effects of the 5-input selector 502Ha are collectively shown in comparison with the comparative example.

  Although illustration is omitted, each comparative example has the following configuration. The 5-input selector of the first comparative example is based on the idea shown in FIG. 1C (1), like the 3-input selector 502W of the first comparative example, and each of the five complementary switches 408 has five sets of complementary control. It is the structure controlled by a signal. In the 5-input selector of the first comparative example, the number of control wirings is 10 (= 2 × 5), and the number of transistors is 10 (= 2 × 5).

  The 5-input selector of the second comparative example is based on the idea shown in FIG. 1C (2), similar to the 3-input selector 502X of the second comparative example, and is based on the 5-input selector of the first comparative example. A CMOS inverter is added, and each CMOS inverter generates the other complementary control signal separately based on one of the complementary control signals. The five-input selector of the second comparative example is reduced to half the number of control wires with respect to the five-input selector of the first comparative example, but the number of transistors is five CMOS inverters (TR number = 2). For this reason, the number of transistors increases by 10 to 20 and the number of transistors increases.

  The 5-input selector of the third comparative example has the same concept as the 3-input selector 502X of the third comparative example. For example, one 4-input selector and a 2-input selector 502V each configured by a combination of 2-input selectors 502V are provided. The output of the 4-input selector and the input 5 are further selected by the 2-input selector 502V. Since a 2-input selector 502V is added to a 2-stage 4-input selector, a 3-stage configuration is used, 3 sets of complementary control signals are used, and the number of control wirings is 6 (= 2 × 3). 4 2-input selectors Since 502V (TR number = 4) is used, the number of transistors is 16. In addition, there are three stages of pMOS between the input and output.

  The 5-input selector of the fourth comparative example has the same idea as the 3-input selector 502Z of the fourth comparative example. Based on the 5-input selector of the third comparative example, three CMOS inverters are added to each CMOS. The inverter generates the other of the complementary control signals separately based on one of the complementary control signals. The five-input selector of the fourth comparative example reduces the number of control wirings to three, which is half of the five-input selector of the third comparative example, but adds three CMOS inverters (TR number = 2). As a result, the number of transistors increases by 6 to 22 transistors.

  The 5-input selector 502Ha of the first example of the present embodiment includes two 2-input selectors 502V (CN number = 2, TR number = 4) in the first stage and one 3-input selector 502A (CN in the second stage). The number of control wirings is 5, the number of transistors is 17 (= 4 × 2 + 9), and the number of serial pMOSs is 2. It can be seen that the 5-input selector 502Ha can reduce the number of control wires, the number of transistors, and the number of series pMOSs in a balanced manner. There is no need to precharge. The 5-input selector 502Ha of the present embodiment is a new option in the 5-input selector, although there is a difficulty that the output change is slow because the number of serial pMOS is two.

<4-input selector: basic>
FIG. 12 is a circuit block diagram of a 4-input / 1-output type signal selection circuit 500 (hereinafter referred to as a 4-input selector 502I), which is a ninth specific example of the signal selection circuit 500 of this embodiment.

  The mechanism of the 6-input selector 502E is used by adding α = 2 to the 6-input type. Any of the three-input selectors 502A to 502C of the present embodiment is used for the portion “3”. Then, α = 2 is made unused.

  In the 4-input selector 502Ia of the second example shown in FIG. 12A, the first-stage 2-input selectors 502V_2 and 502V_3 are removed based on the first-input 6-input selector 502Ea. For the input selector 502A, the output of the first-stage 2-input selector 502V_1 is directly input to the first input terminal, the input 3 is directly input to the second input terminal, and the input 4 is directly input to the third input terminal. In this example, two two-input selectors 502V_2 and 502V_3 are unused for α = 2.

  In the 4-input selector 502Ib of the third example shown in FIG. 12 (2), the one-stage 3-input selector 502A_2 at the first stage is removed based on the 6-input selector 502Eb of the second example. For the second-stage 2-input selector 502V, the output of the first-stage 3-input selector 502A_1 is directly input to the first input terminal, and the input 4 is directly input to the second input terminal.

  Since both use one 2-input selector 502V and one 3-input selector 502A, the number of control wirings, the number of transistors, and the number of series pMOSs are the same.

<Comparison of 4-input selector>
FIG. 12A is a diagram for explaining a comparison between the 4-input selector 502I (502Ia, 502Ib) of the second and third examples and the comparative example. The operational effects of the 4-input selector 502I are collectively shown in comparison with the 4-input selector 502D of the comparative example and the first example. Each comparative example is the same as that described in the above-described 4-input selector 502D.

  In the 4-input selector 502I of the second and third examples, one 2-input selector 502V (CN number = 2, TR number = 4) and one 3-input selector 502A (CN number = 3, TR number = 9). ), The number of control wirings is 5, the number of transistors is 13, and the number of series pMOSs is 2.

  The four-input selector 502I of the second and third examples has one more control wiring and one series pMOS than the four-input selector 502D of the first example, but can reduce three transistors. In terms of the number of control wirings, the number of transistors, and the number of series pMOSs, there is no element superior to the third comparative example, but there are elements superior to the other comparative examples. For example, the number of control wirings can be reduced in comparison with the first comparative example, and the number of transistors can be reduced in comparison with the second and fourth comparative examples.

  As can be inferred from the description of the various M-input / one-output type signal selection circuit 500, in the case of four or more inputs, the three-input / one-output type signal selection circuit 500 of the present embodiment and two Preferably, complementary switches 408 are connected in parallel, and a combination of two-input selectors 502V each controlled by a complementary control signal. In particular, in terms of the total balance of the number of control wirings, the number of transistors, and the number of series pMOSs, the configuration in which the 3-input / 1-output type signal selection circuit 500 (particularly, the 3-input selector 502A) of this embodiment is arranged at the lowest stage. A configuration with 5 inputs or more that is effective is effective. In the configuration in which the three-input selector 502A is arranged at the lowermost stage, the number of transistors, the number of control wirings, and the number of series pMOSs can be reduced in a balanced manner in a semiconductor device in which selector circuits are arranged one-dimensionally or two-dimensionally. Become.

  Next, a preferred application example of the semiconductor device 400 that can be used as the M input-1 output type signal selection circuit and the M input-1 output type signal selection circuit 500 of this embodiment will be described.

<Solid-state imaging device: basic configuration>
FIG. 13 is a basic configuration diagram of a CMOS type solid-state imaging device (CMOS image sensor) which is an embodiment of the solid-state imaging device according to the present invention. A solid-state imaging device is also an example of a semiconductor device.

  In the following, a case where a CMOS type solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. Unless otherwise specified, the CMOS type solid-state imaging device will be described on the assumption that all unit pixels are composed of nMOSs (n-channel type MOS transistors) and the signal charges are negative charges (electrons). However, this is merely an example, and the target device is not limited to a MOS type solid-state imaging device. The unit pixel may be composed of a pMOS (p-channel type MOS transistor), and the signal charge is a positive charge ( Hole).

  For all semiconductor devices for physical quantity distribution detection that read out signals by address control by arranging a plurality of unit pixels that are sensitive to electromagnetic waves input from outside such as light and radiation in a line or matrix form The embodiments to be described later can be similarly applied.

  The solid-state imaging device 1 includes a pixel array unit 10 in which a plurality of unit pixels 3 are arranged in a two-dimensional matrix. The solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter in which, for example, R, G, and B color filters are arranged in a Bayer array.

  In FIG. 13, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. As will be described later, the unit pixel 3 includes, for example, three or four transistors for charge transfer, reset, and amplification in addition to a photodiode as a light receiving element (charge generation unit) which is an example of a detection unit. It has an in-pixel amplifier. A pixel signal voltage Vx is output from the unit pixel 3 via the vertical signal line 19 for each column. The pixel signal voltage Vx includes a reset level Srst (P phase component) and a signal level Ssig (D phase component).

  The solid-state imaging device 1 further includes a column AD conversion unit 26 in which an AD conversion unit 250 having a CDS (Correlated Double Sampling) processing function and a digital conversion function is provided in parallel. “Column parallel” means that a plurality of CDS processing function units and digital conversion units (AD conversion units) are provided substantially in parallel with vertical signal lines 19 (an example of column signal lines) in a vertical column. Means that. Such a reading method is called a column reading method.

  The solid-state imaging device 1 further includes a drive control unit 7, a read current source unit 24 that supplies an operation current (read current) for reading pixel signals to the unit pixel 3, and a reference signal SLP_ADC for AD conversion to the column AD conversion unit 26. Is provided with a reference signal generation unit 27, an output unit 28, and a data selector unit 300.

  The drive control unit 7 includes a horizontal scanning unit 12 (column scanning circuit), a vertical scanning unit 14 (row scanning circuit), and a communication / timing control unit for realizing a control circuit function for sequentially reading signals from the pixel array unit 10. 20 is provided. The horizontal scanning unit 12 instructs the column position of data to be read out during the data transfer operation in the data selector unit 300.

  The horizontal scanning unit 12 includes a horizontal address setting unit 12a and a horizontal driving unit 12b that control column addresses and column scanning. The vertical scanning unit 14 includes a vertical address setting unit 14a and a vertical driving unit 14b that control row addresses and row scanning. The horizontal scanning unit 12 and the vertical scanning unit 14 start the row / column selection operation (scanning) in response to the control signals CN1 and CN2 given from the communication / timing control unit 20.

  The data selector unit 300 selects the horizontal position (column position) of the column AD conversion unit 26 based on the control signal CN9 from the communication / timing control unit 20 and the instruction from the horizontal scanning unit 12, and the selected column position Is transferred to the output unit 28 side. As will be described in detail later, the data selector unit 300 is responsible for the latches 257 for three or more columns and selects one of the data of each latch 257, and a horizontal signal based on the data selected by the subselector 302 There are a plurality of pairs of horizontal transfer drivers 308 that drive the lines 18. The sub-selector 302 performs a data selection operation based on a selection control signal from the communication / timing control unit 20, and the horizontal transfer driver 308 performs a transfer operation based on a selection control signal from the horizontal scanning unit 12.

  The communication / timing control unit 20 is a timing generator (reading address control) that supplies a clock synchronized with the master clock CLK0 input via the terminal 5a to each unit (scanning units 12, 14 and column AD conversion unit 26) in the device. A functional block of an example of the apparatus. Further, the master clock CLK0 supplied from the external main control unit is received via the terminal 5a, and the data for instructing the operation mode supplied from the external main control unit is received via the terminal 5b. A function block of a communication interface that outputs data including information of the device 1 to an external main control unit is provided.

  For example, the communication / timing control unit 20 includes a clock conversion unit 20a having a function of a clock conversion unit that generates an internal clock, and a system control unit 20b having a communication function and a function of controlling each unit. The clock conversion unit 20a has a built-in multiplier circuit that generates a pulse having a higher frequency than the master clock CLK0 based on the master clock CLK0 input via the terminal 5a. The clock conversion unit 20a includes an internal count clock CKcnt1 and count clock CKdac1. Generate a clock.

  The output unit 28 includes a sense amplifier 28a (S · A) that detects a signal (digital data but small amplitude) on the horizontal signal line 18 that is a signal line (transfer wiring) for data transfer, and the solid-state imaging device 1. And an interface unit 28b (IF unit) that functions as an interface with the outside. The output of the interface unit 28b is connected to the output terminal 5c, and the video data is output to the subsequent circuit. The output unit 28 may also be provided with a digital arithmetic unit that performs various digital arithmetic processes between the sense amplifier 28a and the interface unit 28b.

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, and an AD conversion unit 250 provided for each vertical column of the column AD conversion unit 26 via a vertical signal line 19. , Each connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. The vertical address setting unit 14a selects not only a row from which a signal is read (reading row: also referred to as a selected row or a signal output row) but also a row for an electronic shutter.

  Various methods are considered as an AD conversion method in the AD conversion unit 250 from the viewpoint of circuit scale, processing speed (high speed), resolution, and the like. As an example, a reference signal comparison type, a slope integration type, or a ramp An AD conversion method called a signal comparison type is adopted. In the reference signal comparison type AD conversion, the count operation valid period is determined based on the time from the conversion start (comparison process start) to the conversion end (comparison process end), and the count enable signal EN indicating the period is used. Based on this, the analog processing target signal is converted into digital data.

  For this reason, the reference signal generation unit 27 includes a DA conversion unit 270 (DAC; Digital Analog Converter), and synchronizes with the count clock CKdac1 from the initial value indicated by the control data CN4 from the communication / timing control unit 20, A reference signal SLP_ADC having a slope (change rate) indicated by the control data CN4 is generated. The count clock CKdac1 may be the same as the count clock CKcnt1 for the counter unit 254.

  The AD conversion unit 250 includes a comparison unit 252 (COMP) and a counter unit 254 that can switch between an up-count mode and a down-count mode. In this example, a data storage unit 256 incorporating a horizontal transfer latch 257 (data holding circuit, memory) is further provided downstream of the counter unit 254. The comparison unit 252 generates the reference signal SLP_ADC generated by the reference signal generation unit 27 and the analog pixel signal voltage Vx obtained from the unit pixel 3 in the selected row via the vertical signal lines 19 (H1, H2,..., Hh). Compare The counter unit 254 counts the active period of the count enable signal EN having a fixed relationship with the comparison output Co of the comparison unit 252 using the count clock CKcnt1, and holds the count result.

  From the communication / timing control unit 20 to the counter unit 254 of each AD conversion unit 250, whether the counter unit 254 operates in the down-count mode or the up-count mode for the P-phase / D-phase counting process, A control signal CN5 for instructing other control information such as setting of the initial value Dini and reset processing in the counting process is input.

  One input terminal (+) of the comparison unit 252 receives the reference signal SLP_ADC generated by the reference signal generation unit 27 in common with the input terminal (+) of the other comparison unit 252 and the other input terminal (− ) Are connected to the vertical signal lines 19 in the corresponding vertical columns, and the pixel signal voltages Vx from the pixel array unit 10 are individually input thereto.

  The count clock CKcnt1 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254. When the data storage unit 256 is not provided, a control pulse is input to the counter unit 254 from the horizontal scanning unit 12 via the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  In this embodiment, the ADS 250 completes the CDS process. However, the P-phase data at the reset level Srst and the D-phase data at the signal level Ssig are individually transferred to the output unit 28, and the AD converter 250. The CDS process may be performed by a subsequent digital calculation unit. The present applicant has proposed various reference signal comparison type AD conversion methods in which the AD conversion unit 250 performs AD conversion and CDS processing, and these can basically be adopted in each embodiment.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. The solid-state imaging device 1 of the present embodiment is configured as a so-called one-chip product (provided on the same semiconductor substrate).

  As described above, the solid-state imaging device 1 may be formed as a single chip in which each unit is integrally formed in the semiconductor region. Although not illustrated, the pixel array unit 10, the drive control unit 7, In addition to various signal processing units such as the column AD conversion unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as the modular form which has.

  For example, the output side of each AD conversion unit 250 can connect the output of the counter unit 254 to the horizontal signal line 18 via the data selector unit 300. Alternatively, as shown in the figure, it is possible to adopt a configuration in which a data storage unit 256 as a memory device including a latch that holds the count result held by the counter unit 254 is provided at the subsequent stage of the counter unit 254. In the present embodiment, a data selector unit 300 is further provided after the data storage unit 256, and the data storage unit 256 and the data selector unit 300 constitute a horizontal transfer system Htrans. The data storage unit 256 holds and stores the count data output from the counter unit 254 at a predetermined timing.

  The horizontal scanning unit 12 reads the count value held by each data storage unit 256 in parallel with each comparison unit 252 and counter unit 254 of the column AD conversion unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit. The output of the data storage unit 256 is connected to the horizontal signal line 18 via the data selector unit 300. The horizontal signal line 18 has a signal line corresponding to the bit width of the AD conversion unit 250 or a double width thereof (for example, complementary output), and an output unit 28 having a sense amplifier 28a corresponding to each output line. Connected to. The number of horizontal transfer channels of the horizontal signal line 18 is not limited to one, and data transfer may be performed by grouping a plurality of channels into a plurality of columns. Note that each of the counter unit 254, the data storage unit 256, the data selector unit 300, and the horizontal signal line 18 has a configuration corresponding to n bits.

<Problems of horizontal data transfer>
Here, when the data held in the latches 257 of each column is sequentially transferred to the output unit 28 side via the horizontal signal line 18 which is a bus line, the parasitic capacitance is added to the horizontal signal line 18 connected to the output unit 28. Because of the presence of parasitic capacitance, there are various factors due to the presence of parasitic capacitance, such as transfer speed degradation and the increase in chip size that requires increasing the wiring width (Metal width) used for the horizontal signal line 18 in order to suppress parasitic capacitance. Problems arise.

For example, the value of parasitic capacitance is
(1) Capacity due to the horizontal signal line 18,
(2) Capacity due to the input stage of the output unit 28,
(3) Capacitance due to output stage of latch 257 × total number of latches 257,
(4) capacitance of wiring connecting the horizontal signal line 18 and the output stage of one latch 257 × total number of latches 257,
It is the total value.

  Accordingly, when the data held in the latches 257 in each column is sequentially selected and read out to the horizontal signal line 18 by the latches 257, data transfer is hindered due to the parasitic capacitance of the horizontal signal line 18. In particular, if the capacitance value of the parasitic capacitance is increased, it causes signal delay and hinders speeding up of data transfer.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up the horizontal data transfer, the horizontal signal line 18 is driven based on the output data of the latch 257 selected by the horizontal scanning unit 12 and the time until the signal reaches the output unit 28 is reached. Become dominant.

  In the case of the pixel array section 10 having the horizontal pixels, for example, 2000 columns of unit pixels 3, 2000 latches 257 are connected to the horizontal signal line 18, and the parasitic capacitance of each output stage of the latch 257 Are combined, and the selected latch 257 is driven with its large capacity as a load. In recent years, since there is a demand for increasing the number of pixels, the number of latches 257 connected to the horizontal signal line 18 tends to increase, and in recent years, there is a restriction on high speed operation that is particularly required.

  Even when horizontal transfer is performed by complementary (differential) signal line pairs for speeding up, if the number of horizontal transfer drivers 308 connected to the horizontal signal line 18 increases, the parasitic capacitance of the horizontal signal line 18 increases and the current flows. Even if the transfer is performed, the transfer takes time.

  As a method for solving such a problem, a method of widening the wiring width used for the horizontal signal line 18 in order to suppress the parasitic capacitance is conceivable, but bit-specific data is transferred by the horizontal signal line 18 as a bus line. In some cases, the chip size becomes large.

  As another method for solving such a problem, a method of processing in parallel for each number of columns as in JP-A-2000-32344 can be considered. However, the mechanism is an application example in the case where analog information is output to the outside of the solid-state imaging device 1, and the mechanism is particularly applied to a mechanism for digitally converting a pixel signal and outputting the digital signal to the outside of the solid-state imaging device 1. If it is attempted to be applied, the number of output terminals increases, and there is a problem that multiplexing processing of the output part is necessary.

  Therefore, in the present embodiment, in the mechanism in which the pixel signal is digitally converted and output to the outside of the solid-state imaging device 1, the column processing unit 26 and the horizontal scanning unit 12 are caused to have a problem caused by the parasitic capacitance of the horizontal signal line 18. Make it a mechanism that can be improved.

  The basic mechanism is that when the reference signal comparison type column ADC system in which the horizontal transfer latch 257 of the counter unit 254 and the data storage unit 256 is separated is adopted, the horizontal transfer driver is set to M (M is a positive value of 3 or more). The M input-1 output type selector is used to determine which latch is connected to the input of the horizontal transfer driver. By doing so, the horizontal transfer system Htrans is hierarchized to improve efficiency. The adjacent M column has the same structure, but is connected to different horizontal transfer channels. Therefore, when the number of horizontal transfer channels is J, the circuit configuration has a J × M column period.

  One selector is arranged for M columns and one horizontal transfer driver is provided for each selector. However, the number of columns corresponding to one selector is arbitrary as long as it is three or more. In the present embodiment, the above-described signal selection circuit 500 (particularly one having a 3-input / 1-output type) is used for this selector.

<Horizontal data transfer system; basic>
14 to 14B are diagrams illustrating a horizontal data transfer system of the solid-state imaging device 1 according to the present embodiment. Here, FIG. 14 is a diagram showing a basic configuration of a horizontal data transfer system of the solid-state imaging device 1. 14A and 14B are diagrams showing comparative examples for the horizontal data transfer system of the present embodiment shown in FIG. 14 and 14A show the case where there are four horizontal transfer channels, and FIG. 14B shows the case where there is one horizontal transfer channel.

  In the solid-state imaging device 1 of the present embodiment, as a mechanism for reducing the parasitic capacitance of the horizontal signal line 18, the data in each data storage unit 256 is directly output to the horizontal signal line 18 via the output driver for each column. Instead, a configuration is employed in which the output is made to the horizontal signal line 18 via a smaller number of output drivers than the total number of columns in the data storage unit 256.

  Various mechanisms are conceivable for this purpose. In this embodiment, the data selector method is used to output data to the horizontal signal line 18. The data storage unit 256 has a number of latches 257 that hold data for each column (vertical signal line 19). The data selector unit 300 includes a selector unit 301 having a plurality of sub-selectors 302 and a driver unit 307 having a plurality of horizontal transfer drivers 308 (horizontal transfer DR). The sub-selector 302 is an example of a signal selection unit that selects one of the data of the latches 257 in a plurality of columns. The horizontal transfer driver 308 is an example of a transfer driver that drives the horizontal signal line 18 based on the data selected by the sub-selector 302.

  All columns of the data storage unit 256 are divided into a plurality of blocks each including M columns (M is a positive integer of 3 or more), and one horizontal transfer driver 308 is provided for each block. For each block, an M input-1 output type sub-selector 302 is provided between the horizontal transfer driver 308 and each of the M columns of latches 257. The output of the horizontal transfer driver 308 is connected to the output unit 28 (not shown) via the horizontal signal line 18 that is a bus line. The mode shown in FIG. 14 shows a case where the horizontal transfer channels are four channels, and also shows a case where data transfer is performed in a complementary data format, and the above-described configuration is adopted for each channel.

  The horizontal transfer system is hierarchized using the sub-selector 302, the parent hierarchy is selected by a selection transistor (details will be described later) in the horizontal transfer driver 308 controlled by the horizontal scanning unit 12, and the child hierarchy is not shown. Selection is made by the sub-selector 302 controlled by the communication / timing control unit 20.

  In the present embodiment, an example in which M = 6 is shown, and six latches 257 (latch groups) are commonly input to one 6-input type sub-selector 302 (referred to as a 6-input sub-selector 302A). The output of the input sub-selector 302A controls the horizontal transfer driver 308, which drives the horizontal transfer channel. The horizontal scanning unit 12 selects a specific latch group by turning on a selection transistor in a specific horizontal transfer driver 308. One horizontal transfer system Htrans0 includes six latches 257, one 6-input sub-selector 302A, and one horizontal transfer driver 308.

  Each 6-input sub-selector 302A is controlled by a common control wiring from the communication / timing control unit 20. That is, the communication / timing control unit 20 has a function of a selection control unit that controls each sub-selector 302 (here, 6-input sub-selector 302A) of the selector unit 301 to select data. Even when a large number of sub-selectors 302 (6-input sub-selectors 302A) are used, it can be said that there is no significant increase in the number of control wirings from the communication / timing control unit 20.

  There are four horizontal transfer channels, each of which has a horizontal transfer system Htrans0, and the four horizontal transfer systems Htrans0 constitute one horizontal transfer system Htrans1. Four adjacent horizontal transfer drivers 308 drive the horizontal signal lines 18_0 to 18_3 of different horizontal transfer channels. The contents of the horizontal transfer channel (horizontal signal lines 18_0 to 18_3) are read by the sense amplifier 28a of the output unit 28 (not shown), and are read out of the chip after digital processing as necessary.

  As described above, the horizontal transfer system Htrans of the present embodiment includes the data storage unit 256 including the counter unit 254 and the horizontal transfer latch 257, and the horizontal transfer driver 308 of the data selector unit 300 is connected to the M column (this In the example, a horizontal transfer system Htrans0_k shared by 6 columns) is used, and a 6-input sub-selector 302A that determines which latch 257 is connected to the input of the horizontal transfer driver 308 is used. By sharing the horizontal transfer driver 308 in several columns, the horizontal transfer system Htrans can be hierarchized, and the efficiency of horizontal transfer can be improved. The adjacent six-column horizontal transfer system Htrans0_k has the same structure, but is connected to different horizontal transfer channels (four in this example). Therefore, in the case of the 4-channel configuration, the circuit configuration has a 24-column cycle.

  That is, horizontal signal lines 18 for four channels are provided, and each sub-selector 302 (six-input sub-selector 302A) of the selector unit 301 and each horizontal transfer driver 308 of the driver unit 307 have four channel horizontal signal lines 18_1˜. 18_4 is evenly distributed. This is for the purpose of balancing the usage states of the horizontal transfer drivers 308 and the horizontal signal lines 18_1 to 18_4 regardless of the thinning operation. This relationship is also maintained for all the vertical columns of the pixel array unit 10 (see FIG. 15A).

  The same applies when the number of inputs of the sub-selector 302 is other than 6 or when the number of channels is other than 4. When the horizontal signal lines 18 for J channels are provided, each sub-selector 302 and driver unit of the selector unit 301 are provided. The horizontal transfer drivers 308 of 307 are evenly distributed to the horizontal signal lines 18 of the J channel, and this relationship is also maintained for all the vertical columns of the pixel array unit 10.

  On the other hand, in the comparative example shown in FIGS. 14A and 14B, the output data of each latch 257 is transmitted to the horizontal signal line 18 by the individual horizontal transfer driver 308Z. As shown in FIG. 14B, the horizontal transfer driver 308Z includes a pair (two) of transfer transistors 332 and 334 and a pair (two) of selection transistors 336 and 338. Each of the transistors 332, 334, 336, 338 is an nMOS. One horizontal transfer driver 308 uses four transistors. The output data of the latch 257 is input to the gate of the transfer transistor 334, and the output data of the inverter 296 of the latch 257 is input to the gate of the transfer transistor 332.

  In the relationship between the horizontal transfer driver 308 and the horizontal signal line 18 which is a bus line connected to the output side thereof, the horizontal transfer system Htrans of this embodiment has M columns (6 in this embodiment). ) Are grouped in groups. The number of horizontal transfer drivers 308 connected to the horizontal signal line 18 can be reduced to 1 / M compared to the case where the horizontal transfer driver 308 is provided for each column as in the comparative example shown in FIGS. 14A and 14B. As a result, the parasitic capacitance of the horizontal transfer channel that the horizontal transfer driver 308 must drive can be reduced, and as a result, high-speed operation is realized.

  Further, the horizontal transfer driver 308 is not connected in multiple stages, no additional transistor is required on the current path that flows when the horizontal transfer driver 308 drives, and the series resistance does not increase. Regardless of the configuration of the sub-selector 302, the number of horizontal transfer drivers 308 may be one, and the series resistance when driving the horizontal signal line 18 does not increase. As a result, it is possible to reliably transfer data at a higher speed than before.

  In consideration of the number of transistors and the number of control wirings, there is almost no difference when sharing one horizontal transfer driver 308 with two columns, and sharing one horizontal transfer driver 308 with three or more columns has an effect. .

<Horizontal data transfer system: details>
15 to 15B are diagrams for explaining a detailed configuration example of the horizontal transfer system of the present embodiment shown in FIG. Here, FIG. 15 shows one block (portion handled by one 6-input sub-selector 302A), and FIG. 15A shows four horizontal transfer channels in a simplified manner. FIG. 15B is a diagram illustrating a configuration example of a clocked inverter used for the latch 257.

  As shown in FIG. 15, the latch 257 includes two clocked inverters 292 and 294 and one ordinary inverter 296. “Normal” is a CMOS inverter in which a pMOS and an nMOS are cascade-connected like the inverter 409 described above. In the clocked inverters 292 and 294, for example, as shown in FIGS. 15B (1) and (2), the two pMOSs 290_p1 and 290_p2 are on the positive power supply Vdd side, and the two nMOSs 290_n1 and 290_n2 are on the negative power supply Vss or ground GND side. Are connected in cascade, and four transistors are used. Therefore, one latch 257 uses ten transistors when the inverter 296 is included.

  In the clocked inverter, the connection point of each drain of the intermediate pMOS 290_p2 and nMOS 290_n1 is used as the data output terminal OUT. Here, as a usage of the clocked inverter, as shown in FIG. 15B (1), the gates of the intermediate pMOS 290_p2 and nMOS 290_n1 are connected in common to be the data input terminal IN, and the gate of the pMOS 290_p1 on the positive power supply side is inverted There is a first example in which the terminal XCK, the gate of the ground or negative power supply side nMOS 290_n2 is the non-inverted clock terminal CK. When the H level is input to the inverted clock terminal XCK and the L level is input to the non-inverted clock terminal CK, the pMOS 290_p1 and the nMOS 290_n2 are turned off (shut off), and the data output terminal OUT becomes a high impedance so that data passing is shut off. On the other hand, when the L level is input to the inverted clock terminal XCK and the H level is input to the non-inverted clock terminal CK, the pMOS 290_p1 and the nMOS 290_n2 are turned on (conducted), so that the data input to the data input terminal IN is inverted by the pMOS 290_p2 And output from the data output terminal OUT.

  Further, as shown in FIG. 15B (2), the gates of the pMOS 290_p1 and nMOS 290_n2 on both sides are connected in common to be the data input IN, the gate of the pMOS 290_p2 is the inverted clock terminal XCK, and the gate of the nMOS 290_n1 is the non-inverted clock terminal CK. There is a second example. When the H level is input to the inverted clock terminal XCK and the L level is input to the non-inverted clock terminal CK, the pMOS 290_p2 and the nMOS 290_n1 are turned off (shut off), and the data output terminal OUT becomes a high impedance so that data passing is shut off. On the other hand, when the L level is input to the inverted clock terminal XCK and the H level is input to the non-inverted clock terminal CK, the pMOS 290_p2 and the nMOS 290_n1 are turned on (conducted). And output from the data output terminal OUT.

  The outputs of the clocked inverters 292 and 294 are connected in common and become the input of the inverter 296 and also the input of the 6-input sub-selector 302A. Data DATA <K> of the counter unit 254 is input to the clocked inverter 292, and output data of the inverter 296 is input to the clocked inverter 294.

  The load signal CRDL included in the control signal CN9 from the communication / timing control unit 20 is input to the non-inverted clock terminal CK of the clocked inverter 292 and the inverted clock terminal XCK of the clocked inverter 294. The load signal XCRDL included in the control signal CN9 from the communication / timing control unit 20 is input to the inverted clock terminal XCK of the clocked inverter 292 and the non-inverted clock terminal CK of the clocked inverter 294. The load signal CRDL and the load signal XCRDL have a logic inversion (complementary relationship) relationship.

  In this configuration, each data DATA <K> of the counter unit 254 is logically inverted (complementary) by the clocked inverter 292 of the latch 257 so that the data XDATA <K> is supplied to the 6-input sub-selector 302A. Become.

  As the 6-input sub-selector 302A, the configuration of the 6-input selector 502Ea in which the two 2-input selectors 502V_1, 502V_2, and 502V_3 as described above and one 3-input selector 502A are combined is used. Output data is input from the corresponding latch 257 to each input of the two-stage selectors 502V_1, 502V_2, and 502V_3 in the first stage.

  The sub-select signals SUBSEL_D and XSUBSEL_D having a complementary relationship are commonly supplied to the first input selectors 502V_1, 502V_2, and 502V_3. The control signal of the second stage 3-input selector 502A is as follows. The sub-select signal XSUBSEL_A is supplied to the gates of the first transistor 401 and the second transistor 403 in the first stage in common for all sets. The subselect signal XSUBSEL_B is supplied in common to the gates of the first transistor 401 and the second transistor 403 in the second stage. A subselect signal XSUBSEL_C is supplied to the gates of the first transistor 401 and the second transistor 403 in the third stage in common for all sets.

  Only one of the three subselect signals XSUBSEL_A, XSUBSEL_B, and XSUBSEL_C is set to potential low, the other two are set to potential high, and only one of the pair of subselect signals SUBSEL_D and XSUBSEL_D is set to potential high. When the other is set to a low potential, only one output data of the six latches 257 is selected and input to the horizontal transfer driver 308. The output of the 6-input sub-selector 302A is not complementary (differential) but single-ended.

  The horizontal transfer driver 308 has a configuration in which one inverter 331 is added to the horizontal transfer driver 308Z shown in FIG. 14A. The inverter 331 is a CMOS inverter in which a pMOS and an nMOS are cascaded like the inverter 409 described above. Therefore, one horizontal transfer driver 308 uses six transistors.

  The input terminal of the inverter 331 and the gate of the transfer transistor 334 are connected in common, and output data from the six nMOSs 322 and pMOS 324 constituting the six-input sub-selector 302A is input. The output data of the inverter 331 is input to the gate of the transfer transistor 332.

  Each source of the transfer transistors 332 and 334 is grounded. The drain of the transfer transistor 332 is connected to the source of the selection transistor 336, and the drain of the transfer transistor 334 is connected to the source of the selection transistor 338. The drain of the selection transistor 336 is connected to the horizontal signal line 18a for non-inverted data (D0), and the drain of the selection transistor 338 is connected to the horizontal signal line 18b for inverted data (XD0). The gates of the selection transistors 336 and 338 are connected in common and the selection control signal MSEL from the horizontal scanning unit 12 is input. In order to increase the speed, horizontal transfer employs current transfer using a differential signal line pair.

  Transfer transistors 332 and 334 for driving the horizontal signal line 18 are provided for each 6-input sub-selector 302A (that is, a latch group), and the selection transistors 336 and 338 perform selection of a large number of 6-input sub-selectors 302A. A configuration for transferring is used. This can be easily realized by each series circuit of the transfer transistor 332 and the selection transistor 336 or the transfer transistor 334 and the selection transistor 338. Note that the order of arrangement of the transfer transistor 332 and the selection transistor 336 or the transfer transistor 334 and the selection transistor 338 connected in series may be reversed.

  When the gates of the transfer transistor 332 and the selection transistor 336 are at the H level, the transistors 332 and 336 are turned on, and a current is supplied from the sense amplifier 28a not shown through the horizontal signal line 18a for non-inverted data. Flows to the ground side. Similarly, when the gates of the transfer transistor 334 and the selection transistor 338 are at the H level, the transistors 334 and 338 are turned on, and the sense amplifier 28a (not shown) is connected via the horizontal signal line 18b for inverted data. Current flows to the ground side. For example, when the sense amplifier 28a is on the left in the figure, the direction in which current flows from left to right is positive.

  That is, the horizontal transfer driver 308 senses the non-inverted data of the latch 257 based on the selection by the 6-input sub-selector 302A via the horizontal signal line 18a when both the transfer transistor 332 and the selection transistor 336 are turned on. Operate to forward to 28a. Further, when both the transfer transistor 334 and the selection transistor 338 are turned on, the horizontal transfer driver 308 transmits the inverted data of the latch 257 based on the selection by the 6-input sub-selector 302A via the horizontal signal line 18b. Operate to transfer to.

  The horizontal scanning unit 12 has a large number of DFFs 12X (delay flip-flops), but there is one DFF 12X for each of the 6-input sub-selectors 302A. The DFF 12X supplies an active H selection control signal MSEL to the gates of the selection transistors 336 and 338.

  The data DATA <K> of the counter unit 254 is held in six latches 257 and output as logically inverted (complementary) data XDATA <K>. One is selected by the single-ended 6-input sub-selector 302A and is horizontally transferred. Input to the driver 308. One data XDATA <K> selected by the 6-input sub-selector 302A is input to the inverter 331 of the horizontal transfer driver 308 and inverted.

  Here, one data selected by the 6-input sub-selector 302A drives one selection transistor 338 among the selection transistors 336 and 338 in the horizontal transfer driver 308, and the data inverted by the inverter 331 is horizontal The other selection transistor 336 among the selection transistors 336 and 338 in the transfer driver 308 is driven.

  The horizontal transfer driver 308 supplies an active H selection control signal MSEL to the gates of the selection transistors 336 and 338 for each of four horizontal transfer driver sets. That is, the output of the DFF 12X of the horizontal scanning unit 12 selects the selection transistors 336 and 338 in the horizontal transfer driver 308.

  By making the 6-input sub-selector 302A single-ended, the number of transistors can be saved. The output data of the 6-input sub-selector 302A is converted into complementary data (differential signal) by the inverter 331 in relation to the input of the inverter 331, and the complementary (differential) type horizontal transfer channel (two horizontal signal lines 18a, 18b) is driven. In this case, the sense amplifier 28a reproduces data with a differential amplifier circuit.

  If digital data is transferred as complementary data and is reproduced by a differential amplifier circuit provided in a subsequent sense amplifier 28a, the influence can be canceled even if noise is mixed in the horizontal signal lines 18a and 18b. Further, an amplifier circuit is further interposed between the complementary horizontal signal lines 18a and 18b and the sense amplifier 28a to reduce the amplitude on the horizontal signal lines 18a and 18b side and increase the amplitude on the input side of the sense amplifier 28a. By doing so, the problem caused by the parasitic capacitance on the horizontal signal lines 18a and 18b which are bus lines can be improved. This is because a transfer with small amplitude information consumes less power and a high-speed transfer operation is possible than a transfer with large amplitude information.

  Of course, it is not essential to transfer data in a complementary manner as described above, and data transfer using only one of the horizontal signal lines 18a and 18b may be used. When only the horizontal signal line 18 a side is used, the transfer transistor 334 and the selection transistor 338 can be removed from the horizontal transfer driver 308. When only the horizontal signal line 18 b side is used, the inverter 331, the transfer transistor 332, and the selection transistor 336 can be removed from the horizontal transfer driver 308.

  In FIG. 15A, the 96 columns of the horizontal transfer system are shown in a simplified manner, but the horizontal transfer system Htrans0 having the configuration shown in FIG. 15 is prepared for four horizontal transfer channels, and the configuration shown in FIG. A horizontal transfer system Htrans1 is configured. In FIG. 15A, four horizontal transfer systems Htrans1 are arranged. The horizontal transfer driver 308 is selected in units of four. The four horizontal transfer drivers 308 of each group (horizontal transfer system Htrans1) are collectively referred to as a horizontal transfer driver set 309. A selection control signal MSEL is commonly supplied from the DFF 12X of the horizontal scanning unit 12 to the horizontal transfer driver set 309 (four horizontal transfer drivers 308 in the same horizontal transfer system Htrans1).

<Example of basic operation of horizontal transfer system>
FIG. 16 and FIG. 16A are diagrams for explaining the basic operation of the horizontal transfer system Htrans of this embodiment with specific data examples. Here, FIG. 16 shows a data example of the horizontal transfer system Htrans0, and FIG. 16A is a timing chart for explaining a basic operation of the horizontal transfer system Htrans1 (four horizontal transfer systems Htrans0) in the data example of FIG.

  In FIG. 16, a data example of a predetermined bit position (for example, the 0th bit) held by the latch 257 is shown in the latch 257 portion. In the latch 257, “0” or “1” is stored based on the result of AD conversion performed on the pixel information detected by the unit pixel 3 of the pixel array unit 10 by the AD conversion unit 250. For example, in the horizontal transfer system Htrans0_0, “010101” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <0>, which is logically inverted (complementary) and output as output data XD0 <0>. Appear. In the horizontal transfer system Htrans0_1, “101011” is obtained from the upstream side in the horizontal scanning direction, and this appears as output data D0 <1>, which is logically inverted (complementary) and appears as output data XD0 <1>. In the horizontal transfer system Htrans0_2, “000011” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <2>, which is logically inverted (complementary) and appears as output data XD0 <2>. In the horizontal transfer system Htrans0_3, “101110” appears from the upstream side in the horizontal scanning direction, and this appears as output data D0 <3>, which is logically inverted (complementary) and appears as output data XD0 <3>.

  As shown in FIG. 16A, the DFF 12X of the horizontal scanning unit 12 sequentially sets the selection control signal MSEL to active H one by one in order. Accordingly, four horizontal transfer driver sets 309 among the horizontal transfer drivers 308 are sequentially selected.

  The communication / timing control unit 20 sets the subselect signal XSUBSEL_A to the potential low and the subselect signals XSUBSEL_B and XSUBSEL_C to the potential high in the first third of the period when the specific selection control signal MSEL is active H. To do. Further, the communication / timing control unit 20 sets the subselect signal XSUBSEL_B to the potential low, the subselect signals XSUBSEL_A and XSUBSEL_C to the potential high in the next 1/3, and the subselect signal XSUBSEL_C to the potential low in the last 1/3. In addition, the subselect signals XSUBSEL_A and XSUBSEL_B are set to potential high. Further, the communication / timing control unit 20 further sets the subselect signal SUBSELD to the potential high and the subselect signal XSUBSEL_D to the potential low in the first half of each 1/3 period, and the subselect signal SUBSELD to the potential low in the second half. Make XSUBSEL_D high. As a result, a specific latch 257 in the latch group (six latches 257) of the horizontal transfer system Htrans0 is selected.

  The four portions of D0 <k> and XD0 <k> are charts showing whether or not current flows through the horizontal signal lines 18a and 18b. The current flows at the H level and does not represent the potential. .

<Modified operation example of horizontal data transfer system>
FIG. 17 is a diagram for explaining the deformation operation of the horizontal transfer system Htrans in the solid-state imaging device 1 of the present embodiment using the 6-input sub-selector 302A. Here, FIG. 17A is a diagram for explaining the 1/3 decimation operation. FIG. 17B is a diagram for explaining the 1/3 decimation operation. In the figure, the hatched latch 257 has “latch data” and is a transfer target at the time of the thinning operation, and the non-hatched latch 257 has “latch data not” and is a non-transfer target.

  As shown in FIG. 17A, at the time of 1/2 thinning, every other data of the latch 257 is horizontally transferred. The data in every other latch 257 to be transferred is input to the odd three input terminals of the 6-input sub-selector 302A, for example, and sent to the horizontal transfer driver 308. At this time, for every other 6-input sub-selector 302A, the odd-numbered three input terminals with respect to the 6-input terminals are used in the same relationship, and all the 6-input sub-selectors 302A and 302A A horizontal transfer driver 308 is used. In the figure, in order to show this, all horizontal transfer drivers 308 are shown with hatching. Therefore, at the time of 1/2 decimation, the usage state of the horizontal transfer channel is balanced, so that the horizontal transfer channel can be used efficiently.

  Further, as shown in FIG. 17B, at the time of 1/3 decimation, every second data of the latch 257 is horizontally transferred. The data of every second latch 257 to be transferred is input to the k-th and k + 3th (k is any one of 1 to 3) inputs of the 6-input sub-selector 302A and sent to the horizontal transfer driver 308, for example. . At this time, for every other 6-input sub-selector 302A, the k-th and k + 3-th two input terminals are used in the same relationship with respect to the 6-input terminals, and all the 6-input sub-selectors are used. A selector 302A and a horizontal transfer driver 308 are used. In the figure, in order to show this, all horizontal transfer drivers 308 are shown with hatching. Accordingly, the horizontal transfer channel usage state is balanced even during 1/3 decimation, so that the horizontal transfer channel can be used efficiently.

  As described above, by using the 6-input sub-selector 302A, the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning. Even during thinning, all horizontal transfer channels can be used effectively, and the efficiency during thinning can be improved. The frame rate can be improved without increasing the number of horizontal transfer channels. Although not shown in the figure, when a 2-input selector is used as the sub-selector 302, it becomes inefficient at 1/3 decimation, and when a 3-input selector is used, it becomes inefficient at 1/2 decimation. In this regard, the use of the 6-input sub-selector 302A has an advantage that both 1/2 thinning and 1/3 thinning are inefficient.

  Here, it is shown that the horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning in the case of 6 inputs. However, the number of inputs of the sub-selector 302 is 6 (= 2 × 3). The horizontal transfer channel can be efficiently used for both 1/2 thinning and 1/3 thinning as long as there is a relationship of multiples of). In this example, the term “multiple of 6” is used because both 1/2 decimation and 1/3 decimation are taken into account. Each decimation ratio is 1/2 or 1/3. Based on “6” which is the least common multiple of the reciprocal (2, 3).

  It goes without saying that if the ratio of each thinning is different from that in this example, the optimum number of inputs to the sub-selector 302 will be different accordingly. In other words, when dealing with a plurality of thinning modes having different thinning levels, it is not sufficient to use each of the sub-selectors 302 with an input number having a reciprocal number corresponding to any thinning ratio. The number of inputs handled by one sub-selector 302 may be aligned with the least common multiple of the reciprocal of each thinning rate.

<Summary of horizontal data transfer system>
18 and 18A are tables summarizing the effects of the horizontal transfer system Htrans in the solid-state imaging device 1 of the present embodiment in comparison with the prior art. Here, FIG. 18 is a diagram comparing the operational effects of the horizontal transfer systems Htrans of this embodiment and Japanese Patent Application Laid-Open No. 2006-148509. FIG. 18A is a table summarizing the effects of the horizontal transfer system Htrans of this embodiment in comparison with the comparative examples shown in FIGS. 14A and 14B.

  As shown in FIG. 18 (1), in the horizontal transfer system Htrans disclosed in Japanese Patent Application Laid-Open No. 2006-148509, the horizontal transfer driver 308 is connected in multiple stages. Additional transistors are required, increasing the series resistance. On the other hand, as shown in FIG. 18 (2), in the horizontal transfer system Htrans of this embodiment, data is selected in the previous stage of the horizontal transfer driver 308, and the horizontal transfer driver 308 has one stage. It's okay. No additional transistors are required on the current path that flows when the horizontal transfer driver 308 drives, and the series resistance does not increase. Compared with the comparative example, the horizontal transfer driver 308 can be reduced to 1/6, and since there is no cascade connection of the horizontal transfer driver 308, high-speed operation can be realized with certainty.

  As shown in FIG. 18A, the horizontal transfer system Htrans of this embodiment has various other merits. For example, comparing the number of transistors connected in series with the horizontal signal line 18 in the horizontal transfer system Htrans of the comparative example and this embodiment, the number of transistors in series in this embodiment is smaller, so the series resistance is smaller. Work faster. According to the horizontal transfer simulation, it was found that the speed was increased by about 16% compared to the general case such as the comparative example.

  Also, the pair of transfer transistors 332 and 334 and the pair of selection transistors 336 and 338 in the horizontal transfer driver 308 are all doubled in gate width, and the same current flows through these transistors 332, 334, 336, and 338. It has been found that by doubling the gate width of some of the transistors in the sense amplifier 28a through which current flows, the speed is increased by about 32% compared to a general case like the comparative example.

  As described above, at the time of 1/2 thinning or 1/3 thinning, only the control wiring of the 6-input sub-selector 302A, which is a child hierarchy, is skipped and output, so that all horizontal transfers are also performed at 1/2 thinning and 1/3 thinning. The system Htrans can be used effectively and horizontal transfer can be performed efficiently.

  Here, although not shown in the figure, consider a case where the 6-input sub-selector of the first comparative example is used as the 6-input sub-selector 302A instead of the 6-input selector 502Ea (hereinafter referred to as a reference example). In the case of the reference example, the number of control wirings is 12 and the number of transistors is 12 as estimated from the description with reference to FIGS. 8D and 8E. On the other hand, in the horizontal transfer system Htrans of this embodiment, only five control wires are required.

  The portion of the comparative horizontal transfer system Htrans that does not include the horizontal scanning unit 12 includes six latches 257 (TR number = 10) and six horizontal transfer drivers 308Z (TR number = 4). 84 (= 10 × 6 + 4 × 6) transistors are used per digit. When the 6-input sub-selector of the first comparative example is used instead of the 6-input selector 502Ea, the portion not including the horizontal scanning unit 12 of the horizontal transfer system Htrans includes 6 latches 257 (TR number = 10) and 1 There are six 6-input sub-selectors 302A (TR number = 12) and one horizontal transfer driver 308 (TR number = 6), and use 78 (= 10 × 6 + 12 + 6) transistors per digit of 6 columns. become. The portion of the horizontal transfer system Htrans of this embodiment that does not include the horizontal scanning unit 12 includes six latches 257 (TR number = 10), one 6-input sub-selector 302A (TR number = 21), and one. Horizontal transfer driver 308 (TR number = 6), and 87 (= 10 × 6 + 21 + 6) transistors are used per one digit of 6 columns.

  Therefore, in the horizontal transfer system Htrans of the present embodiment, the number of transistors per digit of 6 columns is increased by 3 with respect to the comparative example, and 9 with respect to the reference example using the 6-input sub-selector of the first comparative example. It will increase. However, when the number of horizontal transfer drivers 308 to be controlled is reduced to 1/6, the scale of the horizontal scanning unit 12 can be reduced to about 1/6. Whether the 6-input sub-selector of the first comparative example is used or the horizontal transfer system Htrans of this embodiment has a smaller circuit layout area depends on the pixel pitch and the layout rule.

  As described above, the horizontal transfer system Htrans of this embodiment can perform transfer at a higher speed than the comparative example even when thinning is not performed, and the degree of speeding up is 16% in the simulation as compared with the comparative example. It is about ~ 32%. In addition, all horizontal transfer channels can be effectively used even during thinning, and a horizontal transfer system that improves the efficiency during thinning can be achieved. The frame rate can be improved without increasing the number of horizontal transfer channels, and the control wiring of the 6-input sub-selector 302A can be minimized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  In the above embodiment, the example in which the semiconductor device 400 and the signal selection circuit 500 of this embodiment are applied to the horizontal transfer system of the solid-state imaging device 1 has been described. However, the application range of the above-described embodiment is not limited to the solid-state imaging device. Applicable to any electronic device such as a semiconductor device having a mechanism for sequentially transferring data to the subsequent stage, an imaging device using the solid-state imaging device 1, or an image processing device such as a copying machine or a facsimile device it can. It is sufficient that a specific latch is selected from the one-dimensional or two-dimensionally arranged latches, the latch information is transferred to the transfer wiring, and the data of the transfer wiring is read out to the outside. For example, the mechanism of the semiconductor device 400 and the signal selection circuit 500 of the present embodiment can be applied to a semiconductor memory such as SRAM (Static RAM) or DRAM (Dynamic RAM).

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good. Further, the present invention can be applied not only to a solid-state imaging device but also to an imaging device and any other electronic device. In this case, the same effect as that of the solid-state imaging device can be obtained as the imaging device or other electronic devices. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

It is a figure which shows the basic composition (1st example) of the semiconductor device of this embodiment. It is a figure which shows the basic composition (2nd example) of the semiconductor device of this embodiment. It is a figure explaining the control signal which controls the semiconductor device of this embodiment. It is a figure which shows the semiconductor device of the 1st, 2nd comparative example with respect to the semiconductor device of this embodiment. It is a figure which shows the semiconductor device of the 3rd comparative example with respect to the semiconductor device of this embodiment. It is a figure explaining the basic composition (the 1st example) of the signal selection circuit of this embodiment. It is a figure explaining the basic composition (the 2nd example) of the signal selection circuit of this embodiment. It is a figure explaining the basic composition (the 3rd example) of the signal selection circuit of this embodiment. It is a figure explaining the basic composition (the 4th example) of the signal selection circuit of this embodiment. It is a figure which shows the circuit structure of 3 input selector of this embodiment. It is a figure which shows the selector group which arranged three input selector of this embodiment in one dimension. It is a figure explaining the control signal which controls 3 input selectors of this embodiment. It is a figure which shows the circuit structure of 3 input selector of a 1st comparative example. It is a figure which shows the circuit structure of 3 input selector of a 2nd comparative example. It is a figure which shows the circuit structure of 3 input selector of a 3rd comparative example. It is a figure which shows the circuit structure of 3 input selector of a 4th comparative example. It is a figure which shows the selector group which arranged three input selectors of the 1st comparative example in one dimension. It is the figure (the 1) which summarized the effect of the 3 input selector of this embodiment by contrast with the comparative example. It is the figure (the 2) which summarized the effect of the 3 input selector of this embodiment by contrast with the comparative example. It is a figure which shows the selector group which arranged three input selectors of the 1st modification in one dimension. It is a figure which shows the circuit structure of 3 input selector of a 2nd modification. It is a figure which shows the selector group which arranged three input selectors of the 2nd modification in one dimension. It is a figure explaining the control signal which controls 3 input selector of a 2nd modification. It is a figure which shows the circuit structure of 4 input selector of a 1st example. It is a figure explaining the control signal which controls 4 input selectors of the 1st example. It is a figure explaining contrast with 4 input selector of the 1st example, and a comparative example. It is a circuit block diagram of a 6-input selector of the present embodiment. It is a figure which shows the circuit structure of 6 input selector of this embodiment. It is a figure which shows the selector group which arranged 6 input selector of this embodiment in one dimension. It is a figure explaining the control signal which controls 6 input selectors of this embodiment. It is FIG. (1) explaining contrast with 6-input selector of the 1st example of this embodiment, and a comparative example. It is FIG. (2) explaining contrast with 6-input selector of the 1st example of this embodiment, and a comparative example. It is a circuit block diagram of 9 input selector of this embodiment. It is a figure explaining contrast with 9 input selector of this embodiment, and a comparative example. It is a circuit block diagram of a 12-input selector of this embodiment. It is a figure explaining contrast with 12 input selector of this embodiment, and a comparative example. It is a circuit block diagram of the 5-input selector of this embodiment. It is a figure explaining contrast with 5-input selector of the 1st example of this embodiment, and a comparative example. It is a circuit block diagram of a 4-input selector of the second example and the third example. It is a figure explaining contrast with 4 input selector of the 2nd example and 3rd example, and a 4 input selector of a comparative example and the 1st example. 1 is a basic configuration diagram of a solid-state imaging device (CMOS image sensor). It is a figure which shows the basic composition of the horizontal data transfer system of the solid-state imaging device of this embodiment. It is FIG. (1) which shows the comparative example with respect to the horizontal data transfer type | system | group of this embodiment. It is FIG. (2) which shows the comparative example with respect to the horizontal data transfer type | system | group of this embodiment. It is a figure which shows the detailed structural example (for 1 block: 6 columns) of the horizontal transfer type | system | group of this embodiment. It is a figure which shows the detailed structural example (for four horizontal transfer channels) of the horizontal transfer system of this embodiment. It is a figure which shows the structural example of the clocked inverter used for the latch of a data storage part. It is a figure which shows the example of data for demonstrating the basic operation | movement of the horizontal transfer type | system | group of this embodiment. FIG. 17 is a timing chart for explaining a basic operation of the horizontal transfer system of the present embodiment in the data example of FIG. 16. FIG. It is a figure explaining the deformation | transformation operation | movement of the horizontal transfer system in the solid-state imaging device of this embodiment using 6 input sub-selectors. It is a figure which compares the effect of each horizontal transfer system of this embodiment and Unexamined-Japanese-Patent No. 2006-148509. It is the chart which summarized the operation effect of the horizontal transfer system of this embodiment by contrast with a comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 18 ... Horizontal signal line, 19 ... Vertical signal line, 20 ... Communication / timing control part, 24 ... Read-out current control part , 250 ... AD conversion unit, 252 ... comparison unit, 254 ... counter unit, 256 ... data storage unit, 257 ... latch (data holding circuit), 26 ... column AD conversion unit, 27 ... reference signal generation unit, 270 ... DA conversion 28: Output unit, 3: Unit pixel, 300 ... Data selector unit, 301 ... Selector unit (selection unit), 302 ... Sub-selector (signal selection unit), 307 ... Driver unit (drive unit), 308 ... Horizontal transfer Driver (transfer drive unit), 331... Inverter, 332, 334... Transfer transistor, 336 and 338... Select transistor, 400... Semiconductor device, 401. DESCRIPTION OF SYMBOLS 02 ... 1st transistor part, 403 ... 2nd transistor, 404 ... 2nd transistor part, 408 ... Complementary switch, 500 ... Signal selection circuit, 502 ... Input selector, 502A ... 3 input selector, 502V ... 2 input selector, 7 ... Drive controller

Claims (13)

A first transistor portion having one first transistor of the first conductivity type;
A second transistor portion in which “M−1” second transistors of a second conductivity type different from the first conductivity type are cascade-connected (M is a positive integer of 3 or more);
With
M pairs are arranged in parallel in the pair of the first transistor portion and the second transistor portion,
When an active level for turning on the first transistor is input to the control input terminal of the first transistor for any one of the M sets of the first transistor unit and the second transistor unit, An active level for turning on each second transistor can also be input to the control input terminals of all the second transistors of the set to which the first transistor belongs, and for each of the other sets to which the first transistor does not belong The inactive level for turning off the first transistor can be input to the control input terminal of the first transistor, and the inactive level for turning off the second transistor also at the control input terminal of at least one of the second transistors. A semiconductor device configured to allow level input. The control input terminal of the first transistor to which the active level of each set is input is different from each of the second transistor portions of the other set to which the first transistor does not belong. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a control input terminal of the transistor. The first transistor portion and the second transistor portion of each set are connected to the input end of the second transistor, the input end of the first transistor being closest to the signal input side of the second transistor portion, and The semiconductor device according to claim 1, wherein an output terminal of the first transistor is connected to an output terminal of the second transistor that is closest to the signal output side of the second transistor unit. The signal input sides of the first transistor portion and the second transistor portion of each set are connected in common, and are connected to different signal input ends for each set,
Each signal output side of each pair of the first transistor portion and the second transistor portion is commonly connected to a signal output end,
The semiconductor device according to claim 1, configured to function as a signal selection circuit. The semiconductor device according to claim 4, wherein the M is 3 and is configured to function as a 3-input-1 output-type signal selection circuit. At least one 2-input-1 output-type signal selection circuit configured by connecting two complementary switches in which the first transistor and the second transistor are complementarily connected in parallel;
The semiconductor device according to claim 5, wherein the semiconductor device is configured to function as a “3 + α” input-1 output type signal selection circuit in combination with the 3 input-1 output type signal selection circuit. The semiconductor device according to claim 6, configured to function as a 6-input / 1-output type signal selection circuit. Three signal input circuits of the two input / one output type are provided on the signal input side of the signal input circuit of the three input / one output type,
The semiconductor device according to claim 7, wherein an output signal from the 2-input-1 output-type signal selection circuit is individually input to each input side of the 3-input-1 output-type signal selection circuit. The semiconductor device according to claim 1, wherein the first transistor is a p-channel MOS transistor or an NPN bipolar transistor. A first transistor portion having one first transistor of the first conductivity type;
A second transistor portion in which “M−1” second transistors of a second conductivity type different from the first conductivity type are cascade-connected (M is a positive integer of 3 or more);
With
M pairs are arranged in parallel in the pair of the first transistor portion and the second transistor portion,
The signal input sides of the first transistor portion and the second transistor portion of each set are commonly connected or connectable so that signals are input separately for each set,
Each signal output side of the first transistor portion and the second transistor portion of each set is connected or connectable in common,
One set of the first transistors is connected to or can be connected in common to any one of the second transistors and the control input terminals different from each other in the other second set of the second transistor sections,
The active level of the control signal input to the control input terminal of the first transistor is input as an inactive level to the control input terminal of each second transistor of the other set, and is input to any one group. A semiconductor device that selects and outputs the selected signal. The semiconductor device according to any one of claims 4 to 10, wherein the semiconductor device functions as a one-input / multiple-output type signal selection circuit by reversing the input side and the output side of the signal. A pixel array unit in which unit pixels are arranged in a matrix;
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit;
An AD conversion unit provided for each column for converting an analog pixel signal read from each unit pixel of the pixel array unit into digital data;
A data storage unit provided at a subsequent stage of the AD conversion unit of each column, and having a data holding circuit for holding digital data converted by the AD conversion unit;
A signal selection unit for selecting any of the data of the data holding circuit in M columns (M is a positive integer of 3 or more);
A transfer driver that drives a signal line for data transfer based on the data selected by the signal selector;
A horizontal scanning unit for controlling the transfer driving unit to transfer data to a subsequent circuit via the signal line;
With
The signal selector is
A first transistor section having one first transistor of the first conductivity type and a second transistor in which “M−1” second transistors of a second conductivity type different from the first conductivity type are cascade-connected. M pairs are arranged in parallel with each other,
The signal input sides of the first transistor portion and the second transistor portion of each set are connected in common, and data is input from each separate data holding circuit for each set,
Each signal output side of each of the first transistor section and the second transistor section of each set is connected to the transfer driving section in common. A two-input / one-output type signal selection unit configured by connecting two complementary switches in which the first transistor and the second transistor are complementarily connected in parallel;
The signal input side of the 3-input-1 output type signal selection unit has three 2-input-1 output type signal selection units;
The solid-state imaging device according to claim 12, wherein an output signal from the 2-input-1 output-type signal selection unit is individually input to each input side of the 3-input-1 output-type signal selection unit.

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