JP2009200213A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a hybrid structure, a threshold voltage (Vth) of which is low and the semiconductor characteristics of which bring about no problem. <P>SOLUTION: The semiconductor device having a hybrid structure includes an n-type semiconductor element comprising a first gate insulating film 4, which is a high-k film, on a substrate 1 between a first source region 2 and a first drain region 3 provided on the substrate 1, and a first gate electrode, which is a polysilicon film, on the first gate insulating film 4, and a p-type semiconductor element comprising a second gate insulating film 4, which is a high-k film, on the substrate 1 between a second source region 2 and a second drain region 3 provided on the substrate 1, first metal films 7, 8 on a second insulating film, and a second gate electrode, which is a polysilicon film, on the first metal films 7, 8. Then, the first metal film 8 includes a titanium nitride film to which an additive material that increases the work function compared to titanium nitride alone includes been added. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a hybrid structure and a manufacturing method thereof.

  In recent years, miniaturization of semiconductor devices has progressed, and application of a poly-Si / metal / high-k gate stack structure is being considered instead of poly-Si / SiON in SoC (System On a Chip) devices after 45 nm node. . Specifically, it is described in detail in Patent Document 1 and Non-Patent Documents 1 and 2. Here, high-k is a gate insulating film using a high dielectric constant material, such as an HfSiON film.

  In the poly-Si / high-k structure, particularly in the p-type MIS (Metal Insulator Semiconductor), there is a problem that the threshold voltage (Vth) increases due to the phenomenon of gate depletion and Fermi Level Pinning. The problem has been solved by using TiN, which is easy to apply, only for p-type MIS. Specifically, a hybrid-structure gate transistor including a poly-Si / TiN / HfSiON p-type MIS in which TiN is inserted between poly-Si and HfSiON and a poly-Si / HfSiON n-type MIS, In particular, the problem of gate depletion on the pMIS side was solved.

  On the other hand, as described in Patent Document 2, as a measure for reducing the threshold voltage of p-type MIS, a method of implanting F (fluorine) ions having high electronegativity into a substrate before forming a gate insulating film is effective. Met.

JP 2007-19396 A JP 2003-273350 A T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, and Y. Inoue, "Cost Worthy and High Performance LSTP CMIS; poly-Si / HfSiON nMIS and poly-Si / TiN / HfSiON pMIS", IEDM Tech.Dig., (2006) p.247. M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, "Fluorine Incorporation into HfSiON Dielectric for Vth Control and Its Impact on Reliability for Poly-Si Gate pFET ", IEDM Tech.Dig., (2005) p.425.

  However, when TiN inserted between poly-Si of p-type MIS and HfSiON is formed using PVD (Physical Vapor Deposition) with less damage to the lower layer film, poly-Si / TiN / high The work function (WF) of TiN in the -k structure is about 4.8 eV, and there is a problem that the work function (WF) required in the ITRS 2006 update version does not reach 4.9 eV. Therefore, the threshold voltage (Vth) cannot be sufficiently lowered in the conventional semiconductor device.

  As described in the background art, as a measure for reducing the threshold voltage (Vth) of the p-type MIS, F (fluorine) ion implantation into the substrate before the gate insulating film is effective. Damage causes problems in semiconductor characteristics such as deterioration of S value (Subthreshold Swing) and decrease of Ion value (ON current value).

  Accordingly, an object of the present invention is to provide a semiconductor device having a hybrid structure that has a low threshold voltage (Vth) and does not cause a problem in semiconductor characteristics.

  In one embodiment of the present invention, a first gate insulating film made of a high-k film formed on the substrate between a first source region and a first drain region provided on the substrate, and the first gate Formed on the substrate between an n-type semiconductor element having a first gate electrode made of a polysilicon film formed on an insulating film, and a second source region and a second drain region provided on the substrate. A second gate insulating film made of a high-k film, a first metal film formed on the second insulating film, and a second gate electrode made of a polysilicon film formed on the first metal film And a p-type semiconductor element having a hybrid structure. In one embodiment of the present invention, the first metal film has a titanium nitride film to which an additive substance having a work function higher than that of a single titanium nitride is added.

  In the semiconductor device according to the present invention, the first metal film having the titanium nitride film to which the additive substance having a work function higher than that of the titanium nitride alone is added is formed on the second insulating film. The voltage (Vth) is low, and there is no problem in semiconductor characteristics such as S value and Ion value.

(Embodiment 1)
FIG. 1 shows a cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 1 has a hybrid structure including an n-type MIS (Metal Insulator Semiconductor) having a poly-Si / high-k structure and a p-type MIS having a poly-Si / TiN / high-k structure. This is a semiconductor device. More specifically, the n-type MIS shown on the left side of FIG. 1 gates a high-k HfSiON film 4 on the semiconductor substrate 1 between the source region 2 and the drain region 3 formed in the semiconductor substrate 1. An insulating film is formed, and a poly-Si film 5 is formed as a gate electrode on the HfSiON film 4. Further, sidewalls 6 are formed of insulating films on the side surfaces of the HfSiON film 4 and the poly-Si film 5. Note that the n-type MIS shown in FIG. 1 functions as an nFET (Field effect transistor).

  On the other hand, the p-type MIS shown on the right side of FIG. 1 has a high-k HfSiON film 4 formed as a gate insulating film on the semiconductor substrate 1 between the source region 2 and the drain region 3 formed on the semiconductor substrate 1. A TiN film 7 is formed on the HfSiON film 4. Further, in the p-type MIS, a TiNO film 8 is formed on the TiN film 7, and a poly-Si film 5 is formed on the TiNO film 8 as a gate electrode. Further, sidewalls 6 are formed of insulating films on the side surfaces of the HfSiON film 4, the TiN film 7, the TiNO film 8, and the poly-Si film 5. Note that the p-type MIS shown in FIG. 1 functions as a pFET. Further, as shown in FIG. 1, an element isolation film 9 is provided between the n-type MIS and the p-type MIS to separate the two semiconductor elements.

  In the p-type MIS shown in FIG. 1, since the TiN film 7 and the TiNO film 8 are provided on the HfSiON film 4, the oxygen element (O) in the TiNO film 8 is converted into the HfSiON film 4 during activation annealing at about 1000 ° C. The threshold voltage (Vth) can be reduced by diffusing in the direction. Further, since oxygen element (O) is an additive substance having a work function higher than that of titanium nitride alone, a work function (WF) of 4.9 eV required in the ITRS 2006 update version can be obtained. Here, as an additive substance having a work function higher than that of titanium nitride alone, there are fluorine (F) and chlorine (Cl) in addition to the oxygen element (O). Further, in FIG. 1, the metal film sandwiched between the HfSiON film 4 and the poly-Si film 5 has a two-layer laminated structure of a TiN film 7 and a TiNO film 8, but the present invention is not limited to this, and the metal film May be a single-layer structure of the TiNO film 8.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. Since the configuration of the semiconductor device shown in FIG. 1 is basically similar to the conventional configuration, a detailed manufacturing method is omitted, and a manufacturing method of a two-layer structure of a TiN film 7 and a TiNO film 8 which is a characteristic part is omitted. Only explained. First, a TiN film 7 is formed on the HfSiON film 4 by sputtering using a mixed gas of argon and nitrogen as a Ti target. Thereafter, an oxygen gas is added to the mixed gas of argon and nitrogen, and a TiNO film 8 is formed on the TiN film 7 by using a reactive sputtering method. That is, two layers of the TiN film 7 and the TiNO film 8 can be continuously formed by the same sputtering apparatus depending on the presence or absence of the oxygen gas to be added.

  The TiN film 7 and the TiNO film 8 in the region where the n-type MIS is to be formed are removed by wet etching, and then a p-doped poly-Si film 5 is formed to form the semiconductor device shown in FIG.

  As a method of generating the TiNO film 8, it is conceivable to employ a method of annealing the TiN film 7 in an oxygen atmosphere or a method of implanting oxygen ions into the TiN film 7 in addition to the reactive sputtering method. However, the method of annealing the TiN film 7 in an oxygen atmosphere has a demerit that the formation of the TiNO film 8 cannot be accurately controlled, and it is considered difficult to form the TiNO film 8 having a desired film thickness. Further, in the method of implanting oxygen ions into the TiN film 7, there is a possibility that semiconductor element characteristics such as S value deterioration due to implantation damage to the high-k HfSiON film 4 may be lowered. Note that even when F (fluorine) ion implantation into the semiconductor substrate 1 is performed, there is a possibility that the semiconductor element characteristics such as S value deterioration due to implantation damage to the HfSiON film 4 may be lowered.

  On the other hand, when the TiNO film 8 is formed using the reactive sputtering method described in the present embodiment, since the PVD (Physical Vapor Deposition) method is used, damage to the HfSiON film 4 is caused by ion implantation. Low and does not cause deterioration of semiconductor element characteristics such as S value degradation.

  Note that the p-type MIS is higher than the n-type MIS because a two-layer stacked structure of the TiN film 7 and the TiNO film 8 is added. For this reason, when the p-type MIS and the n-type MIS are processed by etching, a difference in processing may occur between the two. Therefore, in the present embodiment, the thickness of the two-layer laminated structure of the TiN film 7 and the TiNO film 8 is set to about 1/10 of that of the poly-Si film 5 in order to prevent the processing difference between them. It is desirable.

  Further, in the semiconductor device according to the present embodiment, when the configuration of only the TiNO film 8 is adopted instead of the two-layer laminated structure of the TiN film 7 and the TiNO film 8, the thickness of the gate insulating film does not increase. It is necessary to form the TiNO film 8 under the control.

(Embodiment 2)
FIG. 2 is a cross-sectional view of the semiconductor device according to this embodiment. The semiconductor device shown in FIG. 2 is a semiconductor device having a hybrid structure in which the n-type MIS has a poly-Si / TiN / high-k structure unlike the first embodiment. More specifically, the n-type MIS shown on the left side of FIG. 2 gates a high-k HfSiON film 4 on the semiconductor substrate 1 between the source region 2 and the drain region 3 formed in the semiconductor substrate 1. A TiN film 7 is formed on the HfSiON film 4 as an insulating film. Further, in the n-type MIS, an N-rich TiN film 10 is formed on the TiN film 7, and a poly-Si film 5 is formed on the N-rich TiN film 10 as a gate electrode. Further, sidewalls 6 are formed of insulating films on the side surfaces of the HfSiON film 4 and the poly-Si film 5.

  Here, the N-rich TiN film 10 is a titanium nitride film that is richer in nitrogen than titanium nitride having a stoichiometric composition. The stoichiometric titanium nitride refers to titanium nitride in which Ti and N are configured in a one-to-one relationship. On the other hand, the p-type MIS is the same as that shown in the first embodiment, and thus detailed description thereof is omitted.

  Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIGS. First, in FIG. 3, the HfSiON film 4 is formed on the semiconductor substrate 1 in the n-type MIS region and the p-type MIS region separated by the element isolation film 9, and the TiN film 7 is formed thereon by sputtering. Further, in FIG. 3, a TiNO film 8 is formed on the TiN film 7 by a reactive sputtering method in which oxygen is supplied to form a two-layer laminated structure of the TiN film 7 and the TiNO film 8.

  Next, in FIG. 4, resist coating and lithography are performed to form a resist film 11 only in the p-type MIS region, and the TiNO film 8 in the n-type MIS region is removed by performing an etching process. Next, in FIG. 5, the resist film 11 is removed, and an N-rich TiN film 10 is formed on the TiN film 7 by a reactive sputtering method in which excess nitrogen of a predetermined amount or more is supplied. The predetermined amount of excess nitrogen means an amount equal to or more than the amount of nitrogen supplied when forming a TiN film by a normal sputtering method.

  Next, in FIG. 6, resist coating and lithography are performed to form a resist film 12 only in the n-type MIS region. Next, in FIG. 7, the N-rich TiN film 10 in the p-type MIS region is removed by performing an etching process, and then the resist film 12 is also removed.

  Next, in FIG. 8, a poly-Si film 5 is formed on the TiNO film 8 and the N-rich TiN film 10 shown in FIG. 7, and is processed into a predetermined gate electrode and gate insulating film using lithography processing. To do. After that, the semiconductor according to the present embodiment as shown in FIG. 9 is obtained by performing activation annealing, processing of the source region 2, the drain region 3, and the sidewall 6 similar to the conventional method for forming a semiconductor device. A device can be formed. In the semiconductor device shown in FIG. 9, the NiSi film 13 is provided on the poly-Si film 5.

  As a method for generating the N-rich TiN film 10, it is conceivable to employ a method of implanting nitrogen ions into the TiN film 7 in addition to the reactive sputtering method. However, in the method of implanting nitrogen ions into the TiN film 7, there is a possibility that semiconductor element characteristics such as S value deterioration due to implantation damage to the high-k HfSiON film 4 may be lowered.

  On the other hand, when the N-rich TiN film 10 is formed by using the reactive sputtering method described in the present embodiment, the damage to the HfSiON film 4 is lower than that of the ion implantation because of the low damage PVD method. Degradation of semiconductor element characteristics such as value deterioration hardly occurs.

  The etching rate of the p-type MIS TiNO film 8 is lower than that of the n-type MIS N-rich TiN film 10. For this reason, when the p-type MIS and the n-type MIS are processed by etching, a difference in processing may occur between the two. Therefore, in the present embodiment, the thickness of the N-rich TiN film 10 is set to about 1.5 to 2 times the thickness of the TiNO film 8 in order to prevent a difference in processing between them. desirable.

  Further, in the n-type MIS of the semiconductor device according to the present embodiment, it has been described that the TiN film 7 and the N-rich TiN film 10 have a two-layer laminated structure. However, the present invention is not limited to this, and the N-rich TiN. A one-layer structure of the film 10 may be used. However, in this embodiment, the TiNO film 8 is removed by wet or dry etching while leaving a part of the TiN film 7 in the step of FIG. 4, so that etching damage to the HfSiON film 4 can be suppressed, but N-rich In the case of the single layer structure of the TiN film 10, it is necessary to suppress etching damage to the HfSiON film 4 by another method.

  As described above, in the semiconductor device according to the present embodiment, during activation annealing at about 1000 ° C., the nitrogen element (N) in the N-rich TiN film 10 diffuses in the direction of the HfSiON film 4 and the threshold voltage ( Vth) can be reduced. In this embodiment, since the N-rich TiN film 10 is formed by using the reactive sputtering method, S value deterioration due to implantation damage to the HfSiON film 4 hardly occurs.

It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention.

Explanation of symbols

  1 semiconductor substrate, 2 source region, 3 drain region, 4 HfSiON film, 5 poly-Si film, 6 sidewall, 7 TiN film, 8 TiNO film, 9 element isolation film, 10 N-rich TiN film, 11, 12 resist Film, 13 NiSi film.

Claims (8)

A first gate insulating film made of a high-k film formed on the substrate between a first source region and a first drain region provided on the substrate;
An n-type semiconductor element comprising a first gate electrode made of a polysilicon film formed on the first gate insulating film;
A second gate insulating film made of a high-k film formed on the substrate between a second source region and a second drain region provided on the substrate;
A first metal film formed on the second insulating film;
A hybrid semiconductor device including a p-type semiconductor element including a second gate electrode made of a polysilicon film formed on the first metal film,
The semiconductor device according to claim 1, wherein the first metal film includes a titanium nitride film to which an additive material having a work function higher than that of titanium nitride alone is added. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first metal film has a two-layer structure of a titanium nitride film to which the additive substance is not added and a titanium nitride film to which the additive substance is added. The semiconductor device according to claim 1 or 2, wherein
The semiconductor device, wherein the additive material is oxygen, and the titanium nitride film to which the additive material is added is a TiNO film. A method of manufacturing the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the TiNO film is formed by a reactive sputtering method to which the oxygen is supplied. A semiconductor device according to any one of claims 1 to 3,
A semiconductor device, further comprising a second metal film having a titanium nitride film that is more nitrogen-rich than a stoichiometric titanium nitride film between the first gate insulating film and the first gate electrode. The semiconductor device according to claim 5,
The semiconductor device, wherein the second metal film has a two-layer structure of a titanium nitride film having a stoichiometric composition and a titanium nitride film that is richer in nitrogen than the stoichiometric titanium nitride. A method of manufacturing the semiconductor device according to claim 5 or 6,
The method for manufacturing a semiconductor device, wherein the nitrogen-rich titanium nitride film is formed by a reactive sputtering method in which a predetermined amount or more of the nitrogen is supplied. A method of manufacturing the semiconductor device according to claim 5 or 6,
(A) forming a titanium nitride film on the first gate insulating film and the insulating film to be the second gate insulating film;
(B) forming a TiNO film on the surface of the titanium nitride film by a reactive sputtering method to which oxygen is supplied;
(C) removing the TiNO film formed on the region to be the n-type semiconductor element;
(D) forming a nitrogen-rich titanium nitride film on the titanium nitride film from which the TiNO film has been removed in the step (c) by a reactive sputtering method in which a predetermined amount or more of the nitrogen is supplied;
(E) removing the nitrogen-rich titanium nitride film on the TiNO film formed in the step (d);
(F) forming a polysilicon film on the TiNO film and the nitrogen-rich titanium nitride film;
(G) A method of manufacturing a semiconductor device comprising: forming the n-type semiconductor element and the p-type semiconductor element by a predetermined patterning process.

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