JP2009200324A - Manufacturing method of semiconductor device, and electronic information apparatus - Google Patents

Abstract

Even when element components such as a pixel size are further miniaturized, it is possible to suppress a manufacturing variation in a relative position of adjacent ion implantation regions such as a photoelectric conversion unit and a charge transfer unit. A semiconductor device manufacturing method for manufacturing a semiconductor device such as a quality CCD device is obtained.
In a semiconductor device manufacturing method, a first ion implantation mask 11 having first and second mask openings 11a and 11b is formed, and a second mask opening of the first ion implantation mask 11 is formed. 11b is masked with a second ion implantation mask, and ion implantation is performed through the first mask opening 11a of the first ion implantation mask, and then the first mask opening 11a of the first ion implantation mask is made third. Then, ion implantation is performed through the second mask opening 11 b of the first ion implantation mask 11.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device and an electronic information device, and in particular, an ion implantation method for positioning each ion implantation region in a semiconductor device in a self-aligned manner, and such an ion implantation method. The present invention relates to an electronic information device provided with a solid-state imaging device.

  Conventionally, there is a solid-state imaging device called a CCD (Charge Coupled Device) image sensor. This type of solid-state imaging device is arranged in a matrix and has a plurality of light receiving units (photodiodes) that perform photoelectric conversion, A plurality of vertical CCDs that are arranged along each row of the light receiving units and transfer the signal charges obtained by the light receiving units, and a horizontal CCD that transfers the signal charges from the vertical CCDs in the horizontal direction. Yes.

  6 and 7 are diagrams for explaining a conventional method for manufacturing a solid-state imaging device. 6 (a) and 6 (b) show an ion implantation process to a region to be a vertical CCD and a light receiving portion of a semiconductor substrate, and FIGS. 7 (a) and 7 (b) are views between the vertical CCD and the light receiving portion. The ion implantation process into the region to be the charge read gate portion and the region to be the element isolation portion (CS portion) between the vertical CCD portion and the light receiving portion is shown.

  As shown in FIG. 7B, a plurality of ion implantation regions 2 to 5 are formed in the surface region of the P-type semiconductor substrate 1 constituting the conventional solid-state imaging device. In addition, the ion implantation area | region 2 is an area | region which comprises a photoelectric conversion part, and is also only called the photoelectric conversion part 2 for convenience of description below. The ion implantation region 3 constitutes a substrate region constituting a charge transfer portion, the ion implantation region 4 constitutes a substrate region constituting a charge readout portion (TG portion), and the ion implantation region 5 constitutes an element isolation portion (CS portion). The ion implantation regions 3, 4, and 5 are also referred to as a charge transfer unit 3, a charge readout unit 4, and an element isolation unit 5, respectively, for convenience of explanation.

  Here, the photoelectric conversion unit 2 and the charge transfer unit 3 are arranged at a predetermined interval. Between the photoelectric conversion unit 2 and the charge transfer unit 3 on one side thereof, an element separation unit (CS unit) 5 for electrically separating them is disposed, and the photoelectric conversion unit 2 and the charge on the other side are arranged. Between the transfer unit 3, a charge reading unit (TG unit) 4 for reading a signal charge from the photoelectric conversion unit 2 to the charge transfer unit 3 is arranged.

  The photoelectric conversion unit 2, the charge transfer unit 3, the charge readout unit 4, and the element isolation unit 5 are formed by ion implantation masks 62 to 65 formed on the semiconductor substrate 1 through an implantation protective film 9. (See FIGS. 6A to 6B and FIGS. 7A to 7B).

  Next, a conventional method for manufacturing a solid-state imaging device will be described.

  First, an injection protective film 9 is formed on a P-type semiconductor substrate (for example, a P-type silicon substrate) 1, and then a mask opening is formed in the region 3a to be the charge transfer portion 3 of the semiconductor substrate 1 by applying and developing a resist film. A photomask 63 on which 63 a is formed is formed on the implantation protective film 9. Subsequently, an N-type impurity Xa is ion-implanted using the photomask 63 as an ion implantation mask to form an N-type ion implantation region as a charge transfer portion (CCD) 3 in the surface region of the semiconductor substrate 1 (FIG. 6 ( a)).

  Next, after the photomask 63 is removed, a photomask 62 in which a mask opening 62a is formed in the region 2a to be the photoelectric conversion portion 2 of the semiconductor substrate 1 is formed using the photolithography technique in the same manner as described above. Subsequently, an N-type impurity Xa is ion-implanted using the photomask 62 as an ion implantation mask to form an N-type ion implantation region as the photoelectric conversion unit 2 in the surface region of the semiconductor substrate 1 (FIG. 6B). .

  Next, after the photomask 62 is removed, a photomask 64 in which a mask opening 64a is formed in the region 4a to be the charge reading portion 4 of the semiconductor substrate 1 is formed by using the photolithography technique as described above. Subsequently, a P-type impurity Xb is ion-implanted using the photomask 64 as an ion implantation mask to form a P-type ion implantation region as the charge reading portion 4 in the surface region of the semiconductor substrate 1.

  Thereafter, after the photomask 64 is removed, a photomask 65 in which a mask opening 65a is formed in the region 5a to be the element isolation portion 5 of the semiconductor substrate 1 is formed by using the photolithography technique as described above. Subsequently, a P-type impurity Xb is ion-implanted using the photomask 65 as an ion implantation mask to form a P-type ion implantation region as the element isolation portion 5 in the surface region of the semiconductor substrate 1. Here, ion implantation for forming the element isolation portion 5 is performed twice while changing the ion implantation energy. In the element isolation portion 5, the P-type impurity concentration of the shallow portion 51 on the surface side is changed. This is higher than the P-type impurity concentration in the deep portion 52.

  By the way, at present, in order to miniaturize and increase the density of a CCD type solid-state imaging device, an area within a pixel, that is, a photoelectric conversion unit 2, a charge transfer unit 3, a charge reading unit 4, which constitutes one pixel, In addition, various companies are working hard to reduce the alignment accuracy in the region including the element isolation portion 5.

For example, Patent Document 1 discloses a method for forming an element isolation portion (referred to as a PI portion in this document) and a pixel readout portion (TG portion) in a single pixel as a countermeasure. Has been.
Japanese Patent Laid-Open No. 5-190830

  However, in the method disclosed in Patent Document 1 described above, an element isolation portion (referred to as a PI portion in this document) and a pixel readout portion (TG portion) in one pixel are a mask pattern of one resist mask. However, with this resist mask, the photoelectric conversion unit 2 and the charge transfer unit 3 cannot be positioned in a self-aligned manner. Therefore, in Patent Document 1, when the pixel size is further miniaturized, the manufacturing position of the relative position between the photoelectric conversion unit (PD unit) 2 and the charge transfer unit (CCD unit) 4, particularly the variation caused by the mask alignment accuracy. However, this greatly affects the device characteristics.

  The present invention has been made to solve the above-described conventional problems, and even if the miniaturization of the constituent elements of the semiconductor device such as the miniaturization of the pixel size has progressed, the adjacent ion implantation of the photoelectric conversion unit, the charge transfer unit, etc. The manufacturing variation of the relative position of the region can be suppressed to be small, and thereby a semiconductor device manufacturing method capable of manufacturing a semiconductor device such as a high-quality CCD device, and such a semiconductor device manufacturing method can be obtained. Another object of the present invention is to provide an electronic information device having the solid-state imaging device.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a plurality of ion implantation regions, and includes a first mask opening and second mask openings located on both sides of the first mask opening. Forming a first ion implantation mask including: forming a second ion implantation mask so that a second mask opening of the first ion implantation mask is masked; and Using the second ion implantation mask to perform ion implantation through the first mask opening of the first ion implantation mask to form a first ion implantation region; and After removing, a step of forming a third ion implantation mask so that the first mask opening of the first ion implantation mask is masked, and using the first and third ion implantation masks, 1 ion Are those through a second mask opening for entering the mask and forming a second ion-implanted region by ion implantation, it said object is achieved.

  The present invention provides the semiconductor device manufacturing method, wherein the first ion implantation region and the second ion implantation region have the same conductivity type and are ion implanted under different ion implantation conditions. It is preferable.

  According to the present invention, in the semiconductor device manufacturing method, the first ion implantation region and the second ion implantation region are self-aligned by the first and second mask openings of the first ion implantation mask. Are preferably positioned.

  In the method for manufacturing a semiconductor device according to the present invention, the first ion implantation mask is preferably an insulating hard mask formed by patterning an insulating film using one photomask.

  According to the present invention, in the semiconductor device manufacturing method, the first ion implantation mask is an insulating hard mask made of a silicon oxide film, and the second and third ion implantation masks are photomasks. Is preferred.

  According to the present invention, in the method for manufacturing a semiconductor device, a fourth ion implantation mask having a mask pattern obtained by inverting the mask pattern using the first ion implantation mask after removing the third ion implantation mask. And the fourth ion implantation mask is located at a portion between the first mask opening of the first ion implantation mask and the second mask opening located on one side thereof. It is preferable to have a side mask opening and the other side mask opening located in a portion between the first mask opening of the first ion implantation mask and the second mask opening located on the other side.

  According to the present invention, in the method of manufacturing a semiconductor device, a fifth ion implantation mask is formed so that one side mask opening of the fourth ion implantation mask is masked, and the fourth and fifth ions are formed. Preferably, the method includes a step of forming a third ion implantation region by performing ion implantation using the implantation mask through the other side mask opening of the fourth ion implantation mask.

  The present invention provides the method for manufacturing a semiconductor device, wherein the first ion implantation region and the second ion implantation region have the same conductivity type, and the third ion implantation region includes the first and second ion implantation regions. It is preferable to have a conductivity type different from that of the second ion implantation region.

  According to the present invention, in the semiconductor device manufacturing method, the first to third ion implantation regions are positioned in a self-aligned manner by the first and second mask openings of the first ion implantation mask. It is preferable.

  According to the present invention, in the semiconductor device manufacturing method, after the fifth ion implantation mask is removed, the sixth ion implantation mask is formed so that the other side mask opening of the fourth ion implantation mask is masked. And a step of performing ion implantation through one side mask opening of the fourth ion implantation mask using the fifth and sixth ion implantation masks to form a fourth ion implantation region. Is preferred.

  The present invention provides the method for manufacturing a semiconductor device, wherein the first ion implantation region and the second ion implantation region have the same conductivity type, and the third ion implantation region includes the first and second ion implantation regions. It is preferable to have a conductivity type different from that of the second ion implantation region.

  According to the present invention, in the semiconductor device manufacturing method, the first to fourth ion implantation regions are positioned in a self-aligned manner by the first and second mask openings of the first ion implantation mask. It is preferable.

  According to the present invention, in the semiconductor device manufacturing method, the first ion implantation mask is an insulating hard mask formed by patterning an insulating film using one photomask, and the fourth ion implantation mask. Is preferably a conductive hard mask obtained by patterning a conductive film using the insulating hard mask.

  According to the present invention, in the method of manufacturing a semiconductor device, the step of forming the fourth ion implantation mask includes removing the third ion implantation mask and then using a conductive film as the first ion implantation mask. A conductive film forming step for covering the entire surface of the insulating hard mask and the surface of the underlying layer exposed in the mask opening, and conductive film etching for etching the conductive film so that the insulating hard mask is exposed Preferably, the method includes a step and an insulating film etching step of etching the exposed insulating hard mask using the conductive film remaining after the etching as a mask.

  In the method for manufacturing a semiconductor device according to the present invention, in the conductive film etching step, the conductive film and the insulating hard mask covered with the conductive film are formed to a predetermined thickness by a chemical mechanical polishing method. It is preferable that it is the process of removing by etching.

  The present invention provides the semiconductor device manufacturing method, wherein the first ion implantation mask is an insulating hard mask formed by patterning a silicon oxide film, and the second and third ion implantation masks are photomasks. Preferably, the fourth ion implantation mask is a conductive hard mask obtained by patterning a polysilicon film, and the fifth and sixth ion implantation masks are photomasks.

  According to the present invention, in the method for manufacturing a semiconductor device, the semiconductor devices are arranged in a matrix, and a plurality of photoelectric conversion units that generate signal charges by photoelectric conversion of incident light, along each column of the photoelectric conversion units. And a charge transfer unit that transfers a signal charge obtained by the photoelectric conversion unit, and the first ion implantation region includes a charge transfer unit of the solid-state image pickup device. Preferably, the second ion implantation region is a region that constitutes a photoelectric conversion unit of the solid-state imaging device.

  According to the present invention, in the method for manufacturing a semiconductor device, the semiconductor devices are arranged in a matrix, and a plurality of photoelectric conversion units that generate signal charges by photoelectric conversion of incident light, along each column of the photoelectric conversion units. And a charge transfer unit that transfers a signal charge obtained by the photoelectric conversion unit, and the first ion implantation region includes a charge transfer unit of the solid-state image pickup device. The second ion implantation region is a region constituting a photoelectric conversion unit of the solid-state imaging device, and the third ion implantation region is a photoelectric conversion unit of the solid-state imaging device; and The fourth ion implantation region is a region that constitutes a charge readout unit that is located between the charge transfer unit on one side of the photoelectric conversion unit and reads signal charges from the photoelectric conversion unit to the charge transfer unit, A photoelectric conversion unit of the solid-state imaging device; Located between the charge transfer portion of the other side of the photoelectric conversion unit is preferably a region that constitutes the electrically isolated to the element isolation portion and a photoelectric conversion unit and the charge transfer portion.

  According to the present invention, in the method of manufacturing a semiconductor device, the position of the first ion implantation region with respect to the second ion implantation region, and the third and fourth ion implantation regions with respect to the second ion implantation region. The position preferably determines the efficiency of charge transfer in the solid-state imaging device.

  An electronic information device according to the present invention is an electronic information device provided with an imaging unit, and uses the solid-state imaging device obtained by the method for manufacturing a semiconductor device according to claim 17 or 18 as the imaging unit. Thus, the above object is achieved.

  The operation of the present invention will be described below.

  In the present invention, a first ion implantation mask having a first mask opening and a second mask opening located on both sides of the first mask opening is formed, and the second ion implantation mask is formed by the second ion implantation mask. After masking the mask opening with a second ion implantation mask, ion implantation is performed through the first mask opening of the first ion implantation mask to form a first ion implantation region, and then the second ion implantation is performed. After removing the implantation mask, the first mask opening of the first ion implantation mask is masked with the third ion implantation mask, and then ion implantation is performed through the second mask opening of the first ion implantation mask. Since the second ion implantation region is formed, the first and second ion implantation regions having different ion implantation conditions are positioned by the first and second mask openings of the first ion implantation mask to be self-aligned. It can be formed.

  In the present invention, since the first ion implantation mask is an insulating hard mask formed by patterning an insulating film using a single photomask, the second and third ion implantation masks are formed as a photomask. By using the mask, the second and third ion implantation masks can be easily formed without breaking the opening pattern of the first ion implantation mask.

  In the present invention, after removing the third ion implantation mask, a fourth ion implantation mask having a mask pattern obtained by inverting the mask pattern using the first ion implantation mask is formed. By ion implantation using the fourth ion implantation mask, a further ion implantation region can be formed in a self-aligned manner adjacent to the ion implantation region positioned by the mask pattern of the first ion implantation mask.

  In the present invention, after masking one side mask opening of the fourth ion implantation mask with the fifth ion implantation mask, ion implantation is performed through the other side mask opening of the fourth ion implantation mask. Next, after removing the fifth ion implantation mask and masking the other side mask opening of the fourth ion implantation mask with the sixth ion implantation mask, the fourth ion implantation region is formed. Since the fourth ion implantation region is formed by performing ion implantation through the one side mask opening of the implantation mask, the third and fourth ion implantation regions having different ion implantation conditions are arranged on one side of the fourth ion implantation mask and It can be positioned by the other side mask opening and formed in a self-aligning manner. Moreover, since the fourth ion implantation mask has a mask pattern obtained by inverting the mask pattern of the first ion implantation mask, the third and fourth ion implantation regions are changed to the first and second ion implantation regions. In contrast, they can be arranged in a self-aligning manner.

  In the present invention, the first ion implantation mask is an insulating hard mask obtained by patterning an insulating film, and the fourth ion implantation mask is a conductive hard mask obtained by patterning a conductive film. Since the mask is used, the fourth ion implantation mask can be easily formed by selective etching of the conductive film using the insulating hard mask.

  In the present invention, the first ion implantation region is a region constituting a charge transfer unit of a solid-state imaging device, and the second ion implantation region is a region constituting a photoelectric conversion unit of the solid-state imaging device. By doing so, the relative position between the photoelectric conversion unit and the charge transfer unit in the solid-state imaging device can be reduced in manufacturing variation, and the yield of the solid-state imaging device can be suppressed and the performance can be improved. Further, the third ion implantation region is a region constituting a charge reading unit that reads signal charges from the photoelectric conversion unit to the charge transfer unit, and the fourth ion implantation region is the photoelectric conversion unit and the charge transfer unit. By making the region that constitutes the element separation part that electrically separates the photoelectric conversion part and the charge transfer part from each other, the relative position of the charge reading part and the element separation part can also be reduced in manufacturing variation. Thus, the yield and performance of the solid-state imaging device can be further improved.

  As described above, according to the present invention, the first ion implantation mask having the first mask opening and the second mask openings located on both sides of the first mask opening is formed, and the first After masking the second mask opening of the ion implantation mask with the second ion implantation mask, ion implantation is performed through the first mask opening of the first ion implantation mask to form a first ion implantation region. In addition, after removing the second ion implantation mask, the first mask opening of the first ion implantation mask is masked by the third ion implantation mask, and then the second mask opening of the first ion implantation mask. Since the second ion implantation region is formed by performing ion implantation through the first and second ion implantation regions, the first and second ion implantation regions having different ion implantation conditions are positioned by the first and second mask openings of the first ion implantation mask. Shi It can be self-aligned manner.

  As a result, even if the element components such as the pixel size are further miniaturized, it is possible to suppress the manufacturing variation in the relative position of the adjacent ion implantation regions such as the photoelectric conversion unit and the charge transfer unit. There is an effect that a semiconductor device such as a quality CCD device can be manufactured.

  According to the present invention, the third and fourth ion implantation regions are formed using the fourth ion implantation mask having a mask pattern obtained by inverting the mask pattern using the first ion implantation mask. Therefore, the third and fourth ion implantation regions can be arranged in a self-aligned manner with respect to the first and second ion implantation regions.

  As a result, in a semiconductor device such as a CCD device, the manufacturing variation of the relative positions of the charge readout unit (TG unit) and the element isolation unit (CS unit) with respect to the photoelectric conversion region (PD unit), which greatly affects the characteristics, is suppressed. There is an effect that can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention. FIG. 1A shows a CCD solid-state imaging device as an example of a semiconductor device obtained by the method for manufacturing a semiconductor device. A schematic configuration is shown.

  The CCD solid-state imaging device 100 according to the first embodiment is arranged in a matrix (two-dimensional), and corresponds to a plurality of photodiodes (photoelectric conversion units) PD that perform photoelectric conversion, and columns of the photodiodes PD. A vertical CCD unit 30 that transfers signal charges generated by the photodiode PD in the vertical direction, a horizontal CCD unit 40 that transfers signal charges from the vertical CCD unit 30 in the horizontal direction, and a horizontal CCD unit 40 The output unit 50 is connected to the terminal and amplifies the signal charge transferred in the horizontal direction and outputs the signal charge as a signal voltage. Here, each photodiode PD constitutes each pixel Px in the CCD type solid-state imaging device 100 together with a corresponding portion of the vertical CCD unit 30.

  FIG. 1B is a plan view showing the layout of the ion implantation regions constituting the photodiode PD and the vertical CCD unit 30 of the CCD type solid-state imaging device 100.

  As shown in FIG. 1B, for example, N-type ion implantation regions 2 constituting a photodiode (photoelectric conversion unit) PD are arranged in a matrix on the surface region of a semiconductor substrate 1 such as a P-type silicon substrate. An N-type ion implantation region 3 constituting a corresponding vertical CCD unit (charge transfer unit) 30 is arranged along a column of photoelectric conversion units 2 arranged in the vertical direction. Further, a P-type ion implantation region 4 constituting a charge reading part (TG part) is disposed between the photoelectric conversion part 2 and the charge transfer part 3 located on one side thereof, and further adjacent thereto. Between the photoelectric conversion units 2 and between the photoelectric conversion unit 2 and the charge transfer unit 3, a P-type ion implantation region 5 that constitutes an element isolation unit that electrically isolates these components is disposed.

  As described above, the ion implantation regions 2 to 5 are substrate regions constituting the photoelectric conversion unit, the charge transfer unit, the charge readout unit (TG unit), and the element isolation unit (CS unit), respectively. For the sake of simplicity, the ion implantation regions 2 to 5 are also referred to as a photoelectric conversion unit 2, a charge transfer unit 3, a charge readout unit 4, and an element isolation unit 5, respectively. A gate electrode constituting the vertical CCD unit 30 is formed on the semiconductor substrate 1 via an insulating film (not shown), but is not shown here.

  Next, a method for manufacturing the solid-state imaging device according to the first embodiment will be described.

  2 to 5 are cross-sectional views illustrating the manufacturing method of the solid-state imaging device according to this embodiment in the order of steps, and show the structure of the cross section taken along line Ib-Ib in FIG.

  First, as shown in FIG. 2A, an implantation protective film 9 having a thickness of several hundred angstroms is formed on a semiconductor substrate 1 containing a P-type impurity such as a P-type silicon substrate. Here, a silicon oxide film is generally used as the implantation protection film 9, but it is desirable that the implantation protection film 9 has a two-layer structure in which a silicon nitride film is laminated on a silicon oxide film. In this case, the film thickness of the silicon oxide film and the silicon nitride film is set to about 500 angstroms.

  Subsequently, a mask material layer 10 to be an implantation blocking film (first ion implantation mask) 11 is formed on the implantation protective film 9. The implantation blocking film 11 needs to have a film thickness that can sufficiently exhibit the ion implantation blocking ability at the time of ion implantation in the next step, for example, about 1 μm. Is an insulating hard mask, and specifically, it is desirable to use a silicon oxide film formed by a commonly used plasma CVD (P-CVD) method or low pressure CVD (LP-CVD) method. .

  Thereafter, a photomask (hereinafter referred to as a resist mask) 6 is formed on the implantation blocking film 11 by patterning a resist film using a photolithography technique.

  The resist mask 6 has first and second resist openings 6a and 6b in portions corresponding to the arrangement region 3a of the charge transfer unit 3 and the arrangement region 2a of the photoelectric conversion unit 2 on the surface of the P-type semiconductor substrate 1. It is formed and masks the arrangement regions 4a and 5a of the charge readout portion (TG portion) and the element isolation portion (CS portion) on the surface of the semiconductor substrate 1.

  Next, as shown in FIG. 2 (b), the mask material layer 10 is selectively applied to the photoelectric conversion unit 2 and the charge transfer unit 3 in the arrangement regions 2 a and 3 a of the semiconductor substrate 1 using the resist mask 6. Patterning is performed by dry etching so that a mask pattern for implantation is formed. At this time, as an etching condition, in order to prevent the P-type semiconductor substrate 1 which is the base of the injection blocking film 10 from being etched, the etching with the upper silicon nitride film constituting the two-layer structure injection protective film 9 is performed. Select one that has a high etching selectivity. By etching the mask material layer 10, the first ion implantation mask 11 having the first and second mask openings 11a and 11b is formed. In the first mask opening 11a of the first ion implantation mask 11, ions are implanted into the surface region 3a of the P-type semiconductor substrate 1 exposed in the opening, so that a charge transfer portion (first ion implantation region) is obtained. 3, and the second mask opening 11 b implants ions into the surface region 2 a of the semiconductor substrate 1 exposed in the opening, so that a photoelectric conversion unit (second ion implantation) is formed. Region) 2 is formed.

  Next, as shown in FIG. 3A, the resist film is patterned to mask the ion implantation mask 11 other than the arrangement region 3a of the charge transfer portion 3 which is the formation region of the first mask opening 11a. Two ion implantation masks 12 are formed. Thereafter, using the first and second ion implantation masks 11 and 12, phosphorus (P), which is an N-type impurity, is implanted through the first mask opening 11a of the first ion implantation mask 11 with an implantation energy of about 200 KeV. Ion implantation. Thereby, ion implantation is performed in the arrangement region 3 a of the charge transfer unit (vertical CCD unit) 3 to form an ion implantation region as the charge transfer unit (CCD unit) 3.

  Subsequently, after removing the second ion implantation mask 12, as shown in FIG. 3B, the second mask opening 11b of the first ion implantation mask 11 is formed by patterning a resist film. A third ion implantation mask 13 is formed to mask the region other than the region 2a of the photoelectric conversion unit 2 that is a region. Thereafter, using the first and third ion implantation masks 11 and 13, phosphorus (P), which is an N-type impurity, is implanted through the second mask opening 11 b of the first ion implantation mask 11 with an implantation energy of about 750 KeV. Ion implantation. Thereby, ion implantation is performed in the arrangement region 2a of the photoelectric conversion unit 2, and an ion implantation region as the photoelectric conversion unit 2 is formed.

  Next, after the ion implantation, the second ion implantation mask 12 is removed, and then a mask material layer for forming a second hard mask (implantation blocking film) 21 as shown in FIG. 20 is formed on the entire surface. Here, since the CMP (Chemical Mechanical Polishing) is performed in the next step, a material capable of obtaining a sufficient selection ratio by polishing by the CMP method is used as the film forming seed. Here, a polycrystalline silicon film is optimal for the ion implantation mask (implantation blocking film) 21 because it is generally used and has a sufficient selection ratio with the silicon oxide film. In the film formation, the implantation blocking film 21 serves as a mask for ion implantation into the arrangement regions 5a and 4a of the element isolation portion (CS portion) 5 and the charge readout portion (TG portion) 4 in the next process. Therefore, the optimum thickness and film quality (particle size) may be selected in advance.

  After the excess mask material layer 20 is removed by CMP in this way, as shown in FIG. 4B, the first hard mask (in the TG portion or CS portion remaining in the arrangement region 4a or 5a ( The injection blocking film 11 is completely removed by dry etching or wet etching. Thereby, the second hard mask 21 is formed. The hard mask 21 has a one-side mask opening 21 a and the other-side mask opening 21 b of the photoelectric conversion unit 2. The first-side mask opening 21a of the mask 21 is for implanting ions into the surface region of the P-type semiconductor substrate 1 exposed in the opening to form an ion implantation region as the charge reading portion 4. The other side mask opening 21b is for forming an ion implantation region as the element isolation portion 5 by implanting ions into the surface region of the semiconductor substrate 1 exposed in the opening.

  Next, as shown in FIG. 5A, the resist film is patterned to mask the regions other than the arrangement region 4a of the charge reading portion 4 which is the formation region of the one-side mask opening 21a of the ion implantation mask 20. The ion implantation mask 16 is formed. Thereafter, using the fourth and fifth ion implantation masks 21 and 16, boron (B), which is a P-type impurity, is implanted with an implantation energy of about 100 KeV through the one-side mask opening 21 a of the fourth ion implantation mask 21. Ion implantation. Thereby, ion implantation is performed in the arrangement region 4a of the TG portion, and an ion implantation region as the TG portion 4 is formed.

  Subsequently, after the fifth ion implantation mask 16 is removed, as shown in FIG. 5B, an element which is a formation region of the other side mask opening 21b of the ion implantation mask 20 by patterning a resist film. A sixth ion implantation mask 26 is formed to mask areas other than the arrangement region 5a of the separation portion 5.

  Thereafter, boron (B), which is a P-type impurity, is ion-implanted through the other-side mask opening 21 b of the fourth ion implantation mask 21 using the fourth and sixth ion implantation masks 21 and 26. At this time, boron ion implantation is performed twice while changing the implantation energy, and the first implantation energy is 100 Kev and the second implantation energy is several hundred Kev. Thus, an ion implantation region is formed in which the pure concentration in the shallow portion 51 is higher than the impurity concentration in the deep portion 52.

  Thereafter, other components such as electrodes constituting the solid-state imaging device are sequentially formed to complete the solid-state imaging device.

  Through the steps as described above, the ion implantation regions as the PD portion and the CCD portion, and the ion implantation regions as the TG portion and the CS portion can be formed in a self-aligned manner. Accordingly, it is possible to suppress the alignment accuracy variation that increases the influence on the characteristics as the pixel size is miniaturized. As a result, a high-quality CCD device having uniform device characteristics can be manufactured.

  As described above, in the first embodiment, the first ion implantation mask 11 having the first mask opening 11a and the second mask openings 11b located on both sides of the first mask opening is formed, and the first After masking the second mask opening 11b of the second ion implantation mask 11 with the second ion implantation mask 12, ion implantation is performed through the first mask opening 11a of the first ion implantation mask 11, and the charge transfer section (first 1 ion implantation region) 3 and then the second ion implantation mask 12 is removed, and then the first mask opening 11a of the first ion implantation mask 11 is formed by the third ion implantation mask 13. After the masking, ion implantation is performed through the second mask opening 11b of the first ion implantation mask 11 to form the photoelectric conversion portion (second ion implantation region) 2. Therefore, the electric current with different ion implantation conditions is formed. The transfer unit 3 and the photoelectric conversion unit 2, can be formed in a self-aligned manner by positioning the first and second mask openings 11a and 11b of the first ion implantation mask 11.

  In the first embodiment, the first ion implantation mask 11 is an insulating hard mask formed by patterning the insulating film (silicon oxide film) 10 using one photomask 6. By using the third ion implantation masks 11 and 12 as photomasks, the second and third ion implantation masks 12 and 13 can be easily made without breaking the opening patterns 11a and 11b of the first ion implantation mask 11. Can be formed.

  In the first embodiment, since the fourth ion implantation mask 21 has a mask pattern obtained by inverting the mask pattern of the first ion implantation mask 11, ions using the fourth ion implantation mask 12 are used. By implantation, further ion implantation regions (charge reading portions) 4 and (element isolation portions) 5 are formed in a self-aligned manner with respect to the ion implantation regions 2 and 3 positioned by the mask pattern of the first ion implantation mask 11. can do.

  In the first embodiment, after masking one side mask opening 21 a of the fourth ion implantation mask 21 with the fifth ion implantation mask 16, ion implantation is performed through the other side mask opening 21 b of the fourth ion implantation mask 21. To form the third ion implantation region (charge reading portion) 4, and then the fifth ion implantation mask 16 is removed, and the other side mask opening 21 b of the fourth ion implantation mask 21 is changed to the sixth one. After masking with the ion implantation mask 26, ion implantation is performed through the one-side mask opening 21a of the fourth ion implantation mask to form the fourth ion implantation region (element isolation portion) 5. Therefore, different ion implantation conditions are obtained. The third and fourth ion implantation regions (charge readout portions) 4 and (element isolation portions) are connected to one side and the other side mask openings 21a and 21 of the fourth ion implantation mask 21. Can be self-aligned manner is positioned by. Moreover, since the fourth ion implantation mask 21 has a mask pattern obtained by inverting the mask pattern of the first ion implantation mask 11, the third and fourth ion implantation regions (charge reading portions) 4 and (element isolation) are provided. Part) 5 can also be arranged in a self-aligned manner with respect to the first and second ion implantation regions (charge transfer part) 3 and (photoelectric conversion part) 2.

  In the first embodiment, the first ion implantation mask 11 is an insulating hard mask obtained by patterning an insulating film (silicon oxide film), and the fourth ion implantation mask 21 is patterned by a conductive film. Thus, the fourth ion implantation mask 21 can be easily formed by selective etching of the conductive film (polysilicon film) using the insulating hard mask 11.

  As described above, in the first embodiment, the relative position between the photoelectric conversion unit 2 and the charge transfer unit 3 in the solid-state imaging device can be reduced in manufacturing variation, and the yield of the solid-state imaging device can be suppressed and the performance can be improved. Can be planned. Further, the relative positions of the charge reading unit 4 and the element separation unit 5 with respect to the photoelectric conversion unit 2 and the charge transfer unit 3 can be made with small manufacturing variations, thereby further improving the yield and performance of the solid-state imaging device. Can be improved.

  In the first embodiment, the ion implantation region as the photoelectric conversion unit 2 is formed after the ion implantation region as the charge transfer unit 3 is formed. An implantation region may be formed, and then an ion implantation region as the charge transfer unit 3 may be formed.

  In the first embodiment, the ion implantation region as the element separation unit 5 is formed after the ion implantation region as the charge reading unit 4 is formed. An implantation region may be formed, and then an ion implantation region as the charge reading unit 4 may be formed.

Furthermore, in the first embodiment, the semiconductor device manufacturing method has been described by taking a CCD solid-state imaging device as an example of the semiconductor device. However, the semiconductor device manufacturing method of the present invention uses a CCD solid-state imaging device. The present invention is not limited to the target one, and any semiconductor device having a plurality of ion implantation regions arranged adjacent to each other as an element region, for example, a CMOS solid-state imaging device, The manufacturing method of the semiconductor device of the invention can be applied.
(Embodiment 2)
Although not specifically described in the first embodiment, a digital camera such as a digital video camera or a digital still camera using the solid-state imaging device 100 of the first embodiment as an imaging unit, an image input camera, a scanner, An electronic information device having an image input device such as a facsimile or a camera-equipped mobile phone will be described. The electronic information device of the present invention is a memory such as a recording medium for recording data after high-quality image data obtained by using the solid-state imaging device 100 of Embodiment 1 of the present invention as an imaging unit is subjected to predetermined signal processing for recording. A display means such as a liquid crystal display device for displaying the image data on a display screen such as a liquid crystal display screen after the image data is subjected to predetermined signal processing for display; and after the image data is subjected to predetermined signal processing for communication It has at least one of communication means such as a transmission / reception device for performing communication processing and image output means for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. It is understood that the patent documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  In the field of a semiconductor device manufacturing method and electronic information equipment having a solid-state imaging device manufactured by the semiconductor device manufacturing method, by positioning each ion implantation region in the semiconductor device in a self-aligning manner, Even if device components are miniaturized, such as pixel size, manufacturing variations in the relative positions of adjacent ion implantation regions such as photoelectric conversion units and charge transfer units can be kept small. A semiconductor device such as a device can be manufactured.

FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A shows a CCD solid-state imaging device as an example of a semiconductor device obtained by the method of manufacturing a semiconductor device. A schematic configuration is shown, and FIG. 1B shows a layout of an ion implantation region in a pixel constituting the CCD type solid-state imaging device 100. FIG. 2 is a cross-sectional view taken along the line Ib-Ib for explaining the method of manufacturing the solid-state imaging device according to the present embodiment, and shows a step of forming a first hard mask (FIGS. 2A and 2B). ing. FIG. 3 is a cross-sectional view taken along the line Ib-Ib for explaining the method of manufacturing the solid-state imaging device according to the present embodiment, the step of forming an ion implantation region constituting the charge transfer unit (FIG. 3A), FIG. 3B shows a step of forming an ion implantation region constituting the structure (FIG. 3B). FIG. 4 is a cross-sectional view taken along the line Ib-Ib for explaining the method for manufacturing the solid-state imaging device of the present embodiment, and shows a step of forming a second hard mask (FIGS. 4A and 4B). ing. FIG. 5 is a cross-sectional view taken along the line Ib-Ib for explaining the method of manufacturing the solid-state imaging device according to the present embodiment, the step of forming an ion implantation region constituting the charge reading unit (FIG. 5A), FIG. 5B shows a step of forming an ion implantation region constituting the structure (FIG. 5B). FIGS. 6A and 6B are diagrams for explaining a conventional method for manufacturing a solid-state imaging device, and FIGS. 6A and 6B show an ion implantation process to a region to be a vertical transfer portion and a light receiving portion of a semiconductor substrate, respectively. ing. 7A and 7B are diagrams for explaining a conventional method for manufacturing a solid-state imaging device. FIGS. 7A and 7B are a region to be a charge transfer unit between a vertical transfer unit and a light receiving unit, and a vertical unit, respectively. The ion implantation process to the area | region which should become an element isolation part between a transfer part and a light-receiving part is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Photoelectric conversion part (2nd ion implantation area | region)
3 Charge transfer unit (first ion implantation region)
4 Charge readout section (third ion implantation region)
5 Device isolation part (fourth ion implantation region)
6 Photomasks 6a and 6b First and second resist openings 9 Implantation protection film 10 Silicon oxide film 11 First hard mask (first ion implantation mask)
11a, 11b First and second mask openings 12 Photomask (second ion implantation mask)
13 Photomask (third ion implantation mask)
16 Photomask (5th ion implantation mask)
20 Polycrystalline silicon film 21 Second hard mask (fourth ion implantation mask)
21a One side mask opening 21b The other side mask opening 26 Photomask (sixth ion implantation mask)
30 Vertical CCD unit 40 Horizontal CCD unit 50 Output unit 100 CCD type solid-state imaging device PD photodiode Px pixel

Claims (20)

A method of manufacturing a semiconductor device having a plurality of ion implantation regions,
Forming a first ion implantation mask having a first mask opening and a second mask opening located on both sides of the first mask opening;
Forming a second ion implantation mask such that the second mask opening of the first ion implantation mask is masked;
Performing ion implantation through the first mask opening of the first ion implantation mask using the first and second ion implantation masks to form a first ion implantation region;
After removing the second ion implantation mask, forming a third ion implantation mask so that the first mask opening of the first ion implantation mask is masked;
Forming a second ion implantation region by performing ion implantation through the second mask opening of the first ion implantation mask using the first and third ion implantation masks. . In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first ion implantation region and the second ion implantation region have the same conductivity type and are ion implanted under different ion implantation conditions. In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the first ion implantation region and the second ion implantation region are positioned in a self-aligned manner by first and second mask openings of the first ion implantation mask. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the first ion implantation mask is an insulating hard mask formed by patterning an insulating film using a single photomask. In the manufacturing method of the semiconductor device according to claim 4,
The first ion implantation mask is an insulating hard mask made of a silicon oxide film,
The method of manufacturing a semiconductor device, wherein the second and third ion implantation masks are photomasks. In the manufacturing method of the semiconductor device according to claim 1,
Forming a fourth ion implantation mask having a mask pattern obtained by inverting the mask pattern using the first ion implantation mask after removing the third ion implantation mask;
The fourth ion implantation mask includes:
A one-side mask opening located in a portion between the first mask opening of the first ion implantation mask and a second mask opening located on one side thereof;
A method of manufacturing a semiconductor device having a second mask opening located in a portion between a first mask opening of the first ion implantation mask and a second mask opening located on the other side. In the manufacturing method of the semiconductor device according to claim 6,
Forming a fifth ion implantation mask such that one side mask opening of the fourth ion implantation mask is masked;
A semiconductor device including a step of forming a third ion implantation region by performing ion implantation through the other side mask opening of the fourth ion implantation mask using the fourth and fifth ion implantation masks. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 7,
The first ion implantation region and the second ion implantation region have the same conductivity type,
The method of manufacturing a semiconductor device, wherein the third ion implantation region has a conductivity type different from that of the first and second ion implantation regions. In the manufacturing method of the semiconductor device according to claim 8,
The method of manufacturing a semiconductor device, wherein the first to third ion implantation regions are positioned in a self-aligned manner by the first and second mask openings of the first ion implantation mask. In the manufacturing method of the semiconductor device according to claim 7,
After removing the fifth ion implantation mask, forming a sixth ion implantation mask so that the other side mask opening of the fourth ion implantation mask is masked;
Forming a fourth ion implantation region by performing ion implantation through one side mask opening of the fourth ion implantation mask using the fifth and sixth ion implantation masks. . In the manufacturing method of the semiconductor device according to claim 10,
The first ion implantation region and the second ion implantation region have the same conductivity type,
The method of manufacturing a semiconductor device, wherein the third ion implantation region has a conductivity type different from that of the first and second ion implantation regions. In the manufacturing method of the semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the first to fourth ion implantation regions are positioned in a self-aligned manner by the first and second mask openings of the first ion implantation mask. In the manufacturing method of the semiconductor device according to claim 6,
The first ion implantation mask is an insulating hard mask formed by patterning an insulating film using one photomask,
The method of manufacturing a semiconductor device, wherein the fourth ion implantation mask is a conductive hard mask formed by patterning a conductive film using the insulating hard mask. In the manufacturing method of the semiconductor device according to claim 13,
The step of forming the fourth ion implantation mask includes:
After removing the third ion implantation mask, a conductive film is formed on the entire surface so as to cover the surface of the insulating hard mask which is the first ion implantation mask and the surface of the underlayer exposed in the mask opening. A conductive film forming step;
A conductive film etching step of etching the conductive film so that the insulating hard mask is exposed;
An insulating film etching step of etching the exposed insulating hard mask using the conductive film remaining after the etching as a mask. In the manufacturing method of the semiconductor device according to claim 14,
The conductive film etching step is a step of etching and removing the conductive film and the insulating hard mask covered with the conductive film to a predetermined thickness by a chemical mechanical polishing method. Method. In the manufacturing method of the semiconductor device according to claim 15,
The first ion implantation mask is an insulating hard mask formed by patterning a silicon oxide film,
The second and third ion implantation masks are photomasks;
The fourth ion implantation mask is a conductive hard mask formed by patterning a polysilicon film,
The semiconductor device manufacturing method, wherein the fifth and sixth ion implantation masks are photomasks. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor devices are arranged in a matrix, and are arranged adjacent to each other along each column of the photoelectric conversion units, and a plurality of photoelectric conversion units that generate signal charges by photoelectric conversion of incident light. A solid-state imaging device having a charge transfer unit for transferring the obtained signal charge,
The first ion implantation region is a region constituting a charge transfer unit of the solid-state imaging device,
The method of manufacturing a semiconductor device, wherein the second ion implantation region is a region constituting a photoelectric conversion unit of the solid-state imaging device. In the manufacturing method of the semiconductor device according to claim 10,
The semiconductor devices are arranged in a matrix, and are arranged adjacent to each other along each column of the photoelectric conversion units, and a plurality of photoelectric conversion units that generate signal charges by photoelectric conversion of incident light. A solid-state imaging device having a charge transfer unit for transferring the obtained signal charge,
The first ion implantation region is a region constituting a charge transfer unit of the solid-state imaging device,
The second ion implantation region is a region constituting a photoelectric conversion unit of the solid-state imaging device,
The third ion implantation region is located between the photoelectric conversion unit of the solid-state imaging device and the charge transfer unit on one side of the photoelectric conversion unit, and transmits signal charges from the photoelectric conversion unit to the charge transfer unit. It is a region that constitutes a charge reading unit to be read,
The fourth ion implantation region is located between the photoelectric conversion unit of the solid-state imaging device and the charge transfer unit on the other side of the photoelectric conversion unit, and electrically connects the photoelectric conversion unit and the charge transfer unit. A manufacturing method of a semiconductor device which is a region which constitutes an element separation part which is separated into two. In the manufacturing method of the semiconductor device according to claim 18,
The position of the first ion implantation region with respect to the second ion implantation region and the positions of the third and fourth ion implantation regions with respect to the second ion implantation region are the charge transfer efficiency in the solid-state imaging device. Semiconductor device manufacturing method for determining An electronic information device including an imaging unit,
An electronic information device using the solid-state imaging device obtained by the method for manufacturing a semiconductor device according to claim 17 or 18 as the imaging unit.

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