JP2009201048A - Flip-flop circuit and semiconductor device - Google Patents

Abstract

A flip-flop circuit and a semiconductor device capable of suppressing deterioration of data output waveform quality are provided.
[Solution]
The flip-flop circuit includes a first upper circuit including a first differential pair for reading data (Tr11, Tr12) and a first differential pair for holding data (Tr13, Tr14), a first current A master latch circuit is provided that includes a switch differential pair (Tr15, Tr16) and a first current switch circuit including a first current source Is11. In addition, the second upper circuit including the second differential pair for reading data (Tr21, Tr22) and the second differential pair for holding data (Tr23, Tr24) and the difference for the second current switch The slave latch circuit includes a moving pair (Tr25, Tr26) and a second current switch circuit including a second current source Is21. Further, the slave latch circuit has means for reducing the switching speed of the second current switch circuit.
[Selection] Figure 3

Description

  The present invention relates to a flip-flop circuit and a semiconductor device having the flip-flop circuit.

  As a conventional flip-flop circuit, for example, a circuit using an emitter coupled logic (ECL) basic circuit as shown in FIG. 1 is known (see Non-Patent Document 1). The circuit configuration of FIG. 1 is described in FIG. The circuit includes a master latch and a slave latch, and is called a master / slave type flip-flop. The master latch has an upper differential pair for reading data (Tr11, Tr12), a positive feedback differential pair for holding data at the upper stage (Tr13, Tr14), and a differential pair for current switches at the lower stage (Tr15, Tr16). And an emitter follower. The positive phase (complementary phase) data terminal DT / DC is connected to the base terminals of the transistors Tr11 and Tr12 that constitute the differential pair for reading data in the upper stage of the master latch.

  Further, the positive phase (complementary phase) clock terminal CT / CC is connected to the base terminals of the transistors Tr15 and Tr16 constituting the differential pair for the current switch in the lower stage of the master latch. The common point on the emitter terminal side of the transistors Tr15 and Tr16 is connected to the current source Is11, and the transistors Tr15 and Tr16 and the current source Is11 function as a current switch using a clock signal as a control signal. When CT is at a high level and CC is at a low level, the transistor Tr15 is turned on and the transistor Tr16 is turned off. Then, currents from the transistors Tr11 and Tr12 flow to the current source Is11 as a drive current, and the master latch reads data input from the positive phase (complementary phase) data terminal DT / DC. Next, when CT is at a low level and CC is at a high level, the transistor Tr15 is turned off and the transistor Tr16 is turned on. Then, currents from the transistors Tr13 and Tr14 flow to the current source Is11 as a drive current, and the master latch holds data. The emitter follower is a circuit that performs impedance conversion when data held by the master latch is output to the slave latch, and functions as a buffer amplifier (buffer) that outputs the emitter terminals of the transistors Tr17 and Tr18.

  The slave latch includes an upper differential pair for reading data (Tr21, Tr22), a positive feedback differential pair for retaining data at the upper stage (Tr23, Tr24), and a differential pair for current switches at the lower stage (Tr25, Tr26). ) And an emitter follower. The data held and output by the master latch is input to the base terminals of the transistors Tr21 and Tr22 constituting the differential pair for reading data in the upper stage of the slave latch. The positive phase (complementary phase) clock terminal CT / CC is connected to the base terminals of the transistors Tr25 and Tr26 constituting the differential pair for the current switch in the lower stage of the slave latch. The common point on the emitter terminal side of the transistors Tr25 and Tr26 is connected to the current source Is21, and the transistors Tr25 and Tr26 and the current source Is21 function as a current switch using a clock signal as a control signal.

When CT is at a low level and CC is at a high level, the transistor Tr25 is turned on and the transistor Tr26 is turned off. Then, currents from the transistors Tr21 and Tr22 flow to the current source Is21 as a drive current, and the slave latch reads data held and output by the master latch. Next, when CT is at a high level and CC is at a low level, the transistor Tr25 is turned off and the transistor Tr26 is turned on. Then, currents from the transistors Tr23 and Tr24 flow to the current source Is21 as a drive current, and the slave latch holds data. The emitter follower is a circuit that performs impedance conversion when outputting data held by the slave latch, and is a buffer amplifier (buffer) in which the emitter terminals of the transistors Tr27 and Tr28 are respectively positive-phase (complementary) output terminals QT / QC. ). As described above, the master-slave flip-flop temporarily holds the data input from the positive phase (complementary phase) input terminal DT / DC according to the clock and outputs it from the positive phase (complementary phase) output terminal QT / QC. Repeat the operation.
Abed-Elhak Kasbari, Philippe Andre, AgnieszkaKonczykowska, Muriel Riet, Sylvain Blayac, Habiba Ouslimani, and Jean Godin, “Design of High-Speed Master-Slave D-Type Flip-Flop in InP DHBTTechnology”, IEEE Transactions on Microwave Theory andTechnique vol.50, No.12, December 2002

  However, the conventional flip-flop circuit has a problem that the quality of the data output waveform deteriorates due to clock noise. The master latch and slave latch use the clock signal as a control signal to switch the lower current switch and control the operation timing of the upper data reading differential pair and the upper data holding differential pair. However, since switching of the current switch requires a finite time, the master latch and the slave latch have a transient state from the data reading state to the data holding state. Conversely, there is a transient state from the data holding state to the data reading state. Clock noise occurs in the transient state described above.

  Here, in the conventional flip-flop circuit, consider a transient state in which the slave latch transitions from the data reading state to the data holding state. In the data reading state, the positive phase (complementary phase) output terminal QT is set to the high level, and the positive phase (complementary phase) output terminal QC is set to the low level. That is, the transistor Tr21 constituting the differential pair for reading data at the upper stage of the slave latch is Off and the transistor Tr22 is On, and the transistors Tr23 and Tr24 constituting the differential pair for holding data at the upper stage of the slave latch are Off. However, the base terminal of the transistor Tr23 is at the low level, and the base terminal of the transistor Tr24 is at the high level.

  When the slave latch transitions from the data reading state to the data holding state, the current flowing through the differential pair for reading data in the upper stage of the slave latch decreases, and the current flows out to the differential pair for holding data in the upper stage. Therefore, the transistor Tr22 is switched from On to Off, and the transistor Tr24 is switched from Off to On. At this time, since it takes time to charge the base-collector capacitance of the transistor Tr24, the speed at which the transistor Tr24 is turned from Off to On is lower than the speed at which the transistor Tr22 is turned from On to Off. Due to the speed difference, the current flowing through the load resistor R22 decreases. That is, the potential at the collector terminal of the transistor Tr24 increases. As a result, clock noise is generated such that the clock leaks into the positive phase (complementary phase) output terminal QC.

  FIG. 2 shows the output waveform of the flip-flop during 40 Gbps operation. The low level clock noise is 250 mVpp and the high level clock noise is 80 mVpp. It can be seen that the data output waveform quality is degraded due to clock noise, and the effective logic amplitude is reduced.

  The present invention has been made in view of these problems, and provides a flip-flop circuit and a semiconductor device capable of suppressing deterioration in data output waveform quality.

  To achieve the above object, in a flip-flop circuit according to the present invention, a first differential pair for reading data constituted by a pair of transistors and a first differential pair for holding data constituted by a pair of transistors. A master latch circuit including a first upper-stage circuit including a first current switch circuit including a first current switch differential pair and a first current source, and a pair of transistors. A second upper stage circuit including a second data reading differential pair constituted by the second data holding differential pair constituted by the pair of transistors and a second pair constituted by the pair of transistors. A slave latch circuit including a differential pair for the current switch and a second current switch circuit including a second current source. Further, the slave latch circuit has means for reducing the switching speed of the second current switch circuit.

  Moreover, as described in claim 2, in the flip-flop circuit according to the present invention described in claim 1, the means for reducing the switching speed of the second current switch circuit includes the second It is a resistor provided at the emitter terminals of both transistors constituting the differential pair for the current switch.

  According to a third aspect of the present invention, in the flip-flop circuit according to the first or second aspect of the present invention, the means for reducing the switching speed of the second current switch circuit is the second circuit. A resistor provided at the emitter terminal of both transistors constituting the differential pair for reading data and a resistor provided at the emitter terminal of both transistors constituting the differential pair for holding the second data It is characterized by being.

  According to a fourth aspect of the present invention, in the flip-flop circuit according to the second or third aspect of the present invention, the emitter terminals of the two transistors constituting the differential pair for the first current switch are connected to each other. It is characterized by providing a resistor.

  Further, as described in claim 5, the flip-flop circuit according to any one of claims 1 to 4 is a circuit for operation at 40 Gbps or more and 100 Gbps or less.

  According to a sixth aspect of the present invention, a semiconductor device according to the present invention includes the flip-flop circuit according to any of the first to fifth aspects.

  According to the flip-flop circuit of the present invention, since the slave latch circuit has means for reducing the switching speed of the second current switch circuit, it is possible to suppress the deterioration of the data output waveform quality.

  Further, according to the flip-flop circuit of the present invention, since the resistors are provided at the emitter terminals of both transistors constituting the differential pair for the first current switch, the master latch circuit can be obtained without deteriorating the input sensitivity characteristic. As in the slave latch circuit, the leakage of the clock can be suppressed, and the deterioration of the data output waveform quality can be further suppressed.

  The semiconductor devices according to the first to fifth embodiments of the present invention will be described below with reference to FIGS. Note that the semiconductor devices according to the first to fifth embodiments have a flip-flop circuit for 40 Gbps operation using InP heterobipolar transistor (HBT) technology.

(First embodiment)
First, the configuration of the flip-flop circuit included in the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a first embodiment of the present invention. As shown in FIG. 3, the flip-flop circuit according to the first embodiment includes a master latch circuit and a slave latch circuit. The master latch circuit includes a first data reading differential pair constituted by a pair of transistors Tr11 and Tr12 and a first data holding differential pair constituted by a pair of transistors Tr13 and Tr14. The circuit includes an upper stage circuit, a first current switch circuit including a first current switch differential pair constituted by a pair of transistors Tr15 and Tr16, and a first current source Is11, and an emitter follower. Furthermore, the first upper circuit includes load resistors R11 and R12.

  The positive phase (complementary phase) data terminals DT / DC are respectively connected to the base terminals of the transistors Tr11 and Tr12 constituting the first data reading differential pair of the master latch circuit. The positive phase (complementary phase) clock terminal CT / CC is connected to the base terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch of the master latch circuit. The common point on the emitter terminal side of the transistors Tr15 and Tr16 is connected to the current source Is11. The transistors Tr15 and Tr16 and the current source Is11 function as a current switch that uses a clock signal as a control signal.

  When the positive phase (complementary phase) clock terminal CT is at a high level and the positive phase (complementary phase) clock terminal CC is at a low level, the transistor Tr15 is turned on and the transistor Tr16 is turned off. Then, currents from the transistors Tr11 and Tr12 flow to the current source Is11 as a drive current, and the master latch circuit reads data input from the positive phase (complementary phase) data terminal DT / DC. Next, when the positive phase (complementary phase) clock terminal CT is at the low level and the positive phase (complementary phase) clock terminal CC is at the high level, the transistor Tr15 is turned off and the transistor Tr16 is turned on. Then, currents from the transistors Tr13 and Tr14 flow to the current source Is11 as a drive current, and the master latch circuit holds data. The emitter follower is a circuit that performs impedance conversion when outputting data held by the master latch circuit to the slave latch circuit, and functions as a buffer amplifier (buffer) that outputs the emitter terminals of the transistors Tr17 and Tr18. The emitter terminal of the transistor Tr17 and the current source 12 are connected, and the emitter terminal of the transistor Tr18 and the current source 13 are connected.

  On the other hand, the slave latch circuit includes a second data reading differential pair constituted by a pair of transistors Tr21 and Tr22 and a second data holding differential pair constituted by a pair of transistors Tr23 and Tr24. A second upper stage circuit; a second current switch circuit including a second current switch differential pair constituted by a pair of transistors Tr25 and Tr26; and a second current source Is21; and an emitter follower. Yes. Further, the second upper circuit includes load resistors R21 and R22. The data held and output by the master latch circuit is respectively input to the base terminals of the transistors Tr21 and Tr22 constituting the second data reading differential pair of the slave latch circuit. The positive phase (complementary phase) clock terminal CT / CC is connected to the base terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch of the slave latch circuit. The common point on the emitter terminal side of the transistors Tr25 and Tr26 is connected to the current source Is21, and the transistors Tr25 and Tr26 and the current source Is21 function as a current switch using a clock signal as a control signal.

  When the positive phase (complementary phase) clock terminal CT is at the low level and the positive phase (complementary phase) clock terminal CC is at the high level, the transistor Tr25 is turned on and the transistor Tr26 is turned off. Then, currents from the transistors Tr21 and Tr22 flow to the current source Is21 as drive current, and the slave latch circuit reads data held and output by the master latch circuit. Next, when the positive phase (complementary phase) clock terminal CT is at a high level and the positive phase (complementary phase) clock terminal CC is at a low level, the transistor Tr25 is turned off and the transistor Tr26 is turned on. Then, currents from the transistors Tr23 and Tr24 flow to the current source Is21 as drive current, and the slave latch circuit holds data.

  The emitter follower is a circuit that performs impedance conversion when outputting data held by the slave latch circuit, and is a buffer amplifier that uses the emitter terminal side of the transistors Tr27 and Tr28 as the positive phase (complementary phase) output terminals QT / QC, respectively. Function as a buffer). The emitter terminal of the transistor Tr27 and the current source 22 are connected, and the emitter terminal of the transistor Tr28 and the current source 23 are connected. In this way, the flip-flop circuit according to the first embodiment temporarily holds the data input from the positive phase (complementary phase) input terminal DT / DC according to the clock signal, and the positive phase (complementary phase) (complementary phase). Phase) The operation of outputting from the output terminal QT / QC is repeated.

  Next, the effect of suppressing deterioration in data output waveform quality in the flip-flop circuit according to the first embodiment will be described with reference to FIG. As in the prior art, in the flip-flop circuit according to the first embodiment, the master latch circuit and slave latch circuit switch the first and second current switch circuits using the clock signal as a control signal. Since switching of the second current switch circuit requires a finite time, the master latch circuit and the slave latch circuit have a transient state from the data reading state to the data holding state and a transient state from the data holding state to the data reading state. And exist. For this reason, as shown in FIG. 4, clock noise occurs in the transient state.

  Here, the deterioration of the data output waveform quality in the conventional flip-flop circuit was caused by the clock noise generated in the transient state from the data reading state to the data holding state and in the transient state from the data holding state to the data reading state. . Specifically, taking the clock noise generated in the transition state from the data reading state to the data holding state in the slave latch circuit as an example, in the data reading state, the positive phase (complementary phase) output terminal QT is set to the high level, the positive level. When the phase (complementary phase) output terminal QC is set to the Low level, the transistor Tr22 is switched from On to Off and the transistor Tr24 is switched from Off to On as the slave latch circuit transitions from the data reading state to the data holding state. However, since it takes time to charge the capacitance between the base and the collector of the transistor Tr24, the speed at which the transistor Tr24 switches from Off to On is lower than the speed at which the transistor Tr22 switches from On to Off. The current flowing through the load resistor R22 has decreased. That is, the potential at the collector terminal of the transistor Tr24 has increased. As a result, clock noise such as a clock leaking into the positive phase (complementary phase) output terminal QC has occurred.

  On the other hand, in the data reading state, when the positive phase (complementary phase) output terminal QT is set to the low level and the positive phase (complementary phase) output terminal QC is set to the high level, compared with the speed at which the transistor Tr21 is switched from On to Off. The speed at which the transistor Tr23 switches from Off to On becomes low, and the current flowing through the load resistor R21 decreases due to the above speed difference. That is, the potential of the collector terminal of the transistor Tr23 has increased. As a result, clock noise such as a clock leaking into the positive phase (complementary phase) output terminal QT has occurred. Similarly, even in a transient state in which the slave latch circuit transitions from the data holding state to the data reading state, clock noise that leaks the clock occurs. As a result, the data output waveform quality has deteriorated due to the clock noise.

  Therefore, the slave latch circuit of the flip-flop circuit according to the first embodiment further has means for reducing the switching speed of the second current switch circuit. Specifically, the above means are resistors R25 and R26 provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Resistors R25 and R26 reduce the switching speed of the second current switch circuit. Then, in the transient state in which the slave latch circuit transitions from the data reading state to the data holding state, the decrease per unit time of the current flowing through the second data reading differential pair (Tr21, Tr22) is also reduced. It is possible to suppress a decrease in current flowing through the load resistors R21 and R22 that occurs until the second data holding differential pair (Tr23, Tr24) operates. Further, the same can be suppressed even in a transient state in which the slave latch circuit transits from the data holding state to the data reading state. Therefore, it is possible to suppress clock noise such that a clock leaks into the positive phase (complementary phase) output terminals QT / QC, and it is possible to suppress deterioration in data output waveform quality.

  FIG. 4 is a diagram illustrating an output waveform of the flip-flop according to the first embodiment. FIG. 4 shows a simulation result of the data output waveform at the time of 40 Gbps operation in the flip-flop circuit having the configuration shown in FIG. Note that SPICE, which is a general-purpose circuit simulator, was used for the simulation. As shown in FIG. 4, the low level clock noise is 140 mVpp, and the high level clock noise is 50 mVpp. From this, it can be seen that the low-level clock noise is improved by 110 mV and the high-level clock noise is improved by 30 mV compared to the conventional flip-flop circuit.

  As described above, according to the semiconductor device having the flip-flop circuit according to the first embodiment of the present invention, the slave latch circuit has means for reducing the switching speed of the second current switch circuit. The means is resistors R25 and R26 provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Thereby, deterioration of the data output waveform quality can be suppressed.

(Second Embodiment)
Next, the semiconductor device having the flip-flop circuit according to the second embodiment will be described with reference to FIGS. 5 to 6, focusing on the differences from the semiconductor device having the flip-flop circuit according to the first embodiment. explain. In the flip-flop circuit according to the second embodiment, the same reference numerals are given to the same structures as those of the flip-flop circuit according to the first embodiment, and the description thereof is omitted. FIG. 5 is a diagram showing a second embodiment of the present invention. As shown in FIG. 5, the flip-flop circuit according to the second embodiment is almost the same as the flip-flop circuit according to the first embodiment.

  The flip-flop circuit according to the second embodiment is different from the flip-flop circuit according to the first embodiment in that the means for reducing the switching speed of the second current switch circuit is different. Specifically, in the first embodiment, the means for reducing the switching speed of the second current switch circuit is provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Resistances R25 and R26. However, in the second embodiment, the means includes the resistors R211 and R221 provided at the emitter terminals of the transistors Tr21 and Tr22 constituting the second differential pair for reading data and the second data holding function. The resistors R23 and R24 are provided at the emitter terminals of the transistors Tr23 and Tr24 constituting the differential pair.

  A resistor R211 is provided at the emitter terminal of the transistor Tr21, a resistor R221 is provided at the emitter terminal of the transistor Tr22, a resistor R23 is provided at the emitter terminal of the transistor Tr23, and a resistor R24 is provided at the emitter terminal of the transistor Tr24. The load driven by the switch circuit is shown greatly. As the load increases, the switching speed of the second current switch circuit decreases. From this, for the same reason as in the first embodiment, in the slave latch circuit, it is possible to suppress the clock noise generated in the transient state from the data holding state to the data reading state and in the transient state from the data reading state to the data holding state. . Therefore, deterioration of the data output waveform quality can be suppressed.

  FIG. 6 is a diagram illustrating an output waveform of the flip-flop according to the second embodiment. FIG. 6 shows a simulation result of the data output waveform at the time of 40 Gbps operation in the flip-flop circuit having the configuration shown in FIG. Note that SPICE was also used in the simulation. As shown in FIG. 6, the low level clock noise is 130 mVpp, and the high level clock noise is 50 mVpp. From this, it can be seen that the low-level clock noise is improved by 120 mV and the high-level clock noise is improved by 30 mV compared to the conventional flip-flop circuit.

  As described above, according to the semiconductor device having the flip-flop circuit according to the second embodiment of the present invention, the means for reducing the switching speed of the second current switch circuit is the second differential pair for reading data. Are resistors R211, R221 provided at the emitter terminals of the transistors Tr21, Tr22 and resistors R23, R24 provided at the emitter terminals of the transistors Tr23, Tr24 constituting the second data holding differential pair. Even in this case, it is possible to suppress the deterioration of the data output waveform quality.

(Third embodiment)
Next, a semiconductor device having a flip-flop circuit according to the third embodiment will be described with reference to FIGS. 7 to 8 focusing on differences from the semiconductor device having the flip-flop circuit according to the first embodiment. explain. Further, in the flip-flop circuit according to the third embodiment, the same structure as that of the flip-flop circuit according to the first embodiment is denoted by the same reference numeral, and the description thereof is omitted. FIG. 7 is a diagram showing a third embodiment of the present invention. As shown in FIG. 7, the flip-flop circuit according to the third embodiment is almost the same as the flip-flop circuit according to the first embodiment.

  The flip-flop circuit according to the third embodiment is different from the flip-flop circuit according to the first embodiment in that the means for reducing the switching speed of the second current switch circuit is different. Specifically, in the first embodiment, the means for reducing the switching speed of the second current switch circuit is provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Resistances R25 and R26. However, in the third embodiment, this means includes resistors R25 and R26 provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch, and the second data reading-in device. Resistors R211 and R221 provided at the emitter terminals of the transistors Tr21 and Tr22 constituting the differential pair and resistors R23 and R24 provided at the emitter terminals of the transistors Tr23 and Tr24 constituting the second data holding differential pair It is.

  That is, in the flip-flop circuit according to the third embodiment, the means for reducing the switching speed of the second current switch circuit in the second embodiment is replaced with the flip-flop circuit according to the first embodiment. It has an added configuration. For the same reason as in the first and second embodiments, the switching speed of the second current switch circuit decreases. Thus, in the slave latch circuit, it is possible to suppress clock noise that occurs in the transition state from the data holding state to the data reading state and in the transition state from the data reading state to the data holding state. Therefore, deterioration of the data output waveform quality can be suppressed.

  FIG. 8 is a diagram illustrating an output waveform of the flip-flop according to the third embodiment. FIG. 8 shows a simulation result of the data output waveform at the time of 40 Gbps operation in the flip-flop circuit having the configuration shown in FIG. Note that SPICE was also used in the simulation. As shown in FIG. 8, the clock noise at the low level is 120 mVpp, and the clock noise at the high level is 40 mVpp. From this, it can be seen that the low-level clock noise is improved by 130 mV and the high-level clock noise is improved by 40 mV compared to the conventional flip-flop circuit. Compared with the first embodiment and the second embodiment, the low-level clock noise and the high-level clock noise are improved.

  As described above, according to the semiconductor device having the flip-flop circuit according to the third embodiment of the present invention, the means for reducing the switching speed of the second current switch circuit is the differential pair for the second current switch. Resistors R25, R26 provided at the emitter terminals of the transistors Tr25, Tr26 constituting the transistor R2, resistors R211, R221 provided at the emitter terminals of the transistors Tr21, Tr22 constituting the second differential pair for reading data and the second Are resistors R23 and R24 provided at the emitter terminals of the transistors Tr23 and Tr24 constituting the differential pair for holding data. Thereby, deterioration of the data output waveform quality can be further suppressed.

(Fourth embodiment)
Next, a semiconductor device having a flip-flop circuit according to the fourth embodiment will be described with reference to FIGS. 9 to 10, focusing on differences from the semiconductor device having a flip-flop circuit according to the first embodiment. explain. Further, in the flip-flop circuit according to the fourth embodiment, the same reference numerals are given to the same structures as those of the flip-flop circuit according to the first embodiment, and the description thereof is omitted. FIG. 9 is a diagram showing a fourth embodiment of the present invention. As shown in FIG. 9, the flip-flop circuit according to the fourth embodiment is almost the same as the flip-flop circuit according to the first embodiment. The flip-flop circuit according to the fourth embodiment differs from the flip-flop circuit according to the first embodiment in that the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch have resistances. R15 and R16 are provided.

  Hereinafter, the reason why the resistors R15 and R16 are provided at the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch in the flip-flop circuit according to the fourth embodiment will be described. In the conventional flip-flop circuit, clock noise is generated in the slave latch circuit as if the clock leaked into the transient state from the data holding state to the data reading state and the transition state from the data reading state to the data holding state. It was. Due to the clock noise, the data output waveform quality was deteriorated. Therefore, in the flip-flop circuit according to the first embodiment, in order to suppress the clock noise and the deterioration of the data output waveform quality, the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Resistors R25 and R26 are provided at the emitter terminal. However, also in the master latch circuit, the same clock leakage as in the slave latch circuit occurs in the transition state from the data holding state to the data reading state and in the transition state from the data reading state to the data holding state. Due to the leakage of the clock, the waveform of data output from the master latch circuit to the slave latch circuit deteriorates.

  Therefore, in the flip-flop circuit according to the fourth embodiment, the resistors R15 and R16 are provided at the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch, whereby the first current switch The circuit switching speed is reduced. Then, similarly to the slave latch circuit, the current per unit time decreases in the current flowing through the first data reading differential pair (Tr11, Tr12) in the transition state in which the master latch circuit transitions from the data reading state to the data holding state. Therefore, the decrease in the current flowing through the load resistors R11 and R12, which occurs until the first data holding differential pair (Tr13 and Tr14) operates, can be suppressed. Further, it can be similarly suppressed in a transient state in which the master latch circuit transits from the data holding state to the data reading state. Therefore, the same clock leakage as that of the slave latch circuit can be suppressed, and data with relatively good waveform quality can be output from the master latch circuit to the slave latch circuit.

  Furthermore, in the flip-flop circuit according to the fourth embodiment, as in the first embodiment, resistors R25 and R26 are connected to the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Therefore, for the same reason as in the first embodiment, in the slave latch circuit, the clock generated in the transition state from the data holding state to the data reading state and in the transition state from the data reading state to the data holding state Noise can be suppressed. Therefore, deterioration of the data output waveform quality can be suppressed.

  It should be noted that resistors are connected to the emitter terminals of the transistors Tr11 and Tr12 constituting the first data reading differential pair and the emitter terminals of the transistors Tr13 and Tr14 constituting the first data holding differential pair of the master latch circuit. There is a reason not to have established. When resistors are provided in the first differential pair for reading data (Tr11, Tr12) and the first differential pair for holding data (Tr13, Tr14) of the master latch circuit, the gain of the differential pair decreases, and the flip-flop There is a problem that the input sensitivity characteristic of the circuit is deteriorated. Therefore, in order to suppress clock leakage similar to that of the slave latch circuit in the master latch circuit and to output relatively good waveform quality data from the master latch circuit to the slave latch circuit without deteriorating the input sensitivity characteristic, the first latch Resistors R15 and R16 are provided only at the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the current switch.

  FIG. 10 is a diagram illustrating an output waveform of the flip-flop according to the fourth embodiment. FIG. 10 shows a simulation result of the data output waveform at the time of 40 Gbps operation in the flip-flop circuit having the configuration shown in FIG. Note that SPICE was also used in the simulation. As shown in FIG. 10, the low level clock noise is 120 mVpp, and the high level clock noise is 40 mVpp. From this, it can be seen that the low-level clock noise is improved by 130 mV and the high-level clock noise is improved by 40 mV compared to the conventional flip-flop circuit. Compared with the first embodiment and the second embodiment, the low-level clock noise and the high-level clock noise are improved.

  As described above, according to the semiconductor device having the flip-flop circuit according to the fourth embodiment of the present invention, the resistors R25 and R26 are connected to the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Therefore, the same effect as that of the first embodiment can be obtained. Further, since the resistors R15 and R16 are provided at the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch, the input sensitivity characteristic is not deteriorated, and the same as the slave latch circuit in the master latch circuit. Thus, data with relatively good waveform quality can be output from the master latch circuit to the slave latch circuit. From this, it is possible to further suppress the deterioration of the data output waveform quality.

(Fifth embodiment)
Next, a semiconductor device having a flip-flop circuit according to the fifth embodiment will be described with reference to FIGS. 11 to 12, focusing on differences from the semiconductor device having a flip-flop circuit according to the fourth embodiment. explain. Also, in the flip-flop circuit according to the fifth embodiment, the same structure as that of the flip-flop circuit according to the fourth embodiment is denoted by the same reference numeral, and description thereof is omitted. FIG. 11 is a diagram showing a fifth embodiment of the present invention. As shown in FIG. 11, the flip-flop circuit according to the fifth embodiment is almost the same as the flip-flop circuit according to the fourth embodiment.

  The flip-flop circuit according to the fifth embodiment is different from the flip-flop circuit according to the fourth embodiment in that the means for reducing the switching speed of the second current switch circuit is different. Specifically, in the fourth embodiment, means for reducing the switching speed of the second current switch circuit is provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch. Resistances R25 and R26. However, in the fifth embodiment, this means includes resistors R25 and R26 provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch, and the second data reading Resistors R211 and R221 provided at the emitter terminals of the transistors Tr21 and Tr22 constituting the differential pair and resistors R23 and R24 provided at the emitter terminals of the transistors Tr23 and Tr24 constituting the second data holding differential pair It is.

  That is, in the flip-flop circuit according to the fifth embodiment, the means for reducing the switching speed of the second current switch circuit in the second embodiment is replaced with the flip-flop circuit according to the fourth embodiment. It has an added configuration. Alternatively, the resistors R15 and R16 in the fourth embodiment are added to the emitter terminals of the transistors Tr15 and Tr16 forming the differential pair for the first current switch in the flip-flop circuit according to the third embodiment. It has a configuration. For the same reason as in the first and second embodiments, the switching speed of the second current switch circuit decreases. Thus, in the slave latch circuit, it is possible to suppress clock noise that occurs in the transition state from the data holding state to the data reading state and in the transition state from the data reading state to the data holding state. Therefore, deterioration of the data output waveform quality can be suppressed.

  Further, in the flip-flop circuit according to the fifth embodiment, as in the fourth embodiment, resistors R15 and R16 are connected to the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch. Therefore, the switching speed of the first current switch circuit is reduced for the same reason as in the fourth embodiment. In the master latch circuit, the same clock frequency as that of the slave latch circuit, which occurs in the transient state from the data holding state to the data reading state and in the transient state from the data reading state to the data holding state, is obtained without degrading the input sensitivity characteristic. Leakage can be suppressed. Therefore, data with relatively good waveform quality can be output from the master latch circuit to the slave latch circuit. From this, it is possible to further suppress the deterioration of the data output waveform quality.

  FIG. 12 is a diagram illustrating an output waveform of the flip-flop according to the fifth embodiment. FIG. 12 shows a simulation result of the data output waveform at the time of 40 Gbps operation in the flip-flop circuit having the configuration shown in FIG. Note that SPICE was also used in the simulation. As shown in FIG. 12, the low level clock noise is 110 mVpp, and the high level clock noise is 40 mVpp. From this, it can be seen that the low-level clock noise is improved by 140 mV and the high-level clock noise is improved by 40 mV compared to the conventional flip-flop circuit. Compared with the fourth embodiment, low level clock noise is improved.

  As described above, according to the semiconductor device having the flip-flop circuit according to the fifth embodiment of the present invention, the resistors R15 and R16 are connected to the emitter terminals of the transistors Tr15 and Tr16 constituting the first current switch differential pair. Therefore, the same effect as in the fourth embodiment can be obtained. The means for reducing the switching speed of the second current switch circuit includes resistors R25 and R26 provided at the emitter terminals of the transistors Tr25 and Tr26 constituting the differential pair for the second current switch, and second data. Resistors R211 and R221 provided at the emitter terminals of the transistors Tr21 and Tr22 constituting the differential pair for reading and resistors provided at the emitter terminals of the transistors Tr23 and Tr24 constituting the second differential pair for holding data R23 and R24. Thereby, deterioration of the data output waveform quality can be further suppressed.

  The embodiment described above is an example of the implementation of the present invention, and the scope of the present invention is not limited to these. Various other implementations are within the scope described in the claims. It is applicable to the form. For example, the semiconductor device according to the first to fifth embodiments has the flip-flop circuit according to the first to fifth embodiments, but the same effect can be obtained even if other circuits are included. You can get it.

  Further, a circuit in which resistors R15 and R16 are provided at the emitter terminals of the transistors Tr15 and Tr16 constituting the differential pair for the first current switch in the flip-flop circuit according to the first embodiment will be described with reference to the fourth embodiment. A circuit in which resistors R15 and R16 are provided at the emitter terminals of the transistors Tr15 and Tr16 constituting the first current switch differential pair in the flip-flop circuit according to the third embodiment. Although the flip-flop circuit according to the fifth embodiment is used, the present invention is not particularly limited to this, and a differential pair for the first current switch in the flip-flop circuit according to the second embodiment is configured. Resistors R15 and R16 may be provided at the emitter terminals of the transistors Tr15 and Tr16.

  Further, the flip-flop circuit included in the semiconductor device according to the first to fifth embodiments is a circuit for 40 Gbps operation, but is not particularly limited to this, and the same applies to a circuit for operation of 40 Gbps or more. The effect of can be acquired. This is particularly effective in a circuit for operation at 40 Gbps or more and 100 Gbps or less.

It is a figure which shows the circuit structure of the conventional flip-flop. It is a figure which shows the output waveform of the conventional flip-flop. It is a figure which shows the 1st Embodiment of this invention. It is a figure which shows the output waveform of the flip-flop of 1st Embodiment. It is a figure which shows the 2nd Embodiment of this invention. It is a figure which shows the output waveform of the flip-flop of 2nd Embodiment. It is a figure which shows the 3rd Embodiment of this invention. It is a figure which shows the output waveform of the flip-flop in 3rd Embodiment. It is a figure which shows the 4th Embodiment of this invention. It is a figure which shows the output waveform of the flip-flop in 4th Embodiment. It is a figure which shows the 5th Embodiment of this invention. It is a figure which shows the output waveform of the flip-flop in 5th Embodiment.

Explanation of symbols

Tr11, Tr12, Tr13, Tr14, Tr15, Tr16, Tr17, Tr18, Tr21, Tr22, Tr23, Tr24, Tr25, Tr26, Tr27, Tr28 transistors,
Is11, Is12, Is13, Is21, Is22, Is23 current sources,
R11, R12, R21, R22 load resistance,
R15, R16, R23, R24, R25, R26, R211, R221 resistance,
DT, DC positive phase (complementary phase) data terminal,
CT, CC positive phase (complementary phase) clock terminal,
QT, QC Positive phase (complementary phase) output terminal,

Claims (6)

A first upper circuit including a first data reading differential pair constituted by a pair of transistors and a first data holding differential pair constituted by a pair of transistors, and a pair of transistors. A master latch circuit comprising: a first current switch circuit including a differential pair for the first current switch and a first current source;
A second upper stage circuit including a second data reading differential pair constituted by a pair of transistors and a second data holding differential pair constituted by a pair of transistors; and a pair of transistors. A flip-flop circuit having a slave latch circuit including a differential pair for the second current switch and a second current switch circuit including a second current source,
The flip-flop circuit, wherein the slave latch circuit has means for reducing a switching speed of the second current switch circuit.   The means for reducing the switching speed of the second current switch circuit is a resistor provided at the emitter terminals of both transistors constituting the differential pair for the second current switch. The flip-flop circuit according to claim 1.   The means for reducing the switching speed of the second current switch circuit includes a resistor provided at emitter terminals of both transistors constituting the second differential pair for reading data and the second 3. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is a resistor provided at emitter terminals of both transistors constituting the differential pair for holding data.   4. The flip-flop circuit according to claim 2, wherein a resistor is provided at an emitter terminal of both transistors constituting the differential pair for the first current switch.   5. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is an operation circuit at 40 Gbps or more and 100 Gbps or less.   A semiconductor device including the flip-flop circuit according to claim 1.

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