JP2009230475A - Storage system including nonvolatile semiconductor storage section - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restore data by correcting errors periodically by performing refresh within a predetermined period of time, and to perform emergency refresh so that a fatal failure may not occur while an application program is being executed. <P>SOLUTION: A storage system including a nonvolatile semiconductor storage section comprises: an information storage section having a storage area composed of a group of nonvolatile memory cells in which data can be rewritten; an error detection and correction circuit for detecting an error of data read out from the storage area of the information storage section, and correcting the error and outputting the corrected data; a counter of the number of errors for counting the number of the detected errors of data; a readout frequency counter for counting the number of readouts of data from the information storage section; and a refresh control means for correcting data and rewriting the data according to the number of errors of the data read out, and resetting the counted value of the counter of the number of errors of data, and the counted value of the readout frequency counter. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an improvement in a storage system including an electrically rewritable nonvolatile semiconductor memory unit, and more particularly, to provide a nonvolatile semiconductor memory unit having a stored data refresh function to improve the reliability of stored data. It relates to a storage system including.

  As an electrically rewritable nonvolatile semiconductor memory device, a NAND type EEPROM (Electrically Erasable PROM) capable of high integration is known. Conventional nonvolatile semiconductor memory devices are provided with an error detection / correction circuit (abbreviated as ECC) in order to achieve high reliability of stored data, and data read from the memory is error-corrected by ECC. .

  Next, the configuration of the NAND type EEPROM will be described. Data writing and reading are performed for each memory cell having a common word line. This unit is called a page. Data is erased for each memory cell transistor sharing all word lines between the two select gates on the drain side and the source side. This unit is called a block unit.

  In FIG. 8, the state in which an error bit appears in the data held by all the memories when the data of the memory cell at a specific address continues to be read is schematically represented by a graph of the number of read times versus the number of error bits generated. ing. From this figure, it can be seen that if these data are read out while the number of errors that can be corrected is small, it is possible to restore the original correct data by ECC. However, it can also be seen that when only a specific address is accessed, an error by ECC becomes impossible.

  In the conventional nonvolatile semiconductor memory device, the data read from the memory (the above-mentioned page unit) is the data of the memory cell of the page that is not read in the same block, although error correction is performed by ECC. However, there is a problem that errors are accumulated and correction by ECC becomes impossible.

  Therefore, in the storage system including the nonvolatile semiconductor memory unit described in Patent Document 1, rewriting (refreshing) all data or partial data written in the nonvolatile semiconductor memory unit when the ECC correction is effective. Therefore, even when an error due to reading of other data has occurred in the memory cell that holds the data that has not been read, the data is corrected and re-recorded.

Japanese Patent No. 3176019

  However, in the storage system including the non-volatile semiconductor storage unit described in Patent Document 1, as long as the refresh condition is satisfied with respect to the timing of refresh, a method of performing refresh immediately and a method of performing batch refresh periodically Is described.

  When the target of the storage system including the non-volatile semiconductor storage unit is an application program such as an amusement-related role play game, the former refresh method irregularly with respect to the storage system including the non-volatile semiconductor storage unit. This will cause weight to enter and hinder smooth game progress.

  Further, in the latter refresh method, since the refresh is performed collectively, the wait time becomes long. In the case of business application programs, this work is done before business hours, but it may not finish in time, resulting in delays in business start-up, a factor that motivates customers and lowers customer satisfaction become.

  As described above, both refresh methods have a great possibility of causing a fatal failure for an application program that continues to operate for a certain period of time.

  Therefore, the present invention not only restores data errors periodically by performing refresh within a predetermined time, but also minimizes data that must be restored during application program execution. An object of the present invention is to provide a storage system including a non-volatile semiconductor storage unit that can cope with limited emergency refresh.

  A storage system including a nonvolatile semiconductor storage unit according to the present invention includes an information storage unit having a storage area composed of a group of nonvolatile memory cells to which data can be rewritten, and an error in data read from the storage area of the information storage unit. An error detection and correction circuit that detects and corrects and outputs an error; an error number counter that counts errors in the detected data; a read count counter that counts data read from the information storage unit; and A nonvolatile semiconductor memory unit is provided that corrects and rewrites data in accordance with the number of errors, and further includes refresh control means for resetting the count value of the data error count counter and the count value of the read count counter In the storage system, the refresh control means performs error detection by an error number counter before the data in the information storage unit is executed. Even when the error detection circuit corrects the data whose numerical value is the error reference value in the error detection / correction circuit and the data in the information storage unit is being executed, the error count value of the error counter is an error. And a second mode in which data reaching the restoration limit value is corrected by the error detection and correction circuit before exceeding the error restoration limit value.

According to the present invention, it is possible to perform data error restoration in advance for an application program stored in a storage system including a nonvolatile semiconductor storage unit by performing refresh that periodically restores data errors. Play.
In addition, according to the present invention, since an error recovery of data can be executed while an application program stored in a storage system including a nonvolatile semiconductor storage unit is being executed, a fatal failure for the application program can be avoided. There is an effect.

  The best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

  As shown in FIG. 1, a storage system 20 including a nonvolatile semiconductor storage unit according to an embodiment of the present invention includes a memory body 1 and a controller 10 that controls the memory body 1. The memory body 1 includes a control circuit 2, a memory cell array 3, a data input / output 4, a command input buffer 5, and an address input buffer 6. The controller 10 includes a central processing unit (hereinafter abbreviated as CPU) 11, an ECC 12, a buffer memory 13, and a timer 14.

  The control circuit 2 receives the address of the target block from the address input buffer 6, receives various commands from the command input buffer 5, reads data into the memory cell array 3 and the data input / output buffer 4, and performs writing.

  The memory cell array 3 is a NAND type EEPROM and has the above-described configuration. The data input / output buffer 4 is a buffer that temporarily holds input / output data. The command input buffer 5 is a buffer that temporarily holds commands given to the memory. The address input buffer 6 is a buffer that temporarily holds an address signal.

  The CPU 11 has a function of receiving an instruction from the host side CPU and controlling the EEPROM for data processing. The ECC 12 performs error check and error correction on the read data. The buffer memory 13 is a buffer memory provided between the main memory and the nonvolatile memory of the CPU 11.

  2 to 7 are flowcharts for explaining the operation of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  FIG. 2 is a main flowchart showing the operation of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  As shown in FIG. 2, when the power is turned on, the CPU 11 reads the refresh table backup from the memory cell array 3 and stores it in the refresh table of the buffer memory 13 (step S201). The update of the refresh table will be described later.

  Next, the CPU 11 determines whether or not there is a refresh command from a host CPU (not shown) (step S202). If there is a refresh command, the process proceeds to step S203 to perform refresh command processing. The refresh command process will be described with reference to the flowchart of the refresh command process in FIG. If there is no refresh command, the process proceeds to step S204.

  In step S204, the CPU 11 determines whether or not there is a read command from a host CPU (not shown) (step S204). From here, data stored in the nonvolatile storage unit, for example, an amusement-related application program is executed. If there is a read command, the process advances to step S205 to perform read command processing. The read command process will be described with reference to the flowchart of the read command process in FIG. If there is no read command, the process proceeds to step S206.

  In step S206, it is determined whether the CPU 11 has received a power-off command from a host CPU (not shown). If a power-off instruction is received, the power is turned off and the process is terminated. If no power-off command has been received, the process returns to step S202, and the flow so far is executed.

  FIG. 3 is a flowchart of the refresh command processing of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  As illustrated in FIG. 3, the CPU 11 reads the refresh table in the buffer memory 13, specifies a target block to be refreshed, and stores the number of refresh target blocks in a register (not illustrated) in the CPU 11. Here, the priority for refreshing is also determined (step S301). As for the priority order, the one with the refresh command processing flag set is given the highest priority, and the next priority is given that the read count exceeds a certain threshold. The refresh command processing flag shown here will be described with reference to a flowchart (FIG. 6) of the immediate refresh processing described later. Further, the number of these refresh target blocks is within the number of refresh allowable blocks. Note that the refresh allowable block number is set to a fixed value calculated from a time range in which refresh is allowed before the system is operated.

  Next, the CPU 11 determines whether there is a refresh target block in the refresh table (step S302). If there is a refresh target block, the process proceeds to step S303 to perform a refresh process in units of blocks. The block-unit refresh process will be described with reference to the block-unit refresh process flowchart of FIG. After performing the process of step S303, the CPU 11 subtracts 1 from the number of blocks to be refreshed stored in a register (not shown). If there is no refresh target block or there is no refresh time in the refresh table, the refresh command processing is terminated.

  FIG. 4 is a flowchart of the block unit refresh process of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  As shown in FIG. 4, the CPU 11 writes the address of the refresh target block in the address input buffer 6 (step S401). Next, the CPU 11 writes a read command into the command input buffer 5 (step S402). Here, the control circuit 2 of the memory body 1 receives the address of the refresh target block from the address input buffer 6. Then, after receiving a read command from the command input buffer 5, the control circuit 2 reads data from the memory cell array 3 and transfers it to the data input / output buffer 4.

  Next, the CPU 11 reads data from the data input / output buffer 4 via the ECC 12. The read data is corrected to error-free data by the ECC 12. The corrected data is stored in the buffer memory 13 (step S403).

  After writing the address of the block to be refreshed in the address input buffer 6, the CPU 11 writes an erase command in the command input buffer 5 (step S404). Here, the control circuit 2 executes erasing of the addressed block.

  The CPU 11 writes the address of the block to be refreshed in the address input buffer 6, writes the write command in the command input buffer 5, and then transfers the error-free data stored in the buffer memory 13 to the data acquisition buffer 4. (Step S405). Here, after receiving a write command from the command input buffer 6, the control circuit 2 writes the data written in the data input / output buffer 4 into the memory cell array 3.

  The CPU 11 clears the number of reads, the number of errors, and the refresh command target flag for the refresh target block in the refresh table in the buffer memory 13 (step S406). This completes the block unit refresh process.

  FIG. 5 is a flowchart of read command processing of a storage system including a nonvolatile storage unit according to an embodiment of the present invention.

  As shown in FIG. 5, the CPU 11 reads the number of reads of the read target block from the refresh table of the buffer memory 13 into a register (not shown) of the CPU 11 and stores it (step S501).

  The CPU 11 writes the address of the read target block in the address input buffer 6 (step S502). Here, the control circuit 2 receives the address of the read target block from the address input buffer 6.

  The CPU 11 writes a read command into the command input buffer 5 (step S503). Here, after receiving a read command from the command input buffer 5, the control circuit 2 reads data from the memory cell array 3 and transfers it to the data input / output buffer 4.

  The CPU 11 reads data from the data input / output buffer 4 via the ECC 12. The read data is corrected to error-free data by the ECC 12 (step S504).

  The CPU 11 reads the number of errors from the ECC 12, and stores the number in the error number data portion for the read target block in the refresh table in the buffer memory 13 (step S505).

  The CPU 11 stores a value obtained by incrementing the read count in step S501 by 1 in the read count data portion for the read target block in the refresh table in the buffer memory 13 (step S506).

  The CPU 11 determines whether or not the number of errors exceeds the threshold value in the error number data part in the refresh table in the buffer memory 13 (step S507). The threshold value here is a limit value (error recovery) that allows error recovery. If this system continues to operate beyond this value, the target block will not be able to be corrected by ECC.

  If the number of errors exceeds the threshold value, the process proceeds to step S508, and an immediate refresh process is performed. The immediate refresh process will be described with reference to the flowchart of the immediate refresh process in FIG. If the number of errors does not exceed the threshold value, the read command process is terminated.

  FIG. 6 is a flowchart of the immediate refresh process of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  As shown in FIG. 6, the CPU 11 reads the refresh table from the buffer memory 13 (step S601). Then, the process proceeds to step S602, where a block unit refresh process is performed (step S602).

  The CPU 11 sets a refresh command target flag in the refresh table for a block whose error count is in a certain range other than the address corresponding to the block subjected to immediate refresh (step S603). Then, the immediate refresh process ends. Here, the number of errors in a certain range used as a criterion for setting the refresh command target flag corresponds to the error criterion value. The error reference value is a value in which the number of errors is smaller than the error restoration limit value, and does not require immediate refresh processing, but is a determination reference value for performing periodic refresh processing.

  FIG. 7 is a flowchart of the refresh table backup update of the storage system including the nonvolatile storage unit according to the embodiment of the present invention.

  As shown in FIG. 7, when the power is turned on, the CPU 11 generates an interrupt for updating the refresh table backup of the memory cell array 3 based on a value preset in the timer 14 (step S701).

  The CPU 11 writes the refresh table backup address in the address input buffer 6 and writes the write command in the command input buffer 5, and then transfers the refresh table data in the buffer memory 13 to the data input / output buffer 4 (step S 702). ). Here, after receiving the write command from the command input buffer 5, the control circuit 2 writes the data written in the data input / output buffer 4 into the memory cell array 3. As a result, the data in the buffer memory 13 refresh table is overwritten on the refresh table backup in the memory cell array 3, and the data update is completed.

The block diagram of one Example of this invention. The main flowchart figure explaining this invention. The flowchart figure of the refresh command process explaining this invention. The flowchart figure of the block unit refresh process explaining this invention. The flowchart figure of the read command process explaining this invention. The flowchart figure of the immediate refresh process explaining this invention. The refresh flowchart figure of the refresh table backup explaining this invention. The graph which shows the relationship between the frequency | count of read-out and the generation | occurrence | production number of errors.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory main body 2 Control circuit 3 Memory cell array 4 Data input / output buffer 5 Command input buffer 6 Address input buffer 10 Controller 11 CPU
12 ECC
13 Buffer memory 14 Timer

Claims (1)

An information storage unit having a storage area composed of a group of nonvolatile memory cells in which data can be rewritten;
An error detection and correction circuit for detecting an error in data read from the storage area of the information storage unit and correcting and outputting the error;
An error counter that counts errors in the detected data;
A read number counter for counting data read from the information storage unit;
Refresh control means for correcting and rewriting the data in accordance with the number of errors of the read data, and further resetting the count value of the error number counter of the data and the count value of the read count counter; ,
A storage system including a non-volatile semiconductor storage unit comprising:
The refresh control means is a first mode in which the error detection and correction circuit corrects data in which the error count value by the error number counter is an error reference value before the data in the information storage unit is executed. When,
Even when the data in the information storage unit is being executed, the error detection and correction is performed before the error count value by the error number counter reaches the error recovery limit value before the error recovery limit value is exceeded. A second mode for correction in the circuit;
A storage system including a non-volatile semiconductor storage unit.

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