JP2009500871A - 歪み超格子とその上の応力層とを含む半導体デバイス、及びその製造方法 - Google Patents
歪み超格子とその上の応力層とを含む半導体デバイス、及びその製造方法 Download PDFInfo
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- JP2009500871A JP2009500871A JP2008521586A JP2008521586A JP2009500871A JP 2009500871 A JP2009500871 A JP 2009500871A JP 2008521586 A JP2008521586 A JP 2008521586A JP 2008521586 A JP2008521586 A JP 2008521586A JP 2009500871 A JP2009500871 A JP 2009500871A
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
- H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69994905P | 2005-07-15 | 2005-07-15 | |
| US11/457,293 US20070020860A1 (en) | 2003-06-26 | 2006-07-13 | Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods |
| US11/457,286 US7598515B2 (en) | 2003-06-26 | 2006-07-13 | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
| PCT/US2006/027120 WO2007011628A1 (fr) | 2005-07-15 | 2006-07-14 | Dispositif à semi-conducteur comprenant une couche à hétérostructure contrainte sous une couche de contrainte et procédés associés |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2009500871A true JP2009500871A (ja) | 2009-01-08 |
Family
ID=37057155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008521586A Pending JP2009500871A (ja) | 2005-07-15 | 2006-07-14 | 歪み超格子とその上の応力層とを含む半導体デバイス、及びその製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1905091A1 (fr) |
| JP (1) | JP2009500871A (fr) |
| AU (1) | AU2006270324A1 (fr) |
| CA (1) | CA2612123A1 (fr) |
| TW (1) | TW200742058A (fr) |
| WO (1) | WO2007011628A1 (fr) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
| WO2005013371A2 (fr) * | 2003-06-26 | 2005-02-10 | Rj Mears, Llc | Dispositif a semi-conducteur comprenant un super-reseau a modification de bande d'energie |
| JP2005057301A (ja) * | 2000-12-08 | 2005-03-03 | Renesas Technology Corp | 半導体装置及びその製造方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| WO2005018005A1 (fr) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Dispositif a semi-conducteur comprenant un transistor mosfet pourvu d'un super-reseau concu sous forme de bande |
-
2006
- 2006-07-14 JP JP2008521586A patent/JP2009500871A/ja active Pending
- 2006-07-14 WO PCT/US2006/027120 patent/WO2007011628A1/fr active Application Filing
- 2006-07-14 CA CA002612123A patent/CA2612123A1/fr not_active Abandoned
- 2006-07-14 AU AU2006270324A patent/AU2006270324A1/en not_active Abandoned
- 2006-07-14 EP EP06787074A patent/EP1905091A1/fr not_active Withdrawn
- 2006-07-14 TW TW095125959A patent/TW200742058A/zh unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005057301A (ja) * | 2000-12-08 | 2005-03-03 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
| WO2005013371A2 (fr) * | 2003-06-26 | 2005-02-10 | Rj Mears, Llc | Dispositif a semi-conducteur comprenant un super-reseau a modification de bande d'energie |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1905091A1 (fr) | 2008-04-02 |
| TW200742058A (en) | 2007-11-01 |
| CA2612123A1 (fr) | 2007-01-25 |
| WO2007011628A1 (fr) | 2007-01-25 |
| AU2006270324A1 (en) | 2007-01-25 |
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