JP2009536784A - Method and apparatus for processing a semiconductor wafer by etching - Google Patents

Abstract

The subject of the present invention is the following steps in a prescribed order: a) a step of measuring a parameter indicating the characteristics of a semiconductor wafer depending on the position and calculating the value of this parameter depending on the position over the entire surface of the semiconductor wafer B) applying an etching medium having a viscosity of 50 mPas to 2000 mPas over this entire surface of the semiconductor wafer; c) by applying the etching medium while exposing this entire surface of the semiconductor wafer simultaneously. Etching process, in which the removal rate of the etching process depends on the light intensity at the surface of the semiconductor wafer, and the difference in parameter values depending on the position measured in step a) is then position-dependent removal Presetting the light intensity as a function of position so as to be reduced by the rate, and d) the etching medium Removing from the surface of the semiconductor wafer, a method of processing a semiconductor wafer including.
The subject of the invention is also a device for carrying out the method according to the invention.

Description

  The present invention relates to a method and apparatus for planarizing a semiconductor wafer using an etching process with locally different material removal.

Semiconductor wafers, especially single crystal silicon wafers for use in the semiconductor industry, must have high flatness, especially in view of the requirements in the manufacture of integrated circuits. According to the generally accepted Faustregel, the SFQR _max value of a semiconductor wafer should not be larger than the line width of the component to be manufactured on the semiconductor wafer. In addition, in order to be able to integrate as many circuits as possible, the required flatness must be as close as possible to the edge of the front side, with the front side being a component. Is defined as the side surface to be manufactured. This is because the flatness measurement must be performed with very little edge exclusion space (Randausschluss) and the specified flatness value is not only for so-called Full Sites, but also for partial sites. It means that the site (Partial Sites) must also be satisfied. (Full site refers to all surface elements on which a complete component can be fabricated, and partial site refers to a surface element on the wafer edge that does not have a complete component location.)
When the flatness of the semiconductor wafer is defined, SEMI standard M1-94 distinguishes between overall flatness and local flatness. The overall flatness relates to the entire wafer surface minus the edge exclusion space to be defined. It is described by and corresponds to GBIR ("global backsurface-referenced ideal plane / range" = the range of positive and negative deviations from the ideal plane relative to the backside for the entire front side of the semiconductor wafer) Is data of TTV ("total thickness variation") that has been conventionally used. Local flatness generally relates to a limited surface on the semiconductor wafer that corresponds to the surface of the component to be assembled thereon. It is expressed as SFQR (“site front surface referenced least squares / rang” = range of positive and negative deviations from the front surface defined by least square error for a surface of defined dimensions). The size of SFQR _max indicates the largest SFQR value for all component surfaces on a particular semiconductor wafer. In SFQR, it must always be shown which plane the indicated value is for, for example a 26 × 8 mm ² plane is shown by the ITRS roadmap.

Another parameter of flatness is the so-called nanotopography. This is defined as a peak-to-valley deviation (deviation between the maximum value and the minimum value) in a predetermined surface element, for example, 2 × 2 mm ² . Nanotopography is measured using a measuring device such as ADE CR 83 SQM, ADE PhaseShift Nanomapper or KLA Tencor SNT.

  The flatness in the edge region of the semiconductor wafer is decisively influenced by so-called “Edge Roll off”. "A New Method for the Precise Measurement of Wafer Roll off of Silicon Polished Wafer", Jpn.J.Appl.Phys., Vol. 38 (1999), 38-39 "includes" Wafer Roll Off "(" Wafer Roll off ") (= edge roll-off) is described. Edge roll-off can occur not only on the front side surface of the semiconductor wafer but also on the back side surface. It is evident in the SFQR values of the surface elements at the wafer edge. Edge roll-off is particularly disturbing in semiconductor wafers that are bonded (bonded) to other semiconductor wafers, for example, for producing SOI wafers, because the wafers are to be bonded together. This is because the surface edge roll-off greatly affects the bonding quality of the wafer edge portion.

  Currently, semiconductor wafers used as substrates for the manufacture of microelectronic components are generally manufactured according to the following conventional process sequence: Saegen, lapping and / or polishing, chemical wet etching, removal polishing (in English) "stock removal polishing") and finish polishing ("mirror polishing" in English). It has been found that this process sequence cannot guarantee the flatness required for the continuously decreasing line width.

  In EP798766A1, in order to improve the flatness of a semiconductor wafer, a gas phase etching process according to the PACE method ("plasma assisted chemical etching") and a polishing process between removal polishing and finish polishing are performed. Subsequent heat treatment is inserted. With the processing of silicon wafers having a diameter of 200 mm as a clue, it is found that the described process sequence will give a GBIR result of 0.2-0.3 μm. Local flatness data is not shown. Furthermore, it is not shown how large the edge exclusion space for the flatness measurement was.

A similar method is shown in EP 961314 A1, but in this case, only GBIR value of 0.14 μm and SFQR _max value of 0.07 μm at most are achieved through slicing, polishing, PACE and finish polishing. Not.

The PACE method as proposed in EP 961314 A1 results in roughness degradation in the polished wafer, which can be partially reduced by an additional hydrophobing step just before PACE. PACE must be performed in a vacuum, which makes the process complicated in terms of equipment technology. In addition, the semiconductor wafer is contaminated by the decomposition products of the gas used for etching, which makes an additional cleaning step as described in EP 1100117A2 indispensable. In addition, this process is not performed on the entire surface, but on the semiconductor wafer (Abrastern). This is very time consuming on the one hand and on the other hand not only the problem with nanotopography in the overlap region of the scan, but also the flatness (SFQR _max and edge roll) in the outer region of the semiconductor wafer from the wafer edge to a distance of about 5 mm. Off)). A possible cause is an increased suction action at the edge of the semiconductor wafer by working in vacuum and thus a reduction in the etching medium. Due to the essential overlap in scanning, the nanotopography is deteriorated, especially at the overlap position. The larger the nozzle diameter that supplies the etching medium, the more pronounced the deterioration. However, for economic reasons, the nozzle diameter cannot be chosen arbitrarily small.

Therefore, the methods known in the prior art cannot meet the shape requirements for components having a line width of 65 nm or less, ie a maximum SFQR _max value of 65 nm. At that time, the most serious problem occurs in the edge region of the semiconductor wafer. This is because the edge exclusion space of 3 mm (at 90 nm line width) is reduced to 2 mm or 1 mm or less at the future line width of 65 nm, and a partial site is included in the evaluation of flatness. .

  Additional problems arise in so-called SOI wafer cases. These semiconductor wafers have a semiconductor layer present on the surface of a carrier wafer (Traegerscheibe) ("base wafer" or "handle wafer" in English). The thickness of the semiconductor layer varies depending on the component to be processed. A distinction is generally made between so-called “thin layers” (thickness less than 100 nm) and so-called “thick layers” (from 100 nm to about 80 μm). The carrier wafer is composed of a completely electrically insulating material (eg glass, quartz, sapphire) or it is advantageously composed of a semiconductor material, for example, preferably from silicon, and is simply electrically isolated It may be either separated from the semiconductor layer by a conductive layer. The electrically insulating layer may be made of, for example, silicon oxide.

  The semiconductor layer of the SOI wafer must have a very uniform thickness up to the outermost edge region. Especially in the case of a semiconductor layer having a thickness of 100 nm or less, the transistor characteristics, for example the threshold voltage, vary very strongly in the case of a non-uniform layer thickness. The absolute thickness tolerance for SOI wafers with thin and thick semiconductor layers depends on the layer thickness.

  In addition, in order to be able to integrate as many circuits as possible, the necessary layer thickness uniformity must be as close as possible to the edge of the front side. This also means that there is very little edge exclusion space.

  In the prior art, an SOI wafer post-processing method for improving the layer thickness uniformity is known. It is generally a local etching method under the scan of an SOI wafer, in which more etching removal is planned to be performed at locations where the layer thickness is relatively thick: according to US 2004/0063329 A1 In the etching method, the surface of the SOI wafer is scanned with a nozzle, and a gaseous etching medium is locally supplied through the nozzle. EP 488642 A2 and EP 511777 A1 describe a method in which the semiconductor layer of an SOI wafer is exposed to the etching medium over its entire surface. However, this etching medium must be activated locally under surface scanning (photochemical etching) by a laser beam or a light source focused by an optical system.

  All methods in which the surface of the semiconductor layer must be scanned to achieve locally different etch removal are very time consuming and thus costly. Apart from that, scanning requires consumable movement of the light source or nozzle on the one hand and the SOI wafer on the other hand.

  In addition, additional layer thickness non-uniformities occur, particularly in the edge region of the wafer, i.e. in the region of a distance of 5 mm from the wafer edge, as well as in the region where the overlap occurs during scanning. According to EP 488642 A2, a layer thickness uniformity of 10 nm is achieved with a layer thickness of 520 nm, but there is no description of the edge exclusion space. According to EP511777A1, a layer thickness uniformity of 8 nm is achieved with a layer thickness of 108 nm, but there is no description of the edge exclusion space.

  Therefore, in spite of a complicated method, the layer thickness uniformity that is essential especially in the edge region of the SOI wafer is not achieved.

  The problem underlying the present invention is therefore a semiconductor wafer with improved flatness and nanotopography (especially in the edge region) which is suitable for producing structural elements having a line width of 65 nm or less. Is to provide. In this context, the concept “semiconductor wafer” also encompasses SOI wafers. Another object is to provide SOI wafers having improved layer thickness uniformity, especially in the edge region.

The task consists of the following steps in a prescribed order:
a) measuring a parameter indicative of the characteristics of the semiconductor wafer depending on the position and calculating the value of this parameter depending on the position over the entire surface of the semiconductor wafer;
b) applying an etching medium having a viscosity of 50 mPas to 2000 mPas to this whole surface of the semiconductor wafer;
c) etching the entire surface of the semiconductor wafer by applying an etching medium while simultaneously exposing the entire surface, wherein the removal rate of the etching process depends on the light intensity at the surface of the semiconductor wafer; and A step of presetting the light intensity depending on the position so that the difference in the value of the parameter depending on the position measured in step a) is reduced by the position-dependent removal rate, and d) the etching medium This is solved by a method for processing a semiconductor wafer comprising the step of removing from the surface of the semiconductor wafer.

General description of the method:
The subject of the present invention is a method for etching a semiconductor wafer with an etching medium having a viscosity of 50 mPas to 2000 mPas. In the case of this etching method, the surface of the semiconductor wafer (semiconductor layer in the case of SOI wafer) is not processed point by point or scanned unlike the prior art. Rather, the entire surface is processed simultaneously. The locally different etch removal required for correction is achieved with locally different removal rates, which are also achieved with locally different light intensities. The local distribution of light intensity is determined by the local value of the parameter measured in advance. The parameters to be optimized in the method according to the invention are measured in step a). The resulting measurements are then used to control the local light intensity in step c).

  For example, if the uniformity of the thickness of the semiconductor layer of the SOI wafer is to be optimized, the position-dependent layer thickness is measured in step a), and in step c) a high removal rate is obtained at large layer thickness positions. The local light intensity is controlled so that a low removal rate is obtained at a position where the layer thickness is small and obtained.

  If the overall flatness (GBIR) of the semiconductor wafer is to be optimized, in step a) the deviation of the front side surface of the wafer from the ideal plane defined by the back side surface of the wafer is determined, and step c ), The local light intensity is controlled so that a high removal rate can be obtained at the local convex portions and a low removal rate can be obtained at the local concave portions.

If, on the other hand, the local flatness (SFQR) of the semiconductor wafer is to be optimized, in step a) the wafer from an ideal plane, for example of size 26 × 8 mm ² , with reference to a certain measurement window. The deviation of the front side surface is determined and in step c) the local light intensity is controlled so that a high removal rate is obtained at the local convex part and a low removal rate is obtained at the local concave part. The

  Using the measurement in step a) as a clue, the indispensable etching removal amount is determined at each point on the surface of the semiconductor wafer. From the removal rate depending on the light intensity achieved by the etching medium used in the corresponding semiconductor material, not only the duration required for the etching process in step c) but also at each point on the surface of the semiconductor wafer. The light intensity to be calculated can also be determined by calculation.

  The present invention utilizes the relationship between the removal rate of a particular etching reaction and the charge carrier concentration in the semiconductor material, which can also be influenced by the intensity of the irradiated light. This will be specifically described below using silicon as an example. However, the present invention is applicable to other semiconductor materials.

Silicon etching always consists of a two-step reaction: silicon is oxidized in the first step, becoming silicon oxide (SiO ₂ ) in acid and SiO ₃ ²⁻ in alkali. In the second step, silicon oxide is removed by hydrogen fluoride (HF) in the acid, and the SiO ₃ ^2- anion is dissolved in the alkali. If an etching medium with a suitable composition is selected, the etching reaction can be controlled so that the oxidation step is a rate determining step. This can be achieved in the acid, for example by using hydrogen fluoride in excess relative to the oxidant.

  The present invention takes advantage of the fact that the chemical potential and charge carrier concentration in silicon or other semiconductor materials can be affected by light irradiation. Thereby, the rate of the oxidation reaction depends on the light intensity. As a result, the light intensity affects the etching rate. Light having a wavelength shorter than 1100 nm is absorbed by silicon, and charge carrier pairs (electrons and holes) are generated. The absorption coefficient strongly depends on the wavelength of light. Light having a wavelength around 1100 nm penetrates deep into silicon, and for even higher wavelengths, silicon is transmissive.

  This process is done without scanning the entire surface at the same time, which saves a lot of time and thus costs. The position dependent light intensity staging and position resolution can be chosen very finely, so that the overlap effect that occurs during scanning according to the prior art can be avoided.

  The method has the advantage that it operates with local correction until it reaches the edge of the semiconductor wafer, so that the required quality is achieved until it reaches the wafer edge. In particular, it is possible to achieve the required flatness or layer thickness in an edge exclusion space of 2 mm or less and including partial sites. Since the method according to the invention does not require a vacuum, according to the prior art changes in the concentration of the etching medium at the edge of the semiconductor wafer caused by suction can be avoided. In the case where systematic non-uniformities occur during etching removal at specific positions on the semiconductor wafer, for example near the edges, these can be taken into account and compensated for in the calculation of the position-dependent light intensity.

  This method is suitable not only for removing non-uniformity of the semiconductor layer of the SOI wafer but also for removing non-uniformity of the semiconductor wafer including edge roll-off. Thus, semiconductor wafers processed using the method according to the invention are also very suitable for bonding (bonding) with other semiconductor wafers. This is because the joint quality is influenced by the SFQR value and the edge roll-off particularly at the edge. A major economic advantage is that the wafer surface for manufacturing the component is more useful. This has a particularly strong effect in the case of SOI wafers due to its obviously high production costs.

  The method according to the invention is generally performed only on the front side surface (= surface carrying the semiconductor layer) in the case of SOI wafers, and preferably on the front side surface in the case of semiconductor wafers without a layer structure. . If edge roll-off is to be mitigated also on the back side, the method must also be applied on the back side. In this case, the method can be applied sequentially to the back side and the front side.

  Advantageously, no polishing is carried out following the method according to the invention in order not to deteriorate the flatness again.

  In the case of SOI wafers manufactured by transferring semiconductor layers from a donor wafer to a carrier wafer, the method is performed after bonding the wafers and separating the layers from the rest of the donor wafer. The method according to the invention comprises, in the case of SOI wafers, one or more thermal processes for surface smoothing or bonding strength enhancement and / or one or more oxidation treatments for thinning semiconductor layers. Can be combined.

Brief description of the drawings:
FIG. 1 schematically shows the structure of an apparatus suitable for carrying out the method according to the invention.

  FIG. 2 shows the radial thickness profile of the silicon layer of an SOI wafer manufactured according to the prior art.

  FIG. 3 shows the radial thickness profile of the silicon layer of the SOI wafer represented in FIG. 2 after being subjected to the method according to the invention.

apparatus:
In particular, an apparatus for processing a semiconductor wafer 7 (as schematically shown in FIG. 1) suitable for carrying out the method according to the invention is:
A measuring device 11 for measuring parameters indicating the characteristics of the semiconductor wafer 7 depending on the position,
A holding device 12 for the semiconductor wafer 7 arranged so as to be rotatable about its central axis,
A system 9 for supplying and removing an etching medium having a viscosity of -50 mPas to 2000 mPas,
A controllable exposure device 1 arranged so that one surface of the semiconductor wafer 7 present in the holding device 12 can be exposed with a light intensity depending on the position;
A control unit 10 for converting the value of the parameter calculated from the measuring apparatus 11 into a control command for the exposure apparatus 1 and transferring the command to the exposure apparatus 1
Is included.

  Advantageously, the controllable exposure apparatus 1 adjusts the light source 2 having a defined output and wavelength, the optical system 4 enabling a complete exposure 5 of the surface of the semiconductor wafer 7 and the local light intensity. Device 3 for including.

  The apparatus further includes a holding device 12, by which the semiconductor wafer is received, the position of the semiconductor wafer is adjusted, for example by suctioning the semiconductor wafer at a low pressure (so-called "vacuum chuck"), and The part of the semiconductor wafer that is not to be etched, for example the back side, is covered. The holding device is rotatably installed around its central axis, and is connected to a motor that can rotate the holding device. Advantageously, the semiconductor wafer is placed concentrically on the holding device, so that when the holding device is rotated, the semiconductor wafer likewise rotates about its central axis.

  The system 9 for supplying and removing the etching medium includes, for example, a nozzle, through which the semiconductor wafer is selectively supplied with the etching medium in step b) and the cleaning liquid in step d). Can be done.

  The holding device 12 and the system 9 for supplying and removing the etching medium may be integrated in a closed etching chamber 6. This is advantageous, for example, when the etching medium delivers a health threatening component or a corrosive gaseous component to the environment.

  In addition to the exposure apparatus 1, the control unit 10 has other functions of the apparatus, for example, loading and unloading of the semiconductor wafer 7 by using a robot, application and removal of the etching medium by the system 9, and a holding apparatus 12 for the semiconductor wafer. And the etching process parameters, such as the temperature and duration of the etching process.

Description of the individual steps and advantageous embodiments:
In the following, the individual steps of the process according to the invention and the equipment which can be used for this are detailed together with advantageous embodiments of the invention:
Step a) -Measurement The method according to the invention is applicable to all semiconductor wafers that do not have a layer structure, in which case the semiconductor wafer is advantageously silicon, germanium, silicon carbide, III / V compound semiconductor and II. / VI One or more substances selected from the group of compound semiconductors are contained. If the flatness of the front side surface of this type of semiconductor wafer is to be improved, the height deviation from the ideal plane defined above is suitable as a parameter measured in step a) of the method. Yes. This height deviation can be determined by a conventional shape measuring device.

  The method according to the invention is also applicable to all SOI wafers, in which case preferably the semiconductor layer of the SOI wafer is from the group of silicon, germanium, silicon carbide, III / V compound semiconductors and II / VI compound semiconductors. Contains one or more selected substances. If the layer thickness uniformity of the semiconductor layer is to be improved, this layer thickness is measured in step a) of the method according to the invention. The thickness of the semiconductor layer can be measured depending on the position, for example by means of an ellipsometer, interferometer or reflectometer.

In general, the number and position of measurement points depends on the desired resolution. The number of maximum possible measurement points depends on the size of the measurement probe. For example, the size of the measuring probe is 2 × 2 mm ² in the measuring device ADE 9500 (for a semiconductor wafer having a diameter of 200 mm) and in the measuring device ADE AFS (for a semiconductor wafer having a diameter of 300 mm).

  Subsequently, the required local light intensity is calculated and determined from the measured values. A suitable method is described below with the shape data as a clue, ie with regard to the optimization of GBIR or SFQR, but the method also corresponds to the nanotopography data or layer thickness of the semiconductor layer in the case of SOI wafers. It is applicable.

The shape measuring device measures a complete mapping of the thickness t of a semiconductor wafer having a diameter D with a measuring probe of size A × A (typically 4 × 4 mm ² or 2 × 2 mm ² ). In this case, the thickness t is strictly a deviation of the height from the ideal plane defined by the back side surface of the semiconductor wafer. These data can be transferred to a computer as raw data of the shape measuring device. Here, if the Cartesian coordinate system is placed through the center of the semiconductor wafer, there is a thickness value, t (x, y), for each point x, y. In this case, x and y vary within a raster of the measurement window size, which means that t (x, y) is defined by xA / 2 to x + A / 2 and yA / 2 to y + A / 2. This means that it can be understood as the average thickness of the square. The exposure apparatus has a resolution of B × B pixels, for example, a resolution of 1024 × 1024 pixels. By using a matrix inside a computer of size B × B, each matrix element M (a, b) is assigned a corresponding value from the original thickness matrix:
M (a, b) = t (| −D / 2 + a ^* D / B |, | −D / 2 + b ^* D / B |) (1)
The symbol | | represents the absolute value function. The absolute value function is applicable because the exposure apparatus typically has a higher resolution than the original thickness data. In the opposite case, a geometric mean calculation of the original data can be performed.

After this conversion, the data is smoothed. As a control parameter, there is a radius R calculated as an average value. Pixels having coordinates i, j are assigned an average value from all pixels present in a circle having a radius R around point i, j. Points x and y are in a circle centered on i and j when the following conditions are met:
(I−x) ^* (i−x) + (j−y) ^* (j−y) ≦ R ^* R (2)
The new value can be determined by calculating from the average value of all M (x, y) satisfying the above conditions:
M _smooth (i, j) = average value (M (x ₁ , y ₁ ), M (x ₂ , y ₂ ), M (x ₃ , y ₃ ),... M (x _n , y _n )) (3 )
R is typically 0.1 cm to 2 cm with respect to the original coordinate system and is used as a tuning parameter.

  However, in addition to this geometric smoothing, all other standard methods for smoothing, which are common techniques of EDV (electronic data processing), can also be implemented.

The maximum value Max _M and the minimum value Min _M of the matrix M _smooth allow the production of a gray scale matrix for the exposure of semiconductor wafers:
Black portion of pixel i, j = (M _smooth (i, j) −Min _M ) ^* (Max _M− Min _M ) ^* 100% (4)
Pixel transmission part i, j = 100% − (M _smooth (i, j) −Min _M ) ^* (Max _M −Min _M ) ^* 100% (5)
With this algorithm, particularly thin areas of the semiconductor wafer are represented as transparent, so that these areas are exposed with high light intensity in step c). On the other hand, the thickest part is represented in black and thus is not exposed in step c) or is exposed with very little light intensity. This calculation is suitable for cases where material removal decreases with increasing light intensity. In the opposite case, the same calculation can be made.

  The calculation of locally different light intensities to be applied in step c) is detailed in the context of the measurements made in the basic step a). However, it may be performed at any time between the measurement in step a) and the start of the etching process in step c).

Step b) —Etching Medium Application In step b) of the present invention, an etching medium is applied to the semiconductor wafer. The etching medium has a viscosity of 50 mPas to 2000 mPas according to the invention and contains, among other things, reactive compounds required for etching semiconductor materials. Particularly advantageously, gels are used for this purpose. A gel should be understood as a semi-rigid mass from a lyophilic sol in which the dispersion medium is completely absorbed by the sol particles. In particular, gels in which lyophilic sol molecules form a three-dimensional network are known.

  The viscosity of the etching medium is adjusted according to the invention so that it can be spin-coated on the semiconductor wafer and its shape stability is maintained in step c) for the duration of the etching process. The etching medium therefore has a viscosity in the range from 50 mPas to 2000 mPas, particularly preferably from 100 mPas to 1000 mPas. In particular, the composition of the etching medium taking into account the reactive compounds required for etching depends on the combination of the wavelength range of the light used in step c) and on the semiconductor material, and on the removal rate of the etching reaction. It should be chosen so that there is a sufficiently strong relationship with light intensity.

As a basis for the etching medium used according to the invention, conventional etching solutions suitable for etching semiconductor materials may be used. As the acidic etching solution, an aqueous solution containing hydrofluoric acid (HF) and an oxidizing agent such as nitric acid (HNO ₃ ), ozone (O ₃ ), or hydrogen peroxide (H ₂ O ₂ ) may be used. In order to evenly moisten the use of acidic etching media, the addition of substances that reduce the surface tension of the etching media, such as surfactants or acetic acid, is advantageous. Alkaline etching solutions include potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethylammonium hydroxide (N (CH ₃ ) ₄ OH, TMAH), ammonium hydroxide (NH ₄ OH) or ammonium fluoride ( An aqueous solution containing one or more substances from NH ₄ F) may be used. Additionally, the alkaline etching solution may contain other additive substances such as hydrogen peroxide (H ₂ O ₂ ). Advantageously, an acidic solution containing hydrofluoric acid (HF) and hydrogen peroxide (H ₂ O ₂ ) is used.

  To adjust the viscosity of the etching medium, a thickener is preferably added to these conventional etching solutions, in which case these substances should only change the viscosity of the solution. Other changes in the solution or reaction with the species contained in the solution or the semiconductor wafer should not occur advantageously. The shape stability of the viscous solution should be maintained during the etching process in step c). Furthermore, the thickener should be selected such that the resulting viscous etching medium is transparent in the wavelength region selected for irradiation in step c).

  Preferred thickening agents are cellulose derivatives from the group of hydrocolloids. They are soluble or dispersible in water and swell, thereby forming a viscous solution or gel. The most known class is, for example, the class of carboxymethyl cellulose (CMC) to which xanthan belongs. Carboxymethylcellulose is commercially available in high purity and does not react with semiconductor materials. The gels that can be produced thereby have a very high viscosity and in particular are temperature stable. This method is suitable for thickening aqueous solutions having almost any pH value and also having a high concentration of reactive species with respect to the etching reaction.

  Natural resins and artificial polymers such as polymethyl methacrylate, polytetrafluoroethylene and polyvinyl fluoride are also suitable as thickeners for gel production. In general, any polymer that can be cross-linked in three dimensions to a defined degree can be used, the solubility in the desired solvent being very important.

  Viscous etching media exhibit essentially the same etching characteristics as the basic liquid etching solution. Only the rate of the etching reaction is diffusion limited, thereby changing the time course of the etching rate. The relatively small volume of the layer of etching medium additionally limits the total amount of dissolved semiconductor material.

For example, the following aqueous solution based gel with about 0.3-1.0% without auxiliary exposure during the etching process of an orientation 100 silicon wafer having a resistivity in the range of 1-50 Ωcm doped with boron: The following material removal is achieved when thickened with xanthan for 60 seconds:
TMAH 2.5%, room temperature: 6-12 nm removal amount TMAH / H ₂ O ₂ / H ₂ O 1: 1: 5, 85 ° C .: 1-2 nm removal amount NH ₄ OH / H ₂ O ₂ / H ₂ O 1: 1: 5, 85 ° C .: 0.5 nm removal amount HF 1%, O ₃ 20 ppm, room temperature: 1-2 nm
Gels based on aqueous solutions containing hydrofluoric acid and hydrogen peroxide and thickened with xanthan can be used particularly well, the mass proportion of xanthan being 0.3 to 1.0 % Is particularly advantageous. All percentage data relate to mass percentage.

  The application of the etching medium in step b) of the method according to the invention takes place, for example, by application according to a screen printing method, but preferably by spin coating. In doing so, the etching medium is introduced into the surface to be processed of the semiconductor wafer, and the semiconductor wafer is simultaneously or subsequently rotated rapidly, for example at a rotational speed of 2000 to 3000 revolutions per minute. At this time, a film made of an etching medium is quickly formed on the surface of the semiconductor wafer, for example, within a few milliseconds. The thickness of this film depends on the viscosity of the etching medium and should preferably be in the range of 0.1 to 0.5 mm.

  Spin coating is preferably carried out by means of the device represented in FIG. 1: this is provided with a holding device 12 which can be rotated about its central axis. At the same time that the semiconductor wafer 7 attached to the holding device is rotated rapidly, an etching medium is applied to the front side of the semiconductor wafer, for example by a system 9 including a nozzle. The system 9 supplies the etching medium in the required quantity, dosage and quality. Due to the fast rotation, the etching medium is distributed quickly and very evenly across the surface of the semiconductor wafer.

  The use of an etching medium having a viscosity of 50 mPas to 2000 mPas has several essential advantages over dilute etching solutions: so that the semiconductor wafer is immersed in or removed from the immersion bath The phenomenon caused by can be avoided. Thus, when the semiconductor wafer is immersed, the etching of the wafer surface in the region near the edge is strengthened or weakened by the circulation of the wafer edge. When removed from the immersion bath, droplets remaining on the wafer surface can later affect and leave an etch spot on the wafer surface.

  Due to the spin coating process, the other surface, which allows only the front or back surface of the semiconductor wafer to be processed, is protected by a holding device. If the viscosity of the etching medium and the number of revolutions of the semiconductor wafer are suitable, edge wetting that is not possible with low viscosity liquids can also be suppressed. This is especially important when the wafer edge already has a final quality in terms of shape and surface properties prior to the application of the method according to the invention, and thereby no change is desired by the method.

  If the contact angle between the gel and the surface is kept small (this can be achieved by the addition of a surfactant to the etching medium or by the hydrophilic surface of the semiconductor wafer), the structured surface is also completely Can be moistened.

  The method can also be modified so that multiple viscous layers are applied. The bottom layer in direct contact with the semiconductor wafer is advantageously free of reactive species. At least one of the upper layers consists of an etching medium having a viscosity of 50 mPas to 2000 mPas. By thermal, electrical or mechanical treatment of the viscous layer, diffusion of reactive species can be induced from the overlying layer to the semiconductor surface. For example, if only a part of the surface is heated in such a way that reactive species are sufficiently diffused into the bottom layer, and the viscous layer is exposed with a position-dependent light intensity adaptation, etching The reaction can be made to occur only at this part of the wafer surface. In this way, the position dependency of etching removal can be further enhanced.

Step c)-Light controlled etching In step c), the grayscale matrix calculated on the basis of the measurements carried out in step a) was covered with an etching medium by means of an exposure device using suitable optics. It is projected sharply on the surface of the semiconductor wafer and is therefore used for local light intensity control in step c).

  The spectral dependence of the light absorption of the semiconductor material is important for the selection of a suitable light source. For example, optical arc lamps are excellent in terms of a broad spectrum and high light intensity, i.e., they are useful for exposure of the entire semiconductor wafer. By using a suitable filter (high pass, low pass), an appropriate wavelength region can be adjusted. In principle, however, any light source that produces the desired charge carrier concentration at the surface of the semiconductor wafer and the desired depth profile of the charge carrier concentration can be used. For example, mercury or sodium lamps, lasers or LEDs are also suitable.

For example, a halogen lamp that emits light in the wavelength region of 200 nm to 1100 nm can be used as the light source 2 (FIG. 1). As a result, an exposure intensity of 1 to 100 mW / cm ² is formed on the surface to be exposed of the semiconductor wafer. Hit. The wavelength region can then be narrowed by one or more fixed filters and adapted to the semiconductor material to be processed.

  The optical system 4 is preferably designed in such a way that the surface to be processed of the semiconductor wafer 7 is exposed as uniformly as possible over the entire surface, that is to say that there is preferably a filter 3 between the light source and the semiconductor wafer. If not, it is designed to be exposed with a deviation of less than ± 10%. As an alternative, exposure non-uniformities due to light sources or optics can be considered and compensated for in algorithms for grayscale calculations.

  In one embodiment of the invention, the measurement result of the semiconductor wafer obtained in step a) is used for the manufacture of a filter 3 (FIG. 2) that is precisely adapted to this semiconductor wafer, Used in the exposure of this semiconductor wafer in step c). Depending on whether the removal rate of the etching reaction increases or decreases with increasing light intensity in the combination of the etching medium used and the semiconductor material to be etched, the filter requires a particularly high etching removal. In particular, it must have a particularly high or especially low light transmission within the wavelength range used. The gray scale of this filter can be calculated by the above algorithm.

  The filter itself can be made in various ways, for example by the production of filter sheets in the printing process or by the use of LCD filters with a number of individually controllable LCD elements. In principle, however, all types of filters are suitable, which allow a transmission of approximately 0-100% and a suitable local resolution. The filter 3 manufactured for the semiconductor wafer 7 is exposed so that the filter 3 is accurately imaged on the surface of the semiconductor wafer 7 covered with the etching medium for the exposure of the semiconductor wafer 7. 1 is mounted between the light source 2 and the semiconductor wafer 7 in a suitable manner.

  Instead of filters with different light transmission depending on the position, correspondingly manufactured mirrors with different reflectivities depending on the position can also be used.

The production of filters or mirrors that can only be used for one semiconductor wafer each time is very cumbersome. For this reason, the following embodiments of the invention are particularly advantageous: from the value of the parameter depending on the position measured in step a), by using the control unit 10, preferably a computer, a grayscale chart can be obtained. Calculated. For this purpose, the above algorithm can be used. The exposure of the semiconductor wafer 7 in step c) is performed by a projection device, and the device projects an image of this gray scale chart on the surface of the semiconductor wafer 7. In this case, the exposure apparatus 1 is a projection apparatus that can directly project an image of a gray scale chart onto a semiconductor wafer without using a fixed filter or mirror. Advantageously, the projection device operates according to the principle of a data projector or a video projector (so-called “beamer”). In that case, the light of the projection lamp 2 is conducted to a controllable transmissive LCD unit 3 or from a controllable mirror chip (from several hundred thousand small mirrors on a chip of several cm ² size). The matrix). For example, this type of projection apparatus as currently available on the market enables the control of light transmission in the range of 0 to 100% with a resolution of 1024 × 768 dots. This results in a thickness of about 6.5 dots / mm ² on the surface of the semiconductor wafer to be processed having a diameter of 300 mm.

  During the etching process, heating or cooling can be used to adjust the defined uniform temperature. Advantageously, in all etching media, the temperature is selected to obtain a suitable removal rate depending on the semiconductor material and the amount of material removal required.

  In-situ measurement of the amount of material removed during the etching process in step c) is possible by the use of a measurement system integrated for the measurement of the parameters to be optimized, with the latest measurement data being controlled. It can be immediately transferred to the unit 10 and processed.

  In a preferred embodiment of the present invention, in step c) after step c) and before step d), the entire surface of the semiconductor wafer is etched without exposure or while exposing the entire surface simultaneously. In this case, the light intensity is constant over the entire surface of the semiconductor wafer, so that a constant material removal independent of position is achieved. This process reduces the semiconductor layer of the semiconductor wafer or SOI wafer to the required target thickness in the required case. In the case of this two-stage process, only non-uniformity of the measured parameters is taken into account when calculating locally different light intensities. After homogenization in step b), the semiconductor wafer or semiconductor layer is reduced to the desired thickness in step c).

  However, the combination from homogenization and thinning can also be implemented as a one-step process. In this case, the total amount of removal required until the desired final thickness is taken into account when calculating locally different light intensities.

Step d)-Removal of the etching medium In the final step of the method according to the invention, the etching medium is removed from the surface of the semiconductor wafer. Advantageously, the removal is performed by applying a cleaning liquid to the layer of etching medium, whereby the etching medium is diluted and washed away. Advantageously, the cleaning liquid is a solvent, for example water. Advantageously, this step is also carried out in the device represented in FIG. By simultaneously applying the ultrasonic wave, washing of the etching medium is supported.

Product The method according to the invention makes it possible to produce semiconductor wafers with a very flat surface and SOI wafers with a very uniform layer thickness.

In particular, according to the method of the present invention, the front side of the GBIR with a maximum of 0.09 μm, the SFQR _{max with a} maximum of 0.05 μm in a measuring window of size 26 × 8 mm ² including a partial site in an edge exclusion space of 2 mm and a semiconductor It becomes possible to manufacture a semiconductor wafer having an edge roll-off of 0.2 μm at the maximum on the front side surface, measured in the range of a distance interval of 1 mm to 3 mm from the edge of the wafer.

Advantageously, the semiconductor wafer produced according to the invention stands out with a maximum SFQR _{max of} 0.03 μm in a measuring window of size 26 × 8 mm ² including a partial site in an edge exclusion space of 2 mm.

According to the present invention, it is possible to manufacture a semiconductor wafer having a nanotopography (peak to valley deviation) of 16 nm at the maximum in a measurement window having a size of 2 × 2 mm ² with an edge exclusion space of 2 mm on the front side.

  Semiconductor wafers made of the present invention that are made of highly flat, especially monocrystalline silicon, are suitable for use in the semiconductor industry, in particular for the production of electronic devices having a line width of 65 nm or less. It is also particularly well suited as a donor wafer or carrier wafer for producing bonded SOI wafers, especially because of the edge rolls even in the case of very little edge exclusion space which is only 2 mm. This is because flatness including off is guaranteed.

  The present invention also enables the manufacture of SOI wafers including semiconductor layers and carrier wafers, where the semiconductor layers have a thickness of less than 100 nm and a relative standard deviation of 2 mm from the average thickness of the semiconductor layers. The maximum is 3% in the edge exclusion space. The relative standard deviation of the thickness of the semiconductor layer is also referred to below as layer thickness uniformity.

  Advantageously, SOI wafers manufactured according to the invention are distinguished by a layer thickness uniformity of up to 1% with a layer thickness of up to 100 nm and additionally an edge exclusion space of 2 mm.

Particularly advantageous is that the method according to the invention is first applied to the donor wafer and the carrier wafer and then bonded together, after which the carrier wafer with the semiconductor layer is separated from the rest of the donor wafer and so on. The SOI wafer manufactured in this way is again subjected to the method according to the invention in order to make the thickness of the semiconductor layer uniform. The SOI wafer manufactured in this way has a SFQR _{max of} 53 nm at maximum including a partial site in a measurement window of size 26 × 8 mm ² with GBIR of 0.1 μm and edge exclusion space of 2 mm in addition to the above-mentioned characteristics. And marked by edge roll-off of up to 0.25 μm on the front side, measured in the range of 1 mm to 3 mm distance spacing from the edge of the semiconductor wafer.

  The method according to the invention can also be applied to SOI wafers with thick semiconductor layers, so that it is also possible to produce SOI wafers including semiconductor layers and carrier wafers, with the semiconductor layers being between 0.1 μm and 80 μm. And the relative standard deviation from the average thickness of the semiconductor layer is a maximum of 4% in an edge exclusion space of 2 mm.

  Advantageously, SOI wafers produced according to the invention with thick semiconductor layers are distinguished by a layer thickness uniformity of up to 2% in addition to a 2 mm edge exclusion space.

Advantageously, the SOI wafer is produced by application of the method according to the invention to a donor wafer and a carrier wafer, followed by an SOI wafer, as described above for an SOI wafer having a thin semiconductor layer. In some cases, an SOI wafer with a thick semiconductor layer additionally has an SFQR _max and SOI wafer up to 55 nm including partial sites in a measurement window of size 26 × 8 mm ² with a GBIR of up to 0.11 μm and an edge exclusion space of ² mm. It stands out by edge roll-off of up to 0.3 μm on the front side, measured in the range of 1 mm to 3 mm distance spacing from the edge.

Otherwise, advantageously, SOI wafers produced according to the invention with thick or thin semiconductor layers have a maximum of 16 nm, preferably maximum, in a measuring window of size 2 × 2 mm ^{2 with} a 2 mm edge exclusion space. It has a nanotopography of 8 nm and particularly preferably up to 2 nm.

Example Example 1
When an SOI wafer having a diameter of 200 mm is processed, it is manufactured by transferring the silicon layer of the donor wafer to a carrier wafer. The thickness of the wafer is 730 μm, the thickness of the silicon oxide layer is 120 nm, and the target thickness of the silicon layer existing on the silicon oxide layer is 60 nm.

In step a), the thickness of the silicon layer is accurately measured by using an interferometer depending on the position. As a result of measurement with 4000 measurement points and 1 mm edge exclusion space, an average layer thickness of 67.5 nm was obtained, with a standard deviation of 3.5 nm and the difference between the maximum and minimum layer thicknesses. Is 8.8 nm. In FIG. 2, the thickness profile along the diameter, ie the thickness t _SOI of the semiconductor layer measured in nm, is displayed as a function of the radial position r measured in mm. Thickness measurements were stored on a computer and converted to a gray scale chart. At that time, at a position having a larger layer thickness, the percentage of transmission on the gray scale chart is smaller, so that a smaller exposure is performed at these points, and thus a higher removal rate is achieved. And reversed.

Subsequently, in step b), the etching medium is applied by spin coating in the form of a gel on the surface of the silicon layer. The etching medium consists of an aqueous solution containing 5% HF and 10% H ₂ O ₂ and thickened with 0.7% xanthan to obtain a gel. (All percentage data relate to mass percentage). The gel has a viscosity of about 900 mPas. During spin coating, the etching medium forms a uniform film about 0.3 mm thick over the entire surface of the silicon layer. During the spin coating, the SOI wafer is fully exposed and the removal rate is very small.

After covering the entire surface of the silicon layer with the etching medium, the gray scale chart previously calculated in step c) is projected onto the silicon layer of the SOI wafer in the correct alignment and size by the beamer. In this way, the surface of the silicon layer is irradiated with locally different light intensities. The wavelength region used is 250-400 nm, and the light intensity varies locally between about 5-100 mW / cm ² on the wafer. The etching process is continued for 5.5 minutes at room temperature, and the average etching rate is 1.4 nm / min. Subsequently, the SOI wafer is immediately cleaned with deionized water in order to remove the etching medium from the surface of the silicon layer and stop the etching process. Thereafter, the SOI wafer is removed from the apparatus and dried by conventional techniques.

  The position dependent silicon layer thickness is then measured again by the same thickness measurement method as before the etching process. At that time, the average layer thickness is 60.4 nm, in which case the standard deviation is 0.5 nm, and the difference between the maximum layer thickness and the minimum layer thickness is 2.6 nm. The thickness profile of FIG. 3 along the diameter shows that the silicon layer is clearly planarized.

Example 2
In four silicon wafers with a diameter of 300 mm, made from a single crystal (specific resistance 1-10 Ωcm) pulled up according to the Czochralski method and doped with boron and subjected to removal polishing, with a 1 mm edge exclusion space In step a), the local flatness is measured. A measuring device ADE 9900 E + with a surface element size of 26 × 8 mm ² is used. Table 1 shows the SFQR _max value measured including the partial site.

ADE measurement raw data (individual measurement values) are stored in a computer and converted to a gray scale chart. Subsequently, the silicon wafers are individually processed as in Example 1. However, as an etching medium, an aqueous solution containing 10 mol / dm ^{3 of} ammonium fluoride and 1 mol / dm ^{3 of} hydrogen peroxide and thickened with 0.7% xanthan is used. The gel has a viscosity of about 900 mPas, and forms a uniform film with a thickness of about 0.3 mm covering the entire front surface of the silicon wafer during spin coating. The etching process is continued for about 9 minutes using a beamer as in Example 1, with the local light intensity varying in the range of about 5-50 mW / cm ² .

After completion of the etching process, the etching medium is removed from each silicon wafer in the same manner as in Example 1, dried, and the local flatness is newly measured. Table 1 shows that the SFQR _max value (in nm) is clearly reduced by the etching process according to the present invention.

Figure 1 schematically shows the structure of an apparatus suitable for carrying out the method according to the invention FIG. 3 shows a radial thickness profile of a silicon layer of an SOI wafer manufactured according to the prior art. 2 shows the radial thickness profile of the silicon layer of the SOI wafer represented in FIG. 2 after being subjected to the method according to the invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Exposure apparatus, 2 Light source, 3 Filter, 4 Measuring apparatus, 5 Exposure, 6 Etching chamber, 7 Semiconductor wafer, 9 System, 10 Control unit, 12 Holding apparatus

Claims (18)

A method for processing a semiconductor wafer comprising the following steps in a prescribed order:
a) measuring a parameter indicative of the characteristics of the semiconductor wafer depending on the position and calculating the value of this parameter depending on the position over the entire surface of the semiconductor wafer;
b) applying an etching medium having a viscosity of 50 mPas to 2000 mPas over this entire surface of the semiconductor wafer;
c) etching the entire surface of the semiconductor wafer by applying an etching medium while simultaneously exposing the entire surface, wherein the removal rate of the etching process depends on the light intensity at the surface of the semiconductor wafer; and A step of presetting the light intensity depending on the position so that the difference in the value of the parameter depending on the position measured in step a) is reduced by the position-dependent removal rate, and d) the etching medium A method for processing a semiconductor wafer, comprising a step of removing from the surface of the semiconductor wafer.   2. The method of claim 1, wherein the semiconductor wafer contains one or more materials selected from the group of silicon, germanium, silicon carbide, III / V compound semiconductor and II / VI compound semiconductor.   3. A method according to claim 2, characterized in that the parameter measured in step a) is a height deviation from a defined ideal plane.   The method of claim 1, wherein the semiconductor wafer is an SOI wafer including a semiconductor layer on an electrically insulating carrier.   5. The method of claim 4, wherein the semiconductor layer contains one or more materials selected from the group of silicon, germanium, silicon carbide, III / V compound semiconductors and II / VI compound semiconductors.   6. The method according to claim 4, wherein the parameter measured in step a) is the thickness of the semiconductor layer.   7. The method according to claim 1, wherein the application of the etching medium in step b) is performed by spin coating.   8. The method according to claim 1, wherein the etching medium is a gel.   9. The method according to claim 1, wherein the etching medium is an aqueous solution containing hydrofluoric acid and hydrogen peroxide thickened with xanthan.   In step c), the exposure of the semiconductor wafer (7) is performed by the light source (2) and the filter (3) attached between the light source (2) and the semiconductor wafer (7). At this time, the filter (3) 10. The method according to claim 1, wherein the optical transparency has a position-dependent optical transparency, and the optical transparency is uniquely related to a position-dependent parameter value. Method.   A gray scale chart is calculated by a computer from the value of the parameter depending on the position measured in the step a), and the exposure of the semiconductor wafer in the step c) is performed. The method according to claim 1, wherein the method is performed by a projection device that projects onto the screen.   In an additional step between step c) and step d), the entire surface of the semiconductor wafer is etched while simultaneously exposing, where the light intensity is constant or zero over the entire surface of the semiconductor wafer. 12. A method according to any one of claims 1 to 11, characterized in that a constant material removal independent of position is achieved.   13. A method according to claim 12, characterized in that the thickness of the semiconductor wafer is reduced in an additional step between steps c) and d). A semiconductor wafer (7) processing apparatus comprising:
A measuring device (11) for measuring parameters indicative of the characteristics of the semiconductor wafer (7) depending on the position,
A holding device (12) for a semiconductor wafer (7) installed rotatably about its central axis,
A system (9) for supplying and removing an etching medium having a viscosity of -50 mPas to 2000 mPas;
From a controllable exposure device (1) and a measuring device (11) arranged so that one surface of a semiconductor wafer (7) present in the holding device (12) can be exposed with light intensity depending on the position A control unit (10) for converting the calculated parameter value into a control command for the exposure apparatus (1) and transferring the command to the exposure apparatus (1).
A processing apparatus for a semiconductor wafer (7), comprising:   The measuring device (4) is an ellipsometer, interferometer or reflectometer for measuring the layer thickness or a shape measuring device for measuring the height deviation from the defined ideal plane, The apparatus of claim 14.   16. An apparatus according to claim 14 or 15, characterized in that the exposure apparatus (1) is a projection apparatus suitable for projecting an image of a grayscale chart calculated by the control unit (10).   A system (9) for supplying an etching medium is arranged so that the etching medium can be distributed evenly over the entire surface of the semiconductor wafer (7) by rotation of the holding device (12) and thus the semiconductor wafer (7). Device according to any one of claims 14 to 16, characterized in that   The system (9) for supplying and removing the etching medium comprises at least one nozzle, through which the etching medium or cleaning liquid can be selectively applied to the semiconductor wafer. Item 18. The device according to any one of Items 14 to 17.

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