JP2010040899A - Semiconductor device and its production process - Google Patents

Abstract

A semiconductor device capable of reducing on-resistance due to current concentration is provided.
A first conductivity type semiconductor substrate made of silicon carbide, a silicon carbide epitaxial layer formed on a main surface of the semiconductor substrate, and a second conductivity type formed on a part of the silicon carbide epitaxial layer. A well region 22 and a source region 24 of the first conductivity type, and a channel epitaxial layer 30 is formed on the silicon carbide epitaxial layer 20, the well region 22 and the source region 24. 30, the portion located on the well region 22 functions as the channel region 40, and the source electrode 28 formed on the source region 24 covers part of the side surface and the upper surface of the channel epitaxial layer 30. This is a semiconductor device 100.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a power semiconductor device made of silicon carbide used for high breakdown voltage and large current.

  A power semiconductor device is a semiconductor element that is used for a purpose of flowing a large current with a high breakdown voltage, and is desired to have a low loss. Conventionally, power semiconductor devices using silicon (Si) substrates have been mainstream, but in recent years, power semiconductor devices using silicon carbide (SiC) substrates have attracted attention and are being developed (for example, patent documents). 1-4).

  Since silicon carbide (SiC) has a dielectric breakdown voltage that is an order of magnitude higher than that of silicon (Si), the reverse breakdown voltage can be maintained even if the depletion layer at the pn junction or the Schottky junction is thinned. It has the characteristics. Therefore, when SiC is used, the thickness of the device can be reduced and the doping concentration can be increased, so that SiC forms a power semiconductor device with low on-resistance, high withstand voltage, and low loss. Is expected as a material.

  Patent Document 1 discloses a silicon carbide semiconductor device that can improve the on-resistance by improving the channel mobility. The silicon carbide semiconductor device disclosed in Patent Document 1 is shown in FIG.

  A silicon carbide semiconductor device 1000 shown in FIG. 29 is an n-type planar MOSFET (vertical power MOSFET), and includes an n + -type SiC substrate 101. An n − type SiC epi layer 102 is formed on the main surface of n + type SiC substrate 101, and p type SiC base layer 103 a having a predetermined depth in a predetermined region of the surface layer portion of n − type SiC epi layer 102. 103b are formed. A surface channel epi layer 105 is arranged so as to connect the source regions 104a and 104b and the n − type SiC epi layer 102 in the surface layer portions of the base layers 103a and 103b.

  A gate electrode 108 is formed on the surface of the surface channel epilayer 105 via a gate oxide film 107. The gate electrode 108 is covered with an insulating layer 109, and a source electrode 110 is formed thereon so as to be in contact with the base regions 103a and 103b and the source regions 104a and 104b. Furthermore, a drain electrode 111 is formed on the back surface of the SiC substrate 101.

  In the semiconductor device 1000 shown in FIG. 29, by applying a voltage to the gate electrode 108 and applying an electric field to the gate insulating film 107, a storage channel is induced in the surface channel layer 105, and the gate electrode 108 and the drain electrode The carrier flows between 111 and 111. The region 140 in the surface channel layer 105 is a channel region.

In this way, the MOSFET operation mode is set to the accumulation mode that induces the channel without inverting the conductivity type of the channel formation layer, so that the channel movement is compared with the inversion mode MOSFET that induces the channel by inverting the conductivity type. The on-resistance can be improved by increasing the degree.
JP-A-10-308510 Japanese Patent No. 3773489 Japanese Patent No. 3784393 Japanese Patent No. 352796

  According to the semiconductor device 1000 described above, by using the structure in which the surface channel epi layer 105 is formed, channel mobility can be improved and on-resistance can be improved. However, as a result of studies by the inventors of the present application, current may be concentrated in the vicinity of a part of the surface channel epilayer 105, and the current concentration may hinder the effect of improving the on-resistance characteristics. It was found to be possible.

  The present invention has been made in view of such a point, and a main object thereof is to provide a semiconductor device capable of mitigating an increase in on-resistance due to current concentration.

  A semiconductor device according to the present invention has a main surface and a back surface opposite to the main surface, and is formed on a first conductivity type semiconductor substrate made of silicon carbide, and the main surface of the semiconductor substrate. A first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the substrate; a second conductivity type well region formed in a part of the silicon carbide epitaxial layer; and a part of the well region. A channel region made of silicon carbide is formed on the silicon carbide epitaxial layer, the well region, and the source region, and the channel epitaxial layer includes a source region of a first conductivity type. A portion located on the well region functions as a channel region, a source electrode is formed on the source region, and the source electrode It covers at least the side surface of the catcher channel epitaxial layer.

  In a preferred embodiment, a part of the upper surface is covered in addition to the side surface of the channel epitaxial layer.

  In a preferred embodiment, at least one delta doped layer is formed in the channel epitaxial layer.

  In a preferred embodiment, the dopant of the first conductivity type is implanted into both a first part located on the source region and a second part located on the silicon carbide epitaxial layer in the channel epitaxial layer. Has been.

  In a preferred embodiment, the side surface of the channel epitaxial layer is formed in a tapered shape.

  In a preferred embodiment, a gate oxide film is formed on the channel epitaxial layer, a gate electrode is formed on the gate oxide film, and on the back surface of the semiconductor substrate, A drain electrode is formed.

  In a preferred embodiment, a thickness of the gate oxide film located above the first part and the second part into which the dopant of the first conductivity type is implanted has a thickness above the channel region. It is thicker than the gate oxide film.

  In a preferred embodiment, a region sandwiched between the well regions in the surface portion of the silicon carbide epitaxial layer functions as a JFET region.

  In a preferred embodiment, a dopant of a first conductivity type is implanted into the JFET region, and a concentration of the first conductivity type dopant in the JFET region is a second conductivity type included in the well region. It is smaller than the dopant concentration and larger than the dopant concentration of the silicon carbide epitaxial layer.

  In a preferred embodiment, upper surfaces of the silicon carbide epitaxial layer, the well region, and the source region are located on the same plane.

  In the method for manufacturing a semiconductor device according to the present invention, a first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the semiconductor substrate is formed on the main surface of the first conductivity type semiconductor substrate made of silicon carbide. A step (a), a step (b) of forming a second conductivity type well region in a part of the silicon carbide epitaxial layer, and a step of forming a first conductivity type source region in a part of the well region. (C), a step (d) of forming a channel epitaxial layer made of silicon carbide on the silicon carbide epitaxial layer, the well region, and the source region; and forming a source electrode on the source region. And in the step (e), the source electrode is formed so as to cover at least a side surface of the channel epitaxial layer.

  In a preferred embodiment, in the step (e), the source electrode is formed so as to cover a part of the upper surface in addition to the side surface of the channel epitaxial layer.

  In a preferred embodiment, the step (e) includes a step of forming a gate oxide film on the channel epitaxial layer, a step of forming a gate electrode on the gate oxide film, and the gate electrode. Forming an interlayer insulating film on the main surface of the semiconductor substrate on which the source region is formed so as to cover the gate oxide film and the channel epitaxial layer, and etching the interlayer insulating film, Exposing the end of the channel epitaxial layer from the interlayer insulating film, forming a metal film so as to cover the exposed end of the channel epitaxial layer, the interlayer insulating film, and the silicon carbide epitaxial layer; Heat-treating the metal film.

  According to the present invention, the channel epitaxial layer made of silicon carbide is formed on the silicon carbide epitaxial layer, the well region, and the source region, and the source electrode covers a part of the side surface and the upper surface of the channel epitaxial layer. , Current concentration near the boundary with the well region in the source region and / or near the boundary with the well region in the silicon carbide epitaxial layer can be reduced, and as a result, an increase in on-resistance due to current concentration can be reduced. A semiconductor device (a power semiconductor device made of silicon carbide) can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.

  FIG. 1 schematically shows a cross-sectional configuration of a semiconductor device 100 according to an embodiment of the present invention. A semiconductor device 100 of the present embodiment shown in FIG. 1 includes a first conductivity type semiconductor substrate (SiC substrate) 10 made of silicon carbide (SiC) and a first conductivity type having a lower dopant concentration than the semiconductor substrate 10. A silicon carbide epitaxial layer 20, a second conductivity type well region 22 formed in a part of the silicon carbide epitaxial layer 20, and a first conductivity type source region 24 formed in a part of the well region 22. ing. Semiconductor substrate (SiC substrate) 10 has a main surface 10a and a back surface 10b opposite to the main surface 10a. Silicon carbide epitaxial layer 20 is formed on main surface 10a of semiconductor substrate 10. Yes.

  A channel epitaxial layer 30 made of silicon carbide is formed on the silicon carbide epitaxial layer 20, the well region 22, and the source region 24. In the present embodiment, the “epitaxial layer” may be referred to as “epi layer”, the silicon carbide epitaxial layer 20 is referred to as “drift epi layer 20”, and the channel epitaxial layer 30 is referred to as “channel epi layer 30”. It may be called.

  Further, a portion of the channel epi layer 30 located on the well region 22 functions as the channel region 40. Further, a region sandwiched between the well regions 22 in the surface portion of the drift epi layer 20 functions as a JFET (Junction Field-Effect Transistor) region 60.

  In the example of this embodiment, the first conductivity type is n-type. In the example shown in FIG. 1, the semiconductor substrate 10 is an n-type SiC semiconductor substrate (n + SiC substrate), and the drift epi layer 20 is an n-SiC layer. It is. The well region 22 is a p− layer, and the source region 24 is an n ++ layer.

  Note that “+”, “++”, “−”, and the like are symbols representing the n-type or p-type relative dopant concentration. In this example, the n− drift epi layer is more than the n + SiC substrate 10. No. 20 has a lower concentration of n-type dopant. The n ++ source region 24 has a higher n-type dopant concentration than the n + SiC substrate 10.

  A gate oxide film 42 is formed on the channel epilayer 30, and a gate electrode 44 is formed on the gate oxide film 42. A source electrode 28 is formed on the source region 24. In the configuration of the present embodiment, the source electrode 28 is connected to the well region (p− layer) 22 via the contact region (p + layer) 26. Furthermore, a drain electrode 50 is formed on the back surface 10 b of the SiC substrate 10.

  In the configuration of the present embodiment, the source electrode 28 covers at least the side surface of the channel epilayer 30. In the illustrated example, the source electrode 28 includes a part 28 a that contacts the source region 24 and the p + layer 26, a part 28 b that covers the side surface of the channel epilayer 30, and a part 28 c that covers a part of the upper surface of the channel epilayer 30. have. The structure of the source electrode 28 (28a, 28b, 28c) allows a part (28b, 28c) of the source electrode 28 to be in direct contact with the channel epilayer 30, thereby increasing the current path. On-resistance can be reduced. Details of the effect of reducing the on-resistance will be described later.

  The semiconductor device 100 of this embodiment is a power semiconductor device made of SiC, and is preferably used for high withstand voltage and large current. The conditions of the configuration of the present embodiment will be described as an example as follows.

The n + SiC substrate 10 is made of hexagonal silicon carbide. The thickness of the n + SiC substrate 10 is, for example, 250 to 350 μm, and the concentration of the n + SiC substrate 10 is, for example, 8 × 10 ¹⁸ cm ⁻³ . In the case of the n + SiC substrate 10, a substrate made of cubic silicon carbide can also be used.

Drift epi layer 20 is an SiC layer formed epitaxially on main surface 10 a of SiC substrate 10. The thickness of the drift epi layer 20 is, for example, 4 to 15 μm, and the concentration of the n + SiC substrate 10 is, for example, 5 × 10 ¹⁵ cm ⁻³ . An additional SiC epi layer (for example, an SiC epi layer having a concentration of 6 × 10 ¹⁶ cm ⁻³ ) may be provided between the n + SiC substrate 10 and the drift epi layer 20.

The thickness of the well region 22 (that is, the depth from the upper surface of the drift epitaxial layer 20) is, for example, 0.5 to 1.0 μm, and the concentration of the well region 22 is, for example, 1.5 × 10 ¹⁸ cm. ^-3 . The thickness of the source region 24 (that is, the depth from the upper surface of the drift epi layer 20) is, for example, 0.25 μm, and the concentration of the source region 24 is, for example, 5 × 10 ¹⁹ cm ⁻³ . . The thickness of the p + layer 26 is, for example, 0.3 μm, and the concentration of the p + layer 26 is, for example, 2 × 10 ²⁰ cm ⁻³ . The length (width) of the JFET region 60 defined between the well regions 22 is, for example, 3 μm.

  The channel epi layer 30 is an SiC layer epitaxially formed on the drift epi layer 20, and the thickness of the channel epi layer 30 is, for example, 30 nm to 150 nm. The length (width) of the channel region 40 is, for example, 0.5 μm. The gate oxide film 42 is made of SiO2 (silicon oxide) and has a thickness of 70 nm, for example. The gate electrode 44 is made of poly-Si (polysilicon) and has a thickness of, for example, 500 nm.

  Furthermore, the source electrode 28 is made of an alloy of Ti (titanium) and Si (silicon), and the thickness thereof is, for example, 50 nm. The source electrode 28 may be made of an alloy of Ni (nickel) and Si (silicon). The drain electrode 50 is also made of an alloy of Ti (titanium) and Si (silicon), and has a thickness of, for example, 100 nm. The drain electrode 50 may be deposited with Ni and Ag or Ni and Au in order to facilitate soldering when the SiC chip is mounted on the plastic package.

  According to the configuration of the semiconductor device 100 of the present embodiment, the channel epi layer 30 is formed on the drift epi layer 20, the well region 22, and the source region 24, and part of the side surface and upper surface of the channel epi layer 30 is formed. A source electrode 28 is covered. Thereby, current concentration in the source region 24 in the vicinity of the boundary with the well region 22 and / or in the vicinity of the boundary in the drift epi layer 20 with the well region 22 can be alleviated. It is possible to alleviate the rise and the characteristic deterioration.

  Next, with reference to FIG. 2, the problem of deterioration in on-resistance characteristics due to current concentration, which is to be solved by the configuration of this embodiment, will be described.

  FIG. 2 is a cross-sectional view of a comparative example 200 for the configuration 100 of the present embodiment. In the comparative example 200 shown in FIG. 2, the source electrode 28 does not cover the side surface of the channel epilayer 30. Different from the configuration 100 of the present embodiment.

  According to the study of the present inventor, it has been found that the following phenomenon can occur in the configuration of the comparative example 200.

  First, the operation of the vertical MOSFET will be described. A voltage of several hundred volts to several kilovolts is applied to the source electrode 28 via the external resistance (not shown) and 0 V to the drain electrode 50. In an off state in which a voltage (for example, 0 V) equal to or lower than a threshold value (Vth) is applied to the gate electrode 44, a depletion layer spreads between the well region 22 and the drift. Are connected.

  Next, when a voltage (for example, 20 V) higher than the threshold value (Vth) is applied to the gate electrode 44, electrons flow into the channel epilayer 30 in the channel region 40 through the gate insulating film 42. At this time, since a part of the current flows even though it is formed between the well region 22 and the drift (drift epi layer 20), the potential of the well region 22 approaches the source potential and the depletion layer is reduced. A current path of the JFET region 60 is formed and is turned on. At this time, the external resistance is selected so that the drain voltage becomes about 1 to 2 V due to the voltage drop of the external resistance.

  In the comparative example 200, electrons flowing through the channel region 40 of the channel epi layer 30 tend to flow through the interface between the channel epi layer 30 and the gate oxide film 42 as indicated by an arrow 96 due to the influence of the gate electrode 44. Then, electrons 95 that flow vertically through the channel epilayer 30 are generated, and the resistance in the vertical direction is added, resulting in an increase in on-resistance. In order to achieve a normally-off state by setting the threshold value (Vth) of the MOS portion higher than 0 V, it is necessary to reduce the concentration of the channel epi layer 30 and the resistance in the path of the electrons 95 is increased. .

  In addition, the flow of electrons in the channel epilayer 30 results in current concentration near the boundary (98) with the well region 22 in the source region 24, and the boundary with the well region 22 in the drift epilayer 20 Current concentration in the vicinity (99) can also be brought about. This current concentration increases the resistance, resulting in an increase in on-resistance and characteristic deterioration.

  In addition, since electrons try to pass through the region having the lowest resistance as much as possible, the electrons flow through the source region (n ++ layer) 24 as much as possible, and then move in the vertical direction, causing current concentration in the region 98. Similarly, the tendency for current concentration to occur in the region 99 also increases in the electrons going to the JFET region 60. Such a phenomenon may cause an increase in on-resistance and characteristic deterioration.

  On the other hand, in the configuration 100 of the present embodiment, as shown in FIG. 3, since the source electrode 28 covers the side surface (and part of the upper surface) of the channel epilayer 30, the current in the region 98 in FIG. Concentration can be avoided. That is, since the source electrode 28 (28b) covers the side surface of the channel epitaxial layer 30, the current path increases as shown by the arrow 91, and as a result, an increase in on-resistance can be suppressed. Further, as a result of the increase in the current path, electrons are likely to go to the JFET region 60 as indicated by the arrow 92 in the channel epilayer 30. Therefore, current concentration in the region 99 in FIG. 2 can be avoided.

  As described above, according to the configuration 100 of the present embodiment, since the source electrode 28 is formed so as to cover the side surface of the channel epilayer 30, it is possible to mitigate the deterioration in on-resistance characteristics due to current concentration. Note that the source electrode 28 has an effect (an effect of alleviating current concentration) only by providing the portion 28b covering the side surface of the channel epi layer 30, but in addition, the upper surface of the channel epi layer 30 as in the illustrated example. It is preferable to provide the portion 28c that covers the surface because the current path is further increased, and the distance from the source electrode 28 to the JFET region 60 is reduced.

  Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to FIGS. 4 to 11 are process cross-sectional views for explaining the manufacturing method of the present embodiment.

First, an n-type 4H—SiC (0001) substrate is prepared as the n + SiC substrate 10. This substrate is, for example, a substrate that is 8 ° or 4 ° offcut in the <11-20> direction and has an n-type doping concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 4A, an n − drift epi layer 20 is formed on the main surface 10a of the n + SiC substrate 10 by epitaxial growth. Epitaxial conditions are thermal CVD using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. Thus, a thickness of 10 μm or more is deposited at a concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ .

Next, as shown in FIG. 4B, an implantation mask 70 is deposited on the n− drift epi layer 20, and a photoresist 72 is formed on the implantation mask 70. The implantation mask 70 is, for example, SiO ₂ (silicon oxide). The implantation mask 70 made of silicon oxide is formed, for example, by performing plasma CVD at a power of 200 W using silane (SiH ₄ ) and N ₂ O. The thickness of the implantation mask 70 is, for example, 0.5 to 1.0 μm. Photoresist 72 has a position and dimensions that define well region (p-layer 22) and JFET region 60. The photoresist 72 is, for example, a photosensitive organic film, and is formed using a typical photolithography method. The thickness of the photoresist 72 is, for example, 1.5 to 2.0 μm.

Next, using the photoresist 72 as a mask, the implantation mask 70 is etched to form an implantation mask pattern 70A, and then the photoresist 72 is removed. The implantation mask 70 is etched by, for example, an anisotropic dry etching method using CF ₄ gas and CHF ₃ gas, and the removal of the photoresist 72 may be performed by, for example, ashing using oxygen plasma.

  Next, as shown in FIG. 5A, Al + (aluminum ions) are ion-implanted (arrow 80) using the implantation mask pattern 70A as a mask, so that a predetermined depth is formed on the surface of the n-drift epilayer 20. A well region (p−) 22 is formed. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 350 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the well region 22 is, for example, 0.5 to 1.0 μm. The surface portion of the n − drift epi layer 20 defined by the well region 22 becomes the JFET region 60. The width of the JFET region 60 of this embodiment is 3 μm, for example.

Next, as shown in FIG. 5B, an implantation mask 71 is deposited on the surface of the substrate 10 (more specifically, on the well region 22) so as to cover the implantation mask pattern 70A. A photoresist 72 A is formed on the mask 71. The implantation mask 71 is, for example, poly-Si (polysilicon), and is formed by depositing SiH ₄ as a source gas by thermal CVD. The thickness of the implantation mask 71 is, for example, 0.5 to 1.0 μm. Photoresist 72A is provided to define source region 24.

Next, as shown in FIG. 6A, the implantation mask 71 is etched using the photoresist 72A as a mask to form an implantation mask pattern 71A. One of the illustrated implantation mask patterns 71A is a pattern below the photoresist 72A, and the other is a sidewall pattern adjacent to the implantation mask pattern 70A. This etching is performed by, for example, anisotropic etching using a mixed gas of Cl ₂ , O ₂ , and HBr.

  Next, as shown in FIG. 6B, N + (nitrogen ions) or P + (phosphorus ions) are ion-implanted into the surface of the well region (p−) 22 using the implantation mask patterns 70A and 71A as a mask (arrow 82). ) To form the source region (n ++) 24. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 90 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the source region 24 is, for example, 0.25 μm.

Next, as shown in FIG. 7A, after removing the implantation mask patterns 70A and 71A, an implantation mask 72 is formed, and then a photoresist 73A is formed on the implantation mask 72. The removal of the implantation mask patterns 70A and 71A is performed, for example, by wet etching the oxide film with an HF aqueous solution and the polysilicon with a mixed solution of HF, HNO ₃ and H ₂ O. The implantation mask 72 is, for example, SiO ₂ (silicon oxide). Photoresist 73A is provided to define p + layer 26.

  Next, as shown in FIG. 7B, an implantation mask pattern 72A is formed by etching the implantation mask 72 using the photoresist 73A as a mask. Next, after removing the photoresist 73A, ion implantation (arrow 84) of Al + (aluminum ions) or B + (boron ions) is performed on the surface of the well region (p−) 22 using the implantation mask pattern 72A as a mask. , P + layer 26 is formed. The ion implantation conditions are, for example, that the energy is divided into a plurality of portions between 30 keV and 150 keV, and the temperature of the substrate at that time is, for example, 500 ° C. The depth of the p + layer 26 is deeper than the depth of the source region (n ++) 24, for example, 0.3 μm.

Next, as shown in FIG. 8A, after removing the implantation mask pattern 72 </ b> A, cap films 90 are formed on both surfaces of the substrate 10. More specifically, cap film 90 is formed on the upper surface including drift epi layer 20, well region 22, source region 24, and p + region 26, and on rear surface 10 b of SiC substrate 10. The cap film 90 is made of, for example, carbon, and a surface opposite to the main surface is separately deposited by sputtering. After the cap film 90 is formed, the substrate 10 (more precisely, the substrate 10 on which each layer (20, 22, 24, 26) is formed) is activation-annealed at a temperature of 1000 ° C. or higher, here 1800 ° C. . It is also possible to perform annealing in a SiH ₄ atmosphere without the cap film 90.

Next, as shown in FIG. 8B, after the double-sided cap film 90 is removed, the channel epitaxial layer 30 is formed by epitaxial growth. The removal of the double-sided cap film 90 is performed using, for example, an ashing method using oxygen plasma. The channel epi layer 30 in the present embodiment is a layer (epi layer) made of SiC, and the epitaxial growth conditions are, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas, carrier By performing thermal CVD using hydrogen (H ₂ ) as a gas and nitrogen (N ₂ ) gas as a dopant gas, a thickness of 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ is obtained as a thickness. Deposit 30-150 nm. Note that nitrogen (N ₂ ) gas may be introduced during the epitaxial growth so that a part of the channel epitaxial layer has a high concentration.

Next, as shown in FIG. 9A, after forming a photoresist 75A on the channel epitaxial layer 30, the channel epitaxial layer 30 is etched using the photoresist 75A as a mask. The channel epi layer 30 is etched by, for example, dry etching using a mixed gas of CF ₄ and O ₂ .

Next, as shown in FIG. 9B, after removing the photoresist 75A, a gate oxide film (SiO ₂ ) 42 is formed on the channel epitaxial layer 30, and then a gate oxide film 42 is formed on the gate oxide film 42. An electrode (poly-Si) 44 is formed. Thereafter, a photoresist (not shown) is formed on the gate electrode 44, and the gate electrode 44 is etched to remove the photoresist.

Next, as shown in FIG. 10A, an interlayer insulating film 52 is formed on the substrate (10, 20) so as to cover the gate electrode 44 and the channel epilayer 30. The interlayer insulating film 52 is made of, for example, silicon oxide (SiO ₂ ) and has a thickness of, for example, 1000 nm. Next, a photoresist 53 is formed on the interlayer insulating film 52. The photoresist 53 is a mask for forming a source contact and a body contact.

Next, as shown in FIG. 10B, the interlayer insulating film 52 is etched using the photoresist 53 as a mask. Etching of the interlayer insulating film 52 is performed, for example, by dry etching using a mixed gas of CHF ₃ and O ₂ . Next, the photoresist 53 is removed.

  Next, as shown in FIG. 11A, after the interlayer insulating film 52 is wet-etched, a contact metal (titanium (Ti) or nickel (Ni)) 55 is deposited. Etching of the interlayer insulating film 52 is performed, for example, by wet etching using a mixed solution of hydrofluoric acid and water, and the interlayer insulating film 52 recedes by this wet etching, so that the channel epitaxial layer 30 is removed from the interlayer insulating film 52. End portions (side surfaces and part of the upper surface) can be exposed. The reason why the interlayer insulating film 52 is wet-etched is to remove impurities and form a stable ohmic junction in the subsequent steps. It is also possible to form the interlayer insulating film 52 shown in FIG. 11A by etching using a predetermined mask from the structure shown in FIG.

  Next, as shown in FIG. 11B, the contact metal 55 is heat-treated to perform silicidation, and then the unreacted contact metal is removed, thereby forming the source electrode 28. The source electrode 28 of the present embodiment is formed so as to be in contact with the source region 24 and the P + layer 26, and is formed so as to cover the end portion (side surface and part of the upper surface) of the channel epilayer 30. When the contact metal 55 is made of Ti, for example, a heat treatment at 950 ° C. is performed after the Ti is deposited.

  Thereafter, a typical wiring forming process is performed. That is, when the drain electrode (for example, an alloy layer of Ti and Si) 50 is formed after the source electrode (for example, an alloy layer of Ti and Si) 28 is formed, the semiconductor device 100 of the present embodiment is obtained. It is done. The drain electrode 50 is formed on the back surface 10b of the SiC substrate 10, and is formed, for example, by performing a heat treatment at 950 ° C. after depositing Ti. In this way, the semiconductor device 100 of this embodiment can be manufactured.

  In addition, the semiconductor device 100 of the present embodiment can be manufactured by being modified as follows. This will be described with reference to FIGS.

  First, the process shown in FIG. 8B is performed to form the channel epi layer 30. Thereafter, as shown in FIG. 12A, the gate oxide film 42 and the gate electrode 44 are formed on the channel epilayer 30 without etching the channel epilayer 30.

  Next, as shown in FIG. 12B, an interlayer insulating film 52 is formed on the substrate (10, 20) having the channel epitaxial layer 30 so as to cover the gate oxide film 42 and the gate electrode 44. Next, a photoresist 53 is formed on the interlayer insulating film 52. This photoresist 53 is a mask for forming a source contact and a body contact, similar to the one shown in FIG.

Next, as shown in FIG. 13A, the interlayer insulating film 52 and then the channel epitaxial layer 30 are etched using the photoresist 53 as a mask. This etching is performed by, for example, dry etching using a mixed gas of CHF ₃ and O ₂ . Next, the photoresist 53 is removed. The removal of the photoresist 53 may be performed before the channel epi layer 30 is etched.

  Next, as shown in FIG. 13B, after the interlayer insulating film 52 is wet-etched as a pretreatment for depositing the contact metal 55, the contact metal (titanium (Ti) or nickel (Ni)) 55 is deposited. To do. Thereafter, the semiconductor device 100 of this embodiment is obtained through the steps shown in FIGS. 11A and 11B and the subsequent steps.

  Furthermore, as shown in FIGS. 14A and 14B, the semiconductor device 100 of this embodiment can be manufactured.

First, after the structure shown in FIG. 12B is fabricated, the interlayer insulating film 52 is etched using the photoresist 53 as a mask, and then, as shown in FIG. Is etched so as to be tapered (30T). This etching is performed, for example, by increasing the flow rate ratio of CF _{4 in} dry etching using a mixed gas of CF ₄ and O ₂ . Next, the photoresist 53 is removed. The removal of the photoresist 53 may be performed before the channel epi layer 30 is etched.

  Next, as shown in FIG. 14B, after the interlayer insulating film 52 is wet-etched as a pretreatment for depositing the contact metal 55, the contact metal (titanium (Ti) or nickel (Ni)) 55 is deposited. To do. Thereafter, the semiconductor device 100 of the present embodiment is obtained through the steps shown in FIGS. 11A and 11B and the subsequent steps.

  In the semiconductor device 100 manufactured from the structure shown in FIGS. 14A and 14B, the end of the channel epi layer 30 has a tapered shape (30T), so that the source electrode 28b formed on the side surface is formed. There is an advantage that coverage is improved. In addition, the inclination angle θ (angle formed by the bottom surface and the side wall surface) of the tapered portion (30T) can be, for example, less than 90 ° and 45 ° or more.

  As described above, the semiconductor device 100 according to the present embodiment can suppress current concentration in the operation of the vertical MOSFET in the on state, and thus can exhibit low on-resistance and high reliability characteristics. Further, the semiconductor device 100 of the present embodiment can be modified as follows.

  FIG. 15 is a cross-sectional view schematically showing a modified example of the semiconductor device 100 of the present embodiment. The semiconductor device 100 shown in FIG. 15 differs from the semiconductor device 100 shown in FIG. 1 in that a delta doped layer is formed on the channel epi layer 30.

More specifically, the delta doped layer 35 is a layer having a high impurity concentration locally in the channel epilayer 30. For example, if the delta doped layer 35 is an n + layer, the delta doped layer 35 is in the other portion of the channel epilayer 30. The concentration of the n-type impurity is, for example, one tenth or less of the concentration of the n-type impurity in the delta doped layer 35. The delta doped layer 35 is in contact with the source electrode 28. FIG. 16 shows a structure in which an interlayer insulating film 52 is formed in the structure shown in FIG. The delta doped layer 35 can be formed, for example, by increasing the flow rate of the additive gas N ₂ during channel epi film deposition.

  According to the modification shown in FIG. 15, since the delta doped layer 35 is formed in the channel epi layer 30, the effect of suppressing current concentration can be further obtained. That is, since the source electrode 28 covering the side surface of the channel epi layer 30 can be in contact with the delta doped layer 35, the number of horizontal current paths can be increased compared to the current path in the vertical direction. As a result, the modified example shown in FIG. 15 can more easily achieve the effect of suppressing the current concentration than the structure shown in FIG.

  In addition, since the delta doped layer 35 is formed in the channel epi layer 30, an effect of lowering the contact resistance with the source electrode 28b can be obtained in addition to the original purpose of controlling the threshold value.

  FIG. 17 shows an example of the configuration of the channel epi layer 30 in which the delta doped layer 35 is formed. The delta doped layer 35 can be disposed substantially at the center in the thickness direction of the channel epi layer 30 as illustrated in FIG. 15, but is disposed other than the center in the thickness direction of the channel epi layer 30 as illustrated in FIG. 17. It is also possible to do.

  In the example shown in FIG. 17, the delta doped layer 35 is disposed below the center of the channel epi layer 30 in the thickness direction. More specifically, below the channel epi layer 30, there is an undoped layer (i layer) 30A (for example, 30 nm thick), a delta doped layer 35A (for example, 10 nm thick) is disposed thereon, and above that There is an i layer 30A (for example, a thickness of 90 nm). When the delta doped layer 35 is disposed below the channel epi layer 30 as described above, an effect of increasing the channel mobility can be obtained. The effect of increasing the channel mobility can be obtained by reducing impurity scattering by causing carriers in the high-concentration layer to leak into the low-concentration layer in a wave function and acting as carriers in the low-concentration layer with few impurities.

  The delta doped layer 35 can be provided not only in one layer but also in a plurality of layers in the channel epi layer 30. FIG. 18 shows an example in which two delta doped layers 35 (35A, 35B) are provided. More specifically, an i layer 30A (for example, a thickness of 20 nm) is provided below the channel epi layer 30, a delta doped layer 35A (for example, a thickness of 10 nm) is disposed thereon, and then an i layer 30C (for example, a thickness of 10 nm). 20 nm), a delta doped layer 35B (for example, 10 nm in thickness), and an i layer 30B (for example, 90 nm in thickness) are sequentially stacked. Thus, in the channel epilayer 30, there are a plurality of i layers and delta doped layers (n + layers) If the plurality of delta doped layers 35 are disposed, the contact resistance with the source electrode 28b can be further reduced.

  Furthermore, the configuration of the present embodiment can be modified as shown in FIG. The modified example shown in FIG. 19 is different from the configuration shown in FIG. 1 described above in that the injection layer 33 is formed at the end of the channel epilayer 30. The injection layer 33 is an n + layer. In the example shown in FIG. 19, a configuration in which a delta doped layer 35 is formed in the channel epi layer 30 is shown.

  According to the modified example shown in FIG. 19, since the injection layer 33 is formed at the end of the channel epitaxial layer 30, the effect of suppressing current concentration is further obtained as compared with the configuration shown in FIG. 1. be able to. That is, since the source electrode 28 covering the side surface of the channel epi layer 30 can contact the channel epi layer 30 via the injection layer 33, a horizontal current path can be formed rather than a vertical current path. Can do a lot. It becomes easier to achieve the effect of suppressing current concentration than the structure shown in FIG. In addition, when the delta doped layer 35 is formed in the channel epi layer 30, the effect of the structure shown in FIG. 15 can also be obtained.

  The modified example shown in FIG. 19 can be manufactured as follows. A method for manufacturing the semiconductor device 100 shown in FIG. 19 will be described with reference to FIGS.

  After the structure shown in FIG. 8B is fabricated, an implantation mask 74 is deposited on the channel epilayer 30 as shown in FIG. 20A, and then a photoresist 74A is deposited on the implantation mask 74. Form. When the configuration example shown in FIG. 19 is manufactured, the channel epi layer 30 is grown to have the delta doped layer 35 in the structure shown in FIG.

The implantation mask 74 is, for example, SiO ₂ (silicon oxide). Photoresist 74A is provided to define channel region 40. The photoresist 74A is provided above the surface layer portion of the well region (p ⁻ ) 22 to be the channel region 40, but is overlaid on the source region (n ⁺⁺ ) 24 in consideration of misalignment and dimensional variation. A portion (overlapping portion) 45 is provided to ensure a margin, and thereby, the channel region 40 can be reliably formed.

Next, as shown in FIG. 20B, the implantation mask 74 is etched using the photoresist 74A as a mask to form an implantation mask pattern 74B. Next, after removing the photoresist 74A, N ⁺ (nitrogen ions) or P ⁺ (phosphorus ions) are ion-implanted (arrow 86) into the channel epi layer 30 using the implantation mask pattern 74B as a mask, thereby forming a channel epi layer. An n + site (33) is formed in 30. In this example, an n + portion 33 located at the end of the channel epitaxial layer 30 is formed. The n ⁺ concentration in the channel epi layer 30 may not be uniform. Here, the ion implantation conditions are, for example, 5 × 10 ^{15 to} 5 × 10 ²⁰ cm ⁻³ at 30 keV.

Next, as shown in FIG. 21A, after removing the implantation mask pattern 74B, the cap film 90 is formed on both surfaces of the substrate, more precisely, on the surface of the channel epilayer 30 and the back surface 10b of the SiC substrate 10. Form. The cap film 90 is made of, for example, carbon, and a surface opposite to the main surface is separately deposited by sputtering. After the cap film 90 is formed, the substrate is activated and annealed at a temperature of 1000 ° C. or higher (here, 1800 ° C.). It is also possible to perform annealing in a SiH ₄ atmosphere without the cap film 90.

  Next, as shown in FIG. 21B, after the double-sided cap film 90 is removed, the surface of the channel epitaxial layer 30 is subjected to CMP (chemical mechanical polishing). Note that the execution of CMP is optional, and it is not necessary to perform CMP.

  Next, as shown in FIG. 22A, after forming a photoresist 75A on the channel epitaxial layer 30, the channel epitaxial layer 30 is etched using the photoresist 75A as a mask. As described above, the channel epi layer 30 in which the n + dopant (nitrogen ions or phosphorus ions) is implanted is formed in the portion 33 of the channel epi layer 30 located on the source region 24. That is, an n + dopant is formed in a portion 33 of the epi channel layer 30 excluding the channel region 40.

Next, as shown in FIG. 22B, after removing the photoresist 75A, a gate oxide film (SiO ₂ ) 42 is formed on the channel epitaxial layer 30, and then a gate oxide film 42 is formed on the gate oxide film 42. An electrode (poly-Si) 44 is formed. Thereafter, a photoresist (not shown) is formed on the gate electrode 44, and the gate electrode 44 is etched to remove the photoresist. Thereafter, the steps after FIG. 9B may be executed.

  Further, the configuration of the present embodiment can be modified as shown in FIG. In the modified example shown in FIG. 23, in addition to the injection layer 33 at the end of the channel epi layer 30 in the configuration shown in FIG. 19, the injection layer 34 is also formed at the center of the channel epi layer 30. By providing the channel epitaxial layer 30 in the injection layer 34, in addition to the above-described effects, an effect of more effectively avoiding the problem of current concentration in the region 99 shown in FIG. 2 can be obtained.

Here, the injection layers 33 and 34 are n + layers. Further, the n ⁺ concentration in the channel epilayer 30 may not be uniform. In the example shown in FIG. 19, the configuration in which the delta doped layer 35 is formed in the channel epi layer 30 is shown. However, the delta doped layer 35 can also be formed in the example shown in FIG. 23. In the illustrated example, the channel epi layer 30 is not formed with the delta doped layer 35.

  The modified example shown in FIG. 23 can be manufactured as follows. A method for manufacturing the semiconductor device 100 shown in FIG. 23 will be described with reference to FIGS. Note that FIG. 24 to FIG. 26 basically correspond to FIG. 20 to FIG.

First, after the structure shown in FIG. 8B is fabricated, an implantation mask 74 is deposited on the channel epilayer 30 as shown in FIG. 24A, and then a photoresist is formed on the implantation mask 74. 74A is formed. The photoresist 74A is provided above the surface layer portion of the well region (p ⁻ ) 22 to be the channel region 40, and the source region (n ⁺⁺ ) 24 and the JFET region 60 are taken into account in consideration of misalignment and dimensional variation. A margin is secured by providing a portion 45 (overlap portion) overlapped with each other so that the channel region 40 can be reliably formed.

Next, as shown in FIG. 24B, the implantation mask 74 is etched using the photoresist 74A as a mask to form an implantation mask pattern 74B. Next, after removing the photoresist 74A, N ⁺ (nitrogen ions) or P ⁺ (phosphorus ions) are ion-implanted (arrow 86) into the channel epi layer 30 using the implantation mask pattern 74B as a mask, thereby forming a channel epi layer. N + sites (33, 34) are formed in 30.

  Next, as shown in FIG. 25A, after removing the implantation mask pattern 74B, cap films 90 are formed on both surfaces of the substrate. Next, as shown in FIG. 25B, after the double-sided cap film 90 is removed, the surface of the channel epilayer 30 is subjected to CMP (chemical mechanical polishing). Note that the execution of CMP is optional, and it is not necessary to perform CMP.

  Next, as shown in FIG. 26A, after forming a photoresist 75A on the channel epitaxial layer 30, the channel epitaxial layer 30 is etched using the photoresist 75A as a mask. As described above, n + dopant (nitrogen ions or nitrogen ions or both of the first portion 33 located on the source region 24 and the second portion 34 located on the JFET region 60 of the silicon carbide epitaxial layer 20 in the channel epilayer 30 are obtained. A channel epi layer 30 implanted with phosphorus ions) is formed. That is, n + dopant is formed in the portions 33 and 34 excluding the channel region 40 in the epichannel layer 30.

Next, as shown in FIG. 26B, after removing the photoresist 75A, a gate oxide film (SiO ₂ ) 42 is formed on the channel epitaxial layer 30, and then a gate oxide film 42 is formed on the gate oxide film 42. An electrode (poly-Si) 44 is formed. Thereafter, a photoresist (not shown) is formed on the gate electrode 44, and the gate electrode 44 is etched to remove the photoresist. Thereafter, the steps after FIG. 9B may be executed.

  FIG. 27 is a cross-sectional view schematically showing a further modification of the semiconductor device 100 shown in FIG. The semiconductor device 100 shown in FIG. 27 is different in that the thickness of the gate oxide film 42 located on the channel epi layer 30 differs depending on the part.

More specifically, the thickness of the gate oxide film 42 located above the n ⁺ layers (33, 34) formed in the channel epi layer 30 is larger than the thickness of the gate oxide film 42 located above the channel region 40. Is also thicker. Specifically, in the gate oxide film 42, the portion 42 c located above the first portion 33 and the portion 42 b located above the second portion 34 are larger than the thickness of the portion 42 a located above the channel region 40. Also thick.

  In the semiconductor device 200 shown in FIG. 2, the gate capacitance of the portion located above the JFET region 60 is relatively large, which makes it difficult to operate the semiconductor device 200 at high speed. On the other hand, in the semiconductor device 100 shown in FIG. 27, since the portion 42b of the gate oxide film 42 located above the JFET region 60 is thickened, the gate capacitance can be reduced, resulting in high speed operation. It can be realized. The thickness of the thick portion 42 b of the gate oxide film 42 is, for example, 1.2 to 2 times the thickness of the channel region 40 of the gate oxide film 42.

The structure 100 shown in FIG. 27 can be realized by using accelerated oxidation of the gate oxide film. The enhanced oxidation of the gate oxide film is a phenomenon that a region in which impurities (for example, As) are implanted in silicon has a high oxidation rate even under the same oxidation conditions. When the SiC substrate is oxidized at 1000 to 1200 ° C., the inventor of the present application has the same oxidation rate as that of the non-implanted region in comparison with the non-implanted region compared to the non-implanted region. It was experimentally found that the oxidation rate was about 1.2 to 2 times higher. By utilizing this phenomenon of accelerated oxidation found by the present inventor, the dopant of the n ⁺ layer (33, 34) formed in the channel epi layer 30 is phosphorus, and the gate oxide film 42 is formed by the enhanced oxidation by the phosphorus. The thickness of can be changed depending on the part.

  Further, the semiconductor device 100 of the present embodiment can be modified as shown in FIG. The semiconductor device 100 shown in FIG. 28 is different in that it includes a region 62 in which a first conductivity type (here, n-type) dopant is implanted in a JFET region 60. Here, the concentration of the n-type dopant in the region 62 is higher than the concentration of the n-type dopant in the drift epi layer 20.

Further, in the example shown in FIG. 28, the concentration of the n-type dopant implanted into the JFET region 60 (the dopant concentration in the region 62) is the second conductivity type (here, p-type) dopant contained in the well region 22. The concentration is preferably lower than the dopant concentration of the well region 22. Further, the region 62 (n ⁻ -type doped layer 62) is located below the n ⁺ layer 34 formed in the channel epilayer 30. The region 62 in the present embodiment is formed by implanting the JFET region 60 at a concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ with energy of 30 keV to 700 keV.

  In the semiconductor device 100 shown in FIG. 28, the dopant concentration in the JFET region 60 (more specifically, the dopant concentration in the region 62) is made higher than the concentration of the n-type dopant in the drift epi layer 20. Thus, the on-resistance can be reduced as compared with the semiconductor device 100 shown in FIG. Further, in the case where the same JFET resistance is used, in the semiconductor device 100 shown in FIG. 28, the JFET interval can be reduced, so that the chip area can be reduced. Note that the features of the semiconductor device 100 shown in FIG. 28 can also be included in the semiconductor device 100 in the above-described embodiment.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible.

  INDUSTRIAL APPLICABILITY The present invention is suitable for a semiconductor device that can alleviate deterioration in on-resistance characteristics due to current concentration, and particularly for a power semiconductor device made of silicon carbide used for high withstand voltage and large current.

Sectional drawing which shows typically the structure of the semiconductor device 100 which concerns on embodiment of this invention. Sectional drawing which shows the structure of the comparative example 200 Sectional drawing for demonstrating operation | movement of the semiconductor device 100 which concerns on embodiment of this invention. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the semiconductor device 100 of this embodiment. Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. Sectional drawing which shows typically the structure of the channel epilayer 30 in which the delta dope layer 35A was formed Sectional drawing which shows typically the structure of the channel epilayer 30 in which the delta dope layers 35A and 35B were formed Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. (A) And (b) is process sectional drawing for demonstrating the manufacturing method of the modification of the semiconductor device 100 of this embodiment. Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. Sectional drawing which shows typically the modification of the semiconductor device 100 which concerns on embodiment of this invention. Sectional drawing which shows the structure of the conventional silicon carbide semiconductor device 1000

Explanation of symbols

10 Semiconductor substrate 20 Silicon carbide epitaxial layer (drift epi layer)
22 well region 24 source region 26 contact region 28 source electrode 30 channel epitaxial layer (channel epi layer)
35 Delta doped layer 40 Channel region 42 Gate oxide film 44 Gate electrode 50 Drain electrode 52 Interlayer insulating film 53 Photo resist 55 Contact metal 60 JFET region 62 n ^- type doped layer 70 Implant mask 90 Cap film 100 Semiconductor device 1000 Semiconductor device

Claims (13)

A first conductivity type semiconductor substrate having a main surface and a back surface opposite to the main surface, and made of silicon carbide;
A silicon carbide epitaxial layer of a first conductivity type formed on a main surface of the semiconductor substrate and having a dopant concentration lower than that of the semiconductor substrate;
A second conductivity type well region formed in a part of the silicon carbide epitaxial layer;
A source region of a first conductivity type formed in a part of the well region;
With
A channel epitaxial layer made of silicon carbide is formed on the silicon carbide epitaxial layer, the well region, and the source region,
A portion of the channel epitaxial layer located on the well region functions as a channel region,
A source electrode is formed on the source region,
The semiconductor device, wherein the source electrode covers at least a side surface of the channel epitaxial layer. The semiconductor device according to claim 1, wherein the source electrode covers a part of the upper surface in addition to the side surface of the channel epitaxial layer. The semiconductor device according to claim 1, wherein at least one delta doped layer is formed in the channel epitaxial layer. The dopant of the first conductivity type is implanted into both a first portion located on the source region and a second portion located on the silicon carbide epitaxial layer in the channel epitaxial layer. 4. The semiconductor device according to any one of items 1 to 3. 5. The semiconductor device according to claim 1, wherein a side surface of the channel epitaxial layer is formed in a tapered shape. A gate oxide film is formed on the channel epitaxial layer,
A gate electrode is formed on the gate oxide film,
The semiconductor device according to claim 1, wherein a drain electrode is formed on a back surface of the semiconductor substrate. The thickness of the gate oxide film located above the first part and the second part into which the dopant of the first conductivity type is implanted is larger than the thickness of the gate oxide film located above the channel region. The semiconductor device according to claim 6, wherein the semiconductor device is thick. 8. The semiconductor device according to claim 1, wherein a region sandwiched between the well regions in the surface portion of the silicon carbide epitaxial layer functions as a JFET region. 9. The first conductivity type dopant is implanted into the JFET region, and the concentration of the first conductivity type dopant in the JFET region is smaller than the concentration of the second conductivity type dopant contained in the well region, The semiconductor device according to claim 6, wherein the concentration is higher than a dopant concentration of the silicon carbide epitaxial layer. 10. The semiconductor device according to claim 1, wherein upper surfaces of the silicon carbide epitaxial layer, the well region, and the source region are located on the same plane. Forming a first conductivity type silicon carbide epitaxial layer having a dopant concentration lower than that of the semiconductor substrate on the main surface of the first conductivity type semiconductor substrate made of silicon carbide;
A step (b) of forming a second conductivity type well region in a part of the silicon carbide epitaxial layer;
Forming a first conductivity type source region in a part of the well region;
Forming a channel epitaxial layer made of silicon carbide on the silicon carbide epitaxial layer, the well region, and the source region;
Forming a source electrode on the source region (e);
Including
In the step (e), the source electrode is formed so as to cover at least a side surface of the channel epitaxial layer. The method of manufacturing a semiconductor device according to claim 11, wherein, in the step (e), the source electrode is formed so as to cover a part of the upper surface in addition to the side surface of the channel epitaxial layer. The step (e)
Forming a gate oxide film on the channel epitaxial layer;
Forming a gate electrode on the gate oxide film;
Forming an interlayer insulating film on the main surface of the semiconductor substrate on which the source region is formed so as to cover the gate electrode, the gate oxide film, and the channel epitaxial layer;
Exposing the end portion of the channel epitaxial layer from the interlayer insulating film by etching the interlayer insulating film;
Forming a metal film so as to cover the exposed end of the channel epitaxial layer, the interlayer insulating film, and the silicon carbide epitaxial layer;
Heat-treating the metal film;
The manufacturing method of the semiconductor device of Claim 11 containing this.

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