JP2010087133A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same which can enhance an isolation breakdown strength between a source region and a drain region of a planar gate type MOSFET and a semiconductor substrate without increasing an on resistance Ron of a trench gate type VDMOSFET. <P>SOLUTION: In a PMOS region 17, an N-type well region 20 is formed on a surface part of a deep well region 16. A P-type buried layer 36 is formed in contact with the deep well region 16 below of the deep well region 16. Thus, a thickness of a p-type region increases below the N-type well region 20. As a result, it is possible to enhance the isolation breakdown strength between the N-type well region 20 and an N-type semiconductor substrate 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a trench gate type VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor) and a planar gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are mixedly mounted, and a manufacturing method thereof.

For example, in an intelligent power device, a trench gate type VDMOSFET, which is a high breakdown voltage power MOSFET, and a CMOS (Complementary Metal Oxide Semiconductor) circuit may be mounted together.
FIG. 5 is a schematic cross-sectional view showing the structure of a semiconductor device in which a trench gate type VDMOSFET and a CMOS circuit are mixedly mounted.

The semiconductor device 101 includes an N ⁺ type (relatively high concentration N type) semiconductor substrate 102. On the semiconductor substrate 102, an N-type epitaxial layer 103 is stacked. A LOCOS oxide film 106 that separates the VDMOS region 104 and the CMOS region 105 is selectively formed on the surface of the epitaxial layer 103.
In the VDMOS region 104, a trench gate type VDMOSFET 107 is formed.

In the VDMOS region 104, a P-type body region 108 is formed in the surface layer portion of the epitaxial layer 103. In the VDMOS region 104, a trench 109 is formed in the epitaxial layer 103. The trench 109 penetrates the body region 108 and the deepest part reaches the epitaxial layer 103. A gate insulating film 110 is formed on the bottom and side surfaces of the trench 109. A gate electrode 111 is embedded in the trench 109 via a gate insulating film 110. An N ⁺ type source region 112 is formed in the surface layer portion of the body region 108. In the surface layer portion of the body region 108, a P ⁺ -type (relatively high-concentration P-type) body contact region 113 is provided in a layer thickness direction at a position spaced from the trench 109. It is formed through.

  In the CMOS region 105, a P-type deep well region 114 is formed in the surface layer portion of the epitaxial layer 103. A LOCOS oxide film 117 for separating the NMOS region 115 and the PMOS region 116 is formed on the surface of the deep well region 114. The planar gate type N-channel MOSFET 118 and the planar gate type P-channel MOSFET 119 constituting the CMOS circuit are formed in the NMOS region 115 and the PMOS region 116, respectively.

In the NMOS region 115, a P-type well region 120 is formed in the surface layer portion of the deep well region 114. In the surface layer portion of the P-type well region 120, an N ⁺ -type source region 121 and a drain region 122 are formed with a space therebetween. A gate insulating film (not shown) is formed on a region (channel region) between the source region 121 and the drain region 122. A gate electrode 124 is formed on the gate insulating film. A sidewall 125 is formed around the gate electrode 124.

In the PMOS region 116, an N-type well region 126 is formed in the surface layer portion of the deep well region 114. In the surface layer portion of the N-type well region 126, a P ⁺ -type source region 127 and a drain region 128 are formed with a space therebetween. A gate insulating film (not shown) is formed on a region (channel region) between the source region 127 and the drain region 128. A gate electrode 130 is formed on the gate insulating film. A sidewall 131 is formed around the gate electrode 130.

  An interlayer insulating film (not shown) is formed on the epitaxial layer 103 so as to cover the entire surface thereof. Through the interlayer insulating film, plugs 131, 132, 133, 134, 135 connected to the source region 112, the source region 121, the drain region 122, the source region 127, and the drain region 128, respectively, pass through. The plug 131 is connected (batting contact) across the source region 112 and the body contact region 113. Source wirings 136, 137, and 138 are formed on the interlayer insulating film. Plugs 131, 132, and 134 are connected to source wirings 136, 137, and 138, respectively. A wiring 139 connected to the plugs 133 and 135 is formed on the interlayer insulating film.

A drain electrode 140 of a trench gate type VDMOSFET 107 is formed on the back surface of the semiconductor substrate 102.
Japanese Patent Laid-Open No. 2007-150081

  The on-resistance Ron of the trench gate type VDMOSFET 107 is one of performance evaluation indexes. The on-resistance Ron is the total resistance of the carrier moving path from the source wiring 136 to the drain electrode 140. That is, the on-resistance Ron includes the metal resistance Rm of the source wiring 136 and the plug 131, the contact resistance Rc of the connection portion between the plug 131 and the source region 112, the source resistance Rs of the source region 112, and the channel region formed in the body region 108. Channel resistance Rch, drift resistance Rdr of the drift region below the body region 108 in the epitaxial layer 103, and substrate resistance Rsub of the semiconductor substrate 102.

  Since the semiconductor substrate 102 becomes the drain region of the trench gate type VDMOSFET 107, a drain voltage is applied to the entire semiconductor substrate 102. Therefore, between the source region 121 and drain region 122 of the planar gate type N-channel MOSFET 118 and the semiconductor substrate 102 (the portion below the deep well region 114 in the epitaxial layer 103), the source region 127 and drain of the planar gate type P-channel MOSFET 119. It is necessary to ensure a large isolation breakdown voltage between the region 128 and the deep well region 114 and between the N-type well region 126 and the semiconductor substrate 102.

  For example, in order to increase the isolation breakdown voltage between the source region 127 and drain region 128 and the deep well region 114, the depth and impurity concentration of the N-type well region 126 may be increased. However, when the depth and impurity concentration of the N-type well region 126 are increased, the depth of the deep well region 114 (the deep well region 114) is maintained in order to maintain the isolation breakdown voltage between the N-type well region 126 and the semiconductor substrate 102. The thickness of the lower portion of the N-type well region 126 in (1) must be increased. Therefore, the thickness of the epitaxial layer 103 increases by the increase in the depth of the N-type well region 126 and the deep well region 114. As a result, when the thickness of the drift region below the body region 108 increases, the drift resistance Rdr of the trench gate type VDMOSFET 107 increases, and consequently the on-resistance Ron increases.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the isolation breakdown voltage between the source region and drain region of the planar gate type MOSFET and the semiconductor substrate without increasing the on-resistance Ron of the trench gate type VDMOSFET. And a method of manufacturing the same.

  According to a first aspect of the present invention, there is provided a first conductive type semiconductor substrate, a first conductive type semiconductor layer stacked on the semiconductor substrate, and a surface of the semiconductor layer. An element isolation portion for separating the first region for the trench gate type VDMOSFET and the second region for the planar gate type MOSFET, and the second conductivity formed in the surface layer portion of the semiconductor layer in the first region. A body region of the mold, a trench penetrating the body region from the surface thereof, penetrating the body region, a trench gate insulating film formed on a bottom surface and a side surface of the trench, and the trench gate insulating film in the trench A trench gate electrode embedded via the first conductive type trench gate type V formed on the side of the trench in the surface layer portion of the body region A source region for MOSFET, a second conductivity type deep well region formed in a surface layer portion of the semiconductor layer in the second region, and a first conductivity type selectively formed in a surface layer portion of the deep well region First well region, a second conductivity type first planar gate MOSFET source region selectively formed in the surface layer portion of the first well region, and the first well region in the surface layer portion of the first well region. A drain region for a first planar gate MOSFET of a second conductivity type selectively formed with a gap from a source region for a planar gate MOSFET, the source region for the first planar gate MOSFET, and the first planar gate A first planar gate insulating film formed on a surface of a region between the drain region for the type MOSFET, and on the first planar gate insulating film A first planar gate electrode formed, and formed below the deep well region, in contact with the deep well region, and having a second conductivity type higher than an impurity concentration of the second conductivity type in the deepest portion of the deep well region. A semiconductor device including a buried layer having an impurity concentration.

In this semiconductor device, a first conductivity type semiconductor layer is stacked on a first conductivity type semiconductor substrate. On the surface of the semiconductor layer, an element isolation portion for separating the first region for the trench gate type VDMOSFET and the second region for the planar gate type MOSFET is formed.
In the first region, a body region of the second conductivity type is formed in the surface layer portion of the semiconductor layer. A trench that penetrates the body region in the thickness direction is formed in the body region. The deepest portion of the trench reaches a portion (drift region) below the body region in the semiconductor layer. A trench gate electrode is embedded in the trench via a trench gate insulating film. That is, a trench gate type VDMOSFET having a semiconductor substrate as a drain region is formed in the first region.

  In the second region, a second conductivity type deep well region is formed in the surface layer portion of the semiconductor layer. A first well region of the first conductivity type is selectively formed on the surface layer portion of the deep well region. A source region for the first planar gate MOSFET of the second conductivity type and a drain region for the first planar gate MOSFET are selectively formed on the surface layer portion of the first well region with a space therebetween. On the surface of the region (channel region) between the source region for the first planar gate MOSFET and the drain region for the first planar gate MOSFET, the first planar gate electrode is interposed via the first planar gate insulating film. Is provided. That is, the first planar gate type MOSFET is formed in the second region.

A second conductivity type buried layer is formed below the second conductivity type deep well region in contact with the deep well region. This increases the thickness of the region having the second conductivity type below the first well region. As a result, the isolation breakdown voltage between the first well region and the semiconductor substrate can be improved.
Also, by increasing the depth and impurity concentration of the first well region, the isolation voltage between the first planar gate MOSFET source region and the first planar gate MOSFET drain region and the deep well region is improved. be able to. The embedded layer enlarges the distance between the first well region and the semiconductor substrate. Therefore, even if the depth and impurity concentration of the first well region are increased, the gap between the first well region and the semiconductor substrate is increased. The isolation breakdown voltage can be maintained.

The buried layer is formed below the deep well region and is not formed below the body region. Therefore, since the thickness of the semiconductor layer does not increase, the drift resistance Rdr of the trench gate type VDMOSFET is not increased.
Therefore, without increasing the on-resistance Ron of the trench gate type VDMOSFET, the isolation breakdown voltage between the source region and drain region of the first planar gate type MOSFET and the semiconductor substrate (the source region for the first planar gate type MOSFET and the first region). The isolation breakdown voltage between the planar gate MOSFET drain region and the deep well region and the isolation breakdown voltage between the first well region and the semiconductor substrate can be improved.

The buried layer has an impurity concentration of the first conductivity type higher than the impurity concentration of the first conductivity type in the deepest portion of the deep well region. Thereby, the resistance of the region having the second conductivity type below the first well region can be lowered, and the surge resistance can be improved by reducing the resistance.
In the vicinity of the boundary between the semiconductor substrate and the semiconductor layer, the impurity of the first conductivity type diffuses from the semiconductor substrate to the semiconductor layer, so that the impurity concentration of the first conductivity type is increased so as to approach the semiconductor substrate. .

  According to a second aspect of the present invention, it is preferable that the buried layer reaches at least a portion where the impurity concentration changes. As a result, the deepest portion of the buried layer can be brought close to the semiconductor substrate, and the thickness of the buried layer can be increased without increasing the thickness of the semiconductor layer. As a result, the isolation breakdown voltage between the source region and drain region of the first planar gate MOSFET and the semiconductor substrate can be further improved without increasing the on-resistance Ron of the trench gate VDMOSFET.

More preferably, the buried layer reaches at least the semiconductor substrate. Thereby, the thickness of the buried layer can be further increased without increasing the thickness of the semiconductor layer, and the isolation breakdown voltage between the source region and drain region of the first planar gate MOSFET and the semiconductor substrate can be reduced. This can be further improved.
As described in claim 4, it is more preferable that the buried layer straddles the semiconductor substrate and the semiconductor layer. As a result, the thickness of the buried layer can be further increased without increasing the thickness of the semiconductor layer, and the isolation breakdown voltage between the source region and drain region of the first planar gate MOSFET and the semiconductor substrate can be reduced. This can be further improved.

  6. The semiconductor device according to claim 5, wherein the semiconductor device includes a second well region of a second conductivity type selectively formed separately from the first well region in a surface layer portion of the deep well region, A first conductivity type second planar gate type MOSFET source region selectively formed in the surface layer portion of the 2-well region, and selectively formed in the surface layer portion of the second well region with a space from the source region. Formed on the surface of the drain region for the second planar gate MOSFET having the first conductivity type and the source region for the second planar gate MOSFET and the drain region for the second planar gate MOSFET. And a second planar gate insulating film and a second planar gate electrode formed on the second planar gate insulating film. In this case, since the buried layer is provided, the thickness of the region having the second conductivity type is increased below the source region for the second planar gate MOSFET and the drain region for the second planar gate MOSFET. As a result, the isolation breakdown voltage between the source region for the second planar gate MOSFET and the drain region for the second planar gate MOSFET and the semiconductor substrate can be improved.

  The deep well region and the buried layer can be manufactured by the method for manufacturing a semiconductor device according to claim 7. This manufacturing method is a method of manufacturing a semiconductor device in which a trench gate type VDMOSFET and a planar gate type MOSFET are mixed, and a step of stacking a first conductive type first semiconductor layer on a first conductive type semiconductor substrate. And a step of doping the first semiconductor layer with a second conductivity type impurity in a region where the planar gate MOSFET is formed, and diffusing the second conductivity type impurity doped in the first semiconductor layer by heat treatment. A step of forming a buried layer, a step of removing an oxide film formed on a surface of the first semiconductor layer during the heat treatment, and a first conductive layer on the first semiconductor layer after the removal of the oxide film. And a step of doping the second semiconductor layer with a second conductivity type impurity in the step of laminating the second semiconductor layer of the type and the region where the planar gate type MOSFET is formed. When, and a step of said second conductivity type impurity is diffused by heat treatment (drive-in), which is doped in the second semiconductor layer, forming a deep well on the buried layer.

  According to a sixth aspect of the present invention, there is provided a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer stacked on the semiconductor substrate, a first region for a trench gate type VDMOSFET, and a planar gate type MOSFET. An element isolation part for isolating the second region, a second conductivity type body region formed in a surface layer portion of the semiconductor layer in the first region, and the body region being dug down from the surface, A trench penetrating the body region; a trench gate insulating film formed on the bottom and side surfaces of the trench; a trench gate electrode embedded in the trench through the trench gate insulating film; and a surface layer of the body region In the first conductivity type trench gate type VDMOSFET source region formed on the side of the trench, and in the second region, A second conductivity type region formed in the semiconductor layer; a first conductivity type well region selectively formed in a surface layer portion of the second conductivity type region; and a surface layer portion of the well region. A second conductivity type planar gate MOSFET, and a second conductivity type planar gate MOSFET selectively formed on the surface layer of the well region at a distance from the planar gate MOSFET source region. Drain region, a planar gate insulating film formed on the surface of the region between the planar gate MOSFET source region and the planar gate MOSFET drain region, and formed on the planar gate insulating film And a planar gate electrode, wherein the second conductivity type region is at least in contact with the semiconductor substrate.

According to this configuration, the first conductivity type semiconductor layer is stacked on the first conductivity type semiconductor substrate. On the surface of the semiconductor layer, an element isolation portion for separating the first region for the trench gate type VDMOSFET and the second region for the planar gate type MOSFET is formed.
In the first region, a body region of the second conductivity type is formed in the surface layer portion of the semiconductor layer. A trench that penetrates the body region in the thickness direction is formed in the body region. The deepest portion of the trench reaches a portion (drift region) below the body region in the semiconductor layer. A trench gate electrode is embedded in the trench via a trench gate insulating film. That is, a trench gate type VDMOSFET having a semiconductor substrate as a drain region is formed in the first region.

  In the second region, a second conductivity type deep well region is formed in the semiconductor layer. A well region of the first conductivity type is selectively formed in the surface layer portion of the deep well region. A source region for a planar gate type MOSFET and a drain region for a planar gate type MOSFET are selectively formed on the surface layer portion of the well region at intervals from each other. A planar gate electrode is provided on the surface of a region (channel region) between the planar gate MOSFET source region and the planar gate MOSFET drain region via a planar gate insulating film. That is, a planar gate type MOSFET is formed in the second region.

  The second conductivity type region is in contact with at least the semiconductor substrate. In other words, the second conductivity type region is formed over the entire region in the thickness direction of the semiconductor layer in the second region. Thereby, it is possible to ensure a large thickness of the second conductivity type region below the well region. As a result, the isolation breakdown voltage between the well region and the semiconductor substrate can be improved without increasing the thickness of the semiconductor layer.

  Further, by increasing the depth of the well region and the impurity concentration, the isolation breakdown voltage between the planar gate MOSFET source region and the planar gate MOSFET drain region and the second conductivity type region can be improved. Since the thickness of the second conductivity type region below the well region is large, the isolation breakdown voltage between the well region and the semiconductor substrate can be maintained even when the depth and impurity concentration of the well region are increased.

  Accordingly, the isolation breakdown voltage between the source region and drain region of the planar gate type MOSFET and the semiconductor substrate (the source region and the planar region for the planar gate type MOSFET) is increased without increasing the on-resistance Ron (drift resistance Rdr) of the trench gate type VDMOSFET. The isolation breakdown voltage between the gate MOSFET drain region and the second conductivity type region and the isolation breakdown voltage between the well region and the semiconductor substrate can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 1 includes, for example, a trench gate type VDMOSFET (hereinafter referred to as “VDMOS”) 2, a planar gate type P channel MOSFET (hereinafter referred to as “PMOS”) 3 constituting a CMOS circuit, and a planar gate type N channel MOSFET (hereinafter referred to as “PMOS”). "NMOS") 4) is an intelligent device. The semiconductor device 1 includes an N ⁺ type semiconductor substrate 5. The semiconductor substrate 5 is, for example, a silicon (Si) substrate.

On the semiconductor substrate 5, an N-type silicon layer 6 made of silicon doped with an N-type impurity at a lower concentration than the semiconductor substrate 5 is laminated. The thickness of the silicon layer 6 is, for example, 5.0 μm. A LOCOS oxide film 9 that separates the VDMOS region 7 and the CMOS region 8 is selectively formed on the surface of the silicon layer 6.
The VDMOS 2 is formed in the VDMOS region 7.

In the VDMOS region 7, a P-type body region 10 is formed in the surface layer portion of the silicon layer 6. The depth of the body region 10 is, for example, 1 μm.
In the VDMOS region 7, a plurality of trenches 11 are formed in the silicon layer 6. The plurality of trenches 11 each extend in a straight line and are provided in parallel at regular intervals. Each trench 11 digs down the silicon layer 6 from the surface, penetrates through the body region 10, and the deepest part reaches the silicon layer 6 (drift region) below the body region 10.

A trench gate insulating film 12 made of SiO ₂ (silicon oxide) is formed on the inner surface (side surface and bottom surface) of the trench 11. A trench gate electrode 13 made of doped polysilicon (for example, polysilicon doped with an N-type impurity) is buried in the trench 11 with a trench gate insulating film 12 interposed therebetween.
A silicon oxide film is also formed on the surfaces of body region 10 and trench gate electrode 13. The silicon oxide film on the surface of the body region 10 is integrated with the trench gate insulating film 12.

An N ⁺ type source region 14 is formed in the surface layer portion of the body region 10. The source region 14 is formed in the entire region excluding the body contact region 15 described below on both sides in a direction orthogonal to the gate width direction (direction perpendicular to the paper surface of FIG. 1) of each trench gate electrode 13. Thereby, in the VDMOS region 7, the trenches 11 and the source regions 14 are alternately formed in a direction orthogonal to the gate width direction.

Further, a P ⁺ -type body contact region 15 doped with a P-type impurity at a higher concentration than the body region 10 is formed at a position spaced from the trench 11 in the surface layer portion of the body region 10. Yes.
In the CMOS region 8, a P-type deep well region 16 is formed in the surface layer portion of the silicon layer 6. The depth of the deep well region 16 is, for example, 4.0 μm. A LOCOS oxide film 19 for separating the PMOS region 17 and the NMOS region 18 is formed on the surface of the deep well region 16. The PMOS 3 and the NMOS 4 constituting the CMOS circuit are formed in the PMOS region 17 and the NMOS region 18, respectively.

In the PMOS region 17, an N-type well region 20 is formed in the surface layer portion of the deep well region 16. A P ⁺ -type source region 21 and a P ⁺ -type drain region 22 are formed in the surface layer portion of the N-type well region 20 with a space therebetween.
A region between the P ⁺ type source region 21 and the P ⁺ type drain region 22 is a channel region, and a first planar gate insulating film 23 made of SiO ₂ is formed on the surface of the channel region. . A first planar gate electrode 24 made of doped polysilicon is formed on the first planar gate insulating film 23. A sidewall 25 made of SiN (silicon nitride) is formed around the first planar gate insulating film 23 and the first planar gate electrode 24.

Further, an N ⁺ type body contact region 26 doped with an N type impurity at a higher concentration than the N type well region 20 is formed in the surface layer portion of the N type well region 20 so as to be spaced from the P ⁺ type source region 21. ing. A LOCOS oxide film 27 is formed on the surface of the region between the P ⁺ type source region 21 and the body contact region 26.
In the NMOS region 18, a P-type well region 28 is formed in the surface layer portion of the deep well region 16. In the surface layer portion of the P-type well region 28, an N ⁺ -type source region 29 and an N ⁺ -type drain region 30 are formed with a space therebetween.

A region between the N ⁺ type source region 29 and the N ⁺ type drain region 30 is a channel region, and a second planar gate insulating film 31 made of SiO ₂ is formed on the surface of the channel region. . A second planar gate electrode 32 made of doped polysilicon is formed on the second planar gate insulating film 31. A sidewall 33 made of SiN (silicon nitride) is formed around the second planar gate insulating film 31 and the second planar gate electrode 32.

Further, in the surface layer portion of the P-type well region 28, a P ⁺ -type body contact region 34 doped with a P-type impurity at a higher concentration than the P-type well region 28 is formed so as to be separated from the N ⁺ -type source region 29. ing. A LOCOS oxide film 35 is formed on the surface of the region between the N ⁺ type source region 29 and the body contact region 34.
A P type buried layer 36 having a P type impurity concentration higher than the P type impurity concentration in the deepest portion of the deep well region 16 is formed below the deep well region 16. The buried layer 36 has the same planar size as the deep well region 16 and is in contact with the deep well region 16. The deepest portion of the buried layer 36 reaches the surface layer portion of the semiconductor substrate 5 and bites into the surface layer portion.

An interlayer insulating film (not shown) is formed on the silicon layer 6 so as to cover the entire surface. The interlayer insulating film is connected to the source region 14, the P ⁺ type source region 21, the P ⁺ type drain region 22, the body contact region 26, the N ⁺ type source region 29, the N ⁺ type drain region 30 and the body contact region 34. Plugs 37, 38, 39, 40, 41, 42, and 43 are embedded. The plug 37 is connected (batting contact) across the source region 14 and the body contact region 15. Wirings 44, 45, 46, 47, 48 and 49 are formed on the interlayer insulating film. The wirings 44, 45, 46, 47, and 48 are connected to plugs 37, 38, 40, 41, and 43, respectively. The wiring 49 is connected to the plugs 39 and 42 in common.

A drain electrode 50 of the VDMOS 2 is formed on the back surface of the semiconductor substrate 5.
2A to 2M are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG.
First, as shown in FIG. 2A, a first epitaxial layer 51 made of silicon doped with an N-type impurity is formed on the surface of the semiconductor substrate 5 by an epitaxial growth method. Subsequently, a first oxide film 52 made of SiO ₂ is formed on the first epitaxial layer 51 by a thermal oxidation method.

  Next, as shown in FIG. 2B, a resist pattern 53 is formed on the first oxide film 52. Then, the first oxide film 52 is selectively removed by etching using the resist pattern 53 as a mask. Thereafter, a P-type impurity (for example, boron) is implanted into the exposed portion of first epitaxial layer 51 by ion implantation using first oxide film 52 and resist pattern 53 as a mask.

  After the resist pattern 53 is removed, heat treatment is performed. By this heat treatment, as shown in FIG. 2C, the P-type impurity implanted into the first epitaxial layer 51 is diffused. By this diffusion, a P-type buried layer 36 is formed in a region straddling the semiconductor substrate 5 and the first epitaxial layer 51. Further, a thermal oxide film 54 is formed on the surfaces of the first oxide film 52 and the buried layer 36 by the heat treatment. The thermal oxide film 54 grows on the buried layer 36 at a large rate. As a result, the step between the surface of the first oxide film 52 after the heat treatment and the surface of the thermal oxide film 54 is smaller than the step between the surface of the first oxide film 52 and the surface of the first epitaxial layer 51 before the heat treatment. .

  As shown in FIG. 2D, the first oxide film 52 and the thermal oxide film 54 are removed by etching using hydrofluoric acid (HF). Thereafter, a second epitaxial layer 55 made of silicon doped with an N-type impurity is formed on the first epitaxial layer 51 by an epitaxial growth method. The second epitaxial layer 55 is integrated with the first epitaxial layer 51 to become the silicon layer 6.

Next, as shown in FIG. 2E, a through film 56 is formed on the surface of the silicon layer 6 by a thermal oxidation method. Then, a resist pattern 57 having an opening in a portion facing the buried layer 36 is formed on the through film 56. Thereafter, a P-type impurity is implanted into the exposed portion of the silicon layer 6 by ion implantation using the resist pattern 57 as a mask.
Subsequently, as shown in FIG. 2F, the P-type impurity implanted into the silicon layer 6 is diffused (drive-in) by heat treatment. By this diffusion, a deep well region 16 in contact with the buried layer 36 is formed in the silicon layer 6 above the buried layer 36.

After the formation of the deep well region 16, as shown in FIG. 2G, a silicon nitride film 58 is formed on the through film 56 by LPCVD (Low Pressure Chemical Vapor Deposition) method.
Thereafter, a resist pattern is formed on the silicon nitride film 58, and the silicon nitride film 58 and the through film 56 are selectively removed by etching using the resist pattern as a mask. Then, heat treatment is performed. As a result, LOCOS oxide films 9, 19, 27, and 35 are formed on the surface of the silicon layer 6 as shown in FIG. 2H. That is, LOCOS oxide films 9, 19, 27, and 35 are formed on the surface of the silicon layer 6 by the LOCOS method. By forming the LOCOS oxide film 9, the VDMOS region 7 and the CMOS region 8 are partitioned. Further, the PMOS region 17 and the NMOS region 18 are partitioned by forming the LOCOS oxide film 19.

Next, as shown in FIG. 2I, a trench 11 is formed in the silicon layer 6 in the VDMOS region 7 by photolithography and etching.
Thereafter, as shown in FIG. 2J, a trench gate insulating film 12 is formed on the inner surface of the trench 11 by thermal oxidation. Then, doped polysilicon is deposited on the silicon layer 6 so as to fill the trench 11 by a CVD (Chemical Vapor Deposition) method. Then, a trench gate electrode 13 embedded in the trench 11 via the trench gate insulating film 12 is formed by etch back of the deposited layer of doped polysilicon. After the formation of the trench gate electrode 13, the silicon nitride film 58 is removed.

  After removing the silicon nitride film 58, a P-type impurity is implanted into the surface layer portion of the silicon layer 6 in the VDMOS region 7 by ion implantation. Further, a P-type impurity is implanted into the surface layer portion of the deep well region 16 in the NMOS region 18 by ion implantation. The implantation of these P-type impurities may be performed in the same process. Further, when the P-type impurity concentrations injected into the VDMOS region 7 and the NMOS region 18 are different, it may be performed in a separate process of the P-type impurity to each region. Further, an N-type impurity (for example, arsenic) is implanted into the surface layer portion of the deep well region 16 in the PMOS region 17 by ion implantation. Thereafter, heat treatment is performed. By this heat treatment, as shown in FIG. 2K, body region 10, N-type well region 20 and P-type well region 28 are formed.

Thereafter, the through film 56 is removed by etching using hydrofluoric acid. Then, the first planar gate insulating film 23 and the second planar gate insulating film 31 are formed on the surfaces of the N-type well region 20 and the P-type well region 28 by thermal oxidation, respectively. At this time, a silicon oxide film is also formed on the surfaces of the body region 10 and the trench gate electrode 13.
Thereafter, as shown in FIG. 2L, the first planar gate electrode 24 and the second planar gate electrode 32 are respectively formed on the first planar gate insulating film 23 and the second planar gate insulating film 31 by CVD, photolithography and etching. Is formed. Next, a resist pattern 59 is formed on the silicon layer 6. Then, an N-type impurity is implanted into the exposed portion of the silicon layer 6 by ion implantation using the resist pattern 59 as a mask. As a result, the source region 14, the N ⁺ type source region 29, the N ⁺ type drain region 30 and the body contact region 26 are formed.

Thereafter, as shown in FIG. 2M, a resist pattern 60 is formed on the silicon layer 6. Then, by ion implantation, P-type impurities are implanted into the exposed portion of the silicon layer 6 using the resist pattern 60 as a mask. Thereby, the body contact region 15, the P ⁺ type source region 21, the P ⁺ type drain region 22 and the body contact region 34 are formed.

Thereafter, plugs 37 to 43, wirings 44 to 49, drain electrode 50, and the like are formed, and semiconductor device 1 having the structure shown in FIG. 1 is obtained.
In the semiconductor device 1, a P-type buried layer 36 is formed in contact with the deep well region 16 below the P-type deep well region 16. This increases the thickness of the P-type region below the N-type well region 20. As a result, the isolation breakdown voltage between the N-type well region 20 and the N-type semiconductor substrate 5 can be improved.

Further, by increasing the depth and impurity concentration of the N-type well region 20, the isolation breakdown voltage between the P ⁺ -type source region 21 and the P ⁺ -type drain region 22 and the deep well region 16 can be improved. Since the space between the N-type well region 20 and the semiconductor substrate 5 is expanded by the buried layer 36, the N-type well region 20 and the semiconductor can be increased even if the depth and impurity concentration of the N-type well region 20 are increased. The isolation withstand voltage between the substrate 5 can be maintained.

The buried layer 36 is formed below the deep well region 16 and is not formed below the body region 10. Therefore, since the thickness of the silicon layer 6 does not increase, the drift resistance Rdr of the trench gate type VDMOSFET is not increased.
Therefore, the isolation breakdown voltage (P ⁺ -type source region 21 and P ⁺ -type drain between the P ⁺ -type source region 21 and P ⁺ -type drain region 22 of the PMOS 3 and the semiconductor substrate 5 is not increased without increasing the on-resistance Ron of the VDMOS ^2. The isolation breakdown voltage between the region 22 and the deep well region 16 and the isolation breakdown voltage between the N-type well region 20 and the semiconductor substrate 5 can be improved.

The buried layer 36 has a P-type impurity concentration higher than the P-type impurity concentration in the deepest portion of the deep well region 16. Thereby, the resistance of the P-type region below the N-type well region 20 can be lowered, and the surge resistance can be improved by reducing the resistance.
By providing the buried layer 36, the thickness of the region having the P type is increased below the N ⁺ type source region 29 and the N ⁺ type drain region 30. As a result, the isolation breakdown voltage between the N ⁺ type source region 29 and the N ⁺ type drain region 30 and the semiconductor substrate 5 can be improved.

As shown in FIG. 3, the buried layer 36 may be separated from the semiconductor substrate 5. In a region 71 in the vicinity of the boundary between the semiconductor substrate 5 and the silicon layer 6 indicated by a broken line in FIG. 3, N-type impurities diffuse from the semiconductor substrate 5 to the silicon layer 6, so that the N-type impurity concentration approaches the semiconductor substrate 5. It is changing to be higher.
When the buried layer 36 is provided apart from the semiconductor substrate 5, it is preferable that the buried layer 36 reaches at least the region 71 where the impurity concentration changes. As a result, the deepest portion of the buried layer 36 can be brought closer to the semiconductor substrate 5, and the thickness of the buried layer 36 can be increased without increasing the thickness of the silicon layer 6. As a result, the isolation breakdown voltage between the P ⁺ type source region 21 and the P ⁺ type drain region 22 of the PMOS 3 and the semiconductor substrate 5 can be improved without increasing the on-resistance Ron of the VDMOS ² .

Further, as shown in FIG. 4, the buried layer 36 may be in contact with the semiconductor substrate 5 without biting into the surface layer portion of the semiconductor substrate 5. In this structure, the thickness of the buried layer 36 can be further increased as compared with the structure shown in FIG. 3 without increasing the thickness of the silicon layer 6. As a result, the isolation breakdown voltage between the P ⁺ -type source region 21 and the P ⁺ -type drain region 22 of the PMOS 3 can be further improved without increasing the on-resistance Ron of the VDMOS ² .

However, as shown in FIG. 1, in the structure in which the buried layer 36 extends over the semiconductor substrate 5 and the silicon layer 6, the P ⁺ -type source region 21 and the P ⁺ -type drain region of the PMOS 3 than in the structure shown in FIG. 4. The isolation breakdown voltage between 22 and the semiconductor substrate 5 can be further improved.
Although the description of the embodiment of the present invention is as described above, various design changes can be made to the embodiment within the scope of the matters described in the claims.

  For example, in the semiconductor device shown in FIGS. 1, 3, and 4, a structure in which the conductivity type (P type, N type) of each semiconductor portion is inverted may be employed.

FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG. FIG. 2B is a schematic cross-sectional view showing a step subsequent to FIG. 2A. FIG. 2C is a schematic cross-sectional view showing a step subsequent to FIG. 2B. FIG. 2D is a schematic cross-sectional view showing a step subsequent to FIG. 2C. FIG. 2E is a schematic cross-sectional view showing a step subsequent to FIG. 2D. FIG. 2F is a schematic cross-sectional view showing a step subsequent to FIG. 2E. FIG. 2G is a schematic cross-sectional view showing a step subsequent to FIG. 2F. FIG. 2H is a schematic cross-sectional view showing a step subsequent to FIG. 2G. FIG. 2I is a schematic cross-sectional view showing a step subsequent to FIG. 2H. FIG. 2J is a schematic cross-sectional view showing a step subsequent to FIG. 2I. FIG. 2K is a schematic cross-sectional view showing a step subsequent to FIG. 2J. FIG. 2L is a schematic cross-sectional view showing a step subsequent to FIG. 2K. FIG. 2M is a schematic cross-sectional view showing a step subsequent to FIG. 2L. FIG. 3 is a schematic cross-sectional view showing a modification of the semiconductor device shown in FIG. FIG. 4 is a schematic cross-sectional view showing another modification of the semiconductor device shown in FIG. FIG. 5 is a schematic cross-sectional view showing the structure of a semiconductor device in which a trench gate type VDMOSFET and a CMOS circuit are mixedly mounted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Trench gate type VDMOSFET
3 Planar gate type P-channel MOSFET
4 Planar gate type N-channel MOSFET
5 Semiconductor substrate 6 Silicon layer (semiconductor layer)
7 VDMOS region (first region)
8 CMOS area (second area)
9 LOCOS oxide film (element isolation part)
DESCRIPTION OF SYMBOLS 10 Body region 11 Trench 12 Trench gate insulating film 13 Trench gate electrode 14 Source region (source region for trench gate type VDMOSFET)
16 Deep well region (second conductivity type region)
20 N-type well region (first well region)
21 P ⁺ type source region (first planar gate MOSFET source region, planar gate MOSFET source region)
22 P ⁺ type drain region (first planar gate type MOSFET drain region, planar gate type MOSFET drain region)
23 First planar gate insulating film (planar gate insulating film)
24 First planar gate electrode (planar gate electrode)
28 P-type well region (second well region)
29 N ⁺ type source region (source region for second planar gate MOSFET)
30 N ⁺ type drain region (drain region for second planar gate type MOSFET)
31 Second planar gate insulating film 32 Second planar gate electrode 36 Buried layer (second conductivity type region)
51 First epitaxial layer (first semiconductor layer)
55 Second Epitaxial Layer (Second Semiconductor Layer)

Claims (7)

A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer stacked on the semiconductor substrate;
An element isolation portion formed on the surface of the semiconductor layer for separating a first region for a trench gate type VDMOSFET and a second region for a planar gate type MOSFET;
A body region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the first region;
Digging down the body region from its surface, and a trench penetrating the body region;
A trench gate insulating film formed on the bottom and side surfaces of the trench;
A trench gate electrode embedded in the trench via the trench gate insulating film;
A source region for a first conductivity type trench gate type VDMOSFET formed on a side of the trench in a surface layer portion of the body region;
A deep well region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the second region;
A first well region of a first conductivity type selectively formed in a surface layer portion of the deep well region;
A source region for a first planar gate type MOSFET of a second conductivity type selectively formed in a surface layer portion of the first well region;
A drain region for a first planar gate MOSFET of a second conductivity type selectively formed in a surface layer portion of the first well region with a space from the source region for the first planar gate MOSFET;
A first planar gate insulating film formed on a surface of a region between the source region for the first planar gate MOSFET and the drain region for the first planar gate MOSFET;
A first planar gate electrode formed on the first planar gate insulating film;
A buried layer formed below the deep well region, in contact with the deep well region, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration in the deepest portion of the deep well region. , Semiconductor devices. In the vicinity of the boundary between the semiconductor substrate and the semiconductor layer, the impurity concentration of the first conductivity type changes so as to increase as it approaches the semiconductor substrate,
The semiconductor device according to claim 1, wherein the buried layer reaches at least a portion where the impurity concentration changes.   The semiconductor device according to claim 2, wherein the buried layer reaches at least the semiconductor substrate.   The semiconductor device according to claim 3, wherein the buried layer straddles the semiconductor substrate and the semiconductor layer. A second well region of a second conductivity type selectively formed separately from the first well region in a surface layer portion of the deep well region;
A first conductivity type second planar gate type MOSFET source region selectively formed in a surface layer portion of the second well region;
A drain region for the second planar gate MOSFET of the first conductivity type selectively formed on the surface layer portion of the second well region with a space from the source region;
A second planar gate insulating film formed on a surface of a region between the source region for the second planar gate MOSFET and the drain region for the second planar gate MOSFET;
The semiconductor device according to claim 1, further comprising: a second planar gate electrode formed on the second planar gate insulating film. A first conductivity type semiconductor substrate;
A first conductivity type semiconductor layer stacked on the semiconductor substrate;
An element isolation part for separating the first region for the trench gate type VDMOSFET and the second region for the planar gate type MOSFET;
A body region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the first region;
Digging down the body region from its surface, and a trench penetrating the body region;
A trench gate insulating film formed on the bottom and side surfaces of the trench;
A trench gate electrode embedded in the trench via the trench gate insulating film;
A source region for a first conductivity type trench gate type VDMOSFET formed on a side of the trench in a surface layer portion of the body region;
A second conductivity type region formed in the semiconductor layer in the second region;
A first conductivity type well region selectively formed in a surface layer portion of the second conductivity type region;
A source region for a planar gate MOSFET of a second conductivity type selectively formed in a surface layer portion of the well region;
A drain region for a planar gate MOSFET of a second conductivity type selectively formed on the surface layer of the well region at a distance from the source region for the planar gate MOSFET;
A planar gate insulating film formed on the surface of a region between the planar gate MOSFET source region and the planar gate MOSFET drain region;
A planar gate electrode formed on the planar gate insulating film,
The semiconductor device, wherein the second conductivity type region is in contact with at least the semiconductor substrate. A method of manufacturing a semiconductor device in which a trench gate type VDMOSFET and a planar gate type MOSFET are mixed,
Laminating a first conductive type first semiconductor layer on a first conductive type semiconductor substrate;
Doping the first semiconductor layer with a second conductivity type impurity in a region where the planar gate MOSFET is formed;
Diffusing a second conductivity type impurity doped in the first semiconductor layer by heat treatment to form a buried layer;
Removing an oxide film formed on the surface of the first semiconductor layer during the heat treatment;
Laminating a first conductivity type second semiconductor layer on the first semiconductor layer after removing the oxide film;
Doping the second semiconductor layer with a second conductivity type impurity in a region where the planar gate MOSFET is formed;
And a step of diffusing a second conductivity type impurity doped in the second semiconductor layer by heat treatment to form a deep well on the buried layer.

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