JP2010093625A - Video signal demodulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal demodulation circuit capable of simplifying a circuit configuration. <P>SOLUTION: An over modulation detection circuit of a video signal demodulation circuit 100 determines whether a modulation degree of an intermediate frequency (IF) video signal indicates over modulation exceeding 100%. When it is determined that the modulation degree does not indicate over modulation, an output circuit is caused to output the IF video signal while maintaining its phase. When the modulation degree is determined as over modulation, at the same time, the output circuit is caused to output a signal obtained by inverting the phase of the IF video signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a video signal demodulation circuit that demodulates a demodulated video signal from an intermediate frequency video signal.

  The television receiver down-converts a radio frequency television signal received from a target broadcast station into a predetermined intermediate frequency video signal (VIF: Video Intermediate Frequency). Then, the conventional video signal demodulation circuit demodulates a demodulated video signal including luminance information and the like from, for example, an intermediate frequency video signal.

  Here, the conventional video signal demodulation circuit (video detection circuit) includes a PLL circuit that reproduces a signal for detecting the intermediate frequency video signal VIF based on the intermediate frequency video signal VIF (for example, , See Patent Document 1). This video signal demodulating circuit outputs a desired demodulated video signal when the modulation degree of the intermediate frequency video signal VIF is overmodulated, and outputs from a mixer circuit (detector) or phase shifter in the PLL circuit. Switch etc.

  That is, the PLL circuit further has a circuit configuration for switching the output of the mixer circuit and the output of the phase shifter in accordance with the modulation degree of the intermediate frequency video signal.

Therefore, there is a problem that the circuit configuration of the PLL circuit becomes very complicated.
JP 2007-336328 A

  An object of the present invention is to provide a video signal demodulating circuit capable of simplifying the circuit configuration.

A video signal demodulation circuit according to one embodiment of the present invention includes:
An input terminal;
An output terminal;
A voltage-controlled oscillator that outputs a first oscillation signal according to a control voltage and outputs a second oscillation signal that is 90 ° out of phase with the first oscillation signal;
A first mixer circuit that mixes the intermediate frequency video signal input through the input terminal and the first oscillation signal, and outputs the obtained signal to the output terminal as a demodulated video signal;
An output circuit that outputs the intermediate frequency video signal input through the input terminal while maintaining its phase, or outputs a signal obtained by inverting the phase of the intermediate frequency video signal;
A second mixer circuit for mixing the signal output from the output circuit and the second oscillation signal and outputting the obtained signal;
A low-pass filter that filters the signal output from the second mixer circuit and outputs the obtained signal as the control voltage to the voltage-controlled oscillator;
It is determined whether or not the modulation degree of the intermediate frequency video signal is overmodulation exceeding 100%. If it is determined that the modulation degree is not overmodulation, the intermediate frequency video signal is supplied to the output circuit. An overmodulation detection circuit that outputs a signal obtained by inverting the phase of the intermediate frequency video signal to the output circuit when it is determined that the modulation degree is overmodulation. It is characterized by having.

  According to the video signal demodulating circuit of the present invention, the circuit configuration can be simplified.

  Embodiments according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram illustrating a configuration of a main part of a video signal demodulation circuit 100 according to a first embodiment which is an aspect of the present invention. FIG. 2 is a diagram showing an example of the configuration of the overmodulation detection circuit 4 of the video signal demodulation circuit 100 shown in FIG.
As shown in FIG. 1, a video signal demodulation circuit 100 includes an input terminal 100a, an output terminal 100b, a PLL circuit 1, a first mixer circuit (demodulator) 2, an output circuit 3, and an overmodulation detection circuit. 4.

  The PLL circuit 1 includes a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 1a, a second mixer circuit (phase detector) 1b, and a low-pass filter 1c.

  The voltage controlled oscillator 1a of the PLL circuit 1 outputs a first oscillation signal SVCO1 according to the control voltage Sv, and outputs a second oscillation signal SVCO2 whose phase is 90 ° different from that of the first oscillation signal SVCO1. It is supposed to be.

  The first mixer circuit (demodulator) 2 mixes the intermediate frequency video signal VIF inputted through the input terminal 100a and the first oscillation signal SVCO1, and uses the obtained signal as a demodulated video signal Sd. It outputs to the output terminal 100b.

  A phase compensation circuit (not shown) for compensating for the phase shift of the first oscillation signal SVCO1 caused by signal processing in the PLL circuit 1 is provided between the first mixer circuit 2 and the voltage controlled oscillator 1a. It may be provided.

  The second mixer circuit (phase detector) 1b of the PLL circuit 1 mixes the signal S1 output from the output circuit 3 and the second oscillation signal SVCO2, and outputs the obtained signal S2. It has become.

  The low-pass filter 1c of the PLL circuit 1 filters the signal S2 output from the second mixer circuit 1b and outputs the obtained signal to the voltage controlled oscillator 1a as the control voltage Sv.

  The output circuit 3 outputs the intermediate frequency video signal VIF input via the input terminal 100a while maintaining its phase (polarity), or outputs a signal obtained by inverting the phase (polarity) of the intermediate frequency video signal VIF. It is designed to output.

  The overmodulation detection circuit 4 determines whether or not the modulation degree of the intermediate frequency video signal VIF exceeds 100%. The degree of modulation increases in the direction in which the voltage of the demodulated video signal Sd increases. Further, this modulation degree becomes 100% when the amplitude of the intermediate frequency video signal VIF becomes zero. As described above, a state in which the modulation degree exceeds 100% is referred to as overmodulation.

  For example, the overmodulation detection circuit 4 compares the first reference voltage Vref1 with the voltage of the demodulated video signal Sd, and if the voltage of the demodulated video signal Sd is higher than the first reference voltage Vref1, It is determined that the modulation degree of the video signal VIF is overmodulation.

  The first reference voltage Vref1 described above is set to be equal to the voltage of the demodulated video signal Sd output from the first mixer circuit 2 when the modulation degree of the intermediate frequency video signal VIF is 100%. Has been.

  If the overmodulation detection circuit 4 determines that the modulation degree is not overmodulation, the control signal Sc causes the output circuit 3 to output the intermediate frequency video signal VIF while maintaining its phase. ing.

  On the other hand, when it is determined that the modulation degree is overmodulation, the overmodulation detection circuit 4 causes the output circuit 3 to output a signal obtained by inverting the phase of the intermediate frequency video signal VIF using the control signal Sc. ing.

  For example, as shown in FIG. 2, the overmodulation detection circuit 4 compares the reference voltage and the voltage of the demodulated video signal Sd with a power supply 4a that outputs a reference voltage, and controls the control signal Sc according to the comparison result. Is output.

  The power source 4a can output the first reference voltage Vref1 described above and second and third reference voltages Vref2 and Vref3 described later (Example 2).

  Here, as shown in FIG. 1, the output circuit 3 includes a buffer circuit 3a, a phase inverting circuit 3b, and a switch circuit 3c.

  The buffer circuit 3a outputs the intermediate frequency video signal VIF input via the input terminal 100a while maintaining the phase.

  The phase inverting circuit 3b outputs a signal obtained by inverting the phase of the intermediate frequency video signal VIF input via the input terminal 100a.

  The signal delays in the buffer circuit 3a and the phase inversion circuit 3b are set to be equal.

  The switch circuit 3c switches between the output of the buffer circuit 3a and the output of the phase inversion circuit 3b in accordance with the control signal Sc output from the overmodulation detection circuit 4, and outputs it to the second mixer circuit 1b. ing.

  That is, the switch circuit 3c outputs the signal S1 output from the buffer circuit 3a to the second mixer circuit 1b when the overmodulation detection circuit 4 determines that the modulation degree is not overmodulation. It has become. On the other hand, when the overmodulation detection circuit 4 determines that the degree of modulation is overmodulation, the switch circuit 3c outputs the signal S1 output from the phase inversion circuit 3b to the second mixer circuit 1b. It has become.

  Next, an example of the operation of the video signal demodulation circuit 100 having the above configuration will be described.

  FIG. 3 is a waveform diagram showing the relationship between the voltage waveform and the phase of each signal output from the circuit configuration of the video signal demodulation circuit 100 according to the first embodiment.

  As shown in FIG. 3, in the effective display period, when the voltage of the demodulated video signal Sd is equal to or lower than the first reference voltage Vref1 (˜time t1), the overmodulation detection circuit 4 determines that the modulation degree is not overmodulation. to decide. As a result, the overmodulation detection circuit 4 outputs the control signal Sc of “L (Low)” level. The output circuit 3 receives this control signal Sc and outputs the intermediate frequency video signal VIF while maintaining its phase (S1).

  Therefore, the PLL circuit 1 outputs the first oscillation signal SVCO1 whose phase is synchronized with the signal S1 having the same phase as the intermediate frequency video signal VIF to the first mixer circuit 2. Thereby, the amplitude (voltage) of the demodulated video signal Sd increases according to the modulation degree.

  That is, the first mixer circuit 2 outputs a demodulated video signal Sd equal to the expected demodulated video signal during normal modulation (up to time t1).

  Next, in the effective display period, when the voltage of the demodulated video signal Sd exceeds the first reference voltage Vref1 (time t1 to time t2, time t3 to time t4), the overmodulation detection circuit 4 has an overmodulation degree. It is judged that. As a result, the overmodulation detection circuit 4 outputs the control signal Sc at the “H (High)” level. The output circuit 3 receives this control signal Sc and outputs a signal obtained by inverting the phase of the intermediate frequency video signal VIF (S1).

  Therefore, the PLL circuit 1 outputs to the first mixer circuit 2 the first oscillation signal SVCO1 that is inverted in phase of the intermediate frequency video signal VIF but synchronized in phase with the signal S1. That is, the PLL circuit 1 maintains the same phase synchronization state as that during normal modulation, and the phase of the first oscillation signal SVCO1 supplied to the first mixer circuit 2 does not change.

  As a result, even during overmodulation, the phase (polarity) of the demodulated video signal Sd output from the first mixer circuit 2 is not inverted, and the amplitude (voltage) of the demodulated video signal Sd depends on the degree of modulation. Will increase.

  That is, the first mixer circuit 2 outputs a demodulated video signal Sd equal to an expected demodulated video signal during overmodulation (time t1 to time t2, time t3 to time t4).

  Note that the overmodulation detection circuit 4 outputs the control signal Sc of “L” level in the synchronization period (for example, time t2 to time t3). That is, in the synchronization period, the output circuit 3 outputs the intermediate frequency video signal VIF while maintaining its phase (polarity) (S1).

  Thus, unlike the above-described conventional technology, the video signal demodulating circuit 100 does not switch the circuit configuration in the PLL circuit 1 when overmodulation is detected, but the intermediate frequency video signal input to the PLL circuit 1. Invert the phase (polarity). Therefore, the operation speed of the PLL circuit 1 can be increased.

  Further, as described above, the video signal demodulation circuit 100 can use a circuit configuration in a general PLL circuit 1. That is, the video signal demodulating circuit 100 does not have a complicated circuit configuration as compared with the above-described conventional technology.

  As described above, the video signal demodulating circuit according to the present embodiment can simplify the circuit configuration.

  In the second embodiment, when the overmodulation detection circuit 4 of the video signal demodulation circuit 100 of the first embodiment erroneously detects overmodulation despite being in the normal modulation state, the operation shifts to the normal operation state. An example will be described.

  FIG. 4 is a waveform diagram showing voltage waveforms of the demodulated video signal Sd and the control signal Sc of the video signal demodulating circuit 100 according to the second embodiment which is an aspect of the present invention.

  For example, in the normal modulation state, when the output circuit 3 outputs a signal obtained by inverting the phase of the intermediate frequency video signal VIF due to erroneous detection of the overmodulation detection circuit 4, the first mixer circuit 2 changes the polarity of the demodulated video signal Sd. Inverted and output. As a result, the voltage of the demodulated video signal Sd output from the first mixer circuit 2 greatly exceeds the first reference voltage Vref1 (FIG. 4, time t5).

  Therefore, in the second embodiment, the second reference voltage Vref2 higher than the first reference voltage Vref is set. The overmodulation detection circuit 4 compares the second reference voltage Vref2 with the voltage of the demodulated video signal Sd. When the voltage of the demodulated video signal Sd exceeds the second reference voltage Vref2, overmodulation is performed. Judge that it was detected by mistake.

  As a result, the overmodulation detection circuit 4 can determine that the overmodulation has been erroneously detected in spite of the normal modulation state. If the overmodulation detection circuit 4 determines that an erroneous detection has occurred, the overmodulation detection circuit 4 forcibly causes the output circuit 3 to output the intermediate frequency video signal VIF while maintaining the phase. Thus, even when the overmodulation detection circuit 4 erroneously detects overmodulation during normal modulation, the video signal demodulation circuit 100 can output a desired demodulated video signal Sd.

  Here, for example, as shown in FIG. 4, it is assumed that the overmodulation detection circuit 4 of the video signal demodulation circuit 100 erroneously detects overmodulation despite the normal modulation state (˜time t5).

  Thereafter, when the voltage of the demodulated video signal Sd exceeds the second reference voltage Vref2, the overmodulation detection circuit 4 determines that it has been erroneously detected and outputs an “L” level control signal Sc (time). t5). Upon receiving this control signal Sc, the output circuit 3 outputs the intermediate frequency video signal VIF while maintaining its phase.

  As a result, the phase of the first oscillation signal VSCO1 is inverted, and the demodulated video signal Sd output from the first mixer circuit 2 becomes a desired state.

  For example, the overmodulation detection circuit 4 applies the intermediate frequency video signal VIF to the output circuit 3 in the phase until the voltage of the demodulated video signal Sd becomes equal to or lower than the third reference voltage Vref3 lower than the first reference voltage Vref1. Is output while maintaining (time t5 to time t6).

  As a result, the video signal demodulation circuit 100 can appropriately shift to the normal operation state more reliably.

  After time t6, the video signal demodulation circuit 100 returns to the normal operation and operates in the same manner as in the first embodiment.

  As described above, according to the video signal demodulating circuit according to the present embodiment, the circuit configuration can be simplified as in the first embodiment.

  Furthermore, the video signal demodulation circuit can appropriately shift to a normal operation state even when the overmodulation detection circuit malfunctions due to erroneous detection of overmodulation.

  In the first embodiment, the configuration in which the output circuit is provided with the switch circuit has been described.

  However, the same operation is possible even if this switch circuit is omitted and the output of the buffer circuit 3a of the output circuit and the output of the phase inverting circuit 3b are directly controlled by the overmodulation detection circuit.

  In the third embodiment, a configuration in which the switch circuit is omitted will be described.

FIG. 5 is a diagram illustrating a configuration of a main part of the video signal demodulation circuit 200 according to the third embodiment which is an aspect of the present invention.
As shown in FIG. 5, the video signal demodulation circuit 200 includes an input terminal 100a, an output terminal 100b, a PLL circuit 1, a first mixer circuit (demodulator) 2, an output circuit 3, and an overmodulation detection circuit. 4. The configuration of the video signal demodulation circuit 200 other than the output circuit 3 is the same as that of the video signal demodulation circuit 100 of the first embodiment.

  As in the first embodiment, the output circuit 3 outputs the intermediate frequency video signal VIF input via the input terminal 100a while maintaining its phase (polarity), or the phase of the intermediate frequency video signal VIF ( A signal in which the polarity is inverted is output.

  As in the first embodiment, the overmodulation detection circuit 4 determines whether or not the modulation degree of the intermediate frequency video signal VIF exceeds 100%.

  For example, the overmodulation detection circuit 4 compares the first reference voltage Vref1 with the voltage of the demodulated video signal Sd, and if the voltage of the demodulated video signal Sd is higher than the first reference voltage Vref1, It is determined that the modulation degree of the video signal VIF is overmodulation.

  The first reference voltage Vref1 described above is set to be equal to the voltage of the demodulated video signal Sd output from the first mixer circuit 2 when the modulation degree of the intermediate frequency video signal VIF is 100%. Has been.

  As in the first embodiment, when the overmodulation detection circuit 4 determines that the modulation degree is not overmodulation, the phase of the intermediate frequency video signal VIF is maintained in the output circuit 3 by the control signal Sc. The output is made as it is.

  On the other hand, as in the first embodiment, the overmodulation detection circuit 4 inverts the phase of the intermediate frequency video signal VIF to the output circuit 3 by the control signal Sc when determining that the modulation degree is overmodulation. A signal is output.

  Here, as shown in FIG. 5, the output circuit 3 includes a buffer circuit 3a and a phase inversion circuit 3b.

  The buffer circuit 3a outputs the intermediate frequency video signal VIF input via the input terminal 100a while maintaining the phase.

  The phase inverting circuit 3b outputs a signal obtained by inverting the phase of the intermediate frequency video signal VIF input via the input terminal 100a.

  The signal delays in the buffer circuit 3a and the phase inversion circuit 3b are set to be equal.

  The buffer circuit 3a and the phase inversion circuit 3b are controlled by a control signal Sc output from the overmodulation detection circuit 4. In response to the control signal Sc, the output of the buffer circuit 3a and the output of the phase inverting circuit 3b are switched and output to the second mixer circuit 1b.

  That is, when the overmodulation detection circuit 4 determines that the modulation degree is not overmodulation, the buffer circuit 3a outputs the signal S1 to the second mixer circuit 1b. On the other hand, when the overmodulation detection circuit 4 determines that the modulation degree is overmodulation, the phase inversion circuit 3b outputs the signal S1 to the second mixer circuit 1b.

  The operation of the video signal demodulation circuit 200 having the above configuration is the same as that of the first embodiment.

  That is, as in the first embodiment, the video signal demodulating circuit 200 does not switch the circuit configuration in the PLL circuit 1 when overmodulation is detected, and the phase of the intermediate frequency video signal input to the PLL circuit 1 ( Invert the polarity. Therefore, the operation speed of the PLL circuit 1 can be increased.

  Further, as described above, the video signal demodulation circuit 200 can use a circuit configuration in a general PLL circuit 1. That is, the video signal demodulating circuit 200 does not have a complicated circuit configuration as compared with the conventional technology described above.

  As described above, according to the video signal demodulating circuit according to the present embodiment, the circuit configuration can be simplified as in the first embodiment.

It is a figure which shows the structure of the principal part of the video signal demodulation circuit 100 which concerns on Example 1 which is 1 aspect of this invention. FIG. 2 is a diagram illustrating an example of a configuration of an overmodulation detection circuit 4 of the video signal demodulation circuit 100 illustrated in FIG. 1. FIG. 3 is a waveform diagram illustrating a relationship between a voltage waveform and a phase of each signal output from the circuit configuration of the video signal demodulation circuit 100 according to the first embodiment. It is a wave form diagram which shows the voltage waveform of the demodulation video signal Sd of the video signal demodulation circuit 100 which concerns on Example 2 which is one aspect | mode of this invention, and the control signal Sc. It is a figure which shows the structure of the principal part of the video signal demodulation circuit 200 which concerns on Example 3 which is 1 aspect of this invention.

Explanation of symbols

1 PLL circuit 1a Voltage controlled oscillator (VCO)
1b Second mixer circuit (phase detector)
1c Low-pass filter 2 First mixer circuit (demodulator)
3 Output circuit 3a Buffer circuit 3b Phase inversion circuit 3c Switch circuit 4 Overmodulation detection circuit 4a Power supply 4b Comparison circuit 100 Video signal demodulation circuit 100a Input terminal 100b Output terminal S1, S2 Signal Sd Demodulated video signal Sc Control signal Sv Control voltage SVCO1 1 oscillation signal SVCO2 second oscillation signal VIF intermediate frequency video signal Vref1 first reference voltage Vref2 second reference voltage Vref3 third reference voltage

Claims (5)

An input terminal;
An output terminal;
A voltage-controlled oscillator that outputs a first oscillation signal according to a control voltage and outputs a second oscillation signal that is 90 ° out of phase with the first oscillation signal;
A first mixer circuit that mixes the intermediate frequency video signal input through the input terminal and the first oscillation signal, and outputs the obtained signal to the output terminal as a demodulated video signal;
An output circuit that outputs the intermediate frequency video signal input through the input terminal while maintaining its phase, or outputs a signal obtained by inverting the phase of the intermediate frequency video signal;
A second mixer circuit for mixing the signal output from the output circuit and the second oscillation signal and outputting the obtained signal;
A low-pass filter that filters the signal output from the second mixer circuit and outputs the obtained signal as the control voltage to the voltage-controlled oscillator;
It is determined whether or not the modulation degree of the intermediate frequency video signal is overmodulation exceeding 100%. If it is determined that the modulation degree is not overmodulation, the intermediate frequency video signal is supplied to the output circuit. An overmodulation detection circuit that outputs a signal obtained by inverting the phase of the intermediate frequency video signal to the output circuit when it is determined that the modulation degree is overmodulation. A video signal demodulating circuit comprising: The overmodulation detection circuit compares a first reference voltage with the voltage of the demodulated video signal, and when the voltage of the demodulated video signal is higher than the first reference voltage, The video signal demodulation circuit according to claim 1, wherein the modulation degree is determined to be overmodulation. The output circuit is
A buffer circuit for outputting the intermediate frequency video signal input through the input terminal while maintaining its phase;
A phase inversion circuit that outputs a signal obtained by inverting the phase of the intermediate frequency video signal input through the input terminal,
When the overmodulation detection circuit determines that the modulation degree is not overmodulation, it outputs the signal output from the buffer circuit to the second mixer circuit;
On the other hand, when the overmodulation detection circuit determines that the modulation degree is overmodulation, the signal output from the phase inversion circuit is output to the second mixer circuit. Or a video signal demodulating circuit according to 2; The overmodulation detection circuit includes:
When the voltage of the demodulated video signal exceeds a second reference voltage higher than the first reference voltage, the output circuit outputs the intermediate frequency video signal while maintaining its phase. The video signal demodulating circuit according to claim 2. The overmodulation detection circuit includes:
Until the voltage of the demodulated video signal exceeds the second reference voltage and falls below a third reference voltage lower than the first reference voltage, the intermediate frequency video signal is phase-shifted to the output circuit. 5. The video signal demodulating circuit according to claim 4, wherein the video signal demodulating circuit outputs the signal while maintaining the output.

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