JP2010021170A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

An oxide TFT having a channel layer thickness of about 10 nm or less can operate at high speed with reduced contact resistance between the channel layer and the source electrode or between the channel layer and the drain electrode. A semiconductor device is provided.
An oxide TFT is formed so as to realize a fully depleted state in an off state. Then, a contact layer CTS is formed between the channel layer CHN and the source electrode ST, and a contact layer CTD is formed between the channel layer CHN and the drain electrode DT. Further, when the gate insulating film capacitance between the gate electrode GT and the channel layer CHN is Cgi, and the total parasitic capacitance between the structure other than the gate electrode GT and the channel layer CHN is Cp, the ratio of Cp to Cgi Cp / Cgi is formed to be smaller than 0.7.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a field effect transistor using a metal oxide film as a channel layer.

  Thin film transistors (hereinafter referred to simply as TFTs in this specification) (field effect transistors) (field effect transistors) can be formed on a substrate such as glass or plastic film and play an important role in electronics technology. It is a device. However, in the currently most widely used amorphous or polycrystalline silicon TFT, the subthreshold coefficient becomes as large as about 200 mV / decade or more. For this reason, when a circuit is formed using TFTs, a low voltage of about 1 to 3 V, such as a normal large-scale integrated circuit (hereinafter sometimes simply referred to as LSI), is used. There is a problem that it is difficult to drive with voltage. In addition, since the TFT has a large off-state current, it is difficult to reduce the standby current consumption.

  In order to solve these problems, it is only necessary to realize a fully depleted state in the off state of the TFT. However, it is not easy to form a structure that realizes a fully depleted state in a silicon TFT in terms of the manufacturing process.

  On the other hand, in an oxide TFT using a metal oxide film as a channel layer, for example, as shown in Japanese Unexamined Patent Publication No. 2007-250987 (Patent Document 1), the thickness of the channel layer formed of ITO (Indium Tin Oxide) A technique for realizing a fully depleted off state by reducing the thickness to 5 to 15 nm is disclosed. In the disclosed technique, the total amount of carriers in the channel layer is made smaller than the amount of carriers that can be controlled by the gate, and the thickness of the channel layer is made smaller than the maximum depletion layer width. That is, the elementary charge amount is q, the carrier concentration in the channel layer is Nc, the thickness of the channel layer is d, the maximum charge amount that can be controlled by the gate electrode through the gate insulating film is Qg, and the maximum in the channel layer is When the depletion layer width is Wmax, the following conditional expressions (1) and (2) are simultaneously satisfied.

q × Nc × d <Qg (1)
d <Wmax (2)
This realizes a TFT having a subthreshold coefficient of 100 to 200 mV / decade and a small off-current.
JP 2007-250987 A

  Patent Document 1 discloses a configuration of a bottom gate type TFT in which a gate electrode is formed below a channel layer. In this bottom gate type TFT, a source electrode and a drain electrode are directly attached on a channel layer made of ITO. Such a structure is disclosed. However, in general, in order to obtain good electrical contact between different materials, a bonding interface layer of about several to 10 nm is required. Therefore, in the structure disclosed in Patent Document 1, since the thickness of the channel layer is about 10 nm or less, it is not possible to form a sufficient bonding interface layer at the boundary between the channel layer and the source electrode or the drain electrode. The contact resistance of the source electrode and drain electrode is increased. For this reason, there exists a problem that the on-current of TFT falls. That is, according to the technique described in Patent Document 1, it is difficult to form a circuit that operates at high speed.

  The technique described in Patent Document 1 realizes a subthreshold coefficient smaller than that of a conventional silicon TFT, but a field effect transistor (hereinafter referred to as a field effect transistor) used in a general LSI is referred to in this specification. This is larger than the subthreshold coefficient of 80 to 100 mV / decade (which may be simply referred to as FET), and there is a problem that it is difficult to drive at a low voltage as in LSI.

  The present invention has been made based on such circumstances, and the object thereof is as follows.

  It is an object of the present invention to operate at high speed by reducing contact resistance between a channel layer and a source electrode or between a channel layer and a drain electrode in an oxide TFT having a channel layer thickness of about 10 nm or less. It is an object of the present invention to provide a semiconductor device that can be used.

  Another object of the present invention is to provide a semiconductor device which is driven at a low voltage by setting the subthreshold coefficient of a fully depleted TFT to 100 mV / decade or less, which is comparable to an FET using single crystal silicon. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes: (a) a gate electrode made of a conductive material; and (b) a channel layer made of a semiconductor layer that is arranged to face the gate electrode and uses a metal oxide. (C) a gate insulating film sandwiched between the gate electrode and the channel layer, and (d) a source electrode and a drain electrode electrically connected to the channel layer. At this time, the total carrier amount in the channel layer is smaller than the carrier amount that can be controlled by the gate electrode, and the thickness of the channel layer is smaller than the maximum depletion layer width. In addition, a first conductive layer is formed between the channel layer and the source electrode, and a second conductive layer is formed between the channel layer and the drain electrode.

  The semiconductor device manufacturing method according to the representative embodiment includes (a) a step of forming a gate electrode on a substrate, and (b) forming a gate insulating film on the substrate so as to cover the gate electrode. And (c) forming a source electrode and a drain electrode on the gate insulating film through a separation region. And (d) forming a first conductive layer on the source electrode and forming a second conductive layer on the drain electrode; (e) on the first conductive layer, on the separation region, and on the first Forming a channel layer made of a semiconductor layer using a metal oxide over two conductive layers. At this time, the total carrier amount in the channel layer is smaller than the carrier amount that can be controlled by the gate electrode, and the thickness of the channel layer is smaller than the maximum depletion layer width.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a fully depleted TFT with low off-state current, contact resistance can be reduced, and a semiconductor device with low power consumption and operating at high speed can be provided.

  In addition, by setting the subthreshold coefficient of a fully depleted TFT to 100 mV / decade or less, a semiconductor device driven at a low voltage can be provided.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment. A so-called bottom gate / bottom contact type oxide TFT is cited as a semiconductor device. The bottom gate here is a structure in which a gate electrode is formed below the channel layer, and the bottom contact is a contact layer (characteristic of the first embodiment) below the channel layer. A structure in which a conductive layer is formed is shown.

  In the semiconductor device according to the first embodiment, as shown in FIG. 1, the gate electrode GT is formed on the substrate SUB. A gate insulating film GI is formed on the upper surface of the substrate SUB that covers the gate electrode GT. Further, the source electrode ST and the drain electrode DT are formed on the gate insulating film GI so as to straddle the gate electrode GT at least in a plane. That is, the source electrode ST and the drain electrode DT are arranged with a separation region that is a region separated by a certain distance.

  A source-side contact layer (first conductive layer) CTS is formed on the source electrode ST by a semiconductor layer made of a metal oxide, and a drain-side contact layer (second conductive layer) is formed on the drain electrode DT. ) The CTD is formed by a semiconductor layer made of a metal oxide. A channel layer CHN is formed so as to straddle at least the gate electrode GT and both contact layers CTS and CTD. As described above, the first embodiment is characterized in that the contact layer CTS is formed between the channel layer CHN and the source electrode ST instead of being directly connected to the channel layer CHN and the source electrode ST or the drain electrode DT. The contact layer CTD is formed between the CHN and the drain region DT. Thereby, even if the channel layer CHN is formed thin, a sufficient bonding interface layer can be formed at the boundary between the channel layer and the source electrode or the drain electrode. That is, since the source electrode ST is connected to the channel layer CHN via the contact layer CTS having a sufficient thickness, even if the channel layer CHN is sufficiently thin, it is sufficient at the boundary between the contact layer CTS and the source electrode ST. A bonding interface layer having a thickness can be formed. Similarly, since the drain electrode DT is connected to the channel layer CHN via the contact layer CTD having a sufficient thickness, the boundary between the contact layer CTD and the drain electrode DT is sufficient even if the channel layer CHN is sufficiently thin. A bonding interface layer having a sufficient thickness can be formed. Therefore, the contact resistance between the source electrode ST and the channel layer CHN and the contact resistance between the drain electrode DT and the channel layer CHN can be reduced. Therefore, the on-resistance of the TFT can be reduced and the on-current can be improved.

  At this time, if the contact layers CTS and CTD are too thick, parasitic resistance is generated in the thickness direction. Therefore, it is desirable to form the thickness so that the sum of the thickness with the thickness of the channel layer CHN is 100 nm or less. Also, if the contact layers CTS and CTD are too thin, a sufficiently thick bonding interface layer cannot be formed, and the effect of reducing contact resistance cannot be obtained sufficiently. Therefore, the thickness is the sum of the thickness of the channel layer CHN. It is desirable to form it to be 10 nm or more.

  Further, both contact layers CTS and CTD are also formed inside the distance between the source electrode ST and the drain electrode DT so that the connection is formed in the order of the source electrode ST, the drain electrode DT, the contact layer CTS, the CTD, and the channel layer CHN. Is formed. That is, the contact layer CTS is formed on the source electrode ST while covering the end of the source electrode ST on the separated region side, and the contact layer CTD is formed on the drain electrode DT while covering the end of the drain electrode DT on the separated region side. Is formed. As a result, the source electrode ST, the drain electrode DT, the contact layer CTS, and the CTD-channel layer CHN are connected in this order also at the end of the source electrode ST on the side of the separated region and the end of the drain electrode DT on the side of the separated region. It is possible to form a sufficient bonding interface layer by the contact layers CTS and CTD.

  Further, the source electrode ST, the drain electrode DT, and the contact layers CTS and CTD are formed in a tapered shape in order to improve the coverage when forming the channel layer CHN. That is, the end of the source electrode ST on the side of the separated region and the end of the drain electrode DT on the side of the separated region have a tapered shape that decreases in height toward the tip. Similarly, the end of the contact layer CTS on the side of the separation region and the end of the contact layer CTD on the side of the separation region have a tapered shape whose height decreases toward the tip. With this configuration, the coverage of the channel layer CHN formed on the contact layers CTS and CTD can be improved.

  Subsequently, a protective film PRO made of an insulating film is formed on the channel layer CHN, and a wiring WIR is formed on the protective film PRO. The connection between the wiring WIR and the source electrode ST and drain electrode DT is made by plugs (first plug and second plug) penetrating the protective film PRO. This plug is connected to the source electrode ST or the drain electrode DT in a region where the channel layer CHN and the contact layers CTS and CTD are not formed. This is to prevent the channel layer CHN or the contact layers CTS and CTD from being etched by side etching when a contact hole is formed in the protective film PRO. That is, since the channel layer and the contact layers CTS, CTD are formed of a metal oxide which is easily etched, the plug is connected to the channel layer CHN and the source electrode ST or drain electrode in the region where the contact layers CTS, CTD are formed. When connected to DT, the channel layer CHN and the contact layers CTS and CTD are removed by side etching from the side wall of the contact hole during the etching for forming the contact hole. Therefore, the plug connecting the wiring WIR and the source electrode ST or the drain electrode DT is made in a region where the channel layer and the contact layers CTS and CTD are not formed.

The substrate SUB is made of, for example, glass, quartz, a plastic film, a metal film, and the like, and an insulating film is coated on the surface on which the gate electrode GT is formed as necessary. The gate electrode GT, the source electrode ST, the drain electrode DT, and the wiring WIR are, for example, a single film of molybdenum, chromium, tungsten, aluminum, copper, titanium, nickel, tantalum, silver, zinc, or other metal, or an alloy film thereof. , Laminated films thereof, metal oxide conductive films such as ITO, metal nitride conductive films such as titanium nitride (TiN), other conductive metal compound films, highly doped semiconductors, or laminated films thereof Is formed by. The gate electrode GT, the source electrode ST, the drain electrode DT, and the wiring WIR may be formed of the same material or different materials. The insulating film GI is made of, for example, SiO ₂ , SiN, Al ₂ O ₃ , or other insulating films. The channel layer CHN and the contact layers CTS and CTD are made of, for example, ZnO, InGaZnO, InZnO, GaZnO, InGaO, ZnSnO, ITO, or other metal oxides that exhibit conductivity. The channel layer CHN and the contact layers CTS and CTD may be formed from the same material or different materials.

The carrier concentration Nc and the thickness d of the channel layer CHN are formed so as to realize a fully depleted state in the off state of the TFT. That is, the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate electrode, and the thickness of the channel layer is smaller than the maximum depletion layer width. The above two conditions are that the elementary charge amount is q, the carrier concentration in the channel layer is Nc, the thickness of the channel layer is d, the maximum charge amount that can be controlled by the gate electrode through the gate insulating film is Qg, When the maximum depletion layer width in the channel layer is Wmax, the vacuum dielectric constant is ε ₀ , the relative dielectric constant of the material constituting the channel layer is ε _r , and the difference between the Fermi potential and the intrinsic potential is φ _b , the following 2 Are expressed by two conditional expressions (3) and (4).

q × Nc × d <Qg (3)
∴Nc <Qg / (qd)
_{d <Wmax = {(4ε 0} ε r φ b) / (qNc)} 1/2 ··· (4)
_{∴Nc <(4ε 0 ε r φ} b) / (qd 2)
FIG. 2 is a diagram for explaining the conditional expression (3). FIG. 2 shows a gate electrode, a gate insulating film formed on the gate electrode, and a channel layer (semiconductor layer) formed on the gate insulating film. When the TFT is turned off, the channel layer is a depletion layer region in the entire region. When the voltage applied to the gate electrode is gradually increased from the off state, the depletion layer region is reduced and a conductive region appears. When the carrier (electron) concentration of the semiconductor film forming the channel layer is Nc, the width of the channel layer is d, and the elementary charge is q, the total amount of carriers (total charge) existing in the channel layer is q × Nc × d. It becomes. Conditional expression (3) is that the total amount of carriers present in the channel layer is smaller than the amount of carriers Qg that can be controlled by the gate electrode. That is, conditional expression (3) is a condition that all carriers existing in the channel layer can be controlled by the gate electrode. At this time, the carrier amount Qg that can be controlled by the gate electrode is represented by Qg = Cgi × Vgmax, where Cgi is the gate insulating film capacitance and Vgmax is the maximum value of the gate voltage applied to the gate electrode. This indicates the amount of charge that can be accumulated in the gate insulating film capacitance, and means that if the total amount of carriers present in the channel layer is less than this amount of charge, it can be controlled by the gate electrode.

  FIG. 3 is a diagram for explaining the conditional expression (4). FIG. 3 shows a band structure in a semiconductor layer that forms a channel layer in contact with the gate insulating film. As shown in FIG. 3, it can be seen that the band is bent from the surface of the semiconductor layer to a certain region. The region where the band is bent indicates a depletion layer, and the width from the surface of the semiconductor layer to W shown in FIG. 3 is the depletion layer width. The bending of the band is affected by the work function of the material constituting the gate electrode and the voltage applied to the gate electrode. Conditional expression (4) is a condition that the channel layer formed in the semiconductor layer is thinner than the maximum value Wmax of the depletion layer width.

  FIG. 4 shows conditional expressions (3) and (4) as graphs. In FIG. 4, the vertical axis indicates the carrier concentration Nc, and the horizontal axis indicates the thickness d of the channel layer. As shown in FIG. 4, the lower region of both the curve representing the conditional expression (3) and the curve representing the conditional expression (4) is a range satisfying both conditions. This range is indicated by a hatched area in FIG. That is, if the conditions included in the shaded region shown in FIG. 4 are set, the conditional expressions (3) and (4) are satisfied, and a fully depleted state can be realized in the off state of the TFT. Thus, by realizing a fully depleted state in the off state of the TFT, the leakage current when the TFT is off can be reduced.

Next, FIG. 5 is a diagram showing the capacitance formed between the channel layer CHN of the oxide TFT and the surrounding structure. In the oxide TFT according to the first embodiment, the gate insulating film capacitance between the gate electrode GT and the channel layer CHN is Cgi, and the total parasitic capacitance between the structure other than the gate electrode GT and the channel layer CHN is Cp. When (C ₁ + C ₂ + C ₃ + C ₄ + C ₅ +... = ΣC _n = Σ (ε _n / t _n )), Cp / Cgi indicating the ratio of Cp to Cgi is smaller than 0.7. It is formed as follows. Here, ε _n represents the dielectric constant, and t _n represents the thickness of the capacitor.

  In the first embodiment, Cp / Cgi indicating the ratio of Cp to Cgi is formed to be smaller than 0.7. The reason will be described below. The subthreshold coefficient S of the FET is expressed by the following equation (5).

S = ln10 × (1 + Cs / Cgi) × kT / q (5)
Here, k is a Boltzmann constant, and T is an absolute temperature. Cs is the series sum of the depletion layer capacitances Cch and Cp in the channel layer CHN in the fully depleted state, and is expressed by equation (6).

Cs = Cch × Cp / (Cch + Cp) (6)
In the case of the structure of the oxide TFT according to the first embodiment in which the channel layer CHN is thin and the protective film PRO is formed relatively thick with an insulating film having a low dielectric constant, Cp << Cch. The relationship is established.

Cs≈Cp (7)
Therefore, in the structure according to the first embodiment, equation (5) can be rewritten as equation (8).

S = ln10 × (1 + Cp / Cgi) × kT / q (8)
FIG. 6 is a diagram showing the relationship between Cp / Cgi and the subthreshold coefficient S calculated according to equation (8). When Cp / Cgi is smaller than 0.7, the subthreshold coefficient S is smaller than 100 mV / decade, which is comparable to a general single crystal silicon FET. Therefore, the oxide TFT of the present invention is formed so that Cp / Cgi is smaller than 0.7.

Specifically, it can be seen that in order to form Cp / Cgi indicating the ratio of Cp to Cgi to be smaller than 0.7, it is sufficient to make Cp, which is the sum of parasitic capacitances, as small as possible. Cp / Cgi indicating the ratio of Cp to Cgi can be expressed as Σ (ε _n / t _n ) / (ε _gi / t _gi ). Therefore, in order to reduce the total parasitic capacitance, ε _n mainly composed of the dielectric constant of the protective film PRO and the like should be reduced, and an insulating material such as the protective film PRO can be made as low as possible. It can be realized by forming from. Furthermore, since it is possible to reduce the Cp by thickening the t _n is the thickness of the parasitic capacitance, by increasing the thickness of the insulating material such as a protective film PRO, it is possible to reduce the Cp. In addition, if the wiring WIR formed on the protective film PRO exists above the channel layer CHN, the parasitic capacitance increases. Therefore, the wiring layout is devised so that the wiring WIR is not disposed above the channel layer CHN. By doing so, the total Cp of the parasitic capacitance can be reduced.

  By the means described above, the oxide TFT according to the first embodiment can be formed so that Cp / Cgi indicating the ratio of Cp to Cgi is smaller than 0.7. As a result, in the oxide TFT according to the first embodiment, the subthreshold coefficient becomes smaller than 100 mV / decade, and an oxide TFT driven at a low voltage can be realized.

  The oxide TFT according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 7, the gate electrode GT is formed on the substrate SUB by using a film forming technique such as a sputtering method or a CVD (Chemical Vapor Deposition) method used in a normal semiconductor process, or a patterning technique by photolithography and etching. Then, the gate insulating film GI, the source electrode ST, and the drain electrode DT are formed. The source electrode ST and the drain electrode DT are formed in a tapered shape in order to improve the coverage when forming both the source-side and drain-side contact layers CTS and CTD.

  Next, as shown in FIG. 8, an oxide semiconductor layer made of the same material as the channel layer is formed by sputtering, CVD, coating, or the like, and is formed on the source electrode ST and the drain electrode DT by photolithography and etching. Then, both the source-side and drain-side contact layers CTS and CTD are patterned. At this time, the contact layer CTS is formed on a partial region of the source electrode ST, and the contact layer CTD is formed on a partial region of the drain electrode DT.

  Both contact layers CTS, CTD are located inside (spaced area) between the source electrode ST and the drain electrode DT so that the connection is formed in the order of the source electrode ST / drain electrode DT-contact layer CTS, CTD-channel layer. Is also patterned. Further, both contact layers CTS and CTD are formed in a tapered shape in order to improve the coverage when forming the channel layer.

  Subsequently, as shown in FIG. 9, an oxide semiconductor layer having a thickness of several nm to several tens of nm is formed by sputtering, CVD, coating, or the like, and a channel layer CHN is formed by patterning by photolithography and etching. To do.

  Thereafter, as shown in FIG. 10, a protective film PRO made of an insulating film is formed on the channel layer CHN by sputtering, CVD, coating, or the like. Thereafter, contact holes to the source electrode ST and the drain electrode DT are formed by photolithography and etching. In order to prevent the channel layer CHN or the contact layers CTS and CTD from being removed by side etching, the contact hole is formed in a region where the channel layer CHN and the contact layers CTS and CTD are not formed.

  Next, as shown in FIG. 11, a conductor film is formed by sputtering, CVD, coating, or the like, and plugs and wirings WIR are formed by patterning by photolithography and etching.

  Although the semiconductor device according to the first embodiment can be manufactured through the above steps, steps may be added, deleted, or changed as necessary without departing from the spirit of the present invention. . For example, as shown in FIG. 12, a second protective film PRO2 may be formed between the channel layer CHN and the protective film PRO. In this case, in the above-described step (see FIG. 9), after an oxide semiconductor layer having a thickness of several nm to several tens of nm is formed, an insulating film is formed on the channel layer CHN by a sputtering method, a CVD method, a coating method, or the like. A protective film PRO2 made of is formed. Thereafter, the protective film PRO2 and the channel layer CHN are collectively processed by patterning by photolithography and etching. At this time, since the channel layer CHN is covered with the protective film PRO2, damage to the channel layer CHN in the resist removal step after the etching can be reduced.

FIG. 13 shows an ON state in the case where there is a case where there are no contact layers CTS and CTD having a thickness of 20 nm in an oxide TFT manufactured using InGaZnO having a carrier concentration Nc≈10 ¹⁹ cm ⁻³ and a thickness d = 5 nm. It is the figure which compared resistance. As shown in FIG. 13, by forming the contact layers CTS and CTD, the on-resistance can be reduced to nearly 1/3. As a result, the speed of the circuit using the oxide TFT can be increased.

FIG. 14 shows Id-Vg of a TFT manufactured using silicon dioxide SiO ₂ having a thickness of 15 nm for the gate insulating film GI and InGaZnO having a carrier concentration Nc≈10 ¹⁹ cm ⁻³ and a thickness d = 5 nm for the channel layer CHN. Show properties. At this time, in FIG. 14, the vertical axis indicates the drain current Id, and the horizontal axis indicates the gate voltage Vg. As can be seen from FIG. 14, when the oxide TFT is in a fully depleted state, the off-current is less than the detection lower limit, and the subthreshold coefficient S is 63 mV / decade, which is smaller than that of a normal single crystal silicon FET. Thereby, low power consumption and low voltage of the circuit can be achieved.

  In the first embodiment, the bottom gate / bottom contact type oxide TFT has been described as an example. However, the same effect can be obtained by using a top gate / bottom contact type oxide TFT as shown in FIG. be able to. Here, the top gate means a structure in which the gate electrode GT is formed above the channel layer CHN, and the bottom contact means that the contact layers CTS and CTD are formed below the channel layer CHN. Means structure.

  As described above, the oxide TFT according to the first embodiment has been described, but the contents thereof are also effective in other embodiments without departing from the gist of the present invention.

(Embodiment 2)
FIG. 16 is a diagram illustrating a configuration of the semiconductor device according to the second embodiment. In the second embodiment, a so-called bottom gate / top contact type oxide TFT is cited as a semiconductor device. The bottom gate here means a structure in which the gate electrode GT is formed below the channel layer CHN, and the top contact means a structure in which the contact layers CTS and CTD are formed above the channel layer CHN. is doing.

  As shown in FIG. 16, the gate electrode GT is formed on the substrate SUB. A gate insulating film GI is formed on the upper surface of the substrate SUB so as to cover the gate electrode GT. Further, a channel layer CHN is formed of metal oxide so as to straddle at least the gate electrode GT on the gate insulating film GI. Further, the source-side contact layer CTS and the drain-side contact layer CTD are formed of metal oxide so as to straddle at least the gate electrode GT on the channel layer CHN. A source electrode ST is formed on the source-side contact layer CTS, and a drain electrode DT is formed on the drain-side contact layer CTD. A protective film PRO made of an insulating film is formed on these structures, and a plug and a wiring WIR thereon are formed through a contact hole opened in the protective film PRO. The plugs electrically connect the wiring WIR and the source electrode ST, and the wiring WIR and the drain electrode DT.

  The carrier concentration Nc and the thickness d of the channel layer CHN are formed so that a fully depleted state can be realized in the off state of the oxide TFT as in the first embodiment. That is, the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate, and the thickness of the channel layer is smaller than the maximum depletion layer width.

  If both contact layers CTS and CTD are too thick, parasitic resistance is generated in the thickness direction. Therefore, like the first embodiment, the thickness is formed such that the sum of the thickness of the channel layer CHN and the channel layer CHN is 100 nm or less. Is desirable. On the other hand, if the contact layers CTS and CTD are too thin, a sufficiently thick bonding interface layer cannot be formed, and a sufficient effect of reducing contact resistance cannot be obtained. Therefore, the thickness is the sum of the thickness of the channel layer CHN. Is preferably 10 nm or more.

  Also in the oxide TFT according to the second embodiment, the gate insulating film capacitance between the gate electrode GT and the channel layer CHN is Cgi, and the total parasitic capacitance between the structure other than the gate electrode GT and the channel layer CHN is calculated. When Cp, the ratio Cp / Cgi of Cp to Cgi is formed to be smaller than 0.7.

  The oxide TFT according to the second embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 17, a gate electrode GT and a gate insulating film GI are formed on the substrate SUB by using a film forming technique such as sputtering or CVD used in a normal semiconductor process, or a patterning technique by photolithography and etching. The channel layer CHN is formed.

  Next, as shown in FIG. 18, a photoresist PR is applied, and the photoresist PR is opened at least on the gate electrode GT, leaving a region for separating the source electrode and the drain electrode. Thereafter, an oxide semiconductor layer (a layer to be a contact layer CTS, CTD) made of the same material as the channel layer CHN is formed in a region where the photoresist PR is opened by a sputtering method, a CVD method, a coating method, or the like. Further, a conductor film (a film that becomes the source electrode ST and the drain electrode DT) is formed thereon.

  Subsequently, as shown in FIG. 19, the photoresist PR is removed, and the source-side contact layer CTS, the drain-side contact layer CTD, the source electrode ST, and the drain electrode DT are patterned (lift-off method).

  Thereafter, as shown in FIG. 20, a protective film PRO made of an insulating film is formed on the channel layer CHN by sputtering, CVD, coating, or the like. Then, contact holes reaching the source electrode ST and the drain electrode DT are formed by photolithography and etching.

  Next, as shown in FIG. 21, a conductor film is formed by sputtering, CVD, coating, or the like, and plugs and wirings WIR are formed by patterning by photolithography and etching.

  Although the semiconductor device according to the second embodiment can be manufactured through the above steps, steps may be added, deleted, or changed as necessary without departing from the spirit of the present invention. .

  Since the configuration of the second embodiment is a top contact type, a material not suitable for the bottom contact type structure of the first embodiment can be used for the source electrode ST and the drain electrode DT. That is, when a bottom contact type structure is formed of a metal material that is easily oxidized, it is between the formation of the source electrode ST and the drain electrode DT and the formation of both contact layers CTS and CTD (between FIGS. 7 and 8). In addition, a natural oxide film is formed on the surfaces of the source electrode ST and the drain electrode DT, and the contact resistance increases. On the other hand, in the top contact type structure as in the second embodiment, there is no fear that the contact resistance increases even if the same metal material is used. That is, as shown in FIG. 18, since the source electrode ST and the drain electrode DT are formed after the contact layers CTS and CTD are formed, the interface between the source electrode ST and the source-side contact layer CTS and the drain electrode DT and the drain side are formed. It is possible to suppress the interface of the contact layer CTD from being oxidized.

  Also in the configuration of the oxide TFT according to the second embodiment, as in the first embodiment, it is possible to reduce the off current and the subthreshold coefficient S of the TFT and to improve the on current of the oxide TFT. be able to. Thereby, it is possible to reduce the power consumption, the voltage, and the speed of the circuit using the oxide TFT according to the second embodiment.

  In FIG. 16, the bottom gate / top contact type oxide TFT has been described as an example. However, the same effect can be obtained by using a top gate / top contact type oxide TFT as shown in FIG. . Here, the top gate means a structure in which the gate electrode GT is formed above the channel layer CHN, and the top contact means a structure in which the contact layers CTS and CTD are formed above the channel layer CHN. means.

(Embodiment 3)
FIG. 23 is a diagram showing a configuration of the semiconductor device according to the third embodiment. A so-called bottom gate / bottom contact type oxide TFT is cited as a semiconductor device. A difference from the structure of the first embodiment is that a plug formed for electrical connection between the wiring WIR and the source electrode ST or between the wiring WIR and the drain electrode DT penetrates the contact layers CTS and CTD. It is a point. However, in the third embodiment, the position where the plug (contact hole) penetrates is sufficiently separated from the gate electrode GT in order to prevent the channel layer CHN on the gate electrode GT from being etched by side etching.

  The carrier concentration Nc and the thickness d of the channel layer CHN are formed so that a fully depleted state can be realized in the off state of the oxide TFT, as in the first embodiment. That is, the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate, and the thickness of the channel layer is smaller than the maximum depletion layer width.

  Furthermore, if both contact layers CTS and CTD are too thick, parasitic resistance is generated in the thickness direction. Therefore, as in the first embodiment, the total thickness is 100 nm or less with the thickness of the channel layer CHN. It is desirable to form. On the other hand, if the contact layers CTS and CTD are too thin, a sufficiently thick bonding interface layer cannot be formed, and a sufficient effect of reducing contact resistance cannot be obtained. Therefore, the thickness is the sum of the thickness of the channel layer CHN. Is preferably 10 nm or more.

  Also in the oxide TFT according to the third embodiment, the gate insulating film capacitance between the gate electrode GT and the channel layer CHN is Cgi, and the total parasitic capacitance between the structure other than the gate electrode GT and the channel layer CHN is Cp. , The ratio Cp / Cgi of Cp to Cgi is formed to be smaller than 0.7.

  The oxide TFT according to the third embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 24, the gate electrode GT and the gate insulating film GI are formed on the substrate SUB by using a film forming technique such as sputtering or CVD used in a normal semiconductor process, or a patterning technique by photolithography and etching. The source electrode ST, the drain electrode DT, and both the source side / drain side contact layers CTS, CTD are formed. Here, the film for forming the source electrode ST and the drain electrode DT and the film for forming the contact layers CTS and CTD are successively formed, and after patterning the photoresist on the film, the two layers of films are collectively formed. Etch. Thereby, a manufacturing process can be simplified. In order to improve the coverage when forming the channel layer CHN, the source electrode ST, the drain electrode DT, and both the source and drain contact layers CTS and CTD are formed in a tapered shape.

  Next, as shown in FIG. 25, an oxide semiconductor layer having a thickness of several nanometers to several tens of nanometers is formed by sputtering, CVD, coating, or the like, and a channel layer CHN is formed by patterning by photolithography and etching. To do.

  Subsequently, as shown in FIG. 26, a protective film PRO made of an insulating film is formed on the channel layer CHN by sputtering, CVD, coating, or the like. Thereafter, contact holes that reach the source electrode ST and the drain electrode DT through the protective film PRO and the contact layers CTS and CTD are formed by photolithography and etching. In order to prevent the channel layer CHN on the gate electrode GT from being etched by side etching of the oxide semiconductor layer, the position where the contact hole penetrates is sufficiently separated from the gate electrode GT.

  Thereafter, as shown in FIG. 27, a conductor film is formed by sputtering, CVD, coating, or the like, and plugs and wirings WIR are formed by patterning by photolithography and etching.

  In the method of manufacturing a semiconductor device according to the third embodiment, the two layers of the layers constituting the source electrode ST and the drain electrode DT and the layers constituting the contact layers CTS and CTD are patterned at once. The manufacturing process can be simplified compared to the above.

  Also in the configuration of the oxide TFT in the third embodiment, the off-current and subthreshold coefficient S of the TFT can be reduced and the on-current of the oxide TFT can be improved as in the first embodiment. Can do. Thereby, it is possible to reduce the power consumption, the voltage, and the speed of the circuit using the oxide TFT according to the third embodiment.

  In FIG. 23, the bottom gate / bottom contact type oxide TFT has been described as an example. However, the same effect can be obtained with a top gate / bottom contact type oxide TFT as shown in FIG. .

(Embodiment 4)
FIG. 29 is a diagram showing a configuration of the semiconductor device according to the fourth embodiment. In the fourth embodiment, as a semiconductor device, a so-called bottom gate / bottom contact type oxide TFT is taken as an example.

  In the structure shown in the fourth embodiment, a protective film PRO3 made of an insulating film is formed on the wiring WIR, and an oxide TFT (semiconductor device) is stacked on the protective film PRO3. At this time, the number of stacked oxide TFTs (semiconductor devices) may be two, but may be three or more as required. In FIG. 29, the same structure is stacked immediately above, but this is not necessarily required, and the pattern positions may be shifted and stacked, or semiconductor devices having different structures may be stacked.

  The carrier concentration Nc and the thickness d of the channel layer CHN are formed so that a fully depleted state can be realized in the off state of the oxide TFT, as in the first embodiment. That is, the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate, and the thickness of the channel layer is smaller than the maximum depletion layer width.

  Further, if both contact layers CTS and CTD are too thick, parasitic resistance is generated in the thickness direction, so that the sum of the thickness and the thickness of the channel layer CHN is 100 nm or less as in the first embodiment. It is desirable to form. Further, if the contact layers CTS and CTD are too thin, a sufficiently thick junction interface layer cannot be formed, and the effect of reducing the contact resistance cannot be sufficiently obtained. Therefore, the thickness is the sum of the thickness of the channel layer CHN. Is preferably 10 nm or more.

  Also in the oxide TFT according to the fourth embodiment, the gate insulating film capacitance between the gate electrode GT and the channel layer CHN is Cgi, and the total parasitic capacitance between the structure other than the gate electrode GT and the channel layer CHN is Cp. , The ratio Cp / Cgi of Cp to Cgi is formed to be smaller than 0.7.

  In the semiconductor device in Embodiment 4, since the oxide TFTs are stacked, the number of elements per unit area can be increased, and the area of the entire semiconductor device can be reduced while improving the integration degree of elements. . This is particularly effective when manufacturing a large-capacity memory circuit.

  Also in the configuration of the fourth embodiment, as in the first embodiment, the off-current and subthreshold coefficient S of the oxide TFT can be reduced, and the on-current of the oxide TFT can be improved. . Thereby, it is possible to reduce the power consumption, the voltage, and the speed of the circuit using the oxide TFT according to the fourth embodiment.

  Note that FIG. 29 illustrates an example in which a bottom gate / bottom contact type oxide TFT is stacked. However, the present invention is not limited to this. For example, a top gate / bottom contact type, a bottom gate / top contact type, a top gate / The same effect can be obtained by stacking top contact type oxide TFTs. Moreover, you may change the structure of an oxide TFT for every layer as needed.

(Embodiment 5)
FIG. 30 is a diagram showing a configuration of the semiconductor device according to the fifth embodiment. An antenna resonant circuit AR, a rectifier RCT, a modulator MOD, a digital circuit DGC, and the like are formed using the oxide TFTs having the structures described in Embodiments 1 to 4, and a wireless tag is formed. The wireless tag can communicate with the reader RD or the writer WR wirelessly. The wireless tag performs wireless communication with the reader RD and the writer WR, but requires low power consumption and low voltage. At this time, in the oxide TFTs described in Embodiments 1 to 4, the off-current and the subthreshold coefficient S can be reduced, and the on-current of the oxide TFT can be improved. Thereby, low power consumption, low voltage and high speed of the circuit using the oxide TFT in the first to fourth embodiments can be achieved. Thus, it can be said that the oxide TFTs described in Embodiments 1 to 4 are suitable for use in wireless tags that require low power consumption and low voltage.

  Note that the substrate SUB can be a so-called flexible substrate such as a plastic film by utilizing the fact that the oxide TFTs described in Embodiments 1 to 4 can be formed at a low temperature.

(Embodiment 6)
FIG. 31 is a diagram showing a configuration of the semiconductor device according to the sixth embodiment. In the sixth embodiment, elements each including the oxide TFT having the structure of the first to fourth embodiments as constituent elements are arranged in an array on the substrate SUB. The oxide TFTs shown in the first to fourth embodiments are used for switching and driving transistors of each element in the array, and a signal is sent to the gate line GL connected to the gate electrode GT of the oxide TFT. You may use for the transistor which comprises the data line drive circuit DDC which sends the signal to the data line DL connected to the gate line drive circuit GDC to send and the source electrode ST or drain electrode DT of this oxide TFT. In this case, the oxide TFT of each element and the oxide TFT in the gate line driving circuit GDC or the data line driving circuit DDC can be formed in parallel.

  In addition, the substrate SUB can be a so-called flexible substrate such as a plastic film by utilizing the fact that the oxide TFTs described in Embodiments 1 to 4 can be formed at a low temperature.

  When the above-described array is applied to an active matrix liquid crystal display device, each element has a configuration as shown in FIG. 32, for example. When a scanning signal is supplied to the gate line GL extending in the x direction in the figure, the oxide TFT A1 is turned on, and the image from the data line DL extending in the y direction in the figure through the turned on oxide TFT A1. A signal is supplied to the pixel electrode PT. Note that the gate lines GL are juxtaposed in the y direction in the drawing, the data lines DL are juxtaposed in the x direction in the drawing, and a region (pixel region) surrounded by a pair of adjacent drain lines DL and a pair of adjacent gate lines GL. ) Is provided with a pixel electrode PT. In this case, for example, the data line DL is electrically connected to the source electrode ST, and the pixel electrode PT is electrically connected to the drain electrode DT. Alternatively, the data line DL may also serve as the source electrode ST, and the pixel electrode PT may also serve as the drain electrode DT. Further, the above-described array may be applied not only to a liquid crystal display device but also to an OLED display device. In this case, an oxide TFT is applied to a transistor constituting the pixel circuit. Further, the above-described array may be applied to a memory element, and an oxide TFT may be applied to a selection transistor.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The semiconductor device of the present invention can be applied to a transistor, a peripheral circuit, or the like included in a wireless tag, a memory element array, or the like. Further, the present invention can be applied to a transistor, a peripheral circuit, and the like for driving each pixel such as a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device.

It is sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is a figure explaining one conditional expression for an oxide TFT to realize a fully depleted state. It is a figure explaining one conditional expression for an oxide TFT to realize a fully depleted state. It is a graph which illustrates the conditions for an oxide TFT to realize a fully depleted state. It is a figure which shows the electrostatic capacitance which the channel layer of oxide TFT forms between the surrounding structures. It is a figure which shows the relationship between Cp / Cgi and a subthreshold coefficient. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; 6 is a cross-sectional view showing a modification of the first embodiment. FIG. It is a graph which shows that on-resistance changes with the presence or absence of a contact layer. It is a graph which shows the Id (drain current) -Vg (gate voltage) characteristic of oxide TFT. 6 is a cross-sectional view showing a modification of the first embodiment. FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 10 is a cross-sectional view showing a modification of the second embodiment. FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a third embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the third embodiment. FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 10 is a cross-sectional view showing a modification of the third embodiment. FIG. 10 is a cross-sectional view showing a semiconductor device in a fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device (wireless tag) in Embodiment 5. FIG. 10 is a schematic diagram showing a configuration of a semiconductor device in a sixth embodiment. FIG. 16 is a schematic diagram illustrating a structure in which a semiconductor device in Embodiment 6 is applied to an active matrix liquid crystal display device.

Explanation of symbols

A1 TFT
AR antenna resonance circuit CHN channel layer CTD contact layer CTS contact layer DDC data line drive circuit DGC digital circuit DL data line DT drain electrode GDC gate line drive circuit GI gate insulating film GL gate line GT gate electrode MOD modulator PR photoresist PRO protection Film PRO2 Protective film PRO3 Protective film PT Pixel electrode RCT Rectifier RD Reader ST Source electrode SUB Substrate WIR Wiring WR Writer

Claims (20)

(A) a gate electrode made of a conductive material;
(B) a channel layer that is disposed so as to face the gate electrode and is made of a semiconductor layer using a metal oxide;
(C) a gate insulating film sandwiched between the gate electrode and the channel layer;
(D) comprising a source electrode and a drain electrode electrically connected to the channel layer;
A semiconductor device having a field effect transistor in which the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate electrode, and the thickness of the channel layer is smaller than the maximum depletion layer width,
A semiconductor device, wherein a first conductive layer is formed between the channel layer and the source electrode, and a second conductive layer is formed between the channel layer and the drain electrode. The semiconductor device according to claim 1,
The elementary charge amount is q, the carrier concentration in the channel layer is Nc, the thickness of the channel layer is d, the maximum charge amount that can be controlled by the gate electrode through the gate insulating film is Qg, When the maximum depletion layer width is Wmax,
A semiconductor device characterized by satisfying q × Nc × d <Qg and d <Wmax. The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductive layer and the second conductive layer are formed of a semiconductor layer using a metal oxide. The semiconductor device according to claim 3,
The semiconductor device, wherein the first conductive layer, the second conductive layer, and the channel layer are formed of the same material. The semiconductor device according to claim 1,
The source electrode and the drain electrode are formed through a separation region,
The first conductive layer is formed on the source electrode while covering an end portion of the source electrode on the separated region side, and the drain electrode is formed on the drain electrode while covering an end portion of the drain electrode on the separated region side. A second conductive layer is formed, and the first conductive layer and the second conductive layer are separated by the separation region;
The semiconductor device, wherein the channel layer is formed over the first conductive layer, the separation region, and the second conductive layer. The semiconductor device according to claim 5,
The semiconductor device according to claim 1, wherein the gate electrode is formed below the separation region through the gate insulating film. The semiconductor device according to claim 5,
The semiconductor device, wherein the gate electrode is formed in an upper layer of the separation region through the gate insulating film. The semiconductor device according to claim 5,
An end of the source electrode on the side of the separation region and an end of the drain electrode on the side of the separation region have a tapered shape whose height decreases toward the tip. 9. The semiconductor device according to claim 8, wherein
The end of the first conductive layer on the side of the separation region and the end of the second conductive layer on the side of the separation region have a tapered shape that decreases in height toward the tip. Semiconductor device. The semiconductor device according to claim 1,
The first conductive layer is formed on a partial region of the source electrode;
The semiconductor device, wherein the second conductive layer is formed on a partial region of the drain electrode. The semiconductor device according to claim 10,
A wiring layer is formed on the field effect transistor via an insulating film,
A first plug connecting the wiring layer and the source electrode is formed so as to penetrate the insulating film, and the first plug is formed in the source electrode in a region where the channel layer and the first conductive layer are not formed. Is formed to reach
A second plug connecting the wiring layer and the drain electrode is formed so as to penetrate the insulating film, and the second plug is formed in the drain electrode in a region where the channel layer and the second conductive layer are not formed. The semiconductor device is formed so as to reach The semiconductor device according to claim 1,
The total thickness of the channel layer and the first conductive layer, or the total thickness of the channel layer and the second conductive layer is 10 nm to 100 nm. A semiconductor device characterized by the above. The semiconductor device according to claim 1,
When the gate insulating film capacitance between the gate electrode and the channel layer through the gate insulating film is Cgi, and the total parasitic capacitance between the structure other than the gate electrode and the channel layer is Cp, A semiconductor device, wherein a value of Cp / Cgi indicating a ratio of Cp to Cgi is smaller than 0.7. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the field effect transistor is formed on a glass substrate or a plastic substrate. The semiconductor device according to claim 1,
The field effect transistor is formed by laminating two or more layers. (A) forming a gate electrode on the substrate;
(B) forming a gate insulating film on the substrate so as to cover the gate electrode;
(C) forming a source electrode and a drain electrode on the gate insulating film via a separation region;
(D) forming a first conductive layer on the source electrode and forming a second conductive layer on the drain electrode;
(E) forming a channel layer made of a semiconductor layer using a metal oxide over the first conductive layer, over the separation region, and over the second conductive layer,
In the semiconductor device, the total amount of carriers in the channel layer is smaller than the amount of carriers that can be controlled by the gate electrode, and the thickness of the channel layer is smaller than the maximum depletion layer width. Production method. A method of manufacturing a semiconductor device according to claim 16,
The method for manufacturing a semiconductor device, wherein the first conductive layer and the second conductive layer are formed from a semiconductor layer using a metal oxide. A method of manufacturing a semiconductor device according to claim 17,
The method of manufacturing a semiconductor device, wherein the first conductive layer, the second conductive layer, and the channel layer are formed of the same material. A method of manufacturing a semiconductor device according to claim 16,
In the step (d), the first conductive layer is formed on the source electrode while covering an end of the source electrode on the side of the separation region, and the end of the drain electrode on the side of the separation region is covered. However, the method of manufacturing a semiconductor device, wherein the second conductive layer is formed on the drain electrode. A method of manufacturing a semiconductor device according to claim 16,
In the step (c), the end of the source electrode on the side of the separation region and the end of the drain electrode on the side of the separation region are processed into a tapered shape whose height decreases toward the tip.
In the step (d), the end of the first conductive layer on the side of the separation region and the end of the second conductive layer on the side of the separation region are processed into a tapered shape whose height decreases toward the tip. A method of manufacturing a semiconductor device.

Images