[go: up one dir, main page]

JP2010156805A - Liquid crystal display element - Google Patents

Liquid crystal display element Download PDF

Info

Publication number
JP2010156805A
JP2010156805A JP2008334567A JP2008334567A JP2010156805A JP 2010156805 A JP2010156805 A JP 2010156805A JP 2008334567 A JP2008334567 A JP 2008334567A JP 2008334567 A JP2008334567 A JP 2008334567A JP 2010156805 A JP2010156805 A JP 2010156805A
Authority
JP
Japan
Prior art keywords
liquid crystal
pixel
electrode
crystal display
display element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008334567A
Other languages
Japanese (ja)
Other versions
JP2010156805A5 (en
Inventor
Yayoi Nakamura
やよい 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2008334567A priority Critical patent/JP2010156805A/en
Publication of JP2010156805A publication Critical patent/JP2010156805A/en
Publication of JP2010156805A5 publication Critical patent/JP2010156805A5/ja
Pending legal-status Critical Current

Links

Images

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display element improved in numerical aperture and excelling in display quality. <P>SOLUTION: The liquid crystal element includes a plurality of thin-film transistors 13 provided in matrix shape; a plurality of connecting electrodes 17 connected to the corresponding thin-film transistors respectively; insulating layers 20, 21 provided on the plurality of thin-film transistors 13 and the plurality of the connecting electrodes 17 and having contact holes 22 at the center of every pixel; a plurality of pixel electrodes 12 provided on the insulating layer 21 and connected to the corresponding connecting electrodes 17 respectively through the contact holes 22; and a common electrode 33 disposed facing the insulating layer 21 and the plurality of pixel electrodes 12 with liquid crystal 41 held in between and having apertures 33a in conformity with the positions of the contact holes 22 for every pixel. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、開口率を向上した液晶表示素子に関する。   The present invention relates to a liquid crystal display element having an improved aperture ratio.

液晶表示素子は、間隔を開けて対向する一対の基板のうち一方の基板に、マトリックス状に設けられた複数の画素電極と、これらの複数の画素電極にそれぞれ対応して設けられて接続される複数の薄膜トランジスタと、各薄膜トランジスタにゲート信号とデータ信号とをそれぞれ供給する複数の走査線および複数の信号線と、を設ける一方、他方の基板に複数の画素電極と対向する共通の共通電極(対向電極)を設け、一対の基板の対向面のそれぞれに配向膜を設け、液晶を封入して構成されている。液晶表示素子は、画素毎に画素電極に電圧を印加することで液晶の配向を制御している。   The liquid crystal display element is connected to one of a pair of substrates facing each other with a plurality of pixel electrodes provided in a matrix and corresponding to the plurality of pixel electrodes. A plurality of thin film transistors and a plurality of scanning lines and a plurality of signal lines for supplying a gate signal and a data signal to each thin film transistor are provided, and a common common electrode (facing opposite to the plurality of pixel electrodes is provided on the other substrate) Electrode), an alignment film is provided on each of the opposing surfaces of the pair of substrates, and liquid crystal is sealed. The liquid crystal display element controls the orientation of the liquid crystal by applying a voltage to the pixel electrode for each pixel.

そのうち、配向膜を垂直配向膜として負の誘電異方性を有する液晶を用いた垂直配向型液晶表示素子がある。画素電極と共通電極との間に電界が生じていない場合には、液晶分子は配向膜に垂直となっているが、その間に電界が印加されると、液晶分子はその長軸が電界と直交するように傾斜する。そこで、共通電極側に突起を設け、その突起上にも垂直配向膜を形成する。画素電極と共通電極との間に電圧が印加されていない状態でも突起の領域にある液晶分子を共通基板に対してわずかに傾斜しておく。この状態で画素電極と共通電極との間に電圧を印加すると、液晶分子が突起に向かって倒れる、すなわち突起の頂点を境に液晶分子が逆方向に傾斜することにより、広い視野角が得られる(特許文献1参照)。   Among them, there is a vertical alignment type liquid crystal display element using a liquid crystal having negative dielectric anisotropy with an alignment film as a vertical alignment film. When an electric field is not generated between the pixel electrode and the common electrode, the liquid crystal molecules are perpendicular to the alignment film, but when an electric field is applied between them, the major axis of the liquid crystal molecules is perpendicular to the electric field. Tilt to do. Therefore, a protrusion is provided on the common electrode side, and a vertical alignment film is also formed on the protrusion. Even when no voltage is applied between the pixel electrode and the common electrode, the liquid crystal molecules in the region of the protrusion are slightly inclined with respect to the common substrate. When a voltage is applied between the pixel electrode and the common electrode in this state, the liquid crystal molecules are tilted toward the protrusion, that is, the liquid crystal molecules are tilted in the opposite direction with respect to the apex of the protrusion, thereby obtaining a wide viewing angle. (See Patent Document 1).

特開平11−352489号公報Japanese Patent Laid-Open No. 11-352489

しかしながら、画素電極と共通電極との間に電界が生じていない状態であっても、突起の周囲では液晶分子が基板に対し垂直配向せず、一定の傾斜を有し配列される。よって、突起周りの液晶分子は垂直配向でないため、バックライトが透過する。そのため、TFT基板すなわち薄膜トランジスタが構築されている基板側において突起の領域には、光漏れを防止するために、遮光メタルを設ける必要がある。遮光メタルを設けると、一つの画素の面積に対し、表示に寄与する領域の割合が低下し、開口率が低下する。   However, even in the state where no electric field is generated between the pixel electrode and the common electrode, the liquid crystal molecules are not vertically aligned with respect to the substrate around the protrusions and are arranged with a certain inclination. Therefore, since the liquid crystal molecules around the protrusions are not vertically aligned, the backlight is transmitted. Therefore, it is necessary to provide a light shielding metal in the region of the protrusion on the TFT substrate, that is, the substrate side on which the thin film transistor is constructed, in order to prevent light leakage. When the light shielding metal is provided, the ratio of the region contributing to display is reduced with respect to the area of one pixel, and the aperture ratio is reduced.

突起は共通基板(対向基板)側に設けられ、遮光メタルはTFT基板側に設けられるため、対向基板とTFT基板とを間隔を開けて貼り合わせる際、突起と遮光メタルとの位置合わせで生じ得るずれ分だけ遮光メタルの面積を大きくする必要があり、開口率はさらに低下する。特に、高精細液晶表示素子では開口率の低下が著しくなる。   Since the protrusion is provided on the common substrate (counter substrate) side and the light shielding metal is provided on the TFT substrate side, when the counter substrate and the TFT substrate are bonded to each other with a gap therebetween, the protrusion and the light shielding metal may be aligned. The area of the light shielding metal needs to be increased by the amount of deviation, and the aperture ratio further decreases. In particular, in a high-definition liquid crystal display element, the aperture ratio is significantly reduced.

本発明では、開口率を向上した液晶表示素子を提供することを目的とする。   An object of the present invention is to provide a liquid crystal display element having an improved aperture ratio.

本発明の一つの観点は、マトリックス状に設けられる複数の薄膜トランジスタと、それぞれが対応の薄膜トランジスタに接続される複数の接続電極と、複数の薄膜トランジスタおよび複数の接続電極上に設けられ、画素毎の中央にコンタクトホールを有する、絶縁層と、絶縁層上に設けられ、それぞれが対応の接続電極にコンタクトホールを介して接続される複数の画素電極と、絶縁層および複数の画素電極に対向し液晶を挟んで配置され、画素毎にコンタクトホールの位置にあわせて開口を有する共通電極と、を含むことを特徴とする。   One aspect of the present invention is that a plurality of thin film transistors provided in a matrix, a plurality of connection electrodes each connected to a corresponding thin film transistor, a plurality of thin film transistors and a plurality of connection electrodes are provided on the center of each pixel An insulating layer having a contact hole, a plurality of pixel electrodes provided on the insulating layer, each connected to a corresponding connection electrode via the contact hole, and a liquid crystal facing the insulating layer and the plurality of pixel electrodes. And a common electrode having an opening corresponding to the position of the contact hole for each pixel.

特に、絶縁層に画素毎に形成されるコンタクトホールと共通電極に形成される開口とが同軸上に配置されるとよい。共通電極には、絶縁層に画素毎に形成されるコンタクトホールよりも径の大きい開口を有すると好ましい。画素電極を覆って形成された第1の垂直配向膜と共通電極を覆って形成された第2の垂直配向膜と、これら第1及び第2の垂直配向膜間に介在する負の誘電異方性を有する液晶と、を含むと好ましい。接続電極は透明導電物質で形成されているとよい。   In particular, the contact hole formed for each pixel in the insulating layer and the opening formed in the common electrode are preferably arranged coaxially. The common electrode preferably has an opening having a diameter larger than that of a contact hole formed for each pixel in the insulating layer. A first vertical alignment film formed over the pixel electrode, a second vertical alignment film formed over the common electrode, and a negative dielectric anisotropy interposed between the first and second vertical alignment films And a liquid crystal having properties. The connection electrode may be formed of a transparent conductive material.

本発明によれば、画素電極と接続電極とを接触させるコンタクトホールと共通電極の開口とが位置合わせされているので、画素電極と共通電極との間に電界が生じていない場合、コンタクトホール近辺の液晶分子の傾斜による光漏れが共通電極の開口による液晶分子により抑制される。従って、コンタクト比が向上し表示品質が優れた液晶表示素子が得られる。   According to the present invention, since the contact hole that contacts the pixel electrode and the connection electrode and the opening of the common electrode are aligned, when no electric field is generated between the pixel electrode and the common electrode, the vicinity of the contact hole Light leakage due to the inclination of the liquid crystal molecules is suppressed by the liquid crystal molecules due to the opening of the common electrode. Therefore, a liquid crystal display element with improved contact ratio and excellent display quality can be obtained.

以下、本発明の幾つかの実施の形態について図面を参照しつつ詳細に説明する。
図1は本発明の実施形態に係る液晶表示素子1のうちTFT基板10の平面図、図2は液晶表示素子1のうち共通基板30の平面図、図3は図2のIII−III線に沿う断面図、図4は図1に示すIV−IV線に沿う断面図、図5は図1に示すV−V線に沿う断面図である。
Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.
1 is a plan view of a TFT substrate 10 of the liquid crystal display element 1 according to the embodiment of the present invention, FIG. 2 is a plan view of a common substrate 30 of the liquid crystal display element 1, and FIG. 3 is a line III-III in FIG. 4 is a sectional view taken along line IV-IV shown in FIG. 1, and FIG. 5 is a sectional view taken along line VV shown in FIG.

本発明の実施形態に係る液晶表示素子1はアクティブマトリックス液晶表示素子であり、TFT基板10と対向基板(「共通基板」ともいう)30とが予め所定の間隔を開けて対向して設けられ、TFT基板10と対向基板30との間には液晶が封入され液晶層40が形成されている。   The liquid crystal display element 1 according to the embodiment of the present invention is an active matrix liquid crystal display element, in which a TFT substrate 10 and a counter substrate (also referred to as “common substrate”) 30 are provided in front of each other with a predetermined interval therebetween, Liquid crystal is sealed between the TFT substrate 10 and the counter substrate 30 to form a liquid crystal layer 40.

TFT基板10は、透明基板11と、透明基板面内にマトリックス状に配置するよう設けられた複数の画素電極12と、複数の画素電極12のそれぞれに対応するよう設けられる複数の薄膜トランジスタ(TFT:Thin Film Transistor)13と、これら複数の薄膜トランジスタ13のそれぞれにゲート信号およびデータ信号を供給するよう行方向、列方向にそれぞれ設けられる複数のゲート線14および複数の信号線15と、複数の画素電極12のそれぞれに対して設けられる複数の補助容量電極16と、画素電極12と薄膜トランジスタ13とを接続する接続電極17と、画素電極12を含むTFT基板表面に設けられる配向膜18と、を備えている。   The TFT substrate 10 includes a transparent substrate 11, a plurality of pixel electrodes 12 provided so as to be arranged in a matrix on the transparent substrate surface, and a plurality of thin film transistors (TFTs) provided so as to correspond to the plurality of pixel electrodes 12, respectively. Thin Film Transistor) 13, a plurality of gate lines 14 and a plurality of signal lines 15 respectively provided in the row direction and the column direction so as to supply a gate signal and a data signal to each of the plurality of thin film transistors 13, and a plurality of pixel electrodes A plurality of auxiliary capacitance electrodes 16 provided for each of 12, a connection electrode 17 for connecting the pixel electrode 12 and the thin film transistor 13, and an alignment film 18 provided on the surface of the TFT substrate including the pixel electrode 12. Yes.

一方、対向基板30は、透明基板31と、透明基板31面に設けられるカラーフィルター32と、このカラーフィルター32上に設けられ、画素毎に開口33aを有する共通電極(対向電極)33と、対向基板30の表面、すなわち共通電極33およびカラーフィルター32面上に設けられる配向膜34と、を含んでいる。図2に示すように、R、G、Bの各カラーフィルターが順に並んで設けられる。   On the other hand, the counter substrate 30 is opposed to a transparent substrate 31, a color filter 32 provided on the surface of the transparent substrate 31, and a common electrode (counter electrode) 33 provided on the color filter 32 and having an opening 33a for each pixel. An alignment film 34 provided on the surface of the substrate 30, that is, on the surface of the common electrode 33 and the color filter 32 is included. As shown in FIG. 2, R, G, and B color filters are provided in order.

TFT基板10の構成について詳細に説明する。
ガラス基板などの透明基板11上に複数本のゲート線14が列方向に間隔を空けて並んで配置され、それぞれのゲート線14が行方向に配設されている。各ゲート線14には画素領域毎にゲート電極13aを有している。ゲート線14は、例えばCrなどの金属で形成されている。
The configuration of the TFT substrate 10 will be described in detail.
A plurality of gate lines 14 are arranged side by side in the column direction on a transparent substrate 11 such as a glass substrate, and each gate line 14 is arranged in the row direction. Each gate line 14 has a gate electrode 13a for each pixel region. The gate line 14 is formed of a metal such as Cr, for example.

透明基板11、ゲート線14を覆って第1の絶縁層19が形成されている。
第1の絶縁層19上には複数の信号線15が行方向に間隔を空けて並んで設けられ、それぞれの信号線15が列方向に配設されている。信号線15は、図5に示すように、半導体層15aとオーミックコンタクト層15bと金属層15cとの積層で構成され、後述する薄膜トランジスタ13の一部の積層と同一のプロセスで形成される。
A first insulating layer 19 is formed so as to cover the transparent substrate 11 and the gate line 14.
On the first insulating layer 19, a plurality of signal lines 15 are provided side by side in the row direction, and each signal line 15 is arranged in the column direction. As shown in FIG. 5, the signal line 15 is composed of a stacked layer of a semiconductor layer 15a, an ohmic contact layer 15b, and a metal layer 15c, and is formed by the same process as a partially stacked layer of a thin film transistor 13 described later.

隣り合うゲート線14,14および信号線15,15で囲まれる各領域は一つの画素領域を構成し、画素領域毎に薄膜トランジスタ13が設けられる。この薄膜トランジスタ13は、各画素領域の所定位置、図1に示す例では下側のゲート線14の一部がゲート電極13aとなり、第1の絶縁層19のうちこのゲート電極13aを覆う部分がゲート絶縁膜13bとなり、このゲート絶縁膜13bを覆うように半導体層13cが設けられ、ゲート電極13aの領域で半導体層13c面にエッチングストッパー層13dが設けられ、このエッチングストッパー層13d面を一部分覆うよう列方向に対向して延びる一対のオーミックコンタクト層13e,13fと、この一対のオーミックコンタクト層13e,13fをそれぞれ覆うようにドレイン電極13gおよびソース電極13hが設けられることにより、構成されている。   Each region surrounded by adjacent gate lines 14 and 14 and signal lines 15 and 15 constitutes one pixel region, and a thin film transistor 13 is provided for each pixel region. In the thin film transistor 13, a predetermined position in each pixel region, in the example shown in FIG. 1, a part of the lower gate line 14 becomes a gate electrode 13a, and a portion of the first insulating layer 19 covering the gate electrode 13a is a gate. A semiconductor layer 13c is provided so as to cover the gate insulating film 13b, and an etching stopper layer 13d is provided on the surface of the semiconductor layer 13c in the region of the gate electrode 13a, and a part of the surface of the etching stopper layer 13d is covered. A pair of ohmic contact layers 13e and 13f extending opposite to each other in the column direction, and a drain electrode 13g and a source electrode 13h are provided so as to cover the pair of ohmic contact layers 13e and 13f, respectively.

ソース電極13hおよび第1の絶縁層19上には接続電極17が設けられている。
接続電極17は、隣り合うゲート線14,14と隣り合う信号線15,15とのほぼ中間の領域に配置される矩形状の中央部17aと、中央部17aから列方向に細く延びてソース電極13h上に部分的に重なり合う細長部17bとを有する。この細長部17bの行方向幅は、ソース電極13hの行方向幅よりも短い。
A connection electrode 17 is provided on the source electrode 13 h and the first insulating layer 19.
The connection electrode 17 includes a rectangular central portion 17a disposed in a substantially intermediate region between the adjacent gate lines 14 and 14 and the adjacent signal lines 15 and 15, and a source electrode extending thinly from the central portion 17a in the column direction. And an elongated portion 17b that partially overlaps 13h. The row width of the elongated portion 17b is shorter than the row width of the source electrode 13h.

薄膜トランジスタ13の半導体層13c,エッチングストッパー層13d,一対のオーミックコンタクト層13e,13f,ドレイン電極13gおよびソース電極13hの積層構造は第1の絶縁層19面上に形成され、前述の信号線15も第1の絶縁層19面上に形成されるため、信号線15も半導体層15a,オーミックコンタクト層15b,金属層15cの積層構造を有し、薄膜トランジスタ13のプロセスと同時に形成される。   The laminated structure of the semiconductor layer 13c, the etching stopper layer 13d, the pair of ohmic contact layers 13e and 13f, the drain electrode 13g and the source electrode 13h of the thin film transistor 13 is formed on the surface of the first insulating layer 19, and the signal line 15 described above is also formed. Since it is formed on the surface of the first insulating layer 19, the signal line 15 also has a stacked structure of the semiconductor layer 15a, the ohmic contact layer 15b, and the metal layer 15c, and is formed simultaneously with the process of the thin film transistor 13.

信号線15、第1の絶縁層19および各画素領域の薄膜トランジスタ13上に第2の絶縁層20が形成されている。
第2の絶縁層20上において、各ゲート線14および各信号線15の領域には、それぞれ補助容量電極16が設けられ、行方向および列方向で隣り合う補助容量電極16で枠状をなしている。
補助容量電極16および第2の絶縁層20上には第3の絶縁層21が設けられている。第2の絶縁層20および第3の絶縁層21には、各画素領域のほぼ中心部にコンタクトホール22が貫通して形成され、接続電極17の中央部17aの一部を露出している。コンタクトホール22の中心は接続電極17の中央部17aの中心とほぼ同軸上に形成されている。
第3の絶縁層21上において、各画素領域全体に亙って、かつ、コンタクトホール22の開口縁部22aおよび接続電極17上に、画素電極12が形成されている。
A second insulating layer 20 is formed on the signal line 15, the first insulating layer 19, and the thin film transistor 13 in each pixel region.
On the second insulating layer 20, the auxiliary capacitance electrodes 16 are provided in the regions of the gate lines 14 and the signal lines 15, respectively. The auxiliary capacitance electrodes 16 adjacent in the row direction and the column direction form a frame shape. Yes.
A third insulating layer 21 is provided on the auxiliary capacitance electrode 16 and the second insulating layer 20. In the second insulating layer 20 and the third insulating layer 21, a contact hole 22 is formed so as to penetrate almost the center of each pixel region, and a part of the central portion 17 a of the connection electrode 17 is exposed. The center of the contact hole 22 is formed substantially coaxially with the center of the central portion 17 a of the connection electrode 17.
On the third insulating layer 21, the pixel electrode 12 is formed over the entire pixel region and on the opening edge 22 a of the contact hole 22 and the connection electrode 17.

画素電極12は、図4および図5に示す例では、画素電極12における列方向の縁部12a,12bが信号線15,15と部分的に重ならず補助容量電極16と部分的に重なり合い、画素電極12における行方向の縁部12c,12dがゲート線14,14と部分的に重ならず補助容量電極16と部分的に重なり合っている。なお、画素電極12における列方向の縁部12a,12bを信号線15,15と部分的に重なり合い、画素電極12における行方向の縁部12c,12dのうち一方又は双方をゲート線14と部分的に重なり合うように形成されていてもよい。画素電極12および接続電極17は、ITOなどの透明導電物質で形成されている。   In the example shown in FIGS. 4 and 5, the pixel electrode 12 has edge portions 12 a and 12 b in the column direction of the pixel electrode 12 partially overlapping with the auxiliary capacitance electrode 16 instead of partially overlapping with the signal lines 15 and 15. Edges 12 c and 12 d in the row direction of the pixel electrode 12 do not partially overlap the gate lines 14 and 14 but partially overlap the auxiliary capacitance electrode 16. Note that the column-direction edges 12a and 12b of the pixel electrode 12 partially overlap the signal lines 15 and 15, and one or both of the row-direction edges 12c and 12d of the pixel electrode 12 are partially connected to the gate line 14. It may be formed so as to overlap. The pixel electrode 12 and the connection electrode 17 are formed of a transparent conductive material such as ITO.

複数の画素電極12および第3の絶縁層21上には第1の配向膜としての垂直配向膜18が設けられている。この垂直配向膜18はラビング処理がされていても、されていなくてもよい。   A vertical alignment film 18 as a first alignment film is provided on the plurality of pixel electrodes 12 and the third insulating layer 21. The vertical alignment film 18 may or may not be rubbed.

対向基板30、特にCF基板の構造について説明する。
透明基板31面にはRGBの各カラーフィルター32が設けられ、カラーフィルター32上に共通電極33が形成されている。共通電極33には、画素領域毎に、画素電極12の中央部でコンタクトホール22を経由して接続電極17に接続している底部22bの中心軸上に、開口33aを有している。開口33aは、図2に示すように、例えば円形である。コンタクトホール22の底部22b中心と開口33aの中心とはほぼ同軸上にある。ここで、開口33aの径は、コンタクトホール22の寸法よりも大きい。この理由は後述する。
The structure of the counter substrate 30, particularly the CF substrate will be described.
RGB color filters 32 are provided on the surface of the transparent substrate 31, and a common electrode 33 is formed on the color filter 32. The common electrode 33 has an opening 33a on the central axis of the bottom 22b connected to the connection electrode 17 via the contact hole 22 at the center of the pixel electrode 12 for each pixel region. As shown in FIG. 2, the opening 33a is circular, for example. The center of the bottom 22b of the contact hole 22 and the center of the opening 33a are substantially coaxial. Here, the diameter of the opening 33 a is larger than the dimension of the contact hole 22. The reason for this will be described later.

共通電極33およびカラーフィルター32上には、第2の配向膜としての垂直配向膜34が形成されている。この垂直配向膜34はラビング処理がされていてもされていなくてもよい。   A vertical alignment film 34 as a second alignment film is formed on the common electrode 33 and the color filter 32. The vertical alignment film 34 may or may not be rubbed.

TFT基板10と対向基板30とは、前述のように、各画素領域において、コンタクトホール22の中心軸と開口33aの中心軸とがほぼ同軸となるよう、所定の間隔をおいて配置され、垂直配向膜18,34の間に、負の誘電異方性を有する液晶分子が充填され、液晶層40となっている。   As described above, the TFT substrate 10 and the counter substrate 30 are arranged at a predetermined interval so that the central axis of the contact hole 22 and the central axis of the opening 33a are substantially coaxial in each pixel region. Liquid crystal molecules having negative dielectric anisotropy are filled between the alignment films 18 and 34 to form the liquid crystal layer 40.

この液晶表示素子1においては、図示を省略するが、TFT基板10の下側に偏光板が設けられ、共通基板31の上側に偏光板が設けられ、両偏光板は互いに直交している。   In the liquid crystal display element 1, although not shown, a polarizing plate is provided on the lower side of the TFT substrate 10, a polarizing plate is provided on the upper side of the common substrate 31, and the two polarizing plates are orthogonal to each other.

図6は、画素電極12と共通電極33との間の液晶分子41の様子を模式的に示し、(A)は電界が生じていない場合を、(B)は電界が生じている場合を、それぞれ示す図である。
画素電極12と共通電極33との間に電位差が生じていない、すなわち電界が生じていない場合には、図6(A)に示すように、画素電極12側、共通電極33側も、液晶分子41の長軸が配向膜18,34に垂直となるように配向している。とくに、コンタクトホール22側の縁では、液晶分子41はコンタクトホール22の中心軸に傾いている。その結果、TFT基板10の裏面側からのバックライトがわずかに漏れる可能性がある。しかし、共通基板30側の液晶分子41は共通基板30の開口33a内において垂直配向しており、開口33aの径はコンタクトホール22の寸法(幅および長さ)よりも大きいので、その漏れも小さい。
この状態で、画素電極12と共通電極33との間に電位差が生じると、共通電極33と画素電極12との面上では、図6(B)に点線で示すように共通電極33および画素電極12の何れにも直交するように電界が生じるのに対し、共通電極33の開口33aの端では画素電極12に向かって湾曲した電界が生じる。液晶分子41は負の誘電異方性を有するため、液晶分子41はその長軸が電界と直交するように配向する。よって、液晶分子41は、共通電極33の開口33aの周りでは、その開口33aの中心軸に傾斜し、しかも、一つの画素領域内の液晶分子41が開口33aを中心軸として対称となり、広い視野角が得られる。
6 schematically shows the state of the liquid crystal molecules 41 between the pixel electrode 12 and the common electrode 33, where (A) shows a case where no electric field is generated, and (B) shows a case where an electric field is generated. FIG.
When no potential difference is generated between the pixel electrode 12 and the common electrode 33, that is, when an electric field is not generated, the pixel electrode 12 side and the common electrode 33 side also have liquid crystal molecules as shown in FIG. The long axis 41 is aligned so as to be perpendicular to the alignment films 18 and 34. In particular, the liquid crystal molecules 41 are inclined toward the central axis of the contact hole 22 at the edge on the contact hole 22 side. As a result, the backlight from the back side of the TFT substrate 10 may slightly leak. However, since the liquid crystal molecules 41 on the common substrate 30 side are vertically aligned in the opening 33a of the common substrate 30, and the diameter of the opening 33a is larger than the dimensions (width and length) of the contact hole 22, the leakage is small. .
In this state, when a potential difference is generated between the pixel electrode 12 and the common electrode 33, the common electrode 33 and the pixel electrode are shown on the surface of the common electrode 33 and the pixel electrode 12 as indicated by a dotted line in FIG. While an electric field is generated so as to be orthogonal to any of 12, an electric field curved toward the pixel electrode 12 is generated at the end of the opening 33 a of the common electrode 33. Since the liquid crystal molecules 41 have negative dielectric anisotropy, the liquid crystal molecules 41 are aligned so that their long axes are orthogonal to the electric field. Accordingly, the liquid crystal molecules 41 are inclined around the central axis of the opening 33a around the opening 33a of the common electrode 33, and the liquid crystal molecules 41 in one pixel region are symmetric with respect to the central axis of the opening 33a. A corner is obtained.

本発明の実施形態では、列方向に隣り合うゲート線14,14と行方向に隣り合う信号線15,15とで一つの画素領域を画成し、画素電極12を各画素領域全体に亙って形成し、かつ、コンタクトホール22を各画素領域の対角線の略中心に形成し、そのコンタクトホール下で接続電極17の中央部17aが形成されている。一方、共通電極33の開口33aの中心がコンタクトホール22の中心とほぼ同軸に配置されている。よって、画素電極12と共通電極33との間に電界が生じていない状態では黒表示となるが、コンタクトホール22の開口縁部22aでは液晶分子41が傾斜しても、バックライトが光漏れし難い。この状態から電界が生じると、開口33aを中心に液晶分子41が傾斜し、白表示となる。その際、液晶分子41が開口33aを取り囲むように傾斜して配向制御もできる。また、本実施形態では、各接続電極17は、ITOなどの透明導電性物質で形成され、各画素領域の中心領域まで張り出しているため、接続電極17によりコントラス比が低下しない。よって、開口率の低下も阻止することができ、高精細の液晶表示素子を提供することができる。   In the embodiment of the present invention, one pixel region is defined by the gate lines 14 and 14 adjacent in the column direction and the signal lines 15 and 15 adjacent in the row direction, and the pixel electrode 12 extends over the entire pixel region. The contact hole 22 is formed at the approximate center of the diagonal line of each pixel region, and the central portion 17a of the connection electrode 17 is formed under the contact hole. On the other hand, the center of the opening 33 a of the common electrode 33 is arranged substantially coaxially with the center of the contact hole 22. Therefore, black is displayed when no electric field is generated between the pixel electrode 12 and the common electrode 33, but the backlight leaks light even when the liquid crystal molecules 41 are inclined at the opening edge 22a of the contact hole 22. hard. When an electric field is generated from this state, the liquid crystal molecules 41 are tilted around the opening 33a and white display is performed. At that time, the liquid crystal molecules 41 can be tilted so as to surround the opening 33a and the alignment can be controlled. In the present embodiment, each connection electrode 17 is formed of a transparent conductive material such as ITO and extends to the center region of each pixel region. Therefore, the contrast ratio is not lowered by the connection electrode 17. Therefore, a decrease in aperture ratio can be prevented, and a high-definition liquid crystal display element can be provided.

本発明の実施形態は上述したものに限定されることなく、本発明の趣旨の範囲内で種々変形して適用することができる。   Embodiments of the present invention are not limited to those described above, and various modifications can be applied within the scope of the gist of the present invention.

例えば、前述した例では補助容量電極16を画素領域毎に枠状に金属で構成しているが、内側の部分だけITOなどの透明電極材料で構成することで、開口率の低下を免れることができる。   For example, in the above-described example, the auxiliary capacitance electrode 16 is made of a metal in a frame shape for each pixel region. However, if only the inner part is made of a transparent electrode material such as ITO, it is possible to avoid a decrease in the aperture ratio. it can.

図7は本発明の別の実施形態について、隣り合うゲート線と隣り合う信号線とで囲まれる一領域について、接続電極17と画素電極52と、共通電極の位置関係を示す平面図である。一つの画素電極52が図1に示すように列方向に長い場合には、図7に示すように、画素電極52を例えば3つの領域に分割されるように行方向にスリット52aを設け、すなわち、画素電極52を3つの領域に分け、その細分化した領域毎に、その中心に共通電極の開口63を設け、各開口63と対峙するようにコンタクトホールをそれぞれ設け、接続電極17と接続されるとよい。   FIG. 7 is a plan view showing the positional relationship between the connection electrode 17, the pixel electrode 52, and the common electrode in one region surrounded by adjacent gate lines and adjacent signal lines, according to another embodiment of the present invention. When one pixel electrode 52 is long in the column direction as shown in FIG. 1, as shown in FIG. 7, slits 52a are provided in the row direction so as to divide the pixel electrode 52 into, for example, three regions. The pixel electrode 52 is divided into three regions, a common electrode opening 63 is provided at the center of each of the subdivided regions, contact holes are provided so as to face the openings 63, and the pixel electrode 52 is connected to the connection electrode 17. Good.

また、薄膜トランジスタ13のドレイン電極13gおよびソース電極13hをITO等の透明導電性物質で形成してもよく、その場合には、接続電極17をドレイン電極13gおよびソース電極13hと同プロセスで一体的に形成してもよい。   Further, the drain electrode 13g and the source electrode 13h of the thin film transistor 13 may be formed of a transparent conductive material such as ITO. In this case, the connection electrode 17 is integrated with the drain electrode 13g and the source electrode 13h in the same process. It may be formed.

また、図示する例では、TFT基板10においてコンタクトホール22の下側には遮光メタルを配置していないため、開口率がより向上するが、サイズ制限がない場合には、遮光メタルを配置しても構わない。また、共通電極33の開口33aは、平面視で円形でなく多角形状としてもよく、コンタクトホール22も平面視で円形や多角形状とすることもできる。また、コンタクトホール22は、各画素領域の対角線の略中心に形成する場合で説明したが、視野角拡大等、液晶配向を制御可能であれば、各画素領域のどの位置に形成してもよく、その場合、画素領域毎に異なる位置に配置してもよい。さらに、本実施形態では、負の誘電異方性を有する垂直配向型液晶表示素子で説明したが、正の誘電異方性を有する垂直配向型液晶表示素子、あるいは、垂直配向型液晶表示素子とは異なる液晶表示素子に適用することが可能である。   In the illustrated example, since the light shielding metal is not disposed below the contact hole 22 in the TFT substrate 10, the aperture ratio is further improved. However, when there is no size limitation, the light shielding metal is disposed. It doesn't matter. Further, the opening 33a of the common electrode 33 may be a polygonal shape instead of a circle in a plan view, and the contact hole 22 may be a circle or a polygonal shape in a plan view. In addition, the contact hole 22 has been described in the case where it is formed at substantially the center of the diagonal line of each pixel region. However, the contact hole 22 may be formed at any position in each pixel region as long as the liquid crystal orientation can be controlled, such as widening the viewing angle. In this case, the pixel regions may be arranged at different positions. Further, in the present embodiment, the vertical alignment type liquid crystal display element having negative dielectric anisotropy has been described. However, the vertical alignment type liquid crystal display element having positive dielectric anisotropy or the vertical alignment type liquid crystal display element Can be applied to different liquid crystal display elements.

本発明の実施形態に係る液晶表示素子のうちTFT基板の平面図である。It is a top view of a TFT substrate among liquid crystal display elements concerning an embodiment of the present invention. 本発明の実施形態に係る液晶表示素子のうち共通基板の平面図である。It is a top view of a common board | substrate among the liquid crystal display elements which concern on embodiment of this invention. 本発明の実施形態に係る液晶表示素子に関する、図2のIII−III線に沿う断面図である。It is sectional drawing which follows the III-III line | wire of FIG. 2 regarding the liquid crystal display element which concerns on embodiment of this invention. 本発明の実施形態に係る液晶表示素子に関する、図1のIV−IV線に沿う断面図である。It is sectional drawing which follows the IV-IV line | wire of FIG. 1 regarding the liquid crystal display element which concerns on embodiment of this invention. 本発明の実施形態に係る液晶表示素子に関する、図1に示すV−V線に沿う断面図である。It is sectional drawing which follows the VV line | wire shown in FIG. 1 regarding the liquid crystal display element which concerns on embodiment of this invention. 画素電極と共通電極との間の液晶分子の様子を模式的に示し、(A)は電界が生じていない場合を、(B)は電界が生じている場合を、それぞれ示す図である。The state of the liquid crystal molecules between the pixel electrode and the common electrode is schematically shown. (A) shows a case where no electric field is generated, and (B) shows a case where an electric field is generated. 本発明の別の実施形態について、隣り合うゲート線と隣り合う信号線とで囲まれる一領域について、接続電極と画素電極と共通電極の位置関係を示す平面図である。It is a top view which shows the positional relationship of a connection electrode, a pixel electrode, and a common electrode about one area | region enclosed by the adjacent gate line and the adjacent signal line about another embodiment of this invention.

符号の説明Explanation of symbols

1:液晶表示素子
10:TFT基板
11:透明基板
12,52:画素電極
12c,12d:画素電極の縁部
13:薄膜トランジスタ
13a:ゲート電極
13b:ゲート絶縁膜
13c:半導体層
13d:エッチングストッパー層
13e,13f:オーミックコンタクト層
13g:ドレイン電極
13h:ソース電極
14:ゲート線
15:信号線
15a:半導体層
15b:オーミックコンタクト層
15c:金属層
16:補助容量電極
17:接続電極
17a:中央部
17b:細長部
18,34:配向膜
19:第1の絶縁層
20:第2の絶縁層
21:第3の絶縁層
22:コンタクトホール
22a:開口縁部
22b:底部
30:共通基板(対向基板)
31:透明基板
32:カラーフィルター
33:共通電極
33a,63a:共通電極の開口
34:配向膜
40:液晶層
41:液晶分子
52a:スリット
1: liquid crystal display element 10: TFT substrate 11: transparent substrate 12, 52: pixel electrode 12c, 12d: edge of pixel electrode 13: thin film transistor 13a: gate electrode 13b: gate insulating film 13c: semiconductor layer 13d: etching stopper layer 13e , 13f: ohmic contact layer 13g: drain electrode 13h: source electrode 14: gate line 15: signal line 15a: semiconductor layer 15b: ohmic contact layer 15c: metal layer 16: auxiliary capacitance electrode 17: connection electrode 17a: central portion 17b: The elongated portions 18 and 34: the alignment film 19: the first insulating layer 20: the second insulating layer 21: the third insulating layer 22: the contact hole 22a: the opening edge 22b: the bottom 30: a common substrate (counter substrate)
31: Transparent substrate 32: Color filter 33: Common electrode 33a, 63a: Opening of common electrode 34: Alignment film 40: Liquid crystal layer 41: Liquid crystal molecule 52a: Slit

Claims (5)

マトリックス状に設けられる複数の薄膜トランジスタと、
それぞれが対応する前記薄膜トランジスタに接続される複数の接続電極と、
前記複数の薄膜トランジスタおよび前記複数の接続電極上に設けられ、画素毎の中央にコンタクトホールを有する、絶縁層と、
前記絶縁層上に設けられ、それぞれが対応する前記接続電極に前記コンタクトホールを介して接続される複数の画素電極と、
前記絶縁層および前記複数の画素電極に対向し液晶を挟んで配置され、画素毎に前記コンタクトホールの位置にあわせて開口を有する共通電極と、
を含む液晶表示素子。
A plurality of thin film transistors provided in a matrix;
A plurality of connection electrodes each connected to the corresponding thin film transistor;
An insulating layer provided on the plurality of thin film transistors and the plurality of connection electrodes and having a contact hole in the center of each pixel;
A plurality of pixel electrodes provided on the insulating layer, each connected to the corresponding connection electrode via the contact hole;
A common electrode disposed opposite to the insulating layer and the plurality of pixel electrodes with a liquid crystal in between, and having an opening corresponding to the position of the contact hole for each pixel;
A liquid crystal display element comprising:
前記絶縁層に画素毎に形成されるコンタクトホールと前記共通電極に形成される開口とが同軸上に配置される、請求項1に記載の液晶表示素子。   The liquid crystal display element according to claim 1, wherein a contact hole formed in the insulating layer for each pixel and an opening formed in the common electrode are arranged coaxially. 前記共通電極は、前記絶縁層に画素毎に形成されるコンタクトホールよりも径の大きい前記開口を有する、請求項1に記載の液晶表示素子。   The liquid crystal display element according to claim 1, wherein the common electrode has the opening having a diameter larger than a contact hole formed in the insulating layer for each pixel. 前記画素電極を覆って形成された第1の垂直配向膜と、前記共通電極を覆って形成された第2の垂直配向膜と、前記第1及び第2の垂直配向膜間に介在する負の誘電異方性を有する前記液晶と、を含む、請求項1に記載の液晶表示素子。   A first vertical alignment film formed over the pixel electrode; a second vertical alignment film formed over the common electrode; and a negative intervening between the first and second vertical alignment films. The liquid crystal display element according to claim 1, comprising the liquid crystal having dielectric anisotropy. 前記接続電極は透明導電物質で形成されている、請求項1に記載の液晶表示素子。   The liquid crystal display element according to claim 1, wherein the connection electrode is formed of a transparent conductive material.
JP2008334567A 2008-12-26 2008-12-26 Liquid crystal display element Pending JP2010156805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008334567A JP2010156805A (en) 2008-12-26 2008-12-26 Liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008334567A JP2010156805A (en) 2008-12-26 2008-12-26 Liquid crystal display element

Publications (2)

Publication Number Publication Date
JP2010156805A true JP2010156805A (en) 2010-07-15
JP2010156805A5 JP2010156805A5 (en) 2011-11-24

Family

ID=42574778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008334567A Pending JP2010156805A (en) 2008-12-26 2008-12-26 Liquid crystal display element

Country Status (1)

Country Link
JP (1) JP2010156805A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018091947A (en) * 2016-12-01 2018-06-14 株式会社 オルタステクノロジー Liquid crystal display device
JP2020532756A (en) * 2017-09-05 2020-11-12 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co.,Ltd. Array boards, liquid crystal display panels and display devices

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152625A (en) * 1995-08-11 1997-06-10 Sharp Corp Transmissive liquid crystal display device and manufacturing method thereof
JP2005301125A (en) * 2004-04-15 2005-10-27 Seiko Epson Corp Liquid crystal display device, method for manufacturing the same, and electronic apparatus
JP2006058734A (en) * 2004-08-23 2006-03-02 Seiko Epson Corp Liquid crystal display device and electronic device
JP2006072088A (en) * 2004-09-03 2006-03-16 Seiko Epson Corp Liquid crystal display device, electronic equipment
JP2006154362A (en) * 2004-11-30 2006-06-15 Sanyo Epson Imaging Devices Corp Liquid crystal display panel
JP2006245031A (en) * 2005-02-28 2006-09-14 Casio Comput Co Ltd Thin film transistor panel
JP2007094255A (en) * 2005-09-30 2007-04-12 Epson Imaging Devices Corp Liquid crystal device and electronic equipment
JP2007148203A (en) * 2005-11-30 2007-06-14 Epson Imaging Devices Corp LCD panel
JP2007206135A (en) * 2006-01-31 2007-08-16 Epson Imaging Devices Corp Liquid crystal display panel
JP2008116528A (en) * 2006-11-01 2008-05-22 Epson Imaging Devices Corp Liquid crystal display panel
JP2008197493A (en) * 2007-02-14 2008-08-28 Toshiba Matsushita Display Technology Co Ltd Liquid crystal display

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152625A (en) * 1995-08-11 1997-06-10 Sharp Corp Transmissive liquid crystal display device and manufacturing method thereof
JP2005301125A (en) * 2004-04-15 2005-10-27 Seiko Epson Corp Liquid crystal display device, method for manufacturing the same, and electronic apparatus
JP2006058734A (en) * 2004-08-23 2006-03-02 Seiko Epson Corp Liquid crystal display device and electronic device
JP2006072088A (en) * 2004-09-03 2006-03-16 Seiko Epson Corp Liquid crystal display device, electronic equipment
JP2006154362A (en) * 2004-11-30 2006-06-15 Sanyo Epson Imaging Devices Corp Liquid crystal display panel
JP2006245031A (en) * 2005-02-28 2006-09-14 Casio Comput Co Ltd Thin film transistor panel
JP2007094255A (en) * 2005-09-30 2007-04-12 Epson Imaging Devices Corp Liquid crystal device and electronic equipment
JP2007148203A (en) * 2005-11-30 2007-06-14 Epson Imaging Devices Corp LCD panel
JP2007206135A (en) * 2006-01-31 2007-08-16 Epson Imaging Devices Corp Liquid crystal display panel
JP2008116528A (en) * 2006-11-01 2008-05-22 Epson Imaging Devices Corp Liquid crystal display panel
JP2008197493A (en) * 2007-02-14 2008-08-28 Toshiba Matsushita Display Technology Co Ltd Liquid crystal display

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018091947A (en) * 2016-12-01 2018-06-14 株式会社 オルタステクノロジー Liquid crystal display device
JP2020532756A (en) * 2017-09-05 2020-11-12 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co.,Ltd. Array boards, liquid crystal display panels and display devices
JP7341064B2 (en) 2017-09-05 2023-09-08 京東方科技集團股▲ふん▼有限公司 Array substrates, liquid crystal display panels and display devices

Similar Documents

Publication Publication Date Title
JP4946135B2 (en) Liquid crystal display element
US9785017B2 (en) Liquid crystal display
JP4667587B2 (en) Liquid crystal display device
US8988621B2 (en) Array substrate and display panel having the same
US8767147B2 (en) Liquid crystal display wherein a first light blocking portion and a first colored portion extends generally along a gate line and generally covers the gate line and a thin film transistor
US20100007835A1 (en) Liquid crystal display apparatus which performs display by using electric field in direction substantially parallel with substrate surfaces to control alignment direction of liquid crystal molecules
US8384867B2 (en) Liquid crystal display device
JP2009223245A (en) Liquid crystal display device
US8730442B2 (en) Liquid crystal display device and manufacturing method thereof
JP2006201353A (en) Liquid crystal display
JP2010134294A5 (en)
JP4752266B2 (en) Liquid crystal display element
US9835906B2 (en) Liquid crystal display and method for manufacturing the same
US7639339B2 (en) Liquid crystal display device having substrate spacers engaging with contact holes that contact pixel electrode with the electrodes of switching elements
US9494838B2 (en) Liquid crystal display device
JP4658622B2 (en) Substrate for liquid crystal display device and liquid crystal display device
US20160320647A1 (en) Thin film transistor substrate
US8432520B2 (en) Liquid crystal display device
US10890815B2 (en) Display apparatus
US10168581B2 (en) Display device
US10139684B2 (en) Liquid crystal display and electronic apparatus having electrodes with openings therein
WO2013161761A1 (en) Liquid crystal display element and liquid crystal display device
JP2010156805A (en) Liquid crystal display element
JP2010156805A5 (en)
JP2009229970A (en) Liquid crystal display panel

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111006

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111006

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120921

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121009

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130312