JP2010157297A - Arrangement of half-select-prevention cell of semiconductor memory - Google Patents

Abstract

In a semiconductor memory capable of dynamically changing the bit reliability of a memory cell according to an application and a memory condition, ensuring operation stability and realizing low power consumption and high reliability, Provided is a cell arrangement for preventing data destruction in a memory cell pair in a half-selected state, which is a concern during a write operation in a high reliability mode.
In a memory cell array in which memory cell pairs each formed by connecting two memory cells in one bit are arranged in a two-dimensional array, a memory corresponding to one memory cell pair in odd and even columns The layout is arranged so as to be shifted by the cells, two word lines are provided in the same row, two bit lines are provided in the same column, and four types of word line combinations are provided for up to eight memory cell pairs. Two kinds of freedom of selection are provided in the columns and even columns, and only two word lines are set up only in the memory cell pair selected for writing.
[Selection] Figure 9

Description

  The present invention relates to a cell arrangement for preventing half-selection of a semiconductor memory.

  In recent years, memories such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) have progressed with CMOS process technology mounted on SoC, and the processing dimensions (scaling size) of integrated circuits have been reduced, and higher chips. Density and low chip cost are realized and memory capacity is increasing. Such reduction of the scaling size expands the variation in threshold voltage of the transistors constituting the memory cell such as SRAM, reduces the noise margin of reading and writing in the memory cell, destabilizes the memory cell operation, The bit error rate (BER) is increased.

  In view of the above situation, the inventors have already been able to dynamically change the bit reliability of the memory cell according to the application and the memory situation, ensuring the stability of the operation, reducing the power consumption and increasing the power. For the purpose of providing a memory capable of realizing reliability, a mode in which 1 bit is composed of one memory cell (1 bit / 1 cell mode) and n bits (n is 2 or more) A mode (1 bit / n cell mode) configured by connecting memory cells can be dynamically switched. By switching to the 1 bit / n cell mode, the operation stability of 1 bit is increased and reading is performed. A novel semiconductor memory has been proposed in which the cell current of the operation is increased (the read operation is speeded up) and the bit error can be self-corrected (Patent Document 1).

  One embodiment of such a proposed semiconductor memory is cross-coupled as shown in FIG. 1, in which each output is connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells. In a memory cell comprising a pair of inverters, a pair of switch portions provided between the bit line and the output of the inverter, and one word line whose conduction can be controlled, two adjacent A pair of P-type MOS transistors and one control line that can be controlled so that the P-type MOS transistors are made conductive are added between data holding nodes of two memory cells.

  Here, the circuit operation of the memory cell of FIG. 1 will be briefly described. The memory cell (MC01) shown in FIG. 1 includes a P-type MOS transistor (M00) and an N-type MOS transistor (M02) connected in series between the power supply potential VDD and the ground potential, and between the power supply potential VDD and the ground potential. A latch circuit including a P-type MOS transistor (M01) and an N-type MOS transistor (M03) connected in series to each other is formed. The same applies to the memory cell (MC10).

  In the memory cell (MC01), the gate terminals of the P-type MOS transistor (M00) and the N-type MOS transistor (M02) are both connected to the node (N01) of the P-type MOS transistor (M01) and the N-type MOS transistor (M03). Has been. The gate terminals of the P-type MOS transistor (M01) and the N-type MOS transistor (M03) are both connected to the node (N00) of the P-type MOS transistor (M00) and the N-type MOS transistor (M02). Since the transistors M00 to M03 are thus cross-coupled, the P-type MOS transistors (M00, M01) operate as load transistors, and the N-type MOS transistors (M02, M03) operate as drive transistors. The same applies to the memory cell (MC10).

The memory cell (MC01) includes a switch portion of N-type MOS transistors (M04, M05) connected between the complementary bit lines (BL, / BL) and the nodes (N00, N01). The gate terminals of the N-type MOS transistors (M04, M05) are both connected to a common word line (WL), and the gate potential of the N-type MOS transistors (M04, M05) is controlled by the word line (WL). .
That is, in the memory cell (MC01), the P-type MOS transistors (M00, M01) are used as load transistors, the N-type MOS transistors (M02, M03) are driven transistors, and the N-type MOS transistors (M04, M05) are used. It operates as a switch unit. The same applies to the memory cell (MC10).

  A pair of P-type MOS transistors (M20, M21) and the P-type MOS transistor (M20) are arranged between the data holding nodes (between N00 and N10, between N01 and N11) of the memory cell (MC01, MC10). , M21) is added with one control line (/ CTRL) that can be controlled to conduct.

In the memory cell having the circuit configuration as described above, when the control line (/ CTRL) is at the low level “L”, the pair of added P-type MOS transistors (M20, M21) operate, and between the data holding nodes (N00) And N10, and between N01 and N11) are directly connected, so that variations in memory cells during read / write operations can be corrected.
When the control line (/ CTRL) is at the low level “L” and one word line (WL) rises (WL [0] = “H”, WL [1] = “L”), the read stability is improved. Increase. In addition, when two word lines (WL) rise (WL [0] = “H”, WL [1] = “H”), the cell current is improved so that high-speed operation is possible and write stability is also improved. Increase.

  As described above, in the proposed semiconductor memory having high read stability and write stability, the read operation method and the write operation method in the high reliability mode are different. That is, in the high-reliability mode read operation, the added pair of P-type MOS transistors (M20, M21) are in the on state, and only one word line is raised to read the held data (FIG. 2 ( See 1)). In addition, in the high-reliability mode write operation, the added pair of P-type MOS transistors (M20, M21) is in an on state, and both word lines are raised to write data (FIG. 2 ( See 2)).

  As described above, since the proposed semiconductor memory has a different read operation method and write operation method in the high-reliability mode, the conventional cell arrangement has a memory cell that does not need to be written during the write operation. There is a half-select problem in which there is a risk of data destruction because two lines rise (see Non-Patent Document 1).

  FIG. 3 shows a conventional cell arrangement in which a half-select problem occurs during a high-reliability mode write operation that occurs in the proposed semiconductor memory. As shown in FIG. 3, in the case where there are six memory cell pairs (MC1 to MC6) in two columns vertically and three columns horizontally, for example, in the write operation to the memory cell of MC5, two word lines ( WL [3], WL [3]) rises, and two word lines (WL [3], WL [3]) rise to memory cells (MC4 and MC6) that do not need to be written. Therefore, there is a risk that the data will be destroyed due to the half-select state.

  Here, before describing the conventional half-select avoidance method, two types of cell arrangement methods will be described. FIG. 4 shows an address and data configuration when it is assumed that 8-bit data is held at eight addresses (A to H). If the addresses A to H are arranged in the same row in the proposed semiconductor memory on the premise of the address and data configuration, there are two arrangements.

  The first method is a method of arranging each address separately as shown in FIG. In the method of arranging each address separately, if a soft error occurs in two adjacent bits in the horizontal direction (multi-bit error), a 2-bit error occurs in the same address, so ECC (Error Check and Correct) ) Has a problem that the error cannot be remedied.

  The second method is a method in which each bit is arranged separately as shown in FIG. In this method of sorting and arranging for each address, even when a soft error occurs in two adjacent bits in the horizontal direction, unlike the method of arranging and sorting for each address, only a 1-bit error occurs in the same address. Therefore, soft errors can be remedied by ECC.

  Among the two types of cell arrangement methods, a conventional half-select avoidance method will be described. One conventional half-select avoidance method is to use a divided word line structure. As shown in FIG. 6, the divided word line structure is a word line of a selected address by ANDing selected row addresses (WL [0], WL [1]) and selected column addresses. It is a structure that only stands up. In the case illustrated in FIG. 6, for example, the column address (CLB) corresponding to the address B is selected, and the 8-bit data (0 to 7) of the address B is accessed. However, when the divided word line structure is used, it is necessary to arrange an AND circuit in the array of memory cells, which causes a demerit that an area overhead occurs. In addition, when the divided word line structure is used, since it is necessary to adopt the cell arrangement structure of the method of arranging for each address shown in FIG. 5A, there is a demerit that it is vulnerable to soft errors.

Another method for avoiding conventional half-selection is to use write back. Here, the proposed semiconductor memory write-back procedure is as follows. First, as shown in FIG. 7 (1), only one word line is set up, high-reliability mode reading is performed, and the read data is flip-flopped. (FF).
Next, two word lines are started up and writing in the high reliability mode is performed. As shown in FIG. 7B, the input data (DI) is written in the memory cell in the column being accessed. On the other hand, in the memory cell in the half-selected state (the memory cell in the column not accessed), the data held in the flip-flop (FF) is written to avoid the half-select problem.

  However, when the above write back is used, there is a problem that a speed overhead occurs because it is necessary to read in the high reliability mode first.

Japanese Patent Application No. 2008-000357

H. Yamauchi, T. Suzuki, and Y. Yamagami, “A 1R / 1W SRAM Cell Design to Keep Cell Current and Area Saving against SimultaneousRead / Write Disturbed Accesses,” IEICE Trans. Electronics, vol.E90-C, no. 4, pp. 749-757, April 2007.

  As described above, in the proposed semiconductor memory, since the read operation method and the write operation method in the high-reliability mode are different, in the conventional cell arrangement, until the memory cell that does not need to be written in the write operation, Since there are two word lines standing up, there is a risk of data corruption. When using the proposed semiconductor memory, a cell placement technique that avoids and prevents such a half-select problem is required.

  According to the present invention, the bit reliability QoB (Quality of Bit) of a memory cell can be dynamically changed according to the above-described application and memory conditions, and the operation stability is ensured to reduce power consumption and high reliability. An object of the present invention is to provide a cell placement technique for preventing data destruction (half-select problem) in a memory cell pair in a half-selected state, which is a concern during a high-reliability mode write operation in a semiconductor memory that can be realized.

In order to achieve the above object, the cell arrangement of the semiconductor memory according to the first aspect of the present invention is a memory cell array in which memory cell pairs each formed by connecting two memory cells in one bit are arranged in a two-dimensional array. In
The layout is arranged so that the memory cell pair is shifted by one memory cell in the odd and even columns,
・ Two word lines (WLA, WLB) are provided in the same line,
・ Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
For memory cell pairs of up to 8 columns (4 × 2), 4 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word It is characterized by two lines rising up.

According to the above configuration, in the proposed semiconductor memory, the memory cell pair selected at the time of the write operation (the memory cell pair to be written) rises in two word lines, but the half-selected state is the same. Or, only one word line rises in the memory cell pair in the adjacent row. That is, in the proposed semiconductor memory, it is possible to prevent data destruction (half-select problem) in the memory cell pair in the half-selected state, which is a concern during the write operation in the high reliability mode.
In addition, when two memory cell pairs are in a half-selected state in a column where writing is not performed, two bit lines are prepared, so that memory cell pairs on different bit lines are accessed. Become.
Furthermore, in the word line mapping method, there are four types of word line combinations and two types of selection methods for odd columns and even columns, so the half-select problem up to a word length (bit / ward) of 8 columns × 1 word. Can be avoided.

The cell arrangement of the semiconductor memory according to the second aspect of the present invention is a memory cell array in which memory cell pairs each formed by connecting two memory cells in one bit are arranged in a two-dimensional array.
The layout is arranged so that the memory cell pair is shifted by one memory cell in the odd and even columns,
-Three word lines (WLA, WLB, WLC) are provided in the same line,
・ Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
For memory cell pairs of up to 18 columns (9 × 2), 9 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word It is characterized by two lines rising up.

According to the above configuration, in the proposed semiconductor memory, the memory cell pair selected at the time of the write operation (the memory cell pair to be written) rises in two word lines, but the half-selected state is the same. Or, only one word line rises in the memory cell pair in the adjacent row. That is, in the proposed semiconductor memory, it is possible to prevent data destruction (half-select problem) in the memory cell pair in the half-selected state, which is a concern during the write operation in the high reliability mode.
In addition, when two memory cell pairs are in a half-selected state in a column where writing is not performed, two bit lines are prepared, so that memory cell pairs on different bit lines are accessed. Become.
Furthermore, in the word line mapping method, there are nine types of word line combinations and two types of selection methods for odd columns and even columns, so the half-select problem up to a word length (bit / ward) of 18 columns × 1 word. Can be avoided.

The cell arrangement of the semiconductor memory according to the third aspect of the present invention is a memory cell array in which memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array.
The layout is arranged so that the memory cell pair is shifted by one memory cell in the odd and even columns,
-Four word lines (WLA, WLB, WLC, WLD) are provided in the same line,
・ Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
Provides 16 types of word line combinations for memory cell pairs up to 32 columns (16 × 2), and 2 types of freedom for selection in odd and even columns. It is characterized by two lines rising up.

According to the above configuration, in the proposed semiconductor memory, the memory cell pair selected at the time of the write operation (the memory cell pair to be written) rises in two word lines, but the half-selected state is the same. Or, only one word line rises in the memory cell pair in the adjacent row. That is, in the proposed semiconductor memory, it is possible to prevent data destruction (half-select problem) in the memory cell pair in the half-selected state, which is a concern during the write operation in the high reliability mode.
In addition, when two memory cell pairs are in a half-selected state in a column where writing is not performed, two bit lines are prepared, so that memory cell pairs on different bit lines are accessed. Become.
Furthermore, in the word line mapping method, there are 16 types of word line combinations and 2 types of selection methods for odd columns and even columns, so the half-select problem up to word length (bit / ward) of 32 columns × 1 word Can be avoided.

The cell arrangement of the semiconductor memory according to the fourth aspect of the present invention is a memory cell array in which memory cell pairs each formed by connecting two memory cells in one bit are arranged in a two-dimensional array.
The layout is arranged so that the memory cell pair is shifted by one memory cell in the odd and even columns,
・ There are N word lines (N is a natural number of 5 or more)
・ Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
The memory cell pairs 2N to column (N × 2), a combination of the word line N ² types, provides two selection freedom in odd and even columns, only the memory cell pairs which are write select, Two word lines stand up.

According to the above configuration, in the proposed semiconductor memory, the memory cell pair selected at the time of the write operation (the memory cell pair to be written) rises in two word lines, but the half-selected state is the same. Or, only one word line rises in the memory cell pair in the adjacent row. That is, in the proposed semiconductor memory, it is possible to prevent data destruction (half-select problem) in the memory cell pair in the half-selected state, which is a concern during the write operation in the high reliability mode.
In addition, when two memory cell pairs are in a half-selected state in a column where writing is not performed, two bit lines are prepared, so that memory cell pairs on different bit lines are accessed. Become.
Further, in the word line mapping method, there are N types (N is a natural number of 5 or more) for combinations of word lines, and two types of selection methods for odd columns and even columns. Therefore, a word length of 2N columns × 1 word ( bit / word) can be avoided.

Here, the memory cell pair includes a pair of N-type MOS transistors and one control that can be controlled so that the N-type MOS transistors are conductive between data holding nodes of two adjacent memory cells. The configuration is such that a line is added.
Alternatively, the memory cell pair includes a pair of P-type MOS transistors and one control line that can be controlled so that the P-type MOS transistors are conductive between data holding nodes of two adjacent memory cells. It is set as the structure which added.
Alternatively, the memory cell pair has a configuration in which a pair of CMOS switches and one control line capable of controlling the CMOS switches to be conductive are added between data holding nodes of two adjacent memory cells. It is supposed to be.

  According to the cell arrangement of the semiconductor memory according to the present invention, the bit reliability QoB (Quality of Bit) of the memory cell can be dynamically changed according to the application and the memory situation, and the stability of the operation is ensured. In a semiconductor memory capable of realizing low power consumption and high reliability, it is possible to prevent data destruction (half-select problem) in a memory cell pair in a half-selected state, which is a concern during a high-reliability mode write operation.

Explanatory diagram of the circuit operation of the memory cell of the proposed semiconductor memory Explanatory drawing of read operation and write operation of high reliability mode of proposed memory cell of semiconductor memory Conventional cell layout that causes a half-select problem during high-reliability mode write operations that occur in the proposed semiconductor memory Configuration diagram of address and data assuming that 8-bit data is held at 8 addresses (A to H) (1) Explanatory drawing of the method of arranging for each address and (2) the method of arranging for each bit Illustration of a structure where only the word line of the selected address rises Explanatory drawing of the proposed semiconductor memory write-back procedure A circuit configuration diagram in which proposed memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array by a conventional method. Circuit configuration diagram of cell arrangement of embodiment 1 Wordline mapping table in embodiment 1 Example of circuit block diagram of row decoder Example of circuit configuration of row decoder Wordline mapping table in Embodiment 2 Wordline mapping table in embodiment 3

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Example 1 is a memory cell array in which memory cell pairs under proposal configured by connecting two memory cells in one bit are arranged in a two-dimensional array.
1) The memory cell pairs are laid out so as to be shifted by one memory cell in odd and even columns,
2) Two word lines (WLA, WLB) are provided in the same row,
3) Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
For memory cell pairs of up to 8 columns (4 × 2), 4 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word A case where two lines rise will be described.

  FIG. 8 shows a circuit configuration in which a proposed memory cell pair configured by connecting two memory cells in one bit is arranged in a two-dimensional array by a conventional method. As shown in FIG. 8, in the case where there are six memory cell pairs (MC1 to MC6) in two columns in the vertical direction and three columns in the horizontal direction, for example, in the write operation to the memory cell of MC5, two word lines (WL [2 (n + 1)], WL [2 (n + 1) +1]) rises, so that there are two word lines (WL [2]) up to the memory cells (MC4 and MC6) that do not need to be written. 2 (n + 1)], WL [2 (n + 1) +1]), and a half-select state occurs, possibly destroying data.

  Therefore, in the first embodiment, only two word lines are raised only for the selected memory cell pair, and the memory cell pair in the half-selected state is allowed to rise to one word line. That is, as in the read operation, one word line is brought up.

FIG. 9 shows a circuit configuration of the cell arrangement of the first embodiment. In the middle memory cell pair (MC5) of FIG. 9, both word lines rise at the time of write operation, but only one word line is present in the half-selected memory cell pair (MC1, MC3, MC6). Will stand up. Specifically, MC1 has only one word line (WLA [2n + 1] raised, and MC4 has only one word line (WLA [2 (n + 1)] raised) MC6 has only one word line (WLA [2 (n + 1)]).
In other words, in the proposed semiconductor memory, it is possible to prevent data destruction (half-select problem) in the memory cell pair in the half-selected state, which is a concern during the write operation in the high reliability mode.

  In the cell arrangement of FIG. 9, since two different bit lines are prepared for each memory cell pair (MC1, MC4), access is performed for each memory cell pair on different bit lines. Specifically, MC1 has a complementary bit line BLA (BLA [0], / BLA [0]) connected to a switch portion of an N-type MOS transistor, and MC4 has a complementary bit line BLB (BLB [0], / BLB [0]) is connected to the switch portion of the N-type MOS transistor. In FIG. 9, the N-type MOS transistor surrounded by a circle is conductive.

FIG. 10 shows a word line mapping table in the first embodiment. “WLA” indicates that the switch portion of the N-type MOS transistor is connected to WLA. Further, “WLB” indicates that a switch portion of an N-type MOS transistor is connected to WLB.
In the first embodiment, two word lines (WLA, WLB) are used in the first embodiment, and four types (two squares) of combinations of word lines are used for memory cell pairs in odd and even columns. Since there is a shift by one memory cell, there are two types of selection methods. As a result, the half-select problem can be avoided up to a word length (bit / word) of 8 columns × 1 word.

  11 and 12 show an example of a circuit block diagram and circuit configuration of the row decoder. As a result, an SRAM block of 128 rows × 8 columns × 32 bits / word = 32 KB can be constructed with the memory cell pair of the proposed semiconductor memory as 1 bit.

Example 2 is a memory cell array in which memory cell pairs under proposal configured by connecting two memory cells in one bit are arranged in a two-dimensional array.
1) The memory cell pairs are laid out so as to be shifted by one memory cell in odd and even columns,
2) Three word lines (WLA, WLB, WLC) are provided in the same row,
3) Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
For memory cell pairs of up to 18 columns (9 × 2), 9 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word A case where two lines rise will be described.

  In the second embodiment, as in the first embodiment, two word lines are raised only for the selected memory cell pair, and the memory cell pair in the half-selected state is allowed to rise one word line. I will do it. That is, as in the read operation, one word line is brought up.

FIG. 13 shows a word line mapping table in the second embodiment. “WLA” indicates that the switch portion of the N-type MOS transistor is connected to WLA. Further, “WLB” indicates that a switch portion of an N-type MOS transistor is connected to WLB. In addition, “WLC” indicates that a switch portion of an N-type MOS transistor is connected to WLC.
In the second embodiment, three word lines (WLA, WLB, WLC) are used in the second embodiment, and nine types (2 to the power of 2) of combinations of word lines, memory cells in odd columns and even columns are used. There are two types of selection methods because the memory cells are shifted by one memory cell, and as a result, the half-select problem can be avoided up to a word length (bit / word) of 18 columns × 1 word. .

Example 3 is a memory cell array in which a proposed memory cell pair configured by connecting two memory cells in one bit is arranged in a two-dimensional array.
1) The memory cell pairs are laid out so as to be shifted by one memory cell in odd and even columns,
2) Four word lines (WLA, WLB, WLC, WLD) are provided in the same row,
3) Two bit lines (BLA, / BLA, BLB, / BLB) are provided in the same column,
Provides 16 types of word line combinations for memory cell pairs up to 32 columns (16 × 2), and 2 types of freedom for selection in odd and even columns. A case where two lines rise will be described.

  In the third embodiment, as in the first embodiment, two word lines are raised only for the selected memory cell pair, and the memory cell pair in the half-selected state is allowed to rise one word line. I will do it. That is, as in the read operation, one word line is brought up.

FIG. 14 shows a word line mapping table in the third embodiment. “WLA” indicates that the switch portion of the N-type MOS transistor is connected to WLA. Further, “WLB” indicates that a switch portion of an N-type MOS transistor is connected to WLB. In addition, “WLC” indicates that a switch portion of an N-type MOS transistor is connected to WLC. Further, “WLD” indicates that a switch portion of an N-type MOS transistor is connected to WLD.
In the second embodiment, the conventional word line is four word lines (WLA, WLB, WLC, WLD), and there are 16 kinds (two to the fourth power) of combinations of word lines, odd columns and even columns. There are two types of selection methods because one memory cell is shifted by one memory cell. As a result, the half-select problem can be avoided up to a word length (bit / word) of 32 columns × 1 word. become.

  The present invention is useful for an SRAM used for a cache memory of a computer or the like.

MC1 to MC6 memory cell pair MC01, MC10 memory cell

Claims (7)

In a memory cell array in which memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array,
The memory cell pair is laid out so as to be shifted by one memory cell in the odd and even columns,
Two word lines (WLA, WLB) are provided in the same row,
In the same column, two bit lines (BLA, / BLA, BLB, / BLB) are provided,
For memory cell pairs of up to 8 columns (4 × 2), 4 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word A memory cell arrangement characterized in that two lines rise. In a memory cell array in which memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array,
The memory cell pair is laid out so as to be shifted by one memory cell in the odd and even columns,
In the same row, three word lines (WLA, WLB, WLC) are provided,
In the same column, two bit lines (BLA, / BLA, BLB, / BLB) are provided,
For memory cell pairs of up to 18 columns (9 × 2), 9 types of word line combinations and 2 types of freedom of selection in odd and even columns are provided. Only memory cell pairs selected for writing are provided with word A memory cell arrangement characterized in that two lines rise. In a memory cell array in which memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array,
The memory cell pair is laid out so as to be shifted by one memory cell in the odd and even columns,
In the same row, four word lines (WLA, WLB, WLC, WLD) are provided,
In the same column, two bit lines (BLA, / BLA, BLB, / BLB) are provided,
Provides 16 types of word line combinations for memory cell pairs up to 32 columns (16 × 2), and 2 types of freedom for selection in odd and even columns. A memory cell arrangement characterized in that two lines rise. In a memory cell array in which memory cell pairs configured by connecting two memory cells in one bit are arranged in a two-dimensional array,
The memory cell pair is laid out so as to be shifted by one memory cell in the odd and even columns,
In the same row, N word lines (N is a natural number of 5 or more) are provided,
In the same column, two bit lines (BLA, / BLA, BLB, / BLB) are provided,
The memory cell pairs 2N to column (N × 2), a combination of the word line N ² types, provides two selection freedom in odd and even columns, only the memory cell pairs which are write select, A memory cell arrangement characterized in that two word lines rise.   In the memory cell pair, a pair of N-type MOS transistors and one control line capable of controlling the N-type MOS transistors to conduct are added between data holding nodes of two adjacent memory cells. 5. The memory cell arrangement according to claim 1, wherein the memory cell arrangement is configured.   In the memory cell pair, a pair of P-type MOS transistors and one control line capable of controlling the P-type MOS transistors to be conductive are added between data holding nodes of two adjacent memory cells. 5. The memory cell arrangement according to claim 1, wherein the memory cell arrangement is configured. The memory cell pair has a configuration in which a pair of CMOS switches and one control line capable of controlling the CMOS switches to be conductive are added between data holding nodes of two adjacent memory cells. 5. The memory cell arrangement according to claim 1, wherein the memory cell arrangement is one.