JP2010177474A - Production process of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a trench structure with a high breakdown voltage.
An insulating layer is formed in a lower portion of a trench, an electrode is formed in a trench above the insulating layer, and an insulating film is formed on a wall surface of the trench in a range in contact with the electrode. A method of manufacturing a semiconductor device having a step of forming a trench, a step of forming an insulating layer in a lower portion of the trench, and a step of forming a mask layer on a wall surface of the trench above the insulating layer, Forming a mask layer so that the insulating layer is exposed at the bottom of the gap between the mask layer formed on the wall surface and the mask layer formed on the other wall surface, and forming the insulating layer from the bottom of the gap, etc. A step of forming the upper surface of the insulating layer into a concave curved surface by isotropic etching, a step of removing the mask layer, a step of forming an insulating film on the wall surface of the trench, and a step of forming an electrode in the trench Have is doing.
[Selection] Figure 1

Description

  The present invention has a structure in which an insulating layer is formed in a lower portion of a trench, an electrode is formed in a trench in the upper portion of the insulating layer, and an insulating film is formed on a wall surface of the trench in a range in contact with the electrode. The present invention relates to a method for manufacturing a semiconductor device.

  As disclosed in Patent Document 1, an insulating layer is formed in the lower portion of the trench, an electrode is formed in the upper trench of the insulating layer, and an insulating film is formed on the wall surface of the trench in a range in contact with the electrode A semiconductor device having a structure in which is formed is known. This type of trench structure is generally formed as follows. That is, first, a trench is formed in a silicon substrate. Next, an insulator is filled in the trench. Next, the insulator is etched, leaving the insulator only in the lower part of the trench. As a result, as shown in FIG. 20, an insulating layer 100 is formed in the lower portion of the trench. Next, the surface of the silicon substrate is oxidized by a thermal oxidation method or the like. As a result, as shown in FIG. 21, an insulating film 102 made of silicon oxide is formed on the surface of the silicon substrate. At this time, the insulating film 102 is also formed on the wall surface of the trench. After the insulating film 102 is formed, as shown in FIG. 22, the electrode 104 is formed by filling the trench (upper part of the insulating layer 100) with a conductor. Thereby, the trench structure is completed.

JP 2005-116822 A

  When the trench structure is formed by the above-described method, the following problems occur. That is, as shown in FIG. 20, before the insulating film 102 is formed, the upper surface of the insulating layer 100 is substantially perpendicular to the wall surface of the trench. For this reason, when the insulating film 102 is formed, the oxidizing gas hardly reaches the boundary portion 100a between the upper surface of the insulating layer 100 and the wall surface of the trench. In addition, volume expansion occurs when the insulating film 102 grows. However, since the wall surface of the trench and the upper surface of the insulating layer 100 are substantially perpendicular at the boundary portion 100a, the insulating film 102 is grown between the insulating layer 102 and the insulating layer 100. Thus, stress is generated and volume expansion of the insulating film 102 is suppressed. Therefore, as shown in FIG. 21, the insulating film 102 is thin in the vicinity of the boundary portion 100a. In order to form the electrode 104 by filling the inside of the trench with a conductor, a corner 104a is formed at the lower end of the electrode 104 as shown in FIG. When the corner 104a is formed on the electrode 104, the electric field is easily concentrated in the vicinity of the corner 104a. As described above, the trench structure formed by the conventional method has a problem that the withstand voltage is very low because the insulating film 102 is thinnest in the vicinity of the corner portion 104a where the electric field tends to concentrate.

  The present invention has been created in view of the above-described circumstances, and an object thereof is to provide a method for manufacturing a semiconductor device having a trench structure with a high breakdown voltage.

  In the method of manufacturing a semiconductor device according to the present invention, an insulating layer is formed in the lower portion of the trench, an electrode is formed in the trench in the upper portion of the insulating layer, and an insulating film is formed on the wall surface of the trench in a range in contact with the electrode. A semiconductor device having the formed structure is manufactured. This manufacturing method includes a trench forming step, an insulating layer forming step, a mask layer forming step, an etching step, a mask layer removing step, an insulating film forming step, and an electrode forming step. In the trench formation step, a trench is formed on the surface of the silicon substrate. In the insulating layer forming step, the insulating layer is formed by filling the lower portion of the trench with silicon oxide. In the mask layer forming step, a mask layer is formed on the wall surface of the trench above the insulating layer. The mask layer is formed so that the insulating layer is exposed at the bottom of the gap between the mask layer formed on one wall surface facing the trench and the mask layer formed on the other wall surface. In the insulating layer etching step, the insulating layer is isotropically etched from the bottom of the gap to form a concave curved upper surface of the insulating layer. In the mask layer removing step, the mask layer is removed. In the insulating film forming step, the wall surface of the trench is oxidized to form an insulating film on the wall surface. In the electrode forming step, a conductor is filled in the trench above the insulating layer to form an electrode.

  In this manufacturing method, after the insulating layer and the mask layer are formed, the insulating layer is isotropically etched from the bottom of the gap between the mask layers, so that the upper surface of the insulating layer is formed into a concave curved shape. For this reason, the insulating layer is thinly distributed in the vicinity of the boundary between the upper surface of the insulating layer and the wall surface of the trench. Next, the mask layer is removed, and thereafter, the wall surface of the trench is oxidized to form an insulating film. At this time, since the insulating layer is thinly distributed in the vicinity of the boundary portion, the growth of the insulating film is hardly inhibited. Moreover, since the upper surface of the insulating layer has a concave curved surface shape, the oxidizing gas can easily reach the boundary portion. Therefore, the insulating film grows thick even at the boundary portion. Further, in the portion where the insulating layer at the boundary is thin, the oxidizing gas can reach the wall surface of the trench in the range covered with the thin insulating layer, and the thickness of the thin insulating layer increases. For this reason, after the growth of the insulating film, an insulator (insulating layer and insulating film) having a sufficient thickness is formed in the vicinity of the boundary portion. Further, since the upper surface of the insulating layer before forming the insulating film is formed into a concave curved surface shape, the upper surface of the insulating layer is formed into a concave curved surface shape even after the insulating film is formed. After the insulating film is formed, a conductor is filled in the trench above the insulating layer to form an electrode. As described above, since the upper surface of the insulating layer has a concave curved shape, the shape of the lower end of the electrode is a convex curved shape. That is, no corner is formed at the lower end of the electrode. This completes a trench structure in which no corner is formed at the lower end of the electrode and an insulator (insulating layer and insulating film) having a sufficient thickness is formed in the vicinity of the lower end of the electrode. Therefore, in this trench structure, the electric field is difficult to concentrate on the lower end of the electrode, and the withstand voltage near the lower end of the electrode is high. According to this manufacturing method, a semiconductor device having a high breakdown voltage can be manufactured.

The fragmentary sectional view of MOSFET10. The fragmentary sectional view of the silicon wafer 50 after the mask layer 60 is formed. The fragmentary sectional view of the silicon wafer 50 after a trench formation process. The fragmentary sectional view of the silicon wafer 50 after a protective oxide film formation process. The fragmentary sectional view of the silicon wafer 50 after a floating region formation process. The fragmentary sectional view of the silicon wafer 50 after an oxide film formation process. The fragmentary sectional view of the silicon wafer 50 after a silicon oxide layer formation process. The fragmentary sectional view of the silicon wafer 50 after the 1st etching of a silicon oxide etching process. The fragmentary sectional view of the silicon wafer 50 after mask layer 66 formation. The fragmentary sectional view of the silicon wafer 50 after the 2nd etching of a silicon oxide etching process. The fragmentary sectional view of the silicon wafer 50 after a nitride film formation process. The fragmentary sectional view of the silicon wafer 50 before a trench formation process. The fragmentary sectional view of the silicon wafer 50 after a nitride film etching process. The fragmentary sectional view of the silicon wafer 50 after a silicon oxide wet etching process. The fragmentary sectional view of the silicon wafer 50 after a nitride film removal process. The fragmentary sectional view of the silicon wafer 50 after the 2nd silicon oxide wet etching formation process. The fragmentary sectional view of the silicon wafer 50 after a gate insulating film formation process. FIG. 4 is a partial cross-sectional view of a silicon wafer 50 after a polysilicon layer 26 is formed. The fragmentary sectional view of the silicon wafer 50 after a gate electrode formation process. The fragmentary sectional view of the silicon substrate after insulating layer 100 formation in the formation method of the conventional trench structure. The fragmentary sectional view of the silicon substrate after insulating film 102 formation in the formation method of the conventional trench structure. The fragmentary sectional view of the silicon substrate after electrode 104 formation in the formation method of the conventional trench structure.

  A method of manufacturing a semiconductor device according to the example will be described. In the manufacturing method of the embodiment, the MOSFET 10 shown in the partial cross-sectional view of FIG. 1 is manufactured.

As shown in FIG. 1, the MOSFET 10 is formed of a semiconductor substrate 12 and electrodes, insulating films and the like formed on the upper and lower surfaces of the semiconductor substrate 12. An N-type source region 14, a P-type body region 16, an N ⁻ -type drift region 18, and an N ⁺ -type drain region 20 are formed in the semiconductor substrate 12. A trench 30 is formed in the semiconductor substrate 12 so as to penetrate the source region 14 and the body region 16 and reach the drift region 18 from the upper surface thereof. A P-type floating region 21 is formed in the drift region 18 near the lower end of the trench 30. A silicon oxide layer 22 is formed in the lower portion of the trench 30. A gate insulating film 24 made of silicon oxide is formed on the upper wall surface of the trench 30. A gate electrode 26 made of polysilicon is formed in the upper portion of the trench 30. An upper portion of the gate electrode 26 is covered with a cap insulating film 32. A source electrode 34 is formed on the upper surface of the semiconductor substrate 12. A drain electrode 36 is formed on the lower surface of the semiconductor substrate 12.

  In the MOSFET 10, the floating region 21 prevents the electric field from concentrating on the interface between the body region 16 and the drift region 18 when the MOSFET 10 is turned off. The lower end of the gate electrode 26 is formed in a curved shape, and no corner is formed at the lower end. Therefore, the concentration of the electric field in the vicinity of the lower end of the gate electrode 26 is suppressed when the MOSFET 10 is turned off. Thereby, the breakdown voltage of the MOSFET 10 is improved.

A method for manufacturing MOSFET 10 will be described. In addition, since the manufacturing method of a present Example has the characteristics in the process of forming a trench gate structure, detailed description is abbreviate | omitted about another process.
MOSFET 10 is manufactured from a silicon wafer (hereinafter referred to as silicon wafer 50) having an N-type impurity concentration substantially the same as that of drift region 18. First, diffusion layers (source region 14 and body region 16) are formed on the upper surface side of the silicon wafer 50. Thereafter, a trench formation step is performed.

(Trench formation process)
In the trench formation step, first, as shown in FIG. 2, a mask layer 60 is formed on the upper surface 50 a of the silicon wafer 50. The mask layer 60 is formed in a shape in which an opening is provided in a range corresponding to the trench 30. Thereafter, the silicon wafer 50 is etched from the upper surface 50a side by the RIE method. Thereby, as shown in FIG. 3, the trench 30 is formed in the upper surface 50 a of the silicon wafer 50. In the trench formation step, the trench 30 having a depth of about 2.0 μm, a width of about 0.5 μm, and a wall taper angle of 86.5 degrees to 89.0 degrees is formed.

(Protective oxide film formation process)
When the trench formation process is completed, the silicon wafer 50 is subjected to thermal oxidation. As a result, a protective oxide film 62 is formed on the inner surface of the trench 30 as shown in FIG. This thermal oxidation treatment is performed using an oxidation temperature of 800 ° C. to 1100 ° C. and O ₂ , H ₂ O, N ₂ diluted H ₂ O, or the like as an oxidizing gas. Here, a protective oxide film 62 having a thickness of about 20 nm is formed.

(Floating region formation process)
When the protective oxide film forming step is completed, boron ions are implanted toward the upper surface 50a of the silicon wafer 50. Ion implantation is performed with an acceleration voltage of 20 keV and a dose of 1 × 10 ¹³ / cm ² . At the bottom surface of the trench 30, since the ion implantation direction is substantially perpendicular to the bottom surface of the trench 30, ions are implanted into the silicon wafer 50 through the protective oxide film 62. On the other hand, on the side surface of the trench 30, the ions stop in the protective oxide film 62 because the side surface of the trench 30 and the ion implantation direction are substantially parallel. Further, since the region of the upper surface 50 a of the silicon wafer 50 excluding the trench 30 is covered with the mask layer 60, ions stop in the mask layer 60 in that region. Therefore, ions are implanted into the silicon wafer 50 only near the bottom surface of the trench 30. After the ion implantation, the silicon wafer 50 is heat-treated to activate the implanted boron ions. As a result, a floating region 21 is formed in the vicinity of the lower end of the trench 30 as shown in FIG. After the floating region 21 is formed, the mask layer 60 and the protective oxide film 62 are removed by etching.

(Oxide film formation process)
When the floating region forming step is completed, the silicon wafer 50 is subjected to a thermal oxidation process. As a result, an oxide film 64 is formed on the upper surface 50a of the silicon wafer 50 and the inner surface of the trench 30 as shown in FIG. This thermal oxidation treatment is performed using an oxidation temperature of about 1000 ° C. and O ₂ as an oxidizing gas. Thereby, an oxide film 64 having a thickness of about 40 nm is formed.

(Silicon oxide layer formation process)
When the oxide film forming step is completed, silicon oxide is deposited on the silicon wafer 50 by the CVD method. The CVD method is performed using a film formation temperature of 600 to 700 ° C. and a film formation gas such as TEOS and O ₂ . Silicon oxide is deposited over 600 nm. According to the CVD method, silicon oxide can be deposited also on the inner surface of the trench 30. Accordingly, as shown in FIG. 7, a silicon oxide layer 42 is formed on the silicon wafer 50 and in the trench 30. Since the CVD method has high embeddability, the silicon oxide layer 42 is filled in the trench 30 without any gap.

(Silicon oxide etching process)
When the silicon oxide layer forming step is completed, the silicon oxide layer 42 is etched from the upper surface 50a side of the silicon wafer 50 by the RIE method. As the etching gas, CF ₄ , CHF ₃ or the like is used. Here, as shown in FIG. 8, etching is performed so that the silicon oxide layer 42 on the upper surface 50a of the silicon wafer 50 remains with a thickness of about 50 nm.
Next, as shown in FIG. 9, a mask layer 66 is formed on the silicon wafer 50. The mask layer 66 is formed in a shape in which an opening is provided in a range corresponding to the trench 30.
Next, the silicon oxide (silicon oxide layer 42 and oxide film 64) is etched from the upper surface 50a side of the silicon wafer 50 by RIE. As the etching gas, CF ₄ , CHF ₃ or the like is used. As a result, as shown in FIG. 10, the silicon oxide at the upper part of the trench 30 is removed, and the silicon oxide is left at the lower part of the trench 30. Hereinafter, the silicon oxide (the silicon oxide layer 42 and the oxide film 64) left under the trench 30 is referred to as a silicon oxide layer 22. Here, etching is performed so that the upper surface of the silicon oxide layer 22 is located below the lower end of the body region 16.
After the silicon oxide layer 22 is formed as shown in FIG. 10, the mask layer 66 is removed by etching.

(Base oxide film formation process)
When the silicon oxide etching process is completed, silicon oxide is deposited on the silicon wafer 50 by the CVD method. The CVD method is performed at a film forming temperature of 600 to 700 ° C., and TEOS, O ₂ , a silane gas, or the like is used as a film forming gas. Silicon oxide is deposited about 50 nm. As a result, as shown in FIG. 11, a base oxide film 68 is formed on the silicon wafer 50 and on the inner surface of the trench 30.

(Nitride film formation process)
When the base oxide film forming step is completed, nitride is deposited on the silicon wafer 50 by the CVD method. The CVD method is performed using a film forming temperature of 700 to 800 ° C., and using a silane gas such as SiH ₂ Cl ₂ , NH ₃ or the like as a film forming gas. The nitride is deposited about 100 nm. As a result, a nitride film 70 is formed on the silicon wafer 50 and on the inner surface of the trench 30 as shown in FIG. A gap 72 is formed between the nitride film 70 formed on one wall surface of the trench 30 and the nitride film 70 formed on the other wall surface (that is, the central portion in the width direction of the trench 30).

(Nitride film etching process)
When the nitride film forming step is completed, the nitride film 70 is etched from the upper surface 50a side of the silicon wafer 50 by RIE. As the etching gas, CF ₄ , CHF ₃ or the like is used. Further, here, the etching is performed so that the etching amount is 100 nm or more (a little more than the thickness of the nitride film 70). Since the etching by the RIE method has anisotropy, the etching of the nitride film 70 proceeds mainly in the depth direction of the silicon wafer 50. Therefore, the nitride film 70 on the silicon wafer 50 is etched and removed in the thickness direction. Similarly, the nitride film 70 on the bottom surface of the gap 72 is removed by etching in the thickness direction. On the other hand, since the nitride film 70 formed on the wall surface of the trench 30 is distributed along the depth direction of the silicon wafer 50, it is not etched much. Therefore, when the nitride film etching process is performed, the nitride film 70 remains only on the wall surface of the trench 30 and the other nitride films 70 are removed as shown in FIG. At this time, since the nitride film 70 on the bottom surface of the gap 72 is removed, the base oxide film 68 is exposed on the bottom surface of the gap 72.

(Silicon oxide wet etching process)
When the nitride film forming step is completed, the silicon oxide is wet etched. As the etchant, hydrofluoric acid or buffered hydrofluoric acid is used. Further, wet etching is performed so that the etching amount becomes about 100 nm. In the silicon oxide wet etching process, etching proceeds from the bottom of the gap 72 in the trench 30. Since wet etching is isotropic etching, etching spreads concentrically starting from the bottom of the gap 72. Here, as shown in FIG. 14, etching is performed until the upper surface of the silicon oxide layer 22 has a concave curved surface. Since the upper surface of the silicon oxide layer 22 has a concave curved shape, the upper surface of the silicon oxide layer 22 is formed with a protruding portion 22 a that protrudes upward along the wall surface of the trench 30. In the silicon oxide wet etching process, the silicon oxide on the silicon wafer 50 (that is, the oxide films 42, 64, 68) is also etched. However, as shown in FIG. 14, the oxide film 64 is formed on the silicon wafer 50 after the etching. Partially remains.

(Nitride removal process)
When the silicon oxide wet etching process is completed, the nitride film 70 is wet etched. Thereby, the nitride film 70 is removed as shown in FIG. As the etchant, hot phosphoric acid at about 170 ° C. is used (it can also be performed by dry etching, and in this case, CF ₄ , O ₂ , N ₂ or the like is used as an etching gas).

(Second silicon oxide wet etching process)
When the nitride film removing step is completed, the silicon oxide is wet etched. As the etchant, hydrofluoric acid or buffered hydrofluoric acid is used. Here, as shown in FIG. 16, the silicon oxide layer 22 remains in the trench 30, and the other silicon oxide (that is, the oxide film 64 on the silicon wafer 50 and the base oxide film 68 on the wall surface of the trench 30). Etch until removed.

(Gate insulation film formation process)
When the second silicon oxide wet etching process is completed, the silicon wafer 50 is subjected to thermal oxidation. As a result, an oxide film 24 is formed on the upper surface 50a of the silicon wafer 50 and the wall surface of the trench 30 as shown in FIG. In this thermal oxidation treatment, the oxidation temperature is about 1050 ° C., and O ₂ is used as the oxidizing gas. Here, an oxide film of about 75 nm is formed. The oxide film 24 formed on the wall surface of the trench 30 becomes the gate insulating film 24 in FIG.
In the gate insulating film forming step, the upper surface of the silicon oxide layer 22 has a concave curved surface, so that the oxidizing gas easily spreads throughout the trench 30. Further, since the thickness of the silicon oxide layer 22 (projection 22a) is thin at the boundary between the upper surface of the silicon oxide layer 22 and the wall surface of the trench 30, the gate insulating film 24 grows in the vicinity of the boundary. It is not suppressed. Therefore, the gate insulating film 24 grows on the entire wall surface of the trench 30. Moreover, since the protrusion 22a is thin, the oxidizing gas passes through the protrusion 22a and reaches the wall surface of the trench 30 covered with the protrusion 22a. For this reason, silicon oxide grows also in the protrusion part 22a, and the thickness of the protrusion part 22a increases. Therefore, as shown in FIG. 17, an insulating film having a sufficient thickness is formed on the entire inner surface of the trench 30. That is, the insulating film on the inner surface of the trench 30 is prevented from being locally thinned.

(Gate electrode formation process)
When the gate insulating film forming step is completed, P-doped polysilicon is deposited on the silicon wafer 50 by the CVD method. As a result, a polysilicon layer 26 is formed as shown in FIG. This CVD method is performed using a film forming temperature of 620 ° C. and a film forming gas such as SiH ₄ or PH ₃ . Here, the polysilicon layer 26 having a thickness of about 500 nm is formed. When the CVD method is performed, polysilicon is also deposited on the inner surface of the trench 30 and the trench 30 is filled with the polysilicon layer 26 as shown in FIG.
After the polysilicon layer 26 is formed, the polysilicon layer 26 is etched from the upper surface 50a side of the silicon wafer 50. Thus, as shown in FIG. 19, the polysilicon layer 26 remains in the trench 30 and the polysilicon layer 26 on the silicon wafer 50 is removed. The remaining polysilicon layer 26 becomes the gate electrode 26.
After the gate electrode 26 is formed, the oxide film 24 on the silicon wafer 50 is removed by etching. Thereafter, the cap insulating film 32 is formed by thermal oxidation treatment. Thereby, the trench gate structure is completed.

  When the trench gate structure is formed, a diffusion layer (drain layer) is formed on the lower surface 50b side of the silicon wafer 50. Further, other necessary structures (electrodes, insulating films, etc.) are formed. Thereafter, the silicon wafer 50 is divided by dicing. As a result, the MOSFET 10 shown in FIG. 1 is manufactured.

  As shown in FIG. 1, in the MOSFET 10 manufactured by this manufacturing method, the lower end of the gate electrode 26 is formed in a curved surface shape. That is, no corner is formed at the lower end of the gate electrode 26. Therefore, it is difficult for the electric field to concentrate near the lower end of the gate electrode 26. Further, the protruding portion 22a of the silicon oxide layer 22 exists on the side of the lower end of the gate electrode 26, and there is no portion where the insulating film is thin. Therefore, the withstand voltage of the insulating layer near the lower end of the gate electrode 26 is high. Thus, the electric field concentration in the vicinity of the lower end of the gate electrode 26 is suppressed, and the withstand voltage of the insulating layer in the vicinity thereof is secured, so that the MOSFET 10 is unlikely to break down near the lower end of the gate electrode 26. The MOSFET 10 has a high breakdown voltage.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: MOSFET
12: Semiconductor substrate 14: Source region 16: Body region 18: Drift region 20: Drain region 21: Floating region 22: Silicon oxide layer 22a: Projection 24: Gate insulating film 26: Gate electrode 30: Trench 32: Cap insulating film 34: source electrode 36: drain electrode 42: silicon oxide layer 50: silicon wafer 62: protective oxide film 64: oxide film 68: base oxide film 70: nitride film

Claims (1)

An insulating layer is formed in the lower part of the trench, an electrode is formed in the upper trench of the insulating layer, and an insulating film is formed on the wall surface of the trench in a range in contact with the electrode. A manufacturing method comprising:
A trench forming step of forming a trench on the surface of the silicon substrate;
An insulating layer forming step of forming an insulating layer by filling silicon oxide in the lower part of the trench;
A step of forming a mask layer on the wall surface of the trench above the insulating layer, and insulating at the bottom of the gap between the mask layer formed on one wall surface facing the trench and the mask layer formed on the other wall surface A mask layer forming step of forming a mask layer so that the layer is exposed;
An insulating layer etching step for forming the upper surface of the insulating layer into a concave curved surface by isotropically etching the insulating layer from the bottom of the gap;
A mask layer removing step of removing the mask layer;
An insulating film forming step of oxidizing the wall surface of the trench to form an insulating film on the wall surface;
An electrode forming step of forming an electrode by filling a conductor in a trench above the insulating layer;
A method of manufacturing a semiconductor device having

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