JP2010192660A - Thin-film transistor, and method of manufacturing the same - Google Patents

Abstract

A thin film transistor which can reduce off current without reducing on current and can be applied to control of a pixel circuit and a gate driving circuit is provided.
A thin film transistor includes a microcrystalline silicon layer having a central portion serving as a channel and an amorphous silicon layer provided on the microcrystalline silicon layer, and includes a source electrode and a drain electrode. The lower source electrode 7a and the lower drain electrode 8a connected to the contact layers 6a and 6b, respectively, and the upper source electrode 7b and the upper drain electrode 8b formed on the upper surfaces of the lower source electrode 7a and the lower drain electrode 7b. In addition to the layers, the channel-side end portions of the upper source electrode 7b and the upper drain electrode 8b are configured to project in a bowl shape with respect to the channel-side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively.
[Selection] Figure 1

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same.

  As a conventional thin film transistor, a microcrystalline silicon layer serving as a channel portion on a gate electrode formed on a transparent substrate, an amorphous silicon layer serving as a resistance layer, and a pair of n-type serving as a contact layer via a gate insulating film In some cases, an amorphous silicon layer is sequentially formed, a source electrode and a drain electrode are formed on the n-type amorphous silicon layer, and then the n-type amorphous silicon layer on the channel portion is removed by etching. In such a thin film transistor, an amorphous silicon layer formed over a microcrystalline silicon layer acts as a resistor and relaxes an electric field applied to a drain end portion, so that an increase in off current can be suppressed (for example, Patent Document 1). And Patent Document 2).

Japanese Patent Laid-Open No. 2-1174 (FIG. 1) Japanese Patent Laying-Open No. 2004-304140 (FIG. 4)

However, in the above-described thin film transistor, the amorphous silicon layer provided over the microcrystalline silicon layer acts as a resistor, so that the on-current is reduced together with the off-current, so that the thin film transistor can be used for a pixel circuit or a peripheral driver circuit. Had the problem of lack of driving ability.
On the other hand, when the amorphous silicon layer is formed thin in order to increase the on-current, the resistance of the amorphous silicon layer is lowered, and there is a problem that the off-current increases.

  The present invention has been made to solve the above-described problems, and provides a thin film transistor that can reduce off-current without reducing on-current and can be applied to control of a pixel circuit and a gate drive circuit.

  The thin film transistor according to the present invention includes a transparent substrate, a gate electrode provided on the transparent substrate, a microcrystalline silicon layer provided on the gate electrode via a gate insulating film and having a central portion serving as a channel, An amorphous silicon layer provided on the microcrystalline silicon layer, a pair of contact layers provided on both ends of the amorphous silicon layer, a source electrode provided on each of the pair of contact layers, and A drain electrode, and the source electrode and the drain electrode are formed on a lower source electrode and a lower drain electrode connected to the contact layer, and on an upper surface of the lower source electrode and the lower drain electrode, and the lower source electrode and It is composed of two layers of an upper source electrode and an upper drain electrode that are thinner than the lower drain electrode. The channel-side end portions of the upper source electrode and the upper drain electrode protrude in a bowl shape from the channel-side end portions of the lower source electrode and the lower drain electrode, respectively. .

  According to the thin film transistor according to the present invention, the off current can be reduced without reducing the on current, and display unevenness of an LCD, an OLED display, or the like using the thin film transistor can be reduced.

It is sectional drawing which shows the structure of the thin-film transistor in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the thin-film transistor in Embodiment 1 of this invention. It is a figure which shows the voltage-current characteristic of the thin-film transistor in Embodiment 1 of this invention with a comparative example. It is sectional drawing which shows the structure of the thin-film transistor of the comparative example in FIG. It is a figure which shows the relationship between the protrusion length of the upper source electrode of the thin film transistor in Embodiment 1 of this invention, and an upper drain electrode, and an off-current. It is sectional drawing which shows the structure of the thin-film transistor in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the thin-film transistor in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the thin-film transistor in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the thin-film transistor in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the thin-film transistor in Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the thin-film transistor in Embodiment 2 of this invention. It is a figure which shows the voltage-current characteristic of the thin-film transistor in Embodiment 2 of this invention with a comparative example. It is a figure which shows the relationship between the protrusion length of the upper source electrode of the thin film transistor in Embodiment 2 of this invention, and an upper drain electrode, and an off-current.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of the thin film transistor according to the first embodiment of the present invention, and FIGS. 2 to 6 are cross-sectional views showing the manufacturing steps of the thin film transistor according to the first embodiment of the present invention. 7 and 9 are diagrams showing the characteristics of the thin film transistor according to the first embodiment of the present invention together with a comparative example, and FIG. 8 is a cross-sectional view showing the structure of the comparative example.

First, the structure of the thin film transistor in Embodiment 1 is described with reference to FIG.
In FIG. 1, a thin film transistor 100 includes a transparent glass substrate 1, a gate electrode 2 provided on the glass substrate 1, and a gate insulating film 3 provided on the gate electrode 2. A microcrystalline silicon layer 4, an amorphous silicon layer 5 provided on the microcrystalline silicon layer 4, and an n-type amorphous silicon layer provided on both ends of the amorphous silicon layer 5. A pair of contact layers 6a and 6b, a source electrode 7 and a drain electrode 8 provided on the contact layers 6a and 6b, respectively, and a protective film 9 for protecting the surface. Note that microcrystalline silicon refers to crystalline silicon having an average particle size of approximately 100 nm or less.

  The gate insulating film 3 is formed of a silicon nitride film (SiN) with a film thickness of 200 to 500 nm, the microcrystalline silicon layer 4 has a film thickness of 30 to 100 nm, and the amorphous silicon layer 5 has a film thickness of 50 to 100 nm. Is formed. The contact layers 6a and 6b have a thickness of 10 to 50 nm and are formed of n-type amorphous silicon obtained by doping amorphous silicon with phosphorus (P) as an impurity.

The source electrode 7 and the drain electrode 8 include a lower source electrode 7a and a lower drain electrode 8a connected to the contact layers 6a and 6b, respectively, and an upper source electrode 7b formed on the upper surface of the lower source electrode 7a and the lower drain electrode 7b. And the upper drain electrode 8b. The upper source electrode 7b and the upper drain electrode 8b are formed thinner than the lower source electrode 7a and the lower drain electrode 8a.
In the present embodiment, the lower source electrode 7a and the lower drain electrode 8a are formed of an aluminum (Al) alloy having a film thickness of 100 to 300 nm, and the upper source electrode 7b and the upper drain electrode 8b are formed of chromium (Cr) having a film thickness of 50 nm. It is formed with. The upper source electrode 7b and the upper drain electrode 8b are made of a 4A group, 5A group or 6A group metal such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta) or the like or these metals in addition to Cr. You may form with the alloy containing.

  Further, the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b are configured to project in a bowl shape from the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively. The protruding length is 0.1 μm or more, and a gap is provided between the channel side end of the upper source electrode 7b and the channel side end of the upper drain electrode 8b.

The protective film 9 is formed of a silicon nitride film, a silicon oxide film, or a multilayer film thereof.
In FIG. 1, the central portion of the upper surface of the amorphous silicon layer 5 is etched back and the cross section is formed in a concave shape, but the upper surface of the amorphous silicon layer 5 is not etched back and the cross section is rectangular. You may form in a shape.

Next, a method for manufacturing the thin film transistor 100 will be described with reference to FIGS.
First, in the step shown in FIG. 2, a metal film is formed on the transparent glass substrate 1 by sputtering or the like, and then the gate electrode 2 is patterned by photolithography. Next, a SiN film to be the gate insulating film 3 is formed with a thickness of 200 nm to 500 nm so as to cover the gate electrode 2, and then a microcrystalline silicon layer 4 with a thickness of 30 nm to 100 nm is formed on the gate insulating film 3 by plasma. It is formed by a CVD method or the like. Thereafter, an amorphous silicon layer 5 having a film thickness of 50 nm to 100 nm and not doped with impurities is formed, and an n-type amorphous film doped with phosphorus (P) with a film thickness of 10 nm to 50 nm on the amorphous silicon layer 5. A silicon layer 6 is formed by plasma CVD and patterned. Then, on the n-type amorphous silicon layer 6 and the gate insulating film 3, an Al alloy film is formed to a thickness of 50 nm to 300 nm to form a first metal layer 71, and then Cr is a film of about 50 nm. A second metal layer 72 is formed by forming a film with a thickness.

Next, in a step shown in FIG. 3, a resist pattern 10 for forming a source electrode and a drain electrode is formed on the second metal layer 72 by photolithography or the like.
After that, in the step shown in FIG. 4, the upper source electrode 7b and the upper drain electrode 8b are formed by wet etching the second metal layer 72. As the etchant used at this time, an etchant that does not substantially etch the first metal layer 71 is selected.

  Then, in the step shown in FIG. 5, the lower source electrode 7a and the lower drain electrode 8a are formed by wet etching the first metal layer 71 using an etchant different from the above etchant. At this time, by controlling the over-etching time, the length of the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b projecting from the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively. Adjust the protrusion length to 0.1 μm or more.

Subsequently, in the process shown in FIG. 6, the n-type amorphous silicon layer 6 on the channel is etched by performing dry etching in an anode coupling mode using a dry etching gas to which SF ₆ is added, and a pair of contact layers 6a and 6b are formed. By performing dry etching in the anode coupling mode using the dry etching gas containing SF ₆ in this way, the etching ends of the n-type amorphous silicon layers 6a and 6b are the channel of the lower source electrode 7a and the lower drain electrode 8a. It can be removed without protruding from the side end.
In the present embodiment, the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a and the channel side end portions of the contact layers 6a and 6b are formed on substantially the same plane.

  Then, after removing the resist pattern 10, the upper surface and channel side surface of the upper source electrode 7b and upper drain electrode 8b, the channel side surface of the lower source electrode 7a and lower drain electrode 8a, the channel side surface of the contact layers 6a and 6b, A protective film 9 made of a silicon nitride film, a silicon oxide film or a multilayer film thereof is formed so as to cover the amorphous silicon layer 5 to form the thin film transistor 100 shown in FIG. Thereafter, contact holes (not shown) and transparent electrodes (not shown) which are pixel electrodes are sequentially formed and mounted on an LCD, an OLED display or the like.

  As described above, in the thin film transistor 100 according to the present embodiment, the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b are formed in a bowl shape with respect to the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively. Since it is configured to protrude, the concentration of the electric field generated at the channel side end portion of the contact portion between the lower source electrode 7a and the lower drain electrode 8a and the n-type amorphous silicon layer can be relaxed. In a thin film transistor in which the band gap is narrow and the off current in a high electric field increases, the off current can be significantly reduced.

Next, the characteristics of the thin film transistor 100 will be described with reference to FIGS.
FIG. 7 is a diagram showing a relationship between a gate voltage and a drain current calculated by calculation using a two-dimensional device simulator, together with a comparative example, for the thin film transistor 100 in this embodiment.
Note that the thin film transistor of the comparative example has the configuration shown in FIG. In FIG. 8, the thin film transistor 101 of the comparative example is such that the source electrode 7 and the drain electrode 8 are formed of a single layer of Al alloy as in the prior art, and the channel side ends of the source electrode 7 and the drain electrode 8 are n-type. The channel side ends of the contact layers 6a and 6b made of amorphous silicon are formed on substantially the same plane.

In Comparative Example 1 in FIG. 7, the film thickness A of the amorphous silicon layer in the thin film transistor 101 in FIG. 8 is 50 nm. In Comparative Example 2, the film thickness A of the amorphous silicon layer in the thin film transistor 101 in FIG. 150 nm. In the thin film transistor 100 in this embodiment in FIG. 7, the film thickness A of the amorphous silicon layer is 50 nm.
In all the calculations shown in FIG. 7, the source electrode 7 is grounded and the drain voltage 8 is set to 10V. Further, the interval between the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a is set to 4 μm.

As shown in FIG. 7, when the film thickness of the amorphous silicon layer 5 is increased to 150 nm as in Comparative Example 2, the off-current is compared with that in Comparative Example 1 (film thickness of the amorphous silicon layer 5: 50 nm). Can be reduced, but at the same time, the on-current is also reduced.
However, in the thin film transistor in this embodiment, the off-current can be significantly reduced as compared with Comparative Example 1 while maintaining the on-current equivalent to that of Comparative Example 1. That is, the off current can be greatly reduced without reducing the on current.

Further, FIG. 9 shows a projection length calculated by calculation using a two-dimensional device simulator, at the channel-side end portions of the upper source electrode 7b and the upper drain electrode 8b with respect to the channel-side end portions of the lower source electrode 7a and the lower drain electrode 8a. FIG. The value of the off current is the value of the drain current when a drain voltage of 10 V and a gate voltage of −25 V are applied. As can be seen from FIG. 9, when the protruding length of the upper source electrode 7b and the upper drain electrode 8b on the channel side ends of the lower source electrode 7a and the lower drain electrode 8a with respect to the channel side ends is 0.1 μm or more, Reduce significantly. Therefore, it is desirable that the protruding length of the upper source electrode 7b and the upper drain electrode 8b on the channel side end with respect to the lower source electrode 7a and the lower drain electrode 8a on the channel side end is 0.1 μm or more. Note that since the reduction in off-current is determined by the protrusion length, the protrusion length may be 0.1 μm or more regardless of the size of the thin film transistor.
The film thickness of the lower source electrode 7a and the lower drain electrode 8a is preferably 50 nm to 300 nm of the channel protective film generally used in the etch stopper structure.

In the calculation shown in FIG. 9, the impurity concentration and film thickness of the n-type amorphous silicon layer 6 are 1 × 10 ¹⁷ cm ⁻³ and 30 nm, the film thickness of the microcrystalline silicon layer 4 is 50 nm, and the gate The thickness of the insulating film 3 is 450 nm, the thickness of the lower source electrode 7a and the upper source electrode 8a is 100 nm, and the distance between these channel side end portions is 4 μm.

  According to the present embodiment, source electrode 7 and drain electrode 8 are connected to lower source electrode 7a and lower drain electrode 8a connected to contact layers 6a and 6b made of n-type amorphous silicon, and lower source electrode 7a. The upper source electrode 7b and the upper drain electrode are formed of two layers of the upper source electrode 7b and the upper drain electrode 8b which are formed on the upper surface of the lower drain electrode 8a and are thinner than the lower source electrode 7a and the lower drain electrode 8a. Since the channel-side end portions of 8b protrude in a bowl shape from the channel-side end portions of the lower source electrode 7a and the lower drain electrode 8b, respectively, the off-current can be greatly reduced without reducing the on-current. Since it can be reduced, display unevenness in LCDs and OLED displays using thin film transistors is reduced. Rukoto can.

  Further, according to the present embodiment, since the protruding lengths of the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b are set to 0.1 μm or more, the off-current can be greatly reduced.

  Further, according to the present embodiment, the channel side end portions of the lower source electrode 7a and the lower drain electrode 7b and the channel side end portion of the n-type amorphous silicon layer 6 are formed on substantially the same plane. 7 and the drain electrode 8 can be more effectively reduced.

Embodiment 2. FIG.
FIG. 10 is a cross-sectional view showing the structure of the thin film transistor according to the second embodiment of the present invention, and FIGS. 11 to 15 are cross-sectional views showing the manufacturing steps of the thin film transistor according to the second embodiment of the present invention. FIGS. 16 and 17 are diagrams showing the characteristics of the thin film transistor according to the second embodiment of the present invention together with a comparative example.

First, the structure of the thin film transistor in Embodiment 2 is described with reference to FIG.
In FIG. 10, a thin film transistor 200 includes a transparent glass substrate 1, a gate electrode 2 provided on the glass substrate 1, and a gate insulating film 3 provided on the gate electrode 2. A microcrystalline silicon layer 4, an amorphous silicon layer 5 provided on the microcrystalline silicon layer 4, and a pair of n-type amorphous silicon provided on both ends of the amorphous silicon layer 5 Contact layers 6a, 6b, a lower source electrode 7a provided on one contact layer 6a, a lower drain electrode 8a provided on the other contact layer 6b, a lower source electrode 7a, a lower drain electrode 8a And a protective film 9 formed so as to cover the amorphous silicon layer 5, and the lower source electrode 7 a and the bottom through the contact holes 9 a and 9 b provided in the protective film 9. And an upper source electrode 7b and the upper drain electrode 8b is connected to the drain electrode 8a respectively.

Here, the upper source electrode 7 b and the upper drain electrode 8 b are formed in the same layer as a pixel electrode (not shown) provided on the protective film 9. The upper source electrode 7b and the upper drain electrode 8b are formed thinner than the film thickness of the lower source electrode 7a and the lower drain electrode 8a.
In the present embodiment, the lower source electrode 7a and the lower drain electrode 8a are formed of an aluminum (Al) alloy having a film thickness of 100 to 300 nm, and the upper source electrode 7b and the upper drain electrode 8b are formed of chromium (Cr) having a film thickness of 50 nm. It is formed with. The upper source electrode 7b and the upper drain electrode 8b are made of a 4A group, 5A group or 6A group metal such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta) or the like or these metals in addition to Cr. You may form with the alloy containing.

  Further, the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b are configured to project in a bowl shape from the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively. The protruding length is 0.1 μm or more, and a gap is provided between the channel side end of the upper source electrode 7b and the channel side end of the upper drain electrode 8b.

The gate insulating film 3 is formed of a silicon nitride film (SiN) having a thickness of 200 to 500 nm, the microcrystalline silicon layer 4 is 30 to 100 nm, and the amorphous silicon layer 5 is 50 to 100 nm. Are formed respectively. The contact layers 6a and 6b have a thickness of 10 to 50 nm and are formed of n-type amorphous silicon obtained by doping amorphous silicon with phosphorus (P) as an impurity. The protective film 9 is formed of a silicon nitride film, a silicon oxide film, or a multilayer film thereof.
In FIG. 1, the central portion of the upper surface of the amorphous silicon layer 5 is etched back and the cross section is formed in a concave shape, but the upper surface of the amorphous silicon layer 5 is not etched back and the cross section is rectangular. You may form in.

Next, a method for manufacturing the thin film transistor 200 will be described with reference to FIGS.
First, in the step shown in FIG. 11, after forming a metal film on the transparent glass substrate 1 by sputtering or the like, the gate electrode 2 is patterned by photolithography. Next, a SiN film to be the gate insulating film 3 is formed to 200 nm to 500 nm so as to cover the gate electrode 2, and then a microcrystalline silicon layer 4 having a thickness of 30 nm to 100 nm is formed on the gate insulating film 3 by a plasma CVD method or the like. Form. Thereafter, an amorphous silicon layer 5 having a film thickness of 50 nm to 100 nm and not doped with impurities is formed, and an n-type amorphous film doped with phosphorus (P) with a film thickness of 10 nm to 50 nm on the amorphous silicon layer 5. A silicon layer 6 is formed by plasma CVD and patterned. Then, an Al alloy is formed to a thickness of 50 nm to 300 nm on the n-type amorphous silicon layer 6 and the gate insulating film 3 to form a first metal layer 71, and then the first metal layer 71 is formed. A resist pattern 10 for forming a lower source electrode and a lower drain electrode is formed thereon by photolithography.

  Next, in the step shown in FIG. 12, the first metal layer 71 is wet etched to form the lower source electrode 7a and the lower drain electrode 8a. As an etchant used at this time, an etchant that does not substantially etch the n-type amorphous silicon layer 6 is selected.

Then, in the step shown in FIG. 13, the n-type amorphous silicon layer 6 on the channel is etched by performing dry etching in an anode coupling mode using a dry etching gas to which SF ₆ is added, and a pair of contact layers 6a , 6b. By performing dry etching in the anode coupling mode using the dry etching gas containing SF ₆ in this way, the etching ends of the n-type amorphous silicon layers 6a and 6b are the channel of the lower source electrode 7a and the lower drain electrode 8a. It can be removed without protruding from the side end.
In the present embodiment, the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a and the channel side end portions of the contact layers 6a and 6b are formed on substantially the same plane.

Subsequently, in the step shown in FIG. 14, after removing the resist pattern 10, the upper surfaces and channel side surfaces of the lower source electrode 7a and the lower drain electrode 8a, the channel side surfaces of the contact layers 6a and 6b, and the amorphous silicon layer A protective film 9 made of a silicon nitride film, a silicon oxide film or a multilayer film thereof is formed so as to cover the upper surface.
Then, in the step shown in FIG. 15, after providing contact holes 9a and 9b in the protective film 9, a transparent electrode (not shown) which is a pixel electrode is formed.

  Thereafter, the upper source electrode 7b and the upper drain electrode 8b are formed in the same layer as the transparent electrode (not shown) so as to be connected to the lower source electrode 7a and the lower drain electrode 8a through the contact holes 9a and 9b. The thin film transistor 200 shown in FIG. At this time, the upper source electrode 7b and the upper drain electrode 8b are formed to be thicker than the lower source electrode 7a and the lower drain electrode 8a, and the channel side ends of the upper source electrode 7b and the upper drain electrode 8b are formed at the lower source electrode. The electrode 7a and the lower drain electrode 8a are formed so as to protrude in a bowl shape at least 0.1 μm from the channel side end portions.

  As described above, in the thin film transistor 200 according to the present embodiment, the channel side end portions of the upper source electrode 7b and the upper drain electrode 8b are formed in a bowl shape with respect to the channel side end portions of the lower source electrode 7a and the lower drain electrode 8a, respectively. Since it is configured to protrude, the concentration of the electric field generated at the channel side end portion of the contact portion between the lower source electrode 7a and the lower drain electrode 8a and the n-type amorphous silicon layer can be relaxed. In a thin film transistor in which the band gap is narrow and the off current in a high electric field increases, the off current can be significantly reduced.

Next, the characteristics of the thin film transistor 200 will be described with reference to FIGS.
FIG. 16 is a diagram showing a relationship between a gate voltage and a drain current calculated by calculation using a two-dimensional device simulator, together with a comparative example, for the thin film transistor 200 in this embodiment.
Note that the thin film transistor of the comparative example has the structure shown in FIG. 8 as in the first embodiment, and the comparative example 1 in FIG. 16 has the thickness A of the amorphous silicon layer in the thin film transistor 101 in FIG. In Comparative Example 2, the thickness A of the amorphous silicon layer in the thin film transistor 101 in FIG. 8 is set to 150 nm. In the thin film transistor 200 in this embodiment in FIG. 16, the thickness A of the amorphous silicon layer is 50 nm. In all of the calculations shown in FIG. 16, the source electrode 7 is grounded and the drain voltage is set to 10V.

As shown in FIG. 16, when the film thickness of the amorphous silicon layer is increased to 150 nm as in Comparative Example 2, the off current is smaller than that in Comparative Example 1 (film thickness of the amorphous silicon layer 5: 50 nm). Although the value can be reduced, the on-current is also reduced at the same time.
However, in the configuration of the present embodiment, the off-current can be significantly reduced as compared with Comparative Example 1 while maintaining the on-current equivalent to that of Comparative Example 1. That is, the off current can be greatly reduced without reducing the on current.

FIG. 17 shows the length of protrusion of the upper source electrode 7b and the upper drain electrode 8b on the channel side ends of the lower source electrode 7a and the lower drain electrode 8a with respect to the channel side ends, calculated by calculation using a two-dimensional device simulator. FIG. The value of the off current is the value of the drain current when a drain voltage of 10 V and a gate voltage of −25 V are applied. The parameters used for the calculation are the same as those in the first embodiment.
As can be seen from FIG. 17, when the protruding length of the upper source electrode 7b and the upper drain electrode 8b on the channel side ends of the lower source electrode 7a and the lower drain electrode 8a with respect to the channel side ends is 0.1 μm or more, Reduce significantly. Therefore, it is desirable that the protruding length of the upper source electrode 7b and the upper drain electrode 8b on the channel side end with respect to the lower source electrode 7a and the lower drain electrode 8a on the channel side end is 0.1 μm or more.
Further, when the film thickness of the lower source electrode 7a and the lower drain electrode 8a is about 100 nm to 300 nm, the effect of reducing the off-current becomes high.

  According to the present embodiment, the source and drain electrodes are divided into lower source electrode 7a and lower drain electrode 7b provided on contact layers 6a and 6b, lower source electrode 7a and lower drain electrode 7b, and protective film 9 respectively. Are connected through contact holes 9a and 9b provided in the upper layer, and are composed of two layers of an upper source electrode 7b and an upper drain electrode 8b formed in the same layer as the pixel electrode provided on the protective film 9, and The channel-side end portions of the upper source electrode 7b and the upper drain electrode 8b are configured to project in a bowl shape from the channel-side end portions of the lower source electrode 7a and the lower drain electrode 8b, respectively, thereby reducing the on-current. Therefore, the off-state current can be greatly reduced, so that LCDs and OLED displays using thin film transistors can be used. It is possible to reduce the display unevenness such as Rei.

  1 glass substrate (transparent substrate), 2 gate electrode, 3 gate insulating film, 4 microcrystalline silicon layer, 5 amorphous silicon layer, 6 n-type amorphous silicon layer, 6a, 6b contact layer, 7 source electrode, 7a Lower source electrode, 7b Upper source electrode, 8 Drain electrode, 8a Lower drain electrode, 8b Upper drain electrode, 9 Protective film, 9a, 9b Contact hole, 10 Resist pattern, 71 First metal layer, 72 Second metal layer .

Claims (11)

A transparent substrate;
A gate electrode provided on the transparent substrate;
A microcrystalline silicon layer provided on the gate electrode via a gate insulating film and having a central portion serving as a channel;
An amorphous silicon layer provided on the microcrystalline silicon layer;
A pair of contact layers provided at both ends on the amorphous silicon layer;
A source electrode and a drain electrode respectively provided on the pair of contact layers,
The source electrode and the drain electrode are formed on a lower source electrode and a lower drain electrode connected to the contact layer, and on an upper surface of the lower source electrode and the lower drain electrode, and more than the lower source electrode and the lower drain electrode. It is composed of two layers of a thin upper source electrode and upper drain electrode,
The thin film transistor, wherein the channel-side end portions of the upper source electrode and the upper drain electrode protrude in a bowl shape with respect to the channel-side end portions of the lower source electrode and the lower drain electrode, respectively. A transparent substrate;
A gate electrode provided on the transparent substrate;
A microcrystalline silicon layer provided on the gate electrode via a gate insulating film and having a central portion serving as a channel;
An amorphous silicon layer provided on the microcrystalline silicon layer;
A pair of contact layers provided at both ends on the amorphous silicon layer;
A lower source electrode provided on the one contact layer;
A lower drain electrode provided on the other contact layer;
A protective film formed to cover the lower source electrode, the lower drain electrode and the contact layer;
An upper source electrode and an upper drain electrode respectively connected to the lower source electrode and the lower drain electrode through a contact hole provided in the protective film;
The upper source electrode and the upper drain electrode are formed in the same layer as the pixel electrode provided on the protective film, and are formed thinner than the film thickness of the lower source electrode and the lower drain electrode,
A thin film transistor, wherein the channel side end portions of the upper source electrode and the upper drain electrode protrude in a bowl shape with respect to the channel side end portions of the lower source electrode and the lower drain electrode, respectively.   3. The thin film transistor according to claim 1, wherein the protruding length of the channel side end portions of the upper source electrode and the upper drain electrode is 0.1 μm or more. 4.   4. The thin film transistor according to claim 3, wherein a gap is provided between a channel side end of the upper source electrode and the channel side end of the upper drain electrode.   5. The channel side end of the lower source electrode and the lower drain electrode and the channel side end of the contact layer are formed on substantially the same plane. The thin film transistor described.   6. The protective film made of a silicon nitride film, a silicon oxide film, or a multilayer film thereof is formed on the upper source electrode and the upper drain electrode. Thin film transistor. The upper source electrode and the upper drain electrode are formed of an aluminum alloy,
7. The lower source electrode and the lower drain electrode are formed of a group 4A, group 5A, or group 6A metal, or an alloy containing these metals. Thin film transistor. Forming a gate electrode on a transparent substrate;
Forming a gate insulating film so as to cover the gate electrode;
Forming a microcrystalline silicon layer having a central portion serving as a channel on the gate insulating film;
Forming an amorphous silicon layer on the microcrystalline silicon layer;
Forming an n-type amorphous silicon layer on the amorphous silicon layer;
Forming a first metal layer on the n-type amorphous silicon layer;
Forming a second metal layer on the first metal layer;
Etching the second metal layer to form an upper source electrode and an upper drain electrode;
Etching the first metal layer to form a lower source electrode and a lower drain electrode;
Etching the n-type amorphous silicon layer on the channel by dry etching in an anode coupling mode using a dry etching gas added with SF ₆ to form a pair of contact layers,
The channel-side end portions of the upper source electrode and the upper drain electrode are formed so as to protrude in a bowl shape with respect to the channel-side end portions of the lower source electrode and the lower drain electrode, respectively. A method for manufacturing a thin film transistor. Forming a gate electrode on a transparent substrate;
Forming a gate insulating film so as to cover the gate electrode;
Forming a microcrystalline silicon layer having a central portion serving as a channel on the gate insulating film;
Forming an amorphous silicon layer on the microcrystalline silicon layer;
Forming an n-type amorphous silicon layer on the amorphous silicon layer;
Forming a first metal layer on the n-type amorphous silicon layer;
Etching the first metal layer to form a lower source electrode and a lower drain electrode;
Etching the n-type amorphous silicon layer on the channel by dry etching in an anode coupling mode using a dry etching gas added with SF ₆ to form a pair of contact layers;
Forming a protective film so as to cover the lower source electrode, the lower drain electrode and the amorphous silicon layer;
Providing a contact hole in the protective film;
Forming an upper source electrode and an upper drain electrode connected to the lower source electrode and the lower drain electrode through the contact hole on the protective film,
The channel-side end portions of the upper source electrode and the upper drain electrode are formed so as to protrude in a bowl shape with respect to the channel-side end portions of the lower source electrode and the lower drain electrode, respectively. A method for manufacturing a thin film transistor.   10. The method of manufacturing a thin film transistor according to claim 8, wherein a protruding length of the channel-side end portions of the upper source electrode and the upper drain electrode is 0.1 μm or more. 11.   11. The channel-side end portions of the lower source electrode and the lower drain electrode and the channel-side end portion of the contact layer are formed on substantially the same plane. The manufacturing method of the thin-film transistor of description.

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