JP2010257559A - High voltage generation circuit and nonvolatile semiconductor memory circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high voltage generation circuit which efficiently generates positive and negative high voltages using a single circuit. <P>SOLUTION: A charge pump circuit which efficiently generates positive and negative high voltages using a single circuit is implemented. The charge pump circuit correctly controls the voltage potentials of a P well including an NMOS transistor constituting the charge pump circuit, and an N well surrounding the circumference and bottom of the P well so that a forward bias is not applied to a parasitic diode formed by the P and N wells. SW2 and SW3 are made conductive when the high negative voltage is output. SW1 and SW4 are made conductive when the positive high voltage is output. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a high voltage generation circuit in an electrically writable nonvolatile semiconductor memory device.

In flash memory and logic embedded non-volatile memory, by using each operation principle such as FN tunneling, BTBT-HE injection, CHE injection, etc., electrons can be put into the charge storage layer or extracted from the charge storage layer. Rewrite data. This rewriting requires a high voltage whose absolute value is larger than the power supply voltage, and a high voltage generation circuit is required inside the chip. The output voltage in the high voltage generation circuit is generally given by the following equation.
Positive high voltage VP = (N + 1) * (VCC−Vd)
-N * T * Iout / Cmain
Negative high voltage VN = -N * (VCC-Vd)
+ N * T * Iout / Cmain
N: number of stages Vd: loss during charge transfer (related to conductance)
(*) Diffusion potential for PN diode
In the case of a MOS transistor, threshold voltage T: clock frequency Iout: output load current Cmain: a high voltage is generated from the pump-up capacitance power supply voltage VCC arranged in each stage. The voltage generation efficiency decreases as the voltage VCC decreases. Further, in order to improve the voltage generation efficiency, it is important to reduce the loss at the time of charge transfer (Vd in the above equation). As shown in Patent Document 1, measures such as reducing Vd in terms of circuit are taken. It becomes necessary. Improving the voltage generation efficiency can reduce the number of stages required to obtain the same output voltage, and contributes to a reduction in the area of the high voltage generation circuit. When the area ratio of the high-voltage generation circuit occupying the module area is small, such as a logic-embedded non-volatile memory, the area of the high-voltage generation circuit is high, and the area is reduced by high efficiency and the high-voltage generation circuit is adapted to optimize the operation of the memory cell. It is also important to reduce the number of types. As shown in Patent Document 2, there is an example in which both positive and negative high voltages are realized by one type of high voltage generation circuit.
US61030572 US6147547

An example shown in Patent Document 1 is shown in FIG. The feature is that an NMOS transistor is used as the rectifying element. In order to increase the voltage generation efficiency, the threshold voltage rise due to the substrate effect is suppressed by controlling the P-well potential of the NMOS transistor of the rectifying element using a bias circuit. In addition, the conductance is improved by boosting the gate potential. However, in this configuration, there is a problem that only a negative voltage can be generated due to the potential relation among the P well, the bottom N well, and the P substrate in the triple well forming the NMOS transistor of the rectifying element.

The example shown by patent document 2 is shown in FIG.13 and FIG.14. It is characterized by using a polydiode as the rectifying element. Since the polydiode is formed on the insulating film, forward bias leakage does not occur between each well and the P substrate during the pump-up operation, and there is an advantage that both positive and negative voltages can be generated. When outputting a positive voltage, SW1 and SW4 are turned on, and SW2 and SW3 are turned off. When outputting a negative voltage, the output can be switched by turning SW2 and SW3 on and turning SW1 and SW4 off. However, in this configuration, there is a problem that a loss at the time of charge transfer in the high voltage generation circuit is large because there is a diffusion potential Vd (about 0.7 V) of the PN junction in the polydiode portion of the rectifying element. For example, when the power supply voltage is 1.2V, if 0.7V is lost, only 0.5V is effectively contributed to charge transfer. This causes deterioration in high voltage generation efficiency, and means that the circuit area increases because of the need to increase the number of stages.

As described above, in order to reduce the area of the high voltage generation circuit, it is desirable to improve the voltage generation efficiency and to generate both positive and negative voltages with one type of high voltage generation circuit.

In order to solve the above problems, typical configurations in the present invention are as follows. The method of switching the positive and negative voltages using SW1 to SW4 in generating both positive and negative high voltages is the same as that of Patent Document 2.

As the rectifying element, an NMOS transistor formed in a P well in a triple well and having a source and a P well connected is used instead of a poly diode. As a result, an increase in threshold voltage due to the substrate effect can be suppressed and conductance can be improved.

As other means for improving the conductance of the rectifying element, there are two types, a method of boosting the gate potential of the NMOS transistor and a method of lowering the threshold voltage of the NMOS transistor.

In order to handle both positive and negative voltages, the P well, the bottom N well, and the P substrate in the triple well in which the NMOS transistor is formed are controlled by using a switching circuit so that the potential relationship does not become a forward bias. .

When outputting a positive voltage, the NMOS source and the P-well are set to the same potential, and the P-well and the bottom N-well are set to the same potential via the PMOS transistor, thereby avoiding a forward bias leak between the wells. An increase in threshold voltage due to the effect is suppressed.

At the time of negative voltage output, the source of the NMOS transistor and the P-well are set to the same potential, and the bottom N-well potential is set to GND via the NMOS transistor, VCC via the PMOS transistor, or floating, so that the order between the wells is increased. While avoiding bias leakage, an increase in threshold voltage due to the substrate effect is suppressed.

Typical effects of the invention disclosed in the present application are as follows. By increasing the conductance of the rectifying element in the high voltage generation circuit and increasing the voltage generation efficiency, both positive and negative voltages can be generated by one type of high voltage generation circuit, so that the circuit area can be greatly reduced.

FIG. 11 shows a block diagram of the nonvolatile memory device. The high voltage generation circuit in the present invention receives a signal from the control circuit, generates a positive high voltage or a negative high voltage according to each operation mode, and applies a high voltage to the memory array via the word line driver and the column system write driver. Supply.

FIG. 1 shows a high voltage generation circuit according to the first embodiment. The method of switching the output of positive and negative voltages using SW1 to SW4 in generating both positive and negative high voltages is the same as that of Patent Document 2. The difference is in the rectifying element portion. In this embodiment, the NMOS transistors N1 and N2 formed in the P well in the same triple well, the NMOS transistor N3 formed in the normal P well, and the triple well The PMOS transistor P1 is formed in an N well having the same potential as the bottom N well.

The cross-sectional structure of each transistor is as shown in FIG. Here, a parasitic diode D1 is formed between the P well and the bottom N well, and a parasitic diode D2 is formed between the P substrate and the bottom N well. The gate of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2 and the boosting capacitive element Cg, and the drain is connected to the pumping capacitive element Cmain and the gate of the NMOS transistor N2. On the other hand, the source is connected to the P well in the triple well together with the source of the NMOS transistor N2. The gate of the NMOS transistor N3 is controlled by the VNE signal, and is inserted between GND and the bottom N well in the triple well. The PMOS transistor P1 is inserted between the bottom N well and the P well with the gate connected to the GND potential and the N well connected to the bottom N well in the triple well.

The rectifying elements are connected in series, and complementary signals CLK and ICLK for controlling the capacitive element Cmain and complementary signals CLKG and ICLKG for controlling the capacitive element Cg are alternately connected.

Charge transfer to the next stage in the high voltage generation circuit is performed by the following method. First, in the period P1, the potential of the node G is boosted through the NMOS transistor N2. Subsequently, with the NMOS transistor N2 turned off, the potential of the node G is further boosted by coupling with the capacitor Cg in the period P2, thereby increasing the conductance of the NMOS transistor N1 and transferring the charge to the next stage. Is done. After that, the potential of the node G is lowered, and during the period P3, the NMOS transistor N1 is turned off to prepare for charge transfer in the next phase. By alternately operating the rectifying elements connected in series in these operations, charge is gradually transferred from the previous stage to the next stage.

The operation for outputting a positive voltage is as follows. By turning on SW1 and SW4 and turning off SW2 and SW3, the node L is connected to the power supply voltage VCC, and the node R is connected to the output VP. At this time, charge transfer is performed so that a positive voltage higher than the power supply voltage VCC is output on the node R side with reference to the node L side set to the power supply voltage VCC.

In each rectifying element, the VNE signal is set to GND, the NMOS transistor N3 is turned OFF, and the bottom N well and the P well in the triple well are electrically connected via the PMOS transistor P1, thereby forming a triple well. It is avoided that the parasitic diodes D1 and D2 between the respective wells are forward biased.

The operation when a negative voltage is output is as follows. By turning off SW1 and SW4 and turning on SW2 and SW3, node R is connected to GND and node L is connected to output VN. At this time, charge transfer is performed such that a negative voltage lower than GND is output on the node L side with reference to the node R side set to GND.

In each rectifying element, the PMOS transistor P1 is turned off, the VNE signal is set to VCC, and the NMOS transistor N3 is turned on to set the bottom N well potential in the triple well to GND. As long as the node IN is a negative voltage, the parasitic diodes D1 and D2 between the wells in the triple well are not forward biased. However, when the node IN is temporarily higher than GND as in the initial negative voltage output, the parasitic diode D1 is temporarily forward biased, and there is a risk of latch-up due to parasitic bipolar action, etc. It is necessary to reinforce the well fixing.

A high voltage generation circuit according to the second embodiment is shown in FIG. The difference from the first embodiment is that a PMOS transistor P2 is inserted instead of the NMOS transistor N3 in order to set the bottom N well potential in the triple well to the power supply voltage VCC. The gate of the PMOS transistor P2 is connected to the VNE1 signal and the source is connected to the gate of the PMOS transistor P1 and is controlled by the VNE2 signal. The PMOS transistors P1 and P2 are formed in the same N well and controlled to the same potential as the bottom N well in the triple well.

As control of the high voltage generation circuit, control of SW1 to SW4 and control of the CLK signal and the like are the same as those in the first embodiment.

The operation for outputting a positive voltage is as follows. In each rectifying element, the VNE1 signal is set to output VP and the VNE2 signal is set to GND, the PMOS transistor P2 is turned OFF, and the bottom N well and the P well in the triple well are electrically connected via the PMOS transistor P1. This prevents the parasitic diodes D1 and D2 between the wells in the triple well from being forward biased.

The operation when a negative voltage is output is as follows. In each rectifying element, the PMOS transistor P1 is turned OFF, the VNE1 signal is set to GND, the VNE2 signal is set to the power supply voltage VCC, and the PMOS transistor P2 is turned ON, so that the bottom N well potential in the triple well is set to the power supply voltage. Set to VCC. As long as the node IN is lower than the power supply voltage VCC, the parasitic diodes D1 and D2 between the wells in the triple well are not forward biased. Even in the case where the node IN is temporarily higher than GND (GND <node IN <VCC) as in the initial negative voltage output, the parasitic diode D1 is not forward-biased in this configuration. The risk of latch-up is less than that. However, in this configuration, the voltage difference between the source and drain of the PMOS transistor P1 is increased by the power supply voltage VCC, and it is necessary to ensure the transistor breakdown voltage.

FIG. 3 shows a high voltage generation circuit according to the third embodiment. In this embodiment, both the NMOS transistor N3 and the PMOS transistor P2 are inserted in order to control the bottom N well potential in the triple well between the power supply voltages VCC and GND.

As the control of the high voltage generation circuit, the control of SW1 to SW4 and the control of the CLK signal and the like are the same as those in the first and second embodiments.

The operation for outputting a positive voltage is as follows. In each rectifying element, the VNE2 signal is set to the output VP, the VNE1 signal and the VNE3 signal are set to GND, the NMOS transistor N3 and the PMOS transistor P2 are turned off, and the bottom N well in the triple well is connected via the PMOS transistor P1. By electrically connecting the P wells, the parasitic diodes D1 and D2 between the wells in the triple well are prevented from being forward biased.

The operation when a negative voltage is output is as follows. As shown in FIG. 9, the operation is switched between the first half and the second half when a negative voltage is output. In the first half of the negative voltage output, the potential of the node IN may be temporarily higher than GND. Therefore, as shown in the second embodiment, the bottom N well potential in the triple well is set to the power supply voltage VCC and the negative voltage output is performed. In the second half, since the potential of the node IN is lower than GND, the bottom N well potential in the triple well is set to GND as shown in the first embodiment. This two-stage control alleviates the voltage difference between the source and drain of the PMOS transistor P1 while preventing the parasitic diodes D1 and D2 between the wells in the triple well from being forward-biased, and provides a sufficient margin for the transistor breakdown voltage. We are trying to secure it.

FIG. 4 shows a high voltage generation circuit according to the fourth embodiment. Unlike the first, second, and third embodiments, the bottom N-well potential in the triple well is floating.

As the control of the high voltage generation circuit, the control of SW1 to SW4 and the control of the CLK signal and the like are the same as those of the first to third embodiments.

Regardless of whether a positive voltage or a negative voltage is output, the bottom N-well potential in the triple well is floating, so that the parasitic diodes D1 and D2 between the wells in the triple well are forward-biased in each operation mode. There is a case. However, since it is not a leak current flowing in a DC manner but a charge / discharge current, the forward bias state is eliminated in a self-aligned manner during the operation period. Since the bottom N well potential in the triple well fluctuates according to the charge / discharge current, it is necessary to reinforce the well fixing as a countermeasure for latch-up. However, the first to third embodiments are preferred in terms of the number of transistor elements and controllability. More advantageous.

FIG. 5 shows a high voltage generation circuit according to the fifth embodiment. The NMOS transistor and the capacitive element Cg connected to the gate of the NMOS transistor N1 are deleted from the first embodiment, and instead the threshold voltage of the NMOS transistor N1 is lowered to about 0V in order to improve conductance. Features. The gate and source of the NMOS transistor N1 are diode-connected.

The rectifying elements are connected in series, and complementary signals CLK and ICLK for controlling the capacitive element Cmain are alternately connected. Unlike the first embodiment, complementary signals CLKG and ICLKG for controlling the capacitive element Cg are not required.

Charge transfer to the next stage in the high voltage generation circuit is performed by the following method. In the first embodiment, the four-phase clocks CLK, ICLK, CLKG, and ICLKG are necessary. However, in this embodiment, the operation is possible with the two-phase clocks CLK and ICLK. CLK and ICLK are complementary signals, and charges are gradually transferred from the previous stage to the next stage by alternately operating rectifying elements connected in series.

The bottom N well potential control in the triple well in the case of outputting the positive voltage and the negative voltage is the same as that in the first embodiment. The voltage generation efficiency depends on the threshold voltage of the NMOS transistor N1, and the voltage generation efficiency can be improved as the threshold voltage is lowered. From the viewpoint of the number of transistor elements and controllability, it is more advantageous than the first embodiment.

A high voltage generating circuit according to the sixth embodiment is shown in FIG. The NMOS transistor and the capacitive element Cg connected to the gate of the NMOS transistor N1 are deleted from the second embodiment, and instead the threshold voltage of the NMOS transistor N1 is lowered to about 0 V in order to improve conductance. Features. The gate and source of the NMOS transistor N1 are diode-connected.

The bottom N well potential control in the triple well in the case of outputting the positive voltage and the negative voltage is the same as that of the second embodiment. The voltage generation efficiency depends on the threshold voltage of the NMOS transistor N1, and the voltage generation efficiency can be improved as the threshold voltage is lowered. From the viewpoint of the number of transistor elements and controllability, it is more advantageous than the second embodiment.

FIG. 7 shows a high voltage generation circuit according to the seventh embodiment. The NMOS transistor and the capacitive element Cg connected to the gate of the NMOS transistor N1 are deleted from the third embodiment, and instead, the threshold voltage of the NMOS transistor N1 is lowered to about 0 V in order to improve conductance. Features. The gate and source of the NMOS transistor N1 are diode-connected.

The bottom N well potential control in the triple well in the case of outputting the positive voltage and the negative voltage is the same as that in the third embodiment. The voltage generation efficiency depends on the threshold voltage of the NMOS transistor N1, and the voltage generation efficiency can be improved as the threshold voltage is lowered. From the viewpoint of the number of transistor elements and controllability, it is more advantageous than the third embodiment.

FIG. 8 shows a high voltage generation circuit according to the eighth embodiment. The NMOS transistor and the capacitive element Cg connected to the gate of the NMOS transistor N1 are deleted from the fourth embodiment, and instead the threshold voltage of the NMOS transistor N1 is lowered to about 0 V in order to improve conductance. Features. The gate and source of the NMOS transistor N1 are diode-connected.

The bottom N well potential control in the triple well in the case of outputting the positive voltage and the negative voltage is the same as that of the fourth embodiment. The voltage generation efficiency depends on the threshold voltage of the NMOS transistor N1, and the voltage generation efficiency can be improved as the threshold voltage is lowered. From the viewpoint of the number of transistor elements and controllability, it is more advantageous than the fourth embodiment.

The high voltage generation circuit described in the first to eighth embodiments is used at the time of writing and erasing operations in the nonvolatile semiconductor memory device of FIG.

The present invention can be applied to a high voltage generation circuit necessary for writing and erasing operations in a nonvolatile semiconductor memory device.

1 is a configuration and control method of a high voltage generation circuit according to Embodiment 1 of the present invention. 4 shows a configuration and control method of a high voltage generation circuit according to Embodiment 2 of the present invention. 10 shows a configuration and control method of a high voltage generation circuit according to Example 3 of the present invention. 7 shows a configuration and a control method of a high voltage generation circuit according to Example 4 of the present invention. 10 shows a configuration and a control method of a high voltage generation circuit according to Embodiment 5 of the present invention. 10 shows a configuration and a control method of a high voltage generation circuit according to Embodiment 6 of the present invention. 12 shows a configuration and a control method of a high voltage generation circuit according to Example 7 of the present invention. 10 shows a configuration and a control method of a high voltage generation circuit according to an eighth embodiment of the present invention. It is an example of the control timing at the time of the negative voltage output concerning Examples 3 and 7 of the present invention. It is an example of a section structure of a transistor which constitutes a high voltage generating circuit concerning Examples 1-8 of the present invention. 1 is a block diagram of a nonvolatile semiconductor memory device including a high voltage generation circuit according to Embodiments 1 to 8 of the present invention. FIG. It is a circuit structural example of the negative high voltage generation circuit in a prior art example (patent document 1). It is a circuit structural example of the positive / negative high voltage generation circuit in a prior art example (patent document 2). It is a structure and control method of the positive / negative high voltage generation circuit in a prior art example (patent document 2).

P1, P2 PMOS transistors N1, N2, N3 NMOS transistors Cmain, Cg Capacitors D1, D2 Parasitic diodes

Claims (5)

  A charge pump circuit provided on a semiconductor substrate, the first power supply node receiving a first power supply potential, and a first switch connected between the first power supply node and a first internal node Means, a first output node for outputting a first output potential, a second switch means connected between the first internal node and the first output node, and the first power supply A second power supply node lower than the potential, a third switch connected between the second power supply node and the second internal node, and a second output node for outputting a second output potential And a fourth switch means connected between the second internal node and the second output node, connected between the first internal node and the second internal node, The electric power of the second internal node is higher than the electric potential of the first internal node. Voltage generating means for increasing the voltage, and the voltage generating means includes a first NMOS transistor connected in series provided to flow current from the first internal node to the second internal node; , Including a first capacitor having one electrode connected to a connection node of the first NMOS transistors connected in series and a clock signal applied to the other electrode. In the first operation mode, the second capacitor The switch means and the third switch means are turned on, the first switch means and the fourth switch means are opened, and in the second operation mode, the first switch means, The charge pump circuit, wherein the fourth switch means is in a conductive state, and the second switch means and the third switch means are in an open state.   2. The charge pump circuit according to claim 1, wherein the first NMOS transistor is formed in a P well whose periphery and bottom are surrounded by an N well, and between the gate terminal and the source terminal of the first NMOS transistor. A second NMOS transistor formed in a P-well having the same potential as the P-well in which the first NMOS transistor is formed, and one electrode connected to the gate terminal of the first NMOS transistor; A second capacitor to which a clock signal is applied to the other electrode; a third NMOS transistor connected between a terminal of the N-well and the second power supply node; and the N-well. A charge pump circuit including a first PMOS transistor connected between a terminal of a P well and a terminal of the N well.   2. The charge pump circuit according to claim 1, wherein the first NMOS transistor is formed in a P-well having a periphery and a bottom surrounded by an N-well, and a gate terminal and a source terminal of the first NMOS transistor are connected, A second NMOS transistor connected between the N-well terminal and the second power supply node, and formed in the N-well, connected between the P-well terminal and the N-well terminal. And a first PMOS transistor.   4. The charge pump circuit according to claim 3, wherein a threshold voltage of the first NMOS transistor is lower than a threshold voltage of the second NMOS transistor.   A nonvolatile semiconductor memory device in which writing and erasing are performed using a high voltage generated by the charge pump circuit according to claim 1.

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