JP2010204749A - Layout support program, layout support device, and layout support method - Google Patents

Abstract

A layout capable of additionally arranging desired cells without losing the timing relationship of the laid-out cells is provided.
When a new cell (additional cell) is added and there is no vacant space that can be arranged, a cell that has the least influence on the signal propagation timing is selected from the laid out cells. The cell is selected as a movement target cell for preparing a free area for placing the. By arranging a new cell in the empty area to which the selected cell has been moved, the timing adjustment associated with the insertion of the additional cell can be unnecessary or kept to the minimum necessary.
[Selection] Figure 1

Description

  The present invention relates to a layout support program, a layout support apparatus, and a layout support method in post-layout ECO (Engineering Change Ordering) processing.

  Conventionally, a post-layout ECO process for adding a new cell has been proposed in order to expand the circuit function of a semiconductor circuit already laid out so that each cell maintains a predetermined timing. In the post-layout ECO process, a technique for extracting a region where a new cell can be inserted by referring to a timing margin until signal propagation for each laid-out cell is disclosed (for example, see Patent Document 1 below). .)

JP 2001-188818 A

  However, in the case of the prior art as described above, if there is no area where a new cell can be inserted, the timing of each laid out cell may not be maintained. For example, in order to insert a new cell, one of the laid-out cells must be moved to prepare an empty area.

  At this time, depending on the cell to be moved, the timing of cells not related to the logic change may be lost. Once the layout timing of a cell has collapsed, timing adjustment is required for each cell again, and there is a problem that a great load and time are consumed for the adjustment processing.

  The present invention provides a layout support program, a layout support apparatus, and a layout support method capable of additionally arranging desired cells without destroying the timing relationship of the laid-out cells in order to solve the above-described problems caused by the prior art. The purpose is to do.

  In order to solve the above-described problems and achieve the object, the layout support program, the layout support apparatus, and the layout support method are configured so that a computer includes layout information indicating an arrangement state of a cell group constituting a semiconductor circuit, and the cell group. Processing for obtaining priority information set in accordance with the type of cell included, processing for receiving information on an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information, and , A process for determining whether or not there is a free area in which the additional cell can be arranged, and when it is determined that there is no free area in which the additional cell can be arranged, the distance from the arbitrary cell, and the priority A process of extracting a movement target cell based on the information, a process of searching a free area where the extracted movement target cell can be arranged, and a free area are searched, The process of moving the movement target cell to the empty area, the process of arranging the additional cell at the position where the movement target cell moved to the empty area is arranged, and the semiconductor circuit in which the additional cell is arranged And a process of outputting the layout information of the above.

  According to the layout support program, the layout support apparatus, and the layout support method, when there is no free area in which an additional cell can be arranged, a cell having a low possibility of affecting the timing is extracted and used as another free area. By moving it, it is possible to realize a layout in which additional cells are arranged in the vicinity of the target cell.

  According to the layout support program, the layout support apparatus, and the layout support method according to the present invention, there is an effect that a desired cell can be additionally arranged without destroying the timing relationship between the laid-out cells.

It is explanatory drawing which shows the outline | summary of the layout assistance process concerning this Embodiment. It is a block diagram which shows the hardware constitutions of the layout assistance apparatus concerning this Embodiment. It is explanatory drawing which shows the functional structure of the layout assistance apparatus concerning this Embodiment. It is a circuit diagram which shows an example of the semiconductor circuit used as layout design object. FIG. 5 is an explanatory diagram showing layout information of each cell of the semiconductor circuit shown in FIG. 4. It is explanatory drawing which shows the priority according to the kind of cell. It is explanatory drawing which shows the procedure which arrange | positions an additional cell and overlaps. 6 is an explanatory diagram showing an arrangement of additional cells using the layout support process in the first embodiment. FIG. 5 is a flowchart illustrating a procedure of layout support processing in the first embodiment. FIG. 10 is an explanatory diagram showing an arrangement of additional cells using the layout support process in the second embodiment. 10 is a flowchart showing a procedure of layout support processing in the second embodiment. FIG. 10 is an explanatory diagram showing an arrangement of additional cells using the layout support process in the third embodiment. 10 is a flowchart illustrating a procedure of layout support processing according to the third embodiment. FIG. 16 is an explanatory diagram showing an arrangement of additional cells using layout support processing in the fourth embodiment.

  Exemplary embodiments of the layout support program, the layout support apparatus, and the layout support method will be described below in detail with reference to the accompanying drawings. In this layout support program, layout support apparatus, and layout support method, when a new cell is added, if there is no vacant space that can be arranged, the timing of signal propagation is not affected most among the laid out cells. The cell is selected as a movement target cell for preparing an empty area for arranging a new cell. By arranging a new cell in the empty area to which the selected cell has been moved, the timing adjustment associated with the insertion of the additional cell can be unnecessary or kept to the minimum necessary. Therefore, a layout support process for realizing the above process will be described below.

(Outline of layout support processing)
First, an outline of the layout support process according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an outline of layout support processing according to the present embodiment. As shown in FIG. 1, in a semiconductor circuit in which a plurality of cell groups are arranged as in layout example A, it is assumed that the function must be expanded by inserting additional cells near the target cell.

  First, it is determined whether or not there is a free area in which an additional cell can be inserted within a predetermined range from the target cell (for example, area R in FIG. 1). Here, if it is determined that there is a free area, an additional cell may be inserted into the free area. However, in the case of layout example A in FIG. 1, there is no empty area into which additional cells can be inserted.

  Then, the priority of the cell arrange | positioned in the area | region R is referred next. The priority is a value indicating the degree of priority when the empty area has to be prepared in order to insert an additional cell. In the layout example A of FIG. 1, priority levels 1 to 4 are set, and a cell having a low priority value is determined as a cell to be moved with priority. Here, the cell that is preferentially moved is a cell that has a small influence on timing due to movement. Therefore, the priority value is set smaller as the influence on the timing is smaller, and the priority value is set larger as the influence on the timing is larger. Therefore, the priority is set according to the cell type.

  In the case of layout example A, a cell with priority 1 is adjacent to the upper stage of the target cell. Therefore, as in layout example B, the cell with priority 1 is moved to the adjacent empty area as the movement target cell. Thereafter, an additional cell is arranged in an empty area generated by the movement of the cell having the priority 1 to generate a rearrangement layout in which the additional cell is added.

  As described above, in the present embodiment, a cell having the least influence on timing due to movement is selected from the cell group based on the priority. Then, the function of the semiconductor circuit can be expanded by arranging an additional cell in an empty area generated by the movement of the selected cell. Hereinafter, a specific configuration for realizing the layout support process described above will be described.

(Hardware configuration of layout support device)
FIG. 2 is a block diagram of a hardware configuration of the layout support apparatus according to the embodiment. In FIG. 2, a layout support apparatus 100 includes a CPU (Central Processing Unit) 201, a ROM (Read-Only Memory) 202, a RAM (Random Access Memory) 203, a magnetic disk drive 204, a magnetic disk 205, and a communication. An I / F (Interface) 206, an input device 207, and an output device 208 are provided. Each component is connected by a bus 210.

  Here, the CPU 201 governs overall control of the layout support apparatus 100. The ROM 202 stores various programs such as a boot program and a layout support program for realizing the layout support process according to the present embodiment. The RAM 203 is used as a work area for the CPU 201. The magnetic disk drive 204 controls data update / reference with respect to the magnetic disk 205 according to the control of the CPU 201. The magnetic disk 205 stores data written under the control of the magnetic disk drive 204. In addition, although the magnetic disk 205 is used in the hardware configuration of FIG. 2, other recording media such as an optical disk and a flash memory may be used.

  The communication I / F 206 is connected to a network (NET) 209 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to another layout support apparatus 100 via the network 209. The The communication I / F 206 controls an internal interface with the network 209 and controls data input / output from an external device. As a configuration example of the communication I / F 206, for example, a modem or a LAN adapter can be employed.

  The input device 207 receives an external input to the layout support apparatus 100. Specific examples of the input device 207 include a keyboard and a mouse.

  In the case of a keyboard, for example, keys for inputting letters, numbers, various instructions and the like are provided, and data is input. Moreover, a touch panel type input pad or a numeric keypad may be used. In the case of a mouse, for example, the cursor is moved, a range is selected, or a window is moved or the size is changed. Further, a trackball or a joystick may be used as long as they have the same function as a pointing device.

  The output device 208 outputs the layout information acquired by the layout support apparatus 100 and the layout information generated by the layout support process. Specific examples of the output device 208 include a display and a printer.

  In the case of a display, for example, data such as a cursor, an icon or a tool box, a document, an image, and function information is displayed. Further, a CRT, a TFT liquid crystal display, a plasma display, or the like can be employed as this display. In the case of a printer, for example, image data and document data are printed. Further, a laser printer or an ink jet printer can be employed.

(Functional configuration of layout support device)
Next, a functional configuration of the layout support apparatus 100 will be described. FIG. 3 is a block diagram illustrating a functional configuration of the layout support apparatus. The layout support apparatus 100 includes an acquisition unit 301, a reception unit 302, a determination unit 303, an extraction unit 304, a search unit 305, a movement unit 306, a rearrangement unit 307, and an output unit 308. It is. Specifically, the functions (acquisition unit 301 to output unit 308) serving as the control unit are, for example, the layout support program stored in the storage area such as the ROM 202, RAM 203, and magnetic disk 205 shown in FIG. The function is realized by executing or by the communication I / F 206.

  The acquisition unit 301 has a function of acquiring layout information 101 that indicates the arrangement state of the cell group that constitutes the semiconductor circuit, and priority information 102 that is set according to the type of cell included in the cell group. Specifically, the layout information 101 is information indicating what kind of cell each of the cell groups constituting the semiconductor circuit to be processed is, for example, what interval is arranged on the ROW. It is.

  Here, FIG. 4 is a circuit diagram showing an example of a semiconductor circuit which is a layout support target. As shown in FIG. 4, the semiconductor circuit 400 includes three FF (Flip Flop) circuits 1, 9, 10, two inverter circuits 2, 3, four buffer circuits 4, 5, 6, 7, and one An AND circuit 8, one OR circuit 12, and one clock driver 11 are provided.

  FIG. 5 is an explanatory diagram showing layout information of each cell of the semiconductor circuit shown in FIG. When the layout support apparatus 100 supports layout of the semiconductor circuit 400, the acquisition unit 301 acquires the layout information 500 illustrated in FIG. 5 and uses it for subsequent processing. In the present embodiment, the layout support process will be described using the layout information 500 below.

  FIG. 6 is an explanatory diagram showing priorities according to cell types. In the acquisition unit 301, the priority set according to the type of each cell constituting the semiconductor circuit 400 is acquired together with the layout information 500 described above. As shown in FIG. 6, in the case of a cell constituting the semiconductor circuit 400, priority 1: inverter (inverter circuits 2, 3) → priority 2: buffer (buffer circuits 4, 5, 6, 7) → priority 3 : Logic element (AND circuit 8, OR circuit 12) → priority 4: clock driver (clock driver 11) → priority 5: priority is set in the order of storage elements (FF circuits 1, 9, 10) . These priorities are set such that a cell with less input / output has less influence on the timing of other cells. Further, since the recording element is highly likely to affect the timing of a plurality of cells, the priority is set to the lowest value as the cell that is most not to be moved.

  In this embodiment, the lower the value, the higher the priority is determined (priority 1> priority 5). However, the handling of the priority value can be set as appropriate. . The layout information 101 and priority information 102 acquired by the acquisition unit 301 are stored in a storage area such as the RAM 203 and the magnetic disk 205.

  Returning to the description of FIG. 3, the receiving unit 302 subsequently receives additional cell information 103 to be arranged corresponding to an arbitrary cell in the cell group included in the layout information 101. In the additional cell information 103, what type of cell corresponds to which cell in the cell group represented by the layout information 500 is set. Specifically, the setting is such that the buffer circuit corresponds to the FF circuit 1 in the cell group represented by the layout information 500. The additional cell information 103 received by the receiving unit 302 is stored in a storage area such as the RAM 203 and the magnetic disk 205.

  The determining unit 303 has a function of referring to the additional cell information 103 received by the receiving unit 302 and determining whether or not there is a free area in the layout information 500 where an additional cell can be placed. At this time, the target area for determining whether or not there is a free area may be the entire layout information 500 or may be within a predetermined range based on the target cell. In particular, when the signal propagation time between the target cell and the additional cell is short and there is no room, it is necessary to determine whether or not there is an empty area within a range that does not disturb the timing between the target cell and the additional cell. . Note that the determination result by the determination unit 303 is stored in a storage area such as the RAM 203 and the magnetic disk 205.

  The extraction unit 304 has a function of extracting a movement target cell based on the distance from the target cell and the priority information 102 when the determination unit 303 determines that there is no free area in which the additional cell can be arranged. Have. The movement target cell is a cell to be moved in order to secure an empty area for arranging an additional cell. Therefore, a cell that is arranged near the target cell and has a high priority is extracted as a movement target cell. The extraction result by the extraction unit 304 is stored in a storage area such as the RAM 203 and the magnetic disk 205. If the determination unit 303 determines that there is a free area in which an additional cell can be placed, the additional cell may be placed in this free area.

  The search unit 305 has a function of searching for a free area in which the movement target cell extracted by the extraction unit 304 can be placed. Here, the search range of the empty area by the search unit 305 may be the entire area represented by the layout information 500, or may be set as appropriate according to the type of the movement target cell. As an example of setting a search range, 1) a search is made for a vacant area in which a movement target cell can be arranged from a movement target cell extracted by the extraction unit 304 within a predetermined range. 2) When a free area in which the cell to be moved can be arranged is not searched, a predetermined range is expanded for each specific size until a free area is searched. 3) An example of searching for a free area in which the movement target cell can be arranged is included in a range proportional to the propagation time from the cell connected to the preceding stage of the movement target cell.

  The moving unit 306 has a function of moving the movement target cell to the searched free region when the search unit 305 searches for a free region. Note that the processing object of the movement described here is the layout information 101. In other words, the movement target cell is not actually moved, but only the setting value of the layout information 101 is changed. Therefore, the movement unit 306 changes the address of the arrangement position of the movement target cell set in the layout information 101 to the address of the searched free area. The layout information 101 whose movement target cell has been moved by the moving unit 306 is stored in a storage area such as the RAM 203 and the magnetic disk 205.

  In addition, in the extraction unit 304 described above, there are cases where there are a plurality of cells that satisfy the same condition (for example, cells having the same distance from the target cell and the same cell type). In such a case, since a plurality of movement target cells are extracted by the extraction unit 304, the movement unit 306 compares the plurality of movement target cells and sets a cell that satisfies a specific condition as the movement target cell. Move.

  For example, the moving unit 306 moves a cell having the smallest input / output number from the plurality of moving target cells extracted by the extracting unit 304 to a free area as a cell having a low possibility of affecting the timing of other cells. . The number of inputs / outputs can be confirmed by referring to the fine-out of each cell.

  In addition, the moving unit 306 selects a cell having a large driving current to other connected cells out of the plurality of moving target cells extracted by the extracting unit 304 and has a low possibility of affecting the timing of the other cells. May be moved to an empty area. The magnitude of the drive current to other cells can be confirmed by referring to the drive capability of each cell.

  In addition, the moving unit 306 may affect the timing of other cells by selecting the cell having the longest signal propagation time from the cell connected to the previous stage among the plurality of moving target cells extracted by the extracting unit 304. You may move to an empty area as a low cell. The signal propagation time from the cell connected to the previous stage can be confirmed by referring to the margin value (slack) of the path timing of each cell.

  Next, the rearrangement unit 307 arranges the additional cell at the position where the movement target cell moved to the empty area by the movement unit 306 has been arranged. Similar to the processing of the moving unit 306 described above, the rearrangement processing target is the layout information 101. Therefore, the rearrangement unit 307 generates new layout information 104 including the additional cell information 103 instead of the layout information 101. The layout information 104 generated by the rearrangement unit 307 is stored in a storage area such as the RAM 203 and the magnetic disk 205.

  If the search unit 305 does not search for a free area, the extraction unit 304 may again extract a new movement target cell based on the distance from the movement target cell and the priority information 102. Good. When a new cell to be moved is extracted by this extraction process, the search unit 305 searches for a free area in which the new cell to be moved can be placed. Then, after the search unit 305 searches for a free area, the new movement target cell is moved to the free area searched by the moving unit 306.

  By the above-described processing, the area where the new movement target cell is arranged is provided as a free area to move the movement target cell first extracted by the extraction unit 304. Then, the moving unit 306 can move the new moving target cell to the empty area, and then move the first extracted moving target cell to the position where the new moving target cell was arranged. That is, the movement target cell extracted first pushes out a new movement target cell and replaces the arrangement area like a ball. An empty area generated by this replacement is secured as a rearrangement area for the additional cells.

  Finally, the output unit 308 has a function of outputting the layout information 104 of the semiconductor circuit 400 in which the additional cell is arranged by the rearrangement unit 307. The output format includes, for example, display on the display of the output device 208, print output to a printer, and transmission to an external device via the communication I / F 206. Further, it may be stored in a storage area such as the RAM 203 and the magnetic disk 205.

  As described above, in the layout support processing according to the present embodiment, when additional cells are inserted by post-layout ECO processing, the influence on the timing of other cells is minimized even when there is no free area. Additional cells can be inserted as follows. Specifically, move the cell that has the least effect on the timing of other cells extracted based on the priority and input / output conditions set for each cell, and secure free space to insert additional cells. can do. Therefore, it is possible to generate a layout in which additional cells are inserted without breaking the timing relationship between the laid-out cells.

  Next, four specific embodiments (Embodiments 1 to 4) of the layout support process described above will be described.

(Embodiment 1)
In the first embodiment, based on the priority described with reference to FIG. 6, a cell having a small influence on the timing of other cells due to movement is extracted as a movement target cell, and an area for arranging an additional cell is secured. This movement target cell extraction processing is the most basic processing of the present embodiment. Note that Embodiments 2 to 4 described later also have a configuration in which processing for increasing the accuracy and efficiency of the extraction processing is added to the extraction processing of the movement target cell described in Embodiment 1. .

  Here, first, a conventional example of inserting additional cells will be described. FIG. 7 is an explanatory diagram showing a procedure for arranging additional cells in an overlapping manner. FIG. 7 shows processing for inserting an additional cell corresponding to the FF circuit 1 that is the target cell in the layout information 500. An additional cell (buffer) is added to an area 710 between the FF circuit 1 and the buffer circuit 7. At this time, since the area 710 is smaller than the area of the additional cell, the additional cell overlaps with the FF circuit 1 (STEP 1).

  Thereafter, in order to eliminate the overlap between the additional cell and the FF circuit 1, first, the FF circuit 1 is moved to the right. Then, due to this movement, the region 720 between the FF circuit 1 and the FF circuit 9 arranged in the subsequent stage overlaps (STEP 2).

  Therefore, in order to eliminate the overlap between the FF circuit 1 and the FF circuit 9, this time, the FF circuit 9 is moved to the right region 730 (STEP 3). As described above, it seems that the additional cells are inserted without any problem by the processing of STEP 1 to STEP 3, but actually, the FF circuit 1 and the FF circuit 9 are moved, so that the timing of many cells is affected. There is a high possibility that Generally, the delay value of the clock signal that changes when the clock signal is connected to the clock signal terminal of the FF circuit changes. The change in the delay value of the clock signal affects all the FF circuits that propagate the clock signal. Therefore, a timing error occurs at many timing points.

  Therefore, in the first embodiment, cells that do not affect the timing of other cells are extracted, and additional cells are efficiently inserted. FIG. 8 is an explanatory diagram showing the arrangement of additional cells using the layout support process in the first embodiment. FIG. 8 also shows processing for inserting an additional cell corresponding to the FF circuit 1 that is the target cell, as in FIG.

  In the layout information 500, since there is no empty area to insert an additional cell in the vicinity of the FF circuit 1, the buffer circuit 4 is extracted as the movement target cell 810 based on the priority (STEP 1). Next, since the cell to be moved 810 has been moved to a nearby empty area 820, the area where the buffer circuit 4 is arranged becomes an empty area (STEP 2). Therefore, an additional cell is inserted into the empty area 830, resulting in a new layout (STEP 3).

  In the case of the process described with reference to FIG. 8, since the buffer circuit 4 is moved unlike the process of FIG. 7, the influence of timing on other cells may be considered for this cell. However, since the buffer circuit 4 has the least influence on the timing of other cells among the cells arranged in the layout information 500, it is necessary even if it has some influence on the timing of other cells. Only minimal timing adjustment is required.

  Next, the procedure of the layout support process in the first embodiment will be described. FIG. 9 is a flowchart illustrating a procedure of layout support processing according to the first embodiment. In the flowchart of FIG. 9, first, the inverter having the highest priority is extracted from the cells adjacent to the target FF circuit 1 (step S901), and it is determined whether or not the inverter is extracted in step S901 (step S902). .

  In the above-described step S902, when an inverter is extracted (step S902: Yes), it is determined whether or not an additional cell can be arranged by moving the extracted inverter (step S903). If it is determined in step S903 that an additional cell can be arranged by moving the inverter (step S903: Yes), the inverter is moved (step S904), and the additional cell is arranged in the free space after the movement ( Step S915), a series of processing ends.

  On the other hand, when the inverter is not extracted (step S902: No), or when it is determined that the additional cell cannot be arranged even if the inverter is moved (step S903: No), the adjacent FF circuit 1 is adjacent. A buffer having the second highest priority among the cells to be extracted is extracted (step S905). Then, it is determined whether or not a buffer has been extracted in step S905 (step S906).

  If a buffer is extracted in step S906 described above (step S906: Yes), it is determined whether an additional cell can be arranged by moving the extracted buffer (step S907). If no buffer is extracted in step S906 (step S906: No), or if it is determined in step S907 that an additional cell cannot be arranged (step S907: No), the third highest priority is given. The logic element is moved (step S908), an additional cell is arranged in the free space after the movement (step S915), and the series of processes is terminated.

  On the other hand, when it is determined in step S907 that an additional cell can be arranged (step S907: Yes), the fine-out of each buffer is further confirmed (step S909). Then, it is determined whether or not there are a plurality of fine-out one-to-one buffers that have little influence on other cells (step S910). If it is determined in this step S910 that there is only one fine-out one-to-one buffer (step S910: No), this buffer is moved (step S911), and an additional cell is placed in the free space after the movement. (Step S915), and a series of processing ends.

  On the other hand, if it is determined in step S910 that there are a plurality of fine-out one-to-one buffers (step S910: Yes), a buffer that does not affect the target FF is extracted in order to extract a buffer that has little effect on other cells. It is determined whether or not there is a buffer having a high drive capability (step S912). The level of drive capability in step S912 is determined based on whether it is greater than or less than a reference value.

  Therefore, if it is determined in step S912 that there is a buffer with high drive capability (step S912: Yes), the buffer with high drive capability is moved (step S913), and an additional cell is moved to the free area after the move. Arrange (step S915), and a series of processing ends.

  If it is determined in step S912 that there is no buffer with high drive capability (step S912: No), a cell with a high timing margin value is moved (step S914), and an additional cell is moved to the free area after movement. Arrange (step S915), and a series of processing ends. The timing margin value (slack) is a value representing a grace period of timing for accepting signal propagation from a path connected to a cell. It is expressed by an actual grace time such as 500 psec.

  As described above, in the first embodiment, the movement target cell is extracted based on the priority and the buffer condition, and is set as the insertion destination of the additional cell. By this process, unlike the conventional insertion process, it is possible to prevent the occurrence of overlap, and it is possible to suppress a change in delay time related to clock signal propagation. Therefore, it is possible to suppress the occurrence of timing violations other than the logic change portion.

(Embodiment 2)
In the second embodiment, when extracting the movement target cell in the layout support process of the first embodiment, the extraction target area is limited, and the extraction target area is expanded stepwise according to the extraction result. It is possible to efficiently extract a movement target cell.

  FIG. 10 is an explanatory diagram showing the arrangement of additional cells using the layout support process in the second embodiment. As shown in FIG. 10, in the second embodiment, when a movement target cell is extracted, first, the first cell selection region is targeted. And when a movement object cell is not extracted from the 1st cell selection area | region, a movement object cell is extracted from the 2nd cell selection area | region which expanded the area | region more.

  Next, the procedure of the layout support process in the second embodiment will be described. FIG. 11 is a flowchart showing a procedure of layout support processing in the second embodiment. In the flowchart of FIG. 11, first, when insertion of an additional cell is accepted, a selection area of a movement target cell is created (step S1101). The selection area of the movement target cell means a first cell selection area or a second cell selection area as shown in FIG. In addition, in the process of step S1101, the size of the selection area to be created can be arbitrarily set.

  Next, it is determined whether or not there is an additional cell insertion area in the selected area (step S1102). That is, it is determined whether or not there is a free area in which the cell to be moved can be inserted in the first cell selection area. If it is determined in step S1102 that there is an additional cell insertion area (step S1102: Yes), the additional cell is inserted in the insertion area (step S1106), and the series of processing ends.

  On the other hand, if it is determined in step S1102 that there is no additional cell insertion area (step S1102: No), a movement target cell is selected from the selection area in order to secure the insertion destination of the additional cell (step S1103). ). And it is judged whether the timing margin value (slack) of the selected movement object cell is larger than a reference value (step S1104).

  In step S1104, when it is determined that the timing margin value (slack) is larger than the reference value (step S1104: Yes), the selection area is moved (step S1105), and the additional cell insertion area is newly set in the selection area. It is determined whether or not there is (step S1102). Moving the selection area in step S1105 means, for example, movement from the first cell selection area to the second cell selection area in the example of FIG.

  On the other hand, when it is determined in step S1104 that the timing margin value (slack) does not satisfy the reference value (step S1104: No), the movement target cell is selected from the selection region created in step S1101. That is, since the timing margin value of the movement target cell is small, expanding the selection area affects the timing. Therefore, the process returns to step S1103 to select the optimum movement target cell in the selection area created first.

  As described above, in the second embodiment, the search is performed by narrowing down the movement target cell to a specific area. When the movement target cell is not searched, the search range is expanded step by step to the limit range based on the timing margin value. Therefore, since the search is started from the minimum necessary area, an efficient search is possible.

(Embodiment 3)
In the third embodiment, when searching for a movement target cell by narrowing down to a specific area, a movable distance is calculated from the above-described timing margin value (slack), and there is an empty area within the calculated area. Determine whether or not.

  FIG. 12 is an explanatory diagram showing the arrangement of additional cells using the layout support process in the third embodiment. For example, when the target cell is the inverter 2, the movable distance is calculated from the timing margin value of the inverter 2 using a Manhattan length-based delay or a wire load model. Therefore, in the case of the inverter 2, the circle 1210 is in a movable range, and the movement target cell is searched for within the circle 1210. Similarly, in the case of the inverter 3, the movable range obtained from the timing margin value is a circle 1220. And a movement object cell is searched in this range.

  FIG. 13 is a flowchart showing a procedure of layout support processing in the third embodiment. In the flowchart of FIG. 13, when insertion of an additional cell is accepted, a selection area of a movement target cell is created (step S1301). The selection area of the movement target cell means a circle 1210 or a circle 1220 as shown in FIG. In addition, in the process of step S1301, the size of the selection area to be created can be arbitrarily set.

  Next, it is determined whether or not there is an additional cell insertion area in the selected area (step S1302). That is, it is determined whether or not there is a free area in the circle 1210 in which the cell to be moved can be inserted. If it is determined in step S1302 that there is an additional cell insertion area (step S1302: Yes), the additional cell is inserted in the insertion area (step S1308), and the series of processing ends.

  On the other hand, if it is determined in step S1302 that there is no additional cell insertion area (step S1302: No), a movement target cell is selected from the selection area in order to secure the insertion destination of the additional cell (step S1303). ). Then, the timing margin value (slack) of the selected movement target cell is confirmed (step S1304), and a movable area is calculated (step S1305).

  Then, it is determined whether or not there is an insertion area n of the movement target cell in the calculated movable area (step S1306). If it is determined in step S1306 that there is an additional cell insertion area n (step S1306: Yes), the process returns to step S1303, and the processes from step S1303 to 1306 are performed until it is determined that there is no longer the insertion area n of the movement target cell. repeat. On the other hand, when it is determined in step S1306 that the insertion area n of the movement target cell has disappeared (step S1306: No), the movement target cell is moved (step S1307), and the process returns to step S1302.

  As described above, in the third embodiment, since a moving target cell is selected within a range obtained by calculating a movable distance based on a timing margin value, only a cell that does not cause a timing delay is moved. It can be selected as a target cell.

(Embodiment 4)
In the fourth embodiment, when a free area for inserting a movement target cell is not searched, first, a free area for inserting the movement target cell is prepared. Then, the movement target cell is inserted into the prepared empty area, and the additional cell is inserted into the area where the movement target cell is arranged. That is, empty areas are prepared in order and the cells are moved.

  FIG. 14 is an explanatory diagram showing the arrangement of additional cells using the layout support process in the fourth embodiment. In FIG. 14, the inverter circuit 3 is first selected as the cell to be moved, but there is no empty area in which the inverter circuit 3 can be inserted in the selectable range 1410 of the inverter circuit 3. Therefore, the movement target cell is selected using the inverter circuit 3 as the target cell. Then, the FF circuit 9 is selected as the movement target cell. Therefore, when the FF circuit 9 is moved to a free area in the selectable range 1420, the inverter circuit 3 is inserted into the free area of the FF circuit 9, and a free area in which an additional cell can be inserted is secured.

  As described above, in the fourth embodiment, a new movement target cell is pushed out and the arrangement area is replaced like a ball hit. An empty area generated by this replacement is secured as a rearrangement area for the additional cells.

  As described above, according to the present embodiment, when there is no free space in which an additional cell can be placed, a cell having a low possibility of affecting the timing is extracted and moved to another free space. Thus, it is possible to realize a layout in which the additional cells are arranged in the vicinity of the target cell. Therefore, a desired cell can be additionally arranged without destroying the timing relationship between the laid-out cells, and the processing load on the layout designer can be greatly reduced.

  The layout support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a medium that can be distributed via a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) Computer
Obtaining means for obtaining layout information representing an arrangement state of a cell group constituting a semiconductor circuit and priority information set in accordance with a type of a cell included in the cell group;
Receiving means for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
Determining means for determining whether or not there is a free area in which the additional cell can be placed;
An extraction means for extracting a movement target cell based on the distance from the arbitrary cell and the priority information when it is determined by the determination means that there is no free area in which the additional cell can be placed;
Search means for searching for a free area in which the movement target cell extracted by the extraction means can be placed,
Moving means for moving the movement target cell to the free area when a free area is searched by the search means;
Relocation means for arranging the additional cell at a position where the movement target cell moved to the empty area by the movement means has been arranged;
Output means for outputting layout information of the semiconductor circuit in which additional cells are arranged by the relocation means;
A layout support program characterized by functioning as

(Supplementary note 2) When a plurality of movement target cells are extracted by the extraction unit, the movement unit moves a cell having the smallest number of input / outputs to the empty area among the plurality of movement target cells. The layout support program according to Supplementary Note 1.

(Supplementary Note 3) When a plurality of movement target cells are extracted by the extraction unit, the moving unit moves, among the plurality of movement target cells, a cell having a large driving current to another cell to the empty area. The layout support program according to appendix 1 or 2, characterized in that:

(Supplementary Note 4) When a plurality of movement target cells are extracted by the extraction unit, the movement unit selects a cell having the longest signal propagation time from the cell connected to the previous stage among the plurality of movement target cells. The layout support program according to any one of appendices 1 to 3, wherein the layout support program is moved to an empty area.

(Additional remark 5) The said search means searches the empty area | region which can arrange | position the said movement object cell for the inside of the predetermined range from the movement object cell extracted by the said extraction means. The layout support program according to any one of the above.

(Additional remark 6) When the search means does not search for a free area in which the cell to be moved can be arranged, the search means expands the predetermined range for each specific size until the free area is searched. The layout support program according to appendix 5.

(Additional remark 7) The said search means searches the empty area | region which can arrange | position the said movement object cell from the range proportional to the propagation time from the cell connected to the front | former stage of the said movement object cell, The additional characteristic characterized by the above-mentioned. The layout support program according to any one of 1 to 5.

(Supplementary Note 8) When the search unit does not search for a free area, the extraction unit further determines a new cell to be moved based on the distance from the extracted cell to be moved and the priority information. Extract and
The search means searches for a free area in which a new cell to be moved extracted by the extraction means can be placed,
The moving means moves the new moving target cell to the empty area when the searching means searches for a free area where the new moving target cell can be arranged, and moves the moving target cell to the new movement. The layout support program according to any one of appendices 5 to 7, wherein the layout support program is moved to a position where the target cell has been arranged.

(Supplementary Note 9) Acquisition means for acquiring layout information indicating an arrangement state of a cell group constituting a semiconductor circuit, and priority information set according to a type of a cell included in the cell group;
Receiving means for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
Determining means for determining whether there is a free area in which the additional cell can be placed;
An extraction means for extracting a movement target cell based on the distance from the arbitrary cell and the priority information when it is determined by the determination means that there is no free area in which the additional cell can be arranged;
Search means for searching for a free area where the movement target cell extracted by the extraction means can be arranged;
When a free area is searched by the search means, moving means for moving the movement target cell to the free area;
Relocation means for arranging the additional cell at a position where the movement target cell moved to the empty area by the movement means is arranged;
Output means for outputting layout information of the semiconductor circuit in which additional cells are arranged by the rearrangement means;
A layout support apparatus comprising:

(Supplementary note 10)
An acquisition step of acquiring layout information representing an arrangement state of a cell group constituting a semiconductor circuit, and priority information set according to a type of a cell included in the cell group,
An accepting step for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
A determination step of determining whether there is a free area in which the additional cell can be placed;
When it is determined by the determination step that there is no free space in which the additional cell can be arranged, an extraction step of extracting a movement target cell based on the distance from the arbitrary cell and the priority information;
A search step for searching for a free area where the movement target cell extracted by the extraction step can be arranged;
When an empty area is searched by the search step, a movement step of moving the movement target cell to the empty area;
A rearrangement step of arranging the additional cell at a position where the movement target cell moved to the empty area by the movement step is arranged;
An output step of outputting layout information of the semiconductor circuit in which additional cells are arranged by the rearrangement step;
A layout support method characterized by executing

DESCRIPTION OF SYMBOLS 100 Layout support apparatus 101 Layout information 102 Priority information 103 Additional cell information 104 Layout information (including an additional cell)
301 Acquiring Unit 302 Accepting Unit 303 Judging Unit 304 Extracting Unit 305 Searching Unit 306 Moving Unit 307 Relocation Unit 308 Output Unit

Claims (7)

Computer
Obtaining means for obtaining layout information representing an arrangement state of a cell group constituting a semiconductor circuit and priority information set in accordance with a type of a cell included in the cell group;
Receiving means for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
Determining means for determining whether or not there is a free area in which the additional cell can be placed;
An extraction means for extracting a movement target cell based on the distance from the arbitrary cell and the priority information when it is determined by the determination means that there is no free area in which the additional cell can be placed;
Search means for searching for a free area in which the movement target cell extracted by the extraction means can be placed,
Moving means for moving the movement target cell to the free area when a free area is searched by the search means;
Relocation means for arranging the additional cell at a position where the movement target cell moved to the empty area by the movement means has been arranged;
Output means for outputting layout information of the semiconductor circuit in which additional cells are arranged by the relocation means;
A layout support program characterized by functioning as   2. The layout support program according to claim 1, wherein the search unit searches for a free area in which the movement target cell can be arranged within a predetermined range from the movement target cell extracted by the extraction unit. .   The search means, when a free area where the cell to be moved can be arranged is not searched, expands the predetermined range for each specific size until the free area is searched. 2. The layout support program according to 2.   The search means searches for a free area in which the cell to be moved can be arranged from a range proportional to a propagation time from a cell connected to the previous stage of the cell to be moved. The layout support program according to any one of the above. If the search means does not search for an empty area, the extraction means further extracts a new movement target cell based on the distance from the extracted movement target cell and the priority information,
The search means searches for a free area in which a new cell to be moved extracted by the extraction means can be placed,
The moving means moves the new moving target cell to the empty area when the searching means searches for a free area where the new moving target cell can be arranged, and moves the moving target cell to the new movement. The layout support program according to any one of claims 2 to 4, wherein the program is moved to a position where the target cell has been arranged. Obtaining means for obtaining layout information representing an arrangement state of a cell group constituting a semiconductor circuit, and priority information set in accordance with a type of a cell included in the cell group;
Receiving means for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
Determining means for determining whether there is a free area in which the additional cell can be placed;
An extraction means for extracting a movement target cell based on the distance from the arbitrary cell and the priority information when it is determined by the determination means that there is no free area in which the additional cell can be arranged;
Search means for searching for a free area where the movement target cell extracted by the extraction means can be arranged;
When a free area is searched by the search means, moving means for moving the movement target cell to the free area;
Relocation means for arranging the additional cell at a position where the movement target cell moved to the empty area by the movement means is arranged;
Output means for outputting layout information of the semiconductor circuit in which additional cells are arranged by the rearrangement means;
A layout support apparatus comprising: Computer
An acquisition step of acquiring layout information representing an arrangement state of a cell group constituting a semiconductor circuit, and priority information set according to a type of a cell included in the cell group,
An accepting step for receiving information of an additional cell to be arranged corresponding to an arbitrary cell in the cell group included in the layout information;
A determination step of determining whether there is a free area in which the additional cell can be placed;
When it is determined by the determination step that there is no free space in which the additional cell can be arranged, an extraction step of extracting a movement target cell based on the distance from the arbitrary cell and the priority information;
A search step for searching for a free area where the movement target cell extracted by the extraction step can be arranged;
When an empty area is searched by the search step, a movement step of moving the movement target cell to the empty area;
A rearrangement step of arranging the additional cell at a position where the movement target cell moved to the empty area by the movement step is arranged;
An output step of outputting layout information of the semiconductor circuit in which additional cells are arranged by the rearrangement step;
A layout support method characterized by executing

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