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JP2010225892A - SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE Download PDF

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JP2010225892A
JP2010225892A JP2009072034A JP2009072034A JP2010225892A JP 2010225892 A JP2010225892 A JP 2010225892A JP 2009072034 A JP2009072034 A JP 2009072034A JP 2009072034 A JP2009072034 A JP 2009072034A JP 2010225892 A JP2010225892 A JP 2010225892A
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Prior art keywords
lead
semiconductor device
protruding
plating
temporary connection
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Yoshiharu Kaneda
芳晴 金田
Motoaki Shimizu
基晶 清水
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Renesas Electronics Corp
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Renesas Electronics Corp
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

【課題】モールド手段から突出するリードの長さに関わらず、モールド手段から突出するリードの全面に外装メッキ処理を施すことが可能な半導体装置を提供すること。
【解決手段】本発明に係る半導体装置の製造方法は、リードカット工程後にリードフレームからリード先端にメッキ電流が流れるように、あらかじめ、前記リード間、又は／及び前記リードとタブ間に仮結線を形成し、前記仮結線を形成後に、モールド成形を行い、前記リードカットを実施し、前記リードに外装メッキを施し、前記仮結線を分断する。
【選択図】図１A semiconductor device capable of performing exterior plating treatment on the entire surface of a lead protruding from a molding means regardless of the length of the lead protruding from the molding means.
A semiconductor device manufacturing method according to the present invention is such that a temporary connection is made in advance between the leads or / and between the leads and tabs so that a plating current flows from the lead frame to the tip of the lead after the lead cutting process. After forming the temporary connection, molding is performed, the lead cut is performed, exterior plating is applied to the lead, and the temporary connection is divided.
[Selection] Figure 1

Description

本発明は、リードを有する半導体装置、及びその製造方法に関する。また、前記半導体装置を搭載した電子機器に関する。   The present invention relates to a semiconductor device having leads and a method for manufacturing the same. The present invention also relates to an electronic device equipped with the semiconductor device.

半導体装置の表面実装パッケージとして、ＳＯＮ（Small Outline Non-lead）パッケージや、ガルウイングタイプのパッケージなどがある。ＳＯＮパッケージは、封止樹脂から突出するリードの長さが短いリードレスタイプのものである。ガルウイングタイプのパッケージは、封止樹脂から水平方向に突出するリードが下方に折り曲げられ、さらに水平方向に折り曲げられたものである。   As surface mount packages for semiconductor devices, there are SON (Small Outline Non-lead) packages and gull-wing type packages. The SON package is a leadless type with a short lead protruding from the sealing resin. In the gull-wing type package, a lead protruding in a horizontal direction from a sealing resin is bent downward and further bent in a horizontal direction.

このような半導体装置は、通常、以下の工程を経て製造される。まず、リードフレームに半導体チップを搭載する。次いで、モールド手段を用いて半導体素子の封止を行う。続いて、リードフレームに対し、外装メッキ処理などの外装処理を行う。その後、リードフレームのリード先端部に対応する部分を切断（リードカット）することにより、半導体装置を個片分離する。   Such a semiconductor device is usually manufactured through the following steps. First, a semiconductor chip is mounted on the lead frame. Next, the semiconductor element is sealed using a mold means. Subsequently, exterior processing such as exterior plating is performed on the lead frame. Thereafter, the semiconductor device is separated into individual pieces by cutting (lead cutting) a portion corresponding to the lead tip of the lead frame.

上記製造工程において製造されたリード先端面（切断面）は、メッキ皮膜が形成されていない。これは、リードの切断工程よりも前の工程において、外装メッキ処理を行っているためである。上記製造工程において製造されたリード先端面は、メッキ皮膜が形成されていないことに起因して半田濡れ性が悪くなる。そして、半田濡れ性不良に起因して、半導体装置を実装基板などに実装する際に、実装強度が低下してしまうという問題が生じていた。   The lead tip surface (cut surface) manufactured in the above manufacturing process is not formed with a plating film. This is because the exterior plating process is performed in a process prior to the lead cutting process. The lead end surface manufactured in the manufacturing process has poor solder wettability due to the absence of a plating film. Then, due to the poor solder wettability, there has been a problem that the mounting strength is reduced when the semiconductor device is mounted on a mounting substrate or the like.

特許文献１においては、上記問題点を解決する方法として、リード先端面が完全にメッキで覆われていなくても、基板実装時に良好な半田フィレットを形成する方法が提案されている。図９（ａ）に、特許文献１に記載のＳＯＮパッケージ構造の半導体装置の平面図を、図９（ｂ）にＡ方向から見た側面図を、図９（ｃ）にＢ方向から見た側面図を、図９（ｄ）に下面図を、図９（ｅ）に図９（ｂ）の破線円で囲まれた部分の拡大図を示す。   In Patent Document 1, as a method for solving the above problems, a method of forming a good solder fillet at the time of board mounting is proposed even if the lead end face is not completely covered with plating. 9A is a plan view of the semiconductor device having the SON package structure described in Patent Document 1, FIG. 9B is a side view seen from the A direction, and FIG. 9C is seen from the B direction. FIG. 9D shows a side view, FIG. 9D shows a bottom view, and FIG. 9E shows an enlarged view of a portion surrounded by a broken-line circle in FIG. 9B.

リード１０３は、半導体チップ（不図示）を封止するための封止樹脂１０１の側面に複数設けられている。リード１０３の一部は、封止樹脂１０１の底面に露出している。リード１０３の先端部１０３ａは半抜き工法（ハーフブランク工法）により、例えばリード１０３の厚みの半分の寸法だけ上方へ折り曲げられており、リード１０３の下面１０３ｂに段差部１０３ｃが形成されている。   A plurality of leads 103 are provided on the side surface of the sealing resin 101 for sealing a semiconductor chip (not shown). A part of the lead 103 is exposed on the bottom surface of the sealing resin 101. The leading end 103a of the lead 103 is bent upward by, for example, a half dimension of the thickness of the lead 103 by a half punching method (half blank method), and a stepped portion 103c is formed on the lower surface 103b of the lead 103.

リード１０３の先端面には、下面１０３ｂ側から上面１０３ｄ側へ順にダレ面１０３ｅ、剪断面１０３ｆ、破断面１０３ｇ、切断バリ１０３ｈが形成されている。リード１０３において、段差部１０３ｃを含む下面１０３ｂ、上面１０３ｄ、側面、及びダレ面１０３ｅにメッキ被膜（不図示）が形成されている。剪断面１０３ｆにはメッキ被膜が形成されている場合と形成されていない場合がある。   A sag surface 103e, a shear surface 103f, a fracture surface 103g, and a cutting burr 103h are formed on the tip surface of the lead 103 in this order from the lower surface 103b side to the upper surface 103d side. In the lead 103, a plating film (not shown) is formed on the lower surface 103b, the upper surface 103d, the side surface, and the sag surface 103e including the stepped portion 103c. The shearing surface 103f may or may not be formed with a plating film.

図１０（ａ）、図１０（ｂ）に、特許文献１に記載の半導体装置を実装基板に実装した状態のリード部分の断面図を示す。図１０（ａ）は、リード先端面の剪断面１０３ｆにメッキ被膜（不図示）が形成されていない場合の断面図であり、図１０（ｂ）は、リード先端面の剪断面１０３ｆにメッキ被膜（不図示）が形成されている場合の断面図である。   10A and 10B are cross-sectional views of a lead portion in a state where the semiconductor device described in Patent Document 1 is mounted on a mounting substrate. FIG. 10A is a cross-sectional view when a plating film (not shown) is not formed on the shearing surface 103f of the lead tip surface, and FIG. 10B is a plating film on the shearing surface 103f of the lead tip surface. It is sectional drawing in case (not shown) is formed.

実装基板１０５上に、ＳＯＮパッケージ構造の半導体装置を搭載してリード１０３と実装基板１０５の電極（不図示）を半田接続すると、リード１０３の段差部１０３ｃを含む下面１０３ｂ及び側面に半田フィレット１０７が形成される（図１０（ａ）、図１０（ｂ）参照）。図１０（ｂ）に示すように、リード１０３の先端面の剪断面１０３ｆにメッキ被膜が形成されている場合には剪断面１０３ｆにも半田フィレット１０７が形成される。   When a semiconductor device having an SON package structure is mounted on the mounting substrate 105 and the lead 103 and the electrode (not shown) of the mounting substrate 105 are soldered, the solder fillet 107 is formed on the lower surface 103b and the side surface including the stepped portion 103c of the lead 103. It is formed (see FIGS. 10A and 10B). As shown in FIG. 10B, when a plating film is formed on the shearing surface 103f of the tip surface of the lead 103, the solder fillet 107 is also formed on the shearing surface 103f.

図１１（ａ）に、別の従来例に係るＳＯＮパッケージ構造の半導体装置において、リードフレームの切断工程前の半導体装置の模式的平面図を示す。また、図１１（ｂ）に、同ＳＯＮパッケージ構造の半導体装置において、リードカット工程後の個片分離された半導体装置の模式的平面図を示す。   FIG. 11A is a schematic plan view of a semiconductor device before a lead frame cutting step in a SON package structure semiconductor device according to another conventional example. FIG. 11B is a schematic plan view of the separated semiconductor device after the lead cut process in the semiconductor device having the SON package structure.

半導体装置２００は、封止樹脂２０１、リードフレーム２０２を備える。リードフレーム２０２には、タイバー２０４が設けられている。外装メッキ処理を施すと、タイバー２０４側面部にメッキ皮膜が形成される。その後、タイバー２０４側面部がリード２０３の先端となる様にリードフレーム２０２を切断することにより、図１１（ｂ）に示すような半導体装置を得る。タイバー２０４側面をリード先端面とすることにより、リード先端面に外装メッキを施すことが可能となる。   The semiconductor device 200 includes a sealing resin 201 and a lead frame 202. The lead frame 202 is provided with a tie bar 204. When the exterior plating process is performed, a plating film is formed on the side surface portion of the tie bar 204. Thereafter, the lead frame 202 is cut so that the side surface of the tie bar 204 becomes the tip of the lead 203, thereby obtaining a semiconductor device as shown in FIG. By using the side surface of the tie bar 204 as the lead tip surface, it is possible to apply exterior plating to the lead tip surface.

特開２００５−２０９９９９号公報 第１図、第２図JP, 2005-209999, A FIG. 1 and FIG.

上記特許文献１の方法においては、前述したように、リード１０３の先端部を上方に折り曲げるので、リード１０３先端部に段差部（くびれ部）が形成されている。このため、当該段差部（くびれ部）のリード強度が低下するという問題があった。これに対し、段差をなくすためにリードカットを段差部端面で実施した場合には、パンチがメッキ付着されたリード先端部に接触し、メッキが剥離したり、メッキ屑が発生したりするという問題が生じる。   In the method of Patent Document 1, as described above, the tip portion of the lead 103 is bent upward, so that a step portion (neck portion) is formed at the tip portion of the lead 103. For this reason, there is a problem that the lead strength of the stepped portion (constricted portion) is lowered. On the other hand, when lead cutting is performed on the end face of the step portion to eliminate the step, the punch comes into contact with the lead tip portion where the plating is adhered, and the plating peels off or plating scraps are generated. Occurs.

図１１に示した従来例においては、封止樹脂から突出するリードの長さが短い場合（例えば、リードの長さが０．２ｍｍ程度）に適用することは困難であった。これは、小型化に伴ってタイバー２０４自体を設けることが困難になるためである。   The conventional example shown in FIG. 11 is difficult to apply when the length of the lead protruding from the sealing resin is short (for example, the length of the lead is about 0.2 mm). This is because it becomes difficult to provide the tie bar 204 itself as the size is reduced.

このため、封止樹脂から突出するリードの長さが０．２ｍｍ程度の半導体装置を製造する場合には、図１２の模式的平面図に示すようなリードフレーム３０２を用いて、外装メッキ処理を行った後に、リードカットを行っていた。すなわち、タイバーが設けられていないリードフレーム３０２を用いて外装メッキ処理を行った後に、封止樹脂３０１から突出するリードの長さが所望の長さとなる位置（図１２の例においては０．２ｍｍ）でリードカットを行っていた。しかしながら、この方法によれば、リード先端面の剪断面のみにメッキが付着し、破断面にはメッキが付着しない。また、剪断面の領域は、パンチと金型ダイのクリアランスやリードカットのショット数によるパンチの汚れ具合や摩耗量によって変化する。このため、安定したメッキ付着部を確保する事が困難であった。   For this reason, when manufacturing a semiconductor device in which the length of the lead protruding from the sealing resin is about 0.2 mm, an exterior plating process is performed using a lead frame 302 as shown in the schematic plan view of FIG. After performing the lead cutting. That is, after the exterior plating process is performed using the lead frame 302 not provided with a tie bar, the lead protruding from the sealing resin 301 has a desired length (0.2 mm in the example of FIG. 12). ) Lead cutting. However, according to this method, plating adheres only to the shearing surface of the lead tip surface, and no plating adheres to the fracture surface. In addition, the area of the shearing surface changes depending on the punch dirt and the amount of wear due to the clearance between the punch and the die and the number of shots of the lead cut. For this reason, it was difficult to ensure a stable plating adhesion portion.

本発明に係る半導体装置の製造方法は、リードカット工程後にリードフレームからリード先端にメッキ電流が流れるように、あらかじめ、前記リード間、又は／及び前記リードとタブ間に仮結線を形成し、前記仮結線を形成後に、モールド成形を行い、前記リードカットを実施し、前記リードに外装メッキを施し、前記仮結線を分断するものである。   In the semiconductor device manufacturing method according to the present invention, a temporary connection is formed in advance between the leads or / and between the lead and the tab so that a plating current flows from the lead frame to the lead tip after the lead cutting step, After forming the temporary connection, molding is performed, the lead cut is performed, exterior plating is applied to the lead, and the temporary connection is divided.

本発明に係る半導体装置の製造方法によれば、仮結線を形成することにより、リードカット工程後にリードフレームからリード先端にメッキ電流が流れるようにすることができる。このため、封止樹脂から突出するリード長さに関わらず、封止樹脂から突出するリードにメッキを施すことができる。   According to the method for manufacturing a semiconductor device of the present invention, by forming a temporary connection, it is possible to cause a plating current to flow from the lead frame to the tip of the lead after the lead cutting process. For this reason, the lead protruding from the sealing resin can be plated regardless of the length of the lead protruding from the sealing resin.

本発明に係る第１の態様の半導体装置は、上記半導体装置の製造方法により製造されたものである。   A semiconductor device according to a first aspect of the present invention is manufactured by the above-described method for manufacturing a semiconductor device.

本発明に係る第２の態様の半導体装置は、半導体素子と、前記半導体素子が封止されたモールド手段と、前記モールド手段から突出するリードと、前記モールド手段によって封止された内部に配設され、前記突出するリードに外装メッキを施す際にメッキ電流を流す役割を担った後に分断された仮結線とを備え、前記突出するリードのうちの少なくとも一部のリードは、全面が外装メッキされているものである。   According to a second aspect of the present invention, there is provided a semiconductor device including a semiconductor element, a molding unit in which the semiconductor element is sealed, a lead protruding from the molding unit, and an interior sealed by the molding unit. And at least some of the protruding leads are externally plated. It is what.

本発明に係る電子機器は、前記第１又は第２の態様の半導体装置のモールド手段から突出するリードと、電子部品の電極が導電性部材を介して接続されているものである。   In the electronic apparatus according to the present invention, the lead protruding from the molding means of the semiconductor device of the first or second aspect and the electrode of the electronic component are connected via a conductive member.

本発明によれば、モールド手段から突出するリードの長さに関わらず、モールド手段から突出するリードの全面に外装メッキ処理を施すことが可能な半導体装置を提供することができるという優れた効果を有する。   According to the present invention, it is possible to provide a semiconductor device capable of providing a semiconductor device capable of performing an exterior plating process on the entire surface of a lead protruding from a molding unit regardless of the length of the lead protruding from the molding unit. Have.

実施形態に係る半導体装置の模式的透視平面図。1 is a schematic perspective plan view of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造方法を説明するためのフローチャート図。FIG. 4 is a flowchart for explaining a method for manufacturing a semiconductor device according to the embodiment. 実施形態に係る半導体装置の製造工程を説明するための模式的透視平面図。1 is a schematic perspective plan view for explaining a manufacturing process of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造工程を説明するための模式的透視平面図。1 is a schematic perspective plan view for explaining a manufacturing process of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造工程を説明するための模式的透視平面図。1 is a schematic perspective plan view for explaining a manufacturing process of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造工程を説明するための模式的透視平面図。1 is a schematic perspective plan view for explaining a manufacturing process of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造工程を説明するための模式的透視平面図。1 is a schematic perspective plan view for explaining a manufacturing process of a semiconductor device according to an embodiment. 実施形態に係る半導体装置を実装基板に実装した状態のリード部分の断面図。Sectional drawing of the lead part of the state which mounted the semiconductor device which concerns on embodiment on the mounting board | substrate. （ａ）特許文献１に記載の半導体装置の平面図。（ｂ）図９（ａ）のＡ方向から見た側面図。（ｃ）図９（ａ）のＢ方向から見た側面図。（ｄ）同下面図。（ｅ）図９（ｂ）の破断線で囲まれた部分の拡大図。(A) The top view of the semiconductor device of patent document 1. FIG. (B) The side view seen from the A direction of Fig.9 (a). (C) The side view seen from the B direction of Fig.9 (a). (D) The bottom view. (E) The enlarged view of the part enclosed by the broken line of FIG.9 (b). （ａ）（ｂ）特許文献１に記載の半導体装置を実装基板に実装した状態のリード部分の断面図。(A) (b) Sectional drawing of the lead part of the state which mounted the semiconductor device of patent document 1 in the mounting board | substrate. （ａ）従来技術に係る半導体装置のリードフレーム切断工程前の模式的平面図。（ｂ）従来技術に係る半導体装置のリードフレーム切断工程後の模式的平面図。(A) The typical top view before the lead frame cutting process of the semiconductor device which concerns on a prior art. (B) The typical top view after the lead frame cutting process of the semiconductor device which concerns on a prior art. 別の従来技術に係る半導体装置のリードフレームの切断工程前の模式的平面図。The typical top view before the cutting process of the lead frame of the semiconductor device concerning another conventional technology.

以下、本発明を適用した実施形態の一例について説明する。なお、本発明の趣旨に合致する限り、他の実施形態も本発明の範疇に属し得ることは言うまでもない。また、以降の図における各部材のサイズや比率は、説明の便宜上のものであり、実際のものとは異なる。   Hereinafter, an example of an embodiment to which the present invention is applied will be described. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention. Moreover, the size and ratio of each member in the following drawings are for convenience of explanation, and are different from actual ones.

図１に、本実施形態に係るＳＯＮパッケージ構造の半導体装置の装置構成の一例を説明するための模式的透視平面図を示す。説明の便宜上、封止樹脂５を透視した図とする。半導体装置５０は、半導体素子１、ワイヤボンディング２、ダミーボンディング細線として機能する仮結線３Ａ，３Ｂ、クリップ４、封止樹脂５を備える。   FIG. 1 is a schematic perspective plan view for explaining an example of a device configuration of a semiconductor device having a SON package structure according to the present embodiment. For convenience of explanation, it is assumed that the sealing resin 5 is seen through. The semiconductor device 50 includes a semiconductor element 1, wire bonding 2, temporary connections 3 </ b> A and 3 </ b> B that function as dummy bonding thin wires, a clip 4, and a sealing resin 5.

また、半導体装置５０は、リードとして、第１リード１１、第２リード１２、第３リード１３、第４リード１４、第５リード１５、第６リード１６、第７リード１７、第８リード１８を具備する。さらに、半導体装置５０は、半導体素子１が載置されるタブ２０、タブ２０と接続される吊りピン１９を備える。   In addition, the semiconductor device 50 includes the first lead 11, the second lead 12, the third lead 13, the fourth lead 14, the fifth lead 15, the sixth lead 16, the seventh lead 17, and the eighth lead 18 as leads. It has. The semiconductor device 50 further includes a tab 20 on which the semiconductor element 1 is placed and a suspension pin 19 connected to the tab 20.

第１リード１１〜第４リード１４は、タブ２０と一体的に形成され、第５リード１５〜第８リード１８は、タブ２０と別体に形成されている。第５リード１５〜第８リード１８のうちの、第５リード１５〜第７リード１７は、互いに電気的に接続されるように封止樹脂５内において一体的に形成されている。一方、第８リード１８は、他のリード及びタブ２０と別体に形成されている。言い換えると、第８リード１８は、他のリード及びタブ２０と電気的に絶縁されている。   The first lead 11 to the fourth lead 14 are formed integrally with the tab 20, and the fifth lead 15 to the eighth lead 18 are formed separately from the tab 20. Of the fifth lead 15 to the eighth lead 18, the fifth lead 15 to the seventh lead 17 are integrally formed in the sealing resin 5 so as to be electrically connected to each other. On the other hand, the eighth lead 18 is formed separately from the other leads and tabs 20. In other words, the eighth lead 18 is electrically insulated from other leads and the tab 20.

半導体素子１は、例えば、半導体チップであり、図１中の紙面表面側に素子形成面が形成されている。半導体素子１の素子形成面の反対側の裏面側は、導電性接着材（不図示）を介してタブ２０に固設されている。   The semiconductor element 1 is, for example, a semiconductor chip, and an element formation surface is formed on the surface side of the paper surface in FIG. The back surface side opposite to the element formation surface of the semiconductor element 1 is fixed to the tab 20 via a conductive adhesive (not shown).

ワイヤボンディング２は、半導体素子１の表面に形成されたパッド（不図示）と、第８リード１８を接続するように、これらの間に配設されている。ワイヤボンディング２の材料としては、特に限定されるものではないが、好適な材料として、Ａｕ線、Ａｌ線、Ｃｕ線、低融点半田ワイヤなどの金属細線を挙げることができる。   The wire bonding 2 is disposed between the pads (not shown) formed on the surface of the semiconductor element 1 and the eighth lead 18 so as to connect them. The material for the wire bonding 2 is not particularly limited, but examples of suitable materials include fine metal wires such as Au wires, Al wires, Cu wires, and low melting point solder wires.

仮結線３Ａは、第８リード１８と第７リード１７の間に形成されている。但し、図１に示すように、仮結線３Ａは、第８リード１８と第７リード１７間において、分断されている。従って、第８リード１８と第５リード１５〜第７リード１７とは、電気的に絶縁状態となっている。   The temporary connection 3 </ b> A is formed between the eighth lead 18 and the seventh lead 17. However, as shown in FIG. 1, the temporary connection 3 </ b> A is divided between the eighth lead 18 and the seventh lead 17. Therefore, the eighth lead 18 and the fifth lead 15 to the seventh lead 17 are electrically insulated.

仮結線３Ｂは、第５リード１５とタブ２０の間に形成されている。但し、図１に示すように、仮結線３Ｂは、第５リード１５とタブ２０の間において、分断されている。従って、第５リード１５〜第７リード１７とタブ２０とは、電気的に絶縁状態となっている。   The temporary connection 3 </ b> B is formed between the fifth lead 15 and the tab 20. However, as shown in FIG. 1, the temporary connection 3 </ b> B is divided between the fifth lead 15 and the tab 20. Accordingly, the fifth lead 15 to the seventh lead 17 and the tab 20 are electrically insulated.

仮結線３Ａ、３Ｂの材料としては、特に限定されるものではないが、好適な材料として、ワイヤボンディング２と同様のＡｕ線、Ａｌ線、Ｃｕ線、低融点半田ワイヤなどの金属細線を挙げることができる。仮結線３Ａ、３Ｂの上述の分断のための手段は、特に限定されるものではないが、溶断により切断することが好ましい。   The material of the temporary connections 3A and 3B is not particularly limited, but examples of suitable materials include fine metal wires such as Au wire, Al wire, Cu wire, and low melting point solder wire similar to the wire bonding 2. Can do. The means for dividing the temporary connections 3A and 3B described above is not particularly limited, but is preferably cut by fusing.

クリップ４は、半導体素子１の素子形成面と第５リード１５〜第７リード１７を電気的に接続するように形成されている。   The clip 4 is formed so as to electrically connect the element formation surface of the semiconductor element 1 and the fifth lead 15 to the seventh lead 17.

封止樹脂５は、モールド手段であり、ＳＯＮパッケージ構造となるようにモールド成形されている。具体的には、封止樹脂５より、第１リード１１〜第８リード１８の先端部が突出するように形成されている。   The sealing resin 5 is a molding means and is molded so as to have a SON package structure. Specifically, the first lead 11 to the eighth lead 18 are formed so as to protrude from the sealing resin 5.

第１リード１１〜第８リード１８は、封止樹脂５からの突出部の全面に外装メッキが施されている。本実施形態においては、第８リード１８がゲート電極として機能し、第５リード１５〜第７リード１７がソース電極として機能する。   The first lead 11 to the eighth lead 18 are externally plated on the entire surface of the protruding portion from the sealing resin 5. In the present embodiment, the eighth lead 18 functions as a gate electrode, and the fifth lead 15 to the seventh lead 17 function as source electrodes.

次に、本実施形態に係る半導体装置の製造方法を、図２のフローチャート図、及び図３〜７の製造工程図を用いつつ説明する。   Next, the manufacturing method of the semiconductor device according to the present embodiment will be described with reference to the flowchart of FIG. 2 and the manufacturing process diagrams of FIGS.

ステップＳ１において、前述した金属細線等によりダミーボンディング細線である仮結線３Ａ、３Ｂをリードフレーム１０上に形成する（図３参照）。具体的には、リードフレーム１０のうちの第８リード１８と、第７リード１７とを互いに接続するように、仮結線３Ａを形成する。また、リードフレーム１０のうちの第５リード１５とタブ２０を互いに接続するように、仮結線３Ｂを形成する。   In step S1, temporary wires 3A and 3B, which are dummy bonding thin wires, are formed on the lead frame 10 using the above-described metal thin wires or the like (see FIG. 3). Specifically, the temporary connection 3 </ b> A is formed so that the eighth lead 18 and the seventh lead 17 of the lead frame 10 are connected to each other. Further, the temporary connection 3B is formed so that the fifth lead 15 and the tab 20 of the lead frame 10 are connected to each other.

ステップＳ２において、タブ２０上に導電性接着剤を塗布して半導体素子１をダイボンディングする（図４参照）。   In step S2, a conductive adhesive is applied on the tab 20, and the semiconductor element 1 is die-bonded (see FIG. 4).

ステップＳ３において、半導体素子１の表面（素子形成面）のパッド（不図示）と、ソース電極として機能する第５リード１５〜第７リード１７を電気的に接続するように、クリップ４を配設する。本実施形態においては、Ｃｕクリップを用いた。   In step S3, the clip 4 is disposed so as to electrically connect the pad (not shown) on the surface (element formation surface) of the semiconductor element 1 and the fifth lead 15 to the seventh lead 17 functioning as the source electrode. To do. In this embodiment, a Cu clip is used.

ステップＳ４において、ゲート電極として機能する第８リード１８と半導体素子１の表面のパッド（不図示）が電気的に接続するように、ワイヤボンディング２を配設する（図５参照）。本実施形態においては、ワイヤボンディング２としてＡｕ線を用いた。   In step S4, wire bonding 2 is disposed so that the eighth lead 18 functioning as a gate electrode and a pad (not shown) on the surface of the semiconductor element 1 are electrically connected (see FIG. 5). In this embodiment, Au wire is used as the wire bonding 2.

ステップＳ５において、封止樹脂５を用いてモールド成形を行う。   In step S5, molding is performed using the sealing resin 5.

ステップＳ６において、切断金型を用いて、各リードを所望の長さにカットする。これにより、図６のような構成となる。換言すると、リードカットにより、封止樹脂５から突出するリードの全面が露出する。   In step S6, each lead is cut into a desired length using a cutting die. Thereby, it becomes a structure like FIG. In other words, the entire surface of the lead protruding from the sealing resin 5 is exposed by the lead cut.

ステップＳ７において、リードフレーム１０に外装メッキを施すためにリードフレームにメッキ電流を流す。リードカットにより、リードフレーム１０の枠と別体となった第５リード１５、第６リード１６、第７リード１７、及び第８リード１８は、上述の仮結線３Ａ，３Ｂを介して、リードフレーム１０に接続されている。これにより、メッキ電流を全てのリード先端に流すことができる。その結果、封止樹脂５から突出しているリードの全面にメッキを施すことができる。   In step S7, a plating current is passed through the lead frame in order to apply exterior plating to the lead frame 10. The fifth lead 15, the sixth lead 16, the seventh lead 17, and the eighth lead 18 separated from the frame of the lead frame 10 by lead cutting are connected to the lead frame via the temporary connections 3A and 3B. 10 is connected. As a result, a plating current can be passed through all the tips of the leads. As a result, the entire surface of the lead protruding from the sealing resin 5 can be plated.

ステップＳ８において、タブ２０の図７中の左右に位置する２つの吊りピン１９を切断することにより、半導体装置を個片分離する。   In step S8, the two suspension pins 19 positioned on the left and right of the tab 20 in FIG.

ステップＳ９において、仮結線３Ａ，３Ｂの分断を行う。仮結線３Ａ，３Ｂの分断方法としては、封止樹脂５を破壊することなく分断できるものであれば特に限定されない。好適には、溶断による分断手段を挙げることができる。仮結線３Ａ、３ＢとしてＡｕ線、Ａｌ線、Ｃｕ線等を適用した場合には、仮結線３Ａ、３Ｂ間に電流を流すことにより溶断することができる。また、仮結線３Ａ、３Ｂとして低融点半田ワイヤを適用した場合、半導体装置を半田ワイヤの融点以上に加熱させることにより溶断することができる。   In step S9, the temporary connections 3A and 3B are divided. A method for dividing the temporary connections 3A and 3B is not particularly limited as long as it can be cut without destroying the sealing resin 5. Preferable examples include cutting means by fusing. When Au wire, Al wire, Cu wire or the like is applied as the temporary connection 3A, 3B, it can be melted by passing a current between the temporary connection 3A, 3B. Moreover, when a low melting point solder wire is applied as the temporary connections 3A and 3B, the semiconductor device can be blown by heating to a temperature equal to or higher than the melting point of the solder wire.

ステップＳ１０において、半導体装置を特性選別する。以上の工程を経て、図１に示すような半導体装置５０を得る。   In step S10, the semiconductor device is subjected to characteristic selection. Through the above steps, a semiconductor device 50 as shown in FIG. 1 is obtained.

なお、本実施形態においては、仮結線３のダミーボンディングをステップＳ１の工程で行う例について述べたが、ステップＳ５のモールド成形工程前であればどの段階でダミーボンディング工程を行ってもよい。例えば、ステップＳ４のワイヤボンディングと同一のタイミングでダミーボンディングを行ってもよい。同一設備で連続して行うことにより、コスト増加を最小限に抑えることができる。   In the present embodiment, the example in which the dummy bonding of the temporary connection 3 is performed in the process of step S1 has been described. However, the dummy bonding process may be performed at any stage before the molding process of step S5. For example, dummy bonding may be performed at the same timing as the wire bonding in step S4. By carrying out continuously with the same equipment, the cost increase can be minimized.

本実施形態に係る半導体装置５０は、電子機器に搭載される。具体的には、半導体装置５０において、封止樹脂５から突出するリードと、実装基板等の電子部品に形成された電極が半田フィレット等の導電性部材を介して接続されている。   The semiconductor device 50 according to this embodiment is mounted on an electronic device. Specifically, in the semiconductor device 50, a lead protruding from the sealing resin 5 and an electrode formed on an electronic component such as a mounting substrate are connected via a conductive member such as a solder fillet.

図８に、本実施形態に係る半導体装置を実装基板に実装した状態のリード部分の断面図を示す。本実施形態に係る半導体装置５０は、封止樹脂５から突出するリード全面にメッキ処理が施されているので、半田濡れ性が良好となる。すなわち、封止樹脂５から突出したリードに半田フィレット３５が良好に形成される。その結果、半導体装置５０を実装基板３０に実装する際に、実装強度が低下してしまうという問題を解決することができる。   FIG. 8 is a cross-sectional view of a lead portion in a state where the semiconductor device according to the present embodiment is mounted on a mounting substrate. In the semiconductor device 50 according to the present embodiment, the entire surface of the lead protruding from the sealing resin 5 is plated, so that the solder wettability is good. That is, the solder fillet 35 is favorably formed on the lead protruding from the sealing resin 5. As a result, it is possible to solve the problem that the mounting strength is reduced when the semiconductor device 50 is mounted on the mounting substrate 30.

上記特許文献１のような半抜き工法においては、メッキ付着状態のばらつきが大きかったが、本実施形態によれば、仮結線３Ａ，３Ｂを形成することにより、封止樹脂５から突出するリード全面に亘ってメッキを良好に付着させることができる。従って、実装基板等に実装する際に、半田濡れ性を良好に保つことができる。これにより、封止樹脂５から突出するリードにおいて、良好な半田フィレットを形成することができる。従って、リード強度が低下するという問題を解決することができる。   In the half punching method as in the above-mentioned Patent Document 1, the dispersion of the plating adhesion state was large. However, according to the present embodiment, the entire lead surface protruding from the sealing resin 5 by forming the temporary connections 3A and 3B. The plating can be satisfactorily adhered over the entire area. Therefore, when mounting on a mounting board etc., solder wettability can be kept favorable. Thereby, a good solder fillet can be formed in the lead protruding from the sealing resin 5. Therefore, the problem that the lead strength is reduced can be solved.

また、図１１に示したようなタイバーを設ける方法は、モールド手段から突出するリードの長さを短くする場合に適用することが困難であったが、本実施形態によれば、封止樹脂から突出するリード長を短くした場合においても、適用可能であるという優れた効果を有する。しかも、モールド手段から突出するリードが短い場合においても、突出するリード全面にメッキを良好に付着させることができる。従って、突出するリードが短い場合においても、基板に実装する際に良好な半田フィレットを形成することが可能となり、実装強度が低下するという問題を解決することができる。   Further, the method of providing a tie bar as shown in FIG. 11 has been difficult to apply when the length of the lead protruding from the mold means is shortened. Even when the protruding lead length is shortened, it has an excellent effect of being applicable. Moreover, even when the lead protruding from the mold means is short, the plating can be satisfactorily adhered to the entire surface of the protruding lead. Therefore, even when the protruding lead is short, it is possible to form a good solder fillet when mounting on the substrate, and the problem that the mounting strength is reduced can be solved.

なお、上記実施形態においては、ＳＯＮパッケージの例で説明したが、本発明は、ガルウイングタイプのパッケージをはじめ、リード構造を有する半導体装置全般において適用可能である。また、本実施形態においては、封止樹脂から突出するリード全てにおいて、メッキ電流を流す例を述べたが、全てのリードに対して、本発明を適用することは必須ではなく、少なくとも一部のリードにおいて、上記製造工程を適用したものも本発明の範疇に含まれる。   In the above embodiment, the example of the SON package has been described. However, the present invention can be applied to all semiconductor devices having a lead structure, including a gull-wing type package. Further, in the present embodiment, an example in which the plating current flows in all the leads protruding from the sealing resin has been described. However, it is not essential to apply the present invention to all the leads, and at least a part of them is applied. Leads to which the above manufacturing process is applied are also included in the scope of the present invention.

また、ワイヤボンディング２やクリップ４を用いた接続方法は、一例であって、他の公知の接続方法を適宜適用できることは言うまでもない。また、仮結線３Ａ，３Ｂは、一例であって、仮結線が１本、若しくは３本以上の場合にも適用可能なことは言うまでもない。半導体素子の数等についても、一例であって、複数配設したものであってもよい。   Further, the connection method using the wire bonding 2 and the clip 4 is an example, and it goes without saying that other known connection methods can be appropriately applied. Needless to say, the temporary connections 3A and 3B are only examples, and can be applied to the case where the number of temporary connections is one or three or more. The number of semiconductor elements is also an example, and a plurality of semiconductor elements may be provided.

１ 半導体素子
２ ボンディングワイヤ
３Ａ，３Ｂ 仮結線
４ グリップ
５ 封止樹脂
１０ リードフレーム
１１ 第１リード
１２ 第２リード
１３ 第３リード
１４ 第４リード
１５ 第５リード
１６ 第６リード
１７ 第７リード
１８ 第８リード
１９ 吊りピン
２０ タブ
３０ 実装基板
３５ 半田フィレット
５０ 半導体装置 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bonding wire 3A, 3B Temporary connection 4 Grip 5 Sealing resin 10 Lead frame 11 1st lead 12 2nd lead 13 3rd lead 14 4th lead 15 5th lead 16 6th lead 17 7th lead 18 1st 8 lead 19 Suspension pin 20 Tab 30 Mounting substrate 35 Solder fillet 50 Semiconductor device

Claims (7)

リードカット工程後にリードフレームからリード先端にメッキ電流が流れるように、あらかじめ、前記リード間、又は／及び前記リードとタブ間に仮結線を形成し、
前記仮結線を形成後に、モールド成形を行い、
前記リードカットを実施し、
前記リードに外装メッキを施し、
前記仮結線を分断する半導体装置の製造方法。 In order to allow a plating current to flow from the lead frame to the lead tip after the lead cutting step, a temporary connection is formed in advance between the leads or / and between the lead and the tab,
After forming the temporary connection, molding is performed,
Performing the lead cut,
The lead is subjected to exterior plating,
A method of manufacturing a semiconductor device for cutting the temporary connection. 前記仮結線の分断は、溶断により行うことを特徴とする請求項１に記載の半導体装置の製造方法。   The semiconductor device manufacturing method according to claim 1, wherein the temporary connection is divided by fusing. 前記溶断は、電流を流す、若しくは加熱により行うことを特徴とする請求項２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 2, wherein the fusing is performed by applying a current or heating. 請求項１〜３のいずれか１項に記載の半導体装置の製造方法により製造した半導体装置。   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. 半導体素子と、
前記半導体素子が封止されたモールド手段と、
前記モールド手段から突出するリードと、
前記モールド手段によって封止された内部に配設され、前記突出するリードに外装メッキを施す際にメッキ電流を流す役割を担った後に分断された仮結線と
を備え、
前記突出するリードのうちの少なくとも一部のリードは、全面が外装メッキされている半導体装置。 A semiconductor element;
Mold means in which the semiconductor element is sealed;
A lead protruding from the mold means;
A provisional connection that is disposed inside the sealed by the mold means and divided after the role of flowing a plating current when performing exterior plating on the protruding leads;
A semiconductor device in which at least some of the protruding leads are externally plated. 前記突出するリードの全てにおいて、全面に外装メッキが施されていることを特徴とする請求項５に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein all of the protruding leads are subjected to exterior plating. 請求項４〜６のいずれか１項に記載の半導体装置のモールド手段から突出するリードと、電子部品の電極が導電性部材を介して接続されている電子機器。   An electronic device in which a lead protruding from the molding means of the semiconductor device according to claim 4 and an electrode of an electronic component are connected via a conductive member.
JP2009072034A 2009-03-24 2009-03-24 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE Pending JP2010225892A (en)

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JP2014174170A (en) * 2013-03-08 2014-09-22 Melexis Technologies Nv Current sensor
JP2016167532A (en) * 2015-03-10 2016-09-15 新日本無線株式会社 Lead frame and manufacturing method of semiconductor device using the same
US10177282B2 (en) 2015-12-09 2019-01-08 Nichia Corporation Method for manufacturing package, method for manufacturing light emitting device, package, and light emitting device
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JP2014174170A (en) * 2013-03-08 2014-09-22 Melexis Technologies Nv Current sensor
US9529013B2 (en) 2013-03-08 2016-12-27 Melexis Technologies Nv Current sensor
JP2016167532A (en) * 2015-03-10 2016-09-15 新日本無線株式会社 Lead frame and manufacturing method of semiconductor device using the same
US10177282B2 (en) 2015-12-09 2019-01-08 Nichia Corporation Method for manufacturing package, method for manufacturing light emitting device, package, and light emitting device
US10847683B2 (en) 2015-12-09 2020-11-24 Nichia Corporation Package and light emitting device
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