JP2010226892A - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous rectifying switching regulator which suppresses the occurrence of ripples of an output voltage to operate stably when a duty ratio is small. <P>SOLUTION: The synchronous rectifying switching regulator includes a high-side transistor 10 and a low-side transistor 20 connected in series between an input terminal (VIN) to which an input voltage is applied and a ground terminal (PGND), a control circuit 30 which controls the length of a period of keeping the high-side transistor 10 in a state of conduction in one cycle to reduce a difference between an output voltage V<SB>OUT</SB>obtained by smoothing a switching voltage V<SB>SW</SB>of a connection point CP between the high-side transistor 10 and the low-side transistor 20 and a target voltage, and a setting circuit 40 which, at the timing when the control circuit 30 controls the high-side transistor 10 in the conduction state, keeps the low-side transistor 20 in a nonconduction state during a cycle in which the high-side transistor 10 does not switch from the nonconduction state to the conduction state. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a switching regulator, and more particularly to a synchronous rectification switching regulator.

  A synchronous rectification switching regulator is used that uses a switching transistor as a rectifying element and converts an input voltage into a predetermined target voltage. The synchronous rectification switching regulator converts the input voltage by adjusting the ratio of the conduction (on) and non-conduction (off) periods of the switching transistor in one cycle by pulse width modulation (PWM) control, etc. To output a constant voltage. When the output voltage of the switching regulator is low, such as during startup, the duty ratio in the conductive state is set high, and the duty ratio in the non-conductive state is set low.

  When the duty ratio is small, a cycle in which a pulse signal with a small pulse width is not generated may occur due to a restriction on the minimum pulse width that can be generated inside the switching regulator. As a result, the operating frequency of the switching regulator is lower than the frequency at which it is intended to operate. In this case, the ripple generated in the output voltage increases as the operating frequency decreases.

  For this reason, the synchronous rectification transistor connected in series with the switching transistor used as the rectifier element is made non-conductive to prevent an increase in ripple current due to the smoothing inductor connected to the output terminal, and the ripple generated in the output voltage. There has been proposed a method for suppressing the increase (see, for example, Patent Document 1).

Japanese Patent No. 3957019

  However, in the method proposed above, the synchronous rectification transistor is always in a non-conductive state for a certain period of time when the output voltage is low, such as at the time of startup. For this reason, at the time of switching from the control for always turning off the synchronous rectification transistor to the normal synchronous rectification control, the synchronous rectification transistor that has been in the non-conduction state for several cycles is suddenly turned on and the output voltage greatly fluctuates. As a result, there is a problem that the operation becomes unstable due to a large ripple in the output voltage.

  In view of the above problems, an object of the present invention is to provide a synchronous rectification type switching regulator that can stably operate with a ripple ratio of an output voltage suppressed when a duty ratio is small.

  According to one aspect of the present invention, there is provided a switching regulator that converts an input voltage to a target voltage by a synchronous rectification method, and (a) a high-side transistor connected in series between an input terminal to which the input voltage is applied and a ground terminal And (b) the high-side transistor in one cycle so that the difference between the output voltage obtained by smoothing the switching voltage at the connection point between the high-side transistor and the low-side transistor and the target voltage is small. And (c) during a cycle in which the high-side transistor does not switch from the non-conductive state to the conductive state at the timing when the control circuit controls the high-side transistor to the conductive state. A switching regulator is provided that includes a setting circuit that maintains the low-side transistor in a non-conductive state.

  ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of the ripple of an output voltage is suppressed when a duty ratio is small, and the synchronous rectification system switching regulator which operate | moves stably can be provided.

It is a typical block diagram which shows the structure of the switching regulator which concerns on embodiment of this invention. It is a table | surface which shows the information of the input / output terminal of the switching regulator which concerns on embodiment of this invention. It is a timing chart for demonstrating operation | movement of the switching regulator which concerns on embodiment of this invention. It is a timing chart for demonstrating operation | movement in case the pulse signal is output normally of the switching regulator which concerns on embodiment of this invention. 6 is a timing chart for explaining an operation when a pulse signal is not normally output in the switching regulator according to the embodiment of the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. The embodiments of the present invention have the following circuit configuration, arrangement, etc. It is not something specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

A switching regulator 1 according to an embodiment of the present invention is a switching regulator that converts an input voltage into a target voltage by a synchronous rectification method. As shown in FIG. 1, the switching regulator 1 includes a high-side transistor 10 and a low-side transistor 20 connected in series between an input terminal (VIN) to which an input voltage is applied and a ground terminal (PGND), and a high-side transistor 10. The high-side transistor 10 in one cycle is in a conductive state so that the difference between the output voltage V _OUT obtained by smoothing the switching voltage V _SW at the connection point CP between the low-side transistor 20 and the target voltage becomes small. The control circuit 30 that controls the length of the period, and the low-side transistor 20 during a cycle in which the high-side transistor 10 is not switched from the non-conducting state to the conducting state at the timing when the control circuit 30 controls the high-side transistor 10 to be in a conducting state. Is set to a non-conducting state.

As described above, the synchronous rectification switching regulator 1 adjusts the ratio of the high-side transistor 10 conduction state and non-conduction state period in one cycle by PWM control, converts the input voltage, and outputs the output voltage. This is a synchronous rectification switching regulator that outputs V _OUT . FIG. 2 shows the terminal numbers, terminal names, and functions of the input / output terminals of the switching regulator 1 shown in FIG.

The high-side transistor 10 is a switching transistor used as a rectifying element, and the low-side transistor 20 is a synchronous rectifying transistor that suppresses an increase in ripple generated in the output voltage. In normal synchronous rectification control, the low-side transistor 20 is in a non-conductive state while the high-side transistor 10 is in a conductive state. As already described, by arranging the low-side transistor 20, an increase in ripple generated in the output voltage V _OUT is suppressed.

  In the example shown in FIG. 1, the high-side transistor 10 and the low-side transistor 20 are N-channel field effect transistors (FETs). The source terminal of the high-side transistor 10 is connected to the VIN terminal, and the drain terminal is connected to the connection point CP. The gate terminal of the high-side transistor 10 is connected to the output terminal of the amplifier 11 that amplifies the switching signal Vg1 output from the control circuit 30. The source terminal of the low-side transistor 20 is connected to the connection point CP, and the drain terminal is connected to the PGND terminal. The gate terminal of the low-side transistor 20 is connected to the output terminal of the amplifier 21 that amplifies the switching signal Vg2 output from the setting circuit 40.

The switching voltage V _SW generated at the connection point CP between the high-side transistor 10 and the low-side transistor 20 is smoothed by the smoothing circuit 110 connected to the SW terminals (3, 4), and the output voltage V _OUT is output. . The smoothing circuit 110 includes a smoothing inductor L1 and a smoothing capacitor C1. One terminal of the smoothing inductor L1 is connected to the SW terminal, and the smoothing capacitor C1 is connected between the other terminal of the smoothing inductor L1 and GND.

The control circuit 30 illustrated in FIG. 1 includes a reset circuit 31, an oscillation circuit 32, and a switching circuit 33. Reset circuit 31, the switching voltage V _SW is, when it reaches the error voltage V _ERR which is set from the difference between the output voltage V _OUT and the target voltage obtained by smoothing the switching voltage V _SW, a high-side transistor 10 A reset signal RST for turning off is output. The target voltage is a target value of the output voltage V _OUT that the switching regulator 1 is to output. The oscillation circuit 32 outputs a set signal SET for turning on the high-side transistor 10 at a constant period. One cycle of PWM control is defined by a period in which the oscillation circuit 32 outputs the set signal SET. The switching circuit 33 receives the reset signal RST and the set signal SET, and outputs a switching signal Vg1 for switching the high-side transistor 10 between the conductive state and the non-conductive state.

The control circuit 30 further includes a slope generation circuit 34 that outputs a slope signal V _SL to the reset circuit 31. As will be described later, the slope generation circuit 34 outputs the slope signal V _SL while the high-side transistor 10 is in a conductive state.

The reset circuit 31 includes a multiplexing circuit 311 and a comparator 312. The multiplexing circuit 311 monitors the current I _L flowing through the connection point CP, converts the current I _L into a voltage, and multiplexes it with the slope signal V _SL generated by the slope generation circuit 34. The combined voltage V _T after combining is input to the non-inverting input terminal of the comparator 312. The error voltage V _ERR output from the error amplifier 50 is input to the inverting input terminal of the comparator 312. Error voltage V _ERR, as will be described later, a voltage obtained by feeding back the output voltage V _OUT, the output voltage V _OUT is a voltage obtained by amplifying the difference between the voltage of the set reference so that the target value. That is, the error voltage V _ERR corresponds to the difference between the value of the output voltage V _OUT that is actually output and the target value of the output voltage V _OUT. When combined voltage V _T obtained with the current I _L flowing through the connection point CP becomes larger than the error voltage V _ERR, the reset signal RST which is the output of the comparator 312 becomes a high level.

  The switching circuit 33 of the reset circuit 31 shown in FIG. 1 is a flip-flop. The reset signal RST output from the reset circuit 31 is input to the reset terminal of the switching circuit 33. On the other hand, the set signal SET output from the oscillation circuit 32 is input to the set terminal of the switching circuit 33. The output signal of the switching circuit 33 is amplified by the amplifier 11 and input to the control terminal (gate terminal) of the high-side transistor 10 as the switching signal Vg1. For this reason, when the set signal SET becomes a high level, the high-side transistor 10 becomes conductive (ON). When the reset signal RST goes high after the set signal SET goes low, the high-side transistor 10 is turned off (off).

FIG. 3 shows a timing chart for explaining the operation of the control circuit 30. As shown in FIG. 3, when the oscillation circuit 32 outputs the set signal SET, the switching signal Vg1 becomes high level. At this time, the high-side transistor 10 is conductive, current I _L flowing through the connection point CP is gradually increased.

Further, the slope signal V _SL output from the slope generation circuit 34 gradually increases from 0 V during a period in which the high-side transistor 10 is in a conductive state after the set signal SET is input to the slope generation circuit 34. When the combined voltage V _T increases and becomes larger than the error voltage V _ERR , the reset signal RST becomes high level.

When the reset signal RST becomes high level, the switching signal Vg1 becomes low level. At this time, the high-side transistor 10 is rendered non-conductive, current I _L flowing through the connection point CP is reduced gradually. Further, the slope signal V _SL becomes 0V.

As described above, the reset circuit 31 operates in the same manner as the peak current detection circuit that detects the maximum current. That is, the current I _L flowing from the VIN terminal to the SW terminal is monitored, and when the current I _L increases and the peak value exceeds the reference value corresponding to the error voltage V _ERR , the reset signal RST becomes high level, and the current I L _L decreases. Thus, the switching regulator 1 employs a current control method using a peak current detection circuit. Further, by superimposing the slope signal V _SL to the voltage converted from the current I _L, the peak of the current I _L in the current even if the oscillation occurs I _L can be detected accurately.

The error amplifier 50 amplifies the difference between the reference voltage V _REF and the feedback voltage V _{FB obtained} by resistance division by feeding back the output voltage V _OUT of the switching regulator 1. The reference voltage V _REF is set according to the target value of the output voltage V _OUT . For example, when the target value of the output voltage V _OUT is 3.3V, the reference voltage V _REF is set to 0.8V. Then, the resistance division ratio is set so that the feedback voltage V _FB becomes 0.8 V when the output voltage V _OUT is 3.3 V.

However, when the switching regulator 1 is started, the error amplifier 50 determines the difference between the feedback voltage V _FB and the soft start voltage V _SS until the soft start voltage V _SS that gradually increases from 0 V reaches the reference voltage V _REF. Amplify.

Specifically, the feedback voltage V _FB obtained by dividing the output voltage V _OUT by the resistor R _FB1 and the resistor R _FB2 is input from the FB terminal (11) to the inverting input terminal of the error amplifier 50. The soft start voltage V _SS output from the soft start circuit 60 to the error amplifier 50 is input to one non-inverting input terminal of the error amplifier 50. The reference voltage V _REF is input to the other non-inverting input terminal of the error amplifier 50. Then, the lower input voltage of the lower one of the reference voltage V _REF and the soft start voltage V _SS is compared with the feedback voltage V _FB , and the error voltage V _ERR that is the output of the error amplifier 50 is determined. When the feedback voltage V _FB is lower than the low input voltage, the error voltage V _ERR becomes high level, and when the feedback voltage V _FB is higher than the low input voltage, the error voltage V _ERR becomes low level.

Since the error voltage V _ERR is set by comparing the low input voltage selected from the reference voltage V _REF and the soft start voltage V _SS and the feedback voltage V _FB , the conduction of the high-side transistor 10 when the switching regulator 1 is started up. The period of the state becomes gradually longer, and a soft start in which the output voltage V _OUT gradually increases can be realized. An excessive inrush current may flow through the high-side transistor 10 and the smoothing inductor L1 due to the long conductive state of the high-side transistor 10 at the time of start-up. However, an excessive inrush current flows through the soft start. Can be prevented.

The soft start voltage V _SS output from the soft start circuit 60 to the error amplifier 50 is given by the terminal voltage of the soft start adjustment capacitor C _SS connected to the SS / DELAY terminal (9). When starting the switching regulator 1, the terminal voltage of the soft-start adjusting capacitor C _SS which has been charged in advance is gradually increased with a constant slope.

  The switching regulator 1 shown in FIG. 1 further includes an off latch time setting circuit 70 and an enable circuit 80. The off latch time setting circuit 70 stops the operation of the switching regulator 1 when the abnormal operation of the switching regulator 1 continues for a certain time or more. For example, when an overcurrent or voltage abnormality occurs in the switching regulator 1, the capacitor Cp connected to the PSET terminal (14) is charged. When an abnormality in the switching regulator 1 continues for a certain time and the terminal voltage of the capacitor Cp exceeds a certain value, the off latch time setting circuit 70 stops the operation of the switching regulator 1. The enable circuit 80 controls the start / stop of the switching regulator 1 by a control signal input from the outside via the EN terminal (15).

As described above, the switching regulator 1 shown in FIG. 1 controls the conduction state and non-conduction state of the high-side transistor by PWM control using the set signal SET and the reset signal RST, and the input voltage is set to a desired target. Converts to a value output voltage V _OUT . However, when the duty ratio is small, a cycle in which a pulse signal with a small pulse width is not generated may occur due to a restriction on the minimum pulse width that can be generated inside the switching regulator 1.

  For example, a signal delay is caused by an inverter circuit or the like included in a path until the reset signal RST output from the reset circuit 31 is transmitted to the high-side transistor 10, and as a result, the pulse width of the pulse signal propagating through this path is reduced. May be subject to minimum pulse width limitation. For example, when it is desired to output a pulse width of 100 ns but the minimum pulse width that can be generated inside the switching regulator 1 is 200 ns, no pulse signal is output. In the next cycle, a pulse signal having a pulse width longer than necessary may be output. In particular, when the duty ratio at the start-up of the switching regulator 1 is small, a problem that the pulse signal is not normally output tends to occur.

FIG. 4 shows waveform examples of the switching voltage V _SW , the current I _L, and the output voltage V _OUT when operating normally. As shown in FIG. 4, when the set signal SET becomes high level, the switching voltage V _SW becomes high level, and when the reset signal RST becomes high level, the switching voltage V _SW becomes low level. While the switching voltage V _SW is at a high level, the current _IL gradually increases and the output voltage V _OUT rises. While the switching voltage V _SW is at a low level, the current _IL gradually decreases and the output voltage V _OUT decreases.

  On the other hand, FIG. 5 shows an operation example in which the pulse signal is not normally output because the pulse width is narrower than the minimum pulse width. FIG. 5 shows that since the pulse signal necessary for normal operation is not generated inside the switching regulator 1, the reset signal RST that has become high level in the cycle t1 does not return to low level in the cycle t1, but low level in the cycle t2. An example to become. For this reason, even if the set signal SET becomes a high level in the cycle t2 and the control circuit 30 tries to make the high-side transistor 10 conductive, the high-side transistor 10 does not become conductive.

At this time, in the switching regulator 1 shown in FIG. 1, when the setting circuit 40 detects that both the set signal SET and the reset signal RST are at the high level, the low-side transistor 20 is turned off during the cycle t2. maintain. For this reason, both the high-side transistor 10 and the low-side transistor 20 are turned off, and the switching voltage V _SW does not become high level. The pulse waveform of the switching voltage V _SW indicated by the broken line in FIG. 5 is the waveform of the switching voltage V _SW when the pulse signal is normally output.

  After the reset signal RST returns to the low level, the set signal SET is at the low level at the timing when the reset signal RST becomes the high level in the cycle t3. For this reason, in the cycle t3, the setting circuit 40 does not maintain the low-side transistor 20 in the non-conductive state, and when the high-side transistor 10 is in the non-conductive state, the low-side transistor 20 is in the conductive state.

As shown in FIG. 5, both the high-side transistor 10 and the low-side transistor 20 are turned off in the cycle t2 when the switching voltage V _SW does not go to the high level, and the connection point CP enters the high impedance state. For this reason, in the cycle t2, the current I _L does not decrease and the output voltage V _OUT does not fluctuate. Therefore, in the next cycle t3, the time for the combined voltage V _T to reach the error voltage V _ERR is not particularly long, and the duty ratio in which the high-side transistor 10 is conductive is the same as in other cycles. .

If If the low-side transistor 20 in cycle t2 becomes conductive, as shown by a broken line in FIG. 5, the current I _L continues to decrease in cycle t2. For this reason, in the next cycle, the time for the combined voltage V _T to reach the error voltage V _ERR becomes longer, and the duty ratio of the high-side transistor 10 in the conductive state becomes longer. For this reason, a cycle with a long duty ratio and a short cycle appear alternately, and the operation is not stable. Further, the amount of variation of the output voltage V _OUT as indicated by broken lines is increased in FIG. 5, a large ripple occurs in the output voltage V _OUT.

  As shown in FIG. 1, the setting circuit 40 for realizing the above operation includes a NAND circuit 41 to which a reset signal RST and a set signal SET are input, an output of the NAND circuit 41 is input to a set terminal, and a switching signal Vg1 is reset. The setting flip-flop 42 input to the terminal, the output of the setting flip-flop 42 and the switching signal Vg1 are input, and the NOR circuit 43 that outputs the switching signal Vg2 to the control terminal of the low-side transistor 20 is provided.

  When the reset signal RST is input to the switching circuit 33 while the set signal SET is input to the switching circuit 33, the outputs of the NAND circuit 41 whose inputs are both at the high level are at the low level. For this reason, the output of the setting flip-flop 42 is at low level, and the switching signal Vg2 output from the NOR circuit 43 is at low level. The switching signal Vg2 is amplified by the amplifier 21 and input to the control terminal of the low-side transistor 20. As described above, when the reset signal RST is input to the switching circuit 33 while the set signal SET is input to the switching circuit 33, the low-side transistor 20 is turned off.

  After the reset signal RST becomes low level, when the reset signal is input after the set signal SET is input to the switching circuit 33 in a new cycle, the low-side transistor 20 can be turned on so that the low-side transistor 20 can be turned on. Is canceled.

According to the related art, for example, there is a method of suppressing an increase in ripple generated in the output voltage V _OUT by setting the low-side transistor 20 in a non-conducting state for a certain period at the time of startup. However, in this method, when the low-side transistor 20 is switched from the non-conductive state for a certain period to the normal synchronous rectification control, the low-side transistor 20 that has been in the non-conductive state for several cycles suddenly becomes conductive. The output voltage V _OUT changes greatly. As a result, there is a problem that the operation becomes unstable due to a large ripple generated in the output voltage V _OUT .

  On the other hand, in the switching regulator 1 shown in FIG. 1, the setting circuit 40 is only in the cycle in which the high-side transistor 10 does not switch from the non-conductive state to the conductive state at the timing when the control circuit 30 controls the high-side transistor 10 to the conductive state. The low-side transistor 20 is maintained in a nonconductive state. When the pulse signal is normally output in the next cycle, the conduction state of the low-side transistor 20 is controlled according to normal PWM control. Specifically, after the high-side transistor 10 switches from the conductive state to the non-conductive state, the low-side transistor 20 becomes conductive. That is, the setting circuit 40 maintains the low-side transistor 20 in the non-conductive state in the cycle in which the high-side transistor 10 switches from the non-conductive state to the conductive state at the timing when the control circuit 30 controls the high-side transistor 10 to the conductive state. There is no.

As described above, in the switching regulator 1, the control method is not suddenly changed after the output voltage V _OUT increases. For this reason, unlike the case where the low-side transistor 20 is always kept in a non-conductive state for a certain period, there is no problem that the operation of the switching regulator 1 becomes unstable.

Furthermore, the switching regulator 1 is also effective when the boot function for securing the gate voltage to drive the high-side transistor 10 is realized with the configuration shown in FIG. The boot function shown in FIG. 1 is realized by driving the high-side transistor 10 by an amplifier 11 that uses a boot voltage with the SW terminal potential as a reference potential as a power supply voltage. This boot function is realized by raising the voltage of the BOOT terminal by a charge pump using a regulator voltage of 5 V and a boot capacitor _CBT connected between the SW terminal and the BOOT terminal (7). The boot capacitor C _BT is discharged when the high-side transistor 10 is turned on, and is charged while the low-side transistor 20 is turned on.

Therefore, when the low-side transistor 20 always non-conductive, it is difficult charged boot capacitor C _BT. However, in the switching regulator 1 shown in FIG. 1, the low-side transistor 20 is always in a conductive state in the cycle in which the high-side transistor 10 is in a conductive state. For this reason, the boot capacitor _CBT can be sufficiently charged.

  Further, when the high-side transistor 10 is in a non-conducting state, a current is passed through a parasitic element of the low-side transistor 20 or the like due to the back electromotive force generated in the smoothing inductor L1 even if the low-side transistor 20 is in a non-conducting state. Flowing. In this case, since the voltage drop due to the current flowing through the parasitic element is larger than the voltage drop due to the current flowing through the low-side transistor 20 in the conductive state, the power loss and the heat generation amount are increased. Furthermore, the potential of the SW terminal to which the smoothing inductor L1 is connected becomes a negative potential, which may cause a phenomenon such as generation of a parasitic element in the switching regulator 1 or unstable ground level. As a result, problems such as unstable circuit operation of the switching regulator and reduced voltage conversion efficiency occur.

  However, in the switching regulator 1 shown in FIG. 1, the low-side transistor 20 is not in a non-conductive state for a certain period of time, but only in a cycle in which the pulse signal is not normally output. To. For this reason, an increase in the amount of heat generation and the generation of parasitic elements are suppressed, and problems such as unstable circuit operation and reduced voltage conversion efficiency do not occur.

Note that the operation of the setting circuit 40 that brings the low-side transistor 20 into a non-conductive state may be enabled only when the switching regulator 1 is activated. Alternatively, the setting circuit 40 may be operated even when the output voltage V _OUT is increased again after the output voltage V _OUT is temporarily decreased after the switching regulator 1 is always activated. Good.

  As described above, according to the switching regulator 1 according to the embodiment of the present invention, in the cycle in which the high-side transistor 10 is not switched from the non-conductive state to the conductive state at the timing of controlling the high-side transistor 10 to the conductive state. By making the low-side transistor 20 non-conductive, a synchronous rectification switching regulator that operates stably even when the duty ratio is small can be realized.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the embodiment already described, the case where the high-side transistor and the low-side transistor are FETs is shown, but switching elements other than FETs may be used.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  The switching regulator of the present invention can be used in the electronic equipment industry including the manufacturing industry that manufactures electronic equipment that supplies constant power supply voltage to equipment such as AV home appliances and personal computers.

C1 ... Smoothing capacitor CP ... Connection point L1 ... Smoothing inductor RST ... Reset signal SET ... Set signal 1 ... Switching regulator 10 ... High side transistor 11, 21 ... Amplifier 20 ... Low side transistor 30 ... Control circuit 31 ... Reset circuit 32 ... Oscillation Circuit 33 ... Switching circuit 34 ... Slope generation circuit 40 ... Setting circuit 41 ... NAND circuit 42 ... Setting flip-flop 43 ... NOR circuit 50 ... Error amplifier 60 ... Soft start circuit 70 ... Off latch time setting circuit 80 ... Enable circuit 110 ... Smoothing circuit 311 ... Multiplexing circuit 312 ... Comparator

Claims (5)

A switching regulator that converts an input voltage to a target voltage by a synchronous rectification method,
A high-side transistor and a low-side transistor connected in series between an input terminal to which the input voltage is applied and a ground terminal;
The high-side transistor in one cycle is conductive so that the difference between the target voltage and the output voltage obtained by smoothing the switching voltage at the connection point between the high-side transistor and the low-side transistor is small. A control circuit for controlling the length of the period;
A setting circuit for maintaining the low-side transistor in a non-conductive state during a cycle in which the high-side transistor is not switched from a non-conductive state to a conductive state at a timing when the control circuit controls the high-side transistor to a conductive state. A switching regulator characterized by that. The control circuit comprises:
An oscillation circuit that outputs a set signal for turning on the high-side transistor at a constant period;
A reset circuit that outputs a reset signal for turning off the high-side transistor when the switching voltage reaches an error voltage set from a difference between the output voltage and the target voltage;
2. The switching regulator according to claim 1, further comprising: a switching circuit that receives the reset signal and the set signal and outputs a switching signal that switches between a conductive state and a non-conductive state of the high-side transistor.   The switching regulator according to claim 2, wherein the switching circuit is a flip-flop in which the set signal is input to a set terminal and the reset signal is input to a reset terminal.   The setting circuit maintains the low-side transistor in a non-conducting state when the set signal is input to the switching circuit in a state where the reset signal is input to the switching circuit. The switching regulator according to 2 or 3. The setting circuit is
A NAND circuit to which the reset signal and the set signal are input;
A setting flip-flop in which an output of the NAND circuit is input to a set terminal, and the switching signal is input to a reset terminal;
The switching regulator according to claim 4, further comprising: a NOR circuit to which an output of the setting flip-flop and the switching signal are input, and an output is input to a control terminal of the low-side transistor.

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