JP2011049426A - Method of designing semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device design method and the like capable of preventing a deep concave portion from being formed on the surface of an interlayer insulating film when wiring is embedded in a trench.
Step S6 for calculating a total perimeter of the wiring pattern per unit area for each unit area, and a first sum of the perimeter of the wiring pattern in the unit area equal to or greater than a first value. Steps S7 and S8 for extracting the region and the second region that is equal to or smaller than the second value, and the sum of the perimeters per unit area in the third region adjacent to the first region is the third value. Steps S9 and S10 in which a certain first dummy pattern is arranged, and a second dummy pattern whose total perimeter per unit area is a fourth value is arranged in a fourth region adjacent to the second region. In the fifth region between the third region and the fourth region, the sum of the perimeters per unit area is a fifth value that is smaller than the third value and larger than the fourth value. Step S11 for arranging three dummy patterns.
[Selection] Figure 15

Description

  The present invention relates to a semiconductor device design method and a semiconductor device manufacturing method.

  Recently, a technique for embedding a wiring or the like in a groove formed in an interlayer insulating film by a damascene method or the like has attracted attention.

  In the damascene method, a conductive film is formed on an interlayer insulating film in which a groove or the like is formed, and the conductive film is polished by CMP until the surface of the interlayer insulating film is exposed. Embedded in the groove.

  However, polishing by the CMP method does not always proceed uniformly, and a recess may be formed on the surface of the interlayer insulating film.

  Accordingly, it has been proposed to make the progress of polishing uniform by appropriately arranging dummy patterns.

Japanese Patent Laying-Open No. 2005-310807 Japanese Patent Laid-Open No. 10-173035 JP 2000-223492 A

  However, in the proposed method for manufacturing a semiconductor device, the progress of polishing cannot be made sufficiently uniform, and a relatively deep recess may occur on the surface of the interlayer insulating film.

  An object of the present invention is to provide a semiconductor device design method and a semiconductor device manufacturing method capable of preventing the formation of deep recesses on the surface of an interlayer insulating film when a wiring or the like is embedded in a trench.

  According to one aspect of the embodiment, a step of arranging a wiring pattern in a predetermined layout region, a step of dividing the layout region into unit regions of a predetermined unit area, and the periphery of the wiring pattern per unit area Calculating a total length for each of the unit areas; and a first area in which the total perimeter of the wiring pattern in the unit area is equal to or greater than a first value that is a predetermined upper limit value. Extracting, extracting a second area in which the total perimeter of the wiring pattern in the unit area is equal to or less than a second value that is a predetermined lower limit, the first area, and the A first dummy pattern in which a total sum of perimeters per unit area is a third value in a third region adjacent to the first region among regions between the second region. Place In a fourth region adjacent to the second region among the step and the region between the first region and the second region, the total perimeter of the unit area is the first region. Arranging a second dummy pattern having a fourth value smaller than a value of 3, and surroundings per unit area in a fifth region between the third region and the fourth region And providing a third dummy pattern having a fifth sum whose length sum is smaller than the third value and larger than the fourth value. Is done.

  According to another aspect of the embodiment, a step of arranging a wiring pattern in a predetermined layout region, a step of dividing the layout region into unit regions of a predetermined unit area, and the wiring pattern per unit area A step of calculating a total perimeter for each of the unit areas, and a first area in which the total perimeter of the wiring pattern in the unit area is equal to or greater than a first value that is a predetermined upper limit value. Extracting a second area in which the total perimeter of the wiring pattern in the unit area is equal to or less than a second value that is a predetermined lower limit; and the first area; In a third region adjacent to the first region among the regions between the second region, the total perimeter per unit area is smaller than the first value, and Value of 2 In the fourth region between the step of arranging the first dummy pattern having a large third value and the fourth region between the third region and the second region, the total perimeter of the unit area is And providing a second dummy pattern having a fourth value smaller than the third value and a fourth value larger than the second value.

  According to still another aspect of the embodiment, a step of forming a wiring groove for embedding a wiring and a dummy pattern groove for embedding a dummy pattern in the insulating film, and in the wiring groove, the dummy Forming a conductive film in a pattern groove and on the insulating film; polishing the conductive film until the insulating film is exposed; and wiring of the conductive film embedded in the wiring groove; Forming the dummy pattern of the conductive film embedded in the dummy pattern groove, and in the step of forming the wiring groove and the dummy pattern groove, a total perimeter per unit area Is formed in the first region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value. The wiring groove is a second A total sum of perimeters per unit area in a third region adjacent to the first region among regions between the first region and the second region formed in the region Is formed in the fourth region adjacent to the second region among the regions between the first region and the second region. Forming a dummy pattern groove having a total perimeter length per unit area that is a fourth value smaller than the third value, and forming a fifth between the third region and the fourth region. In the region, the dummy pattern groove is formed such that a total sum of perimeters per unit area is a fifth value smaller than the third value and larger than the fourth value. A method for manufacturing a semiconductor device is provided.

  According to still another aspect of the embodiment, a step of forming a wiring groove for embedding a wiring and a dummy pattern groove for embedding a dummy pattern in the insulating film, and in the wiring groove, the dummy Forming a conductive film in a pattern groove and on the insulating film; polishing the conductive film until the insulating film is exposed; and wiring of the conductive film embedded in the wiring groove; Forming the dummy pattern of the conductive film embedded in the dummy pattern groove, and in the step of forming the wiring groove and the dummy pattern groove, a total perimeter per unit area Is formed in the first region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value. The wiring groove is a second A total sum of perimeters per unit area in a third region adjacent to the first region among regions between the first region and the second region formed in the region Forming the dummy pattern groove having a third value smaller than the first value and larger than the second value, and forming a fourth gap between the third region and the second region. In the semiconductor device, the dummy pattern trench in which a total sum of perimeters per unit area is smaller than the third value and a fourth value larger than a second value is formed. A manufacturing method is provided.

  According to the disclosed semiconductor device design method and semiconductor device manufacturing method, the sum of the perimeters per unit area is medium between the region where the sum of the perimeters of the wiring pattern per unit area is large and the region where the sum is small. The dummy pattern is arranged. For this reason, it is possible to prevent a portion where the sum of the perimeters per unit area is significantly different from occurring, and to achieve uniform polishing. Therefore, it is possible to prevent a deep recess from being formed on the surface of the interlayer insulating film when the wiring is embedded in the groove formed in the interlayer insulating film by polishing.

It is a top view (the 1) which shows the example of arrangement | positioning of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in the AA 'cross section of FIG. It is a top view (the 2) which shows the example of arrangement | positioning of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in the BB 'cross section of FIG. It is a top view (the 3) which shows the example of arrangement | positioning of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in CC 'cross section of FIG. It is a top view (the 4) which shows the example of arrangement of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in the DD 'cross section of FIG. It is a graph which shows the normalized wiring capacity. It is a top view (the 5) which shows the example of arrangement | positioning of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in the EE 'cross section of FIG. It is a top view (the 6) which shows the example of arrangement | positioning of a dummy pattern. It is a figure which shows the level | step difference of the surface of the interlayer insulation film in the FF 'cross section of FIG. 1 is a plan view illustrating a method for designing a semiconductor device according to a first embodiment. 3 is a flowchart illustrating a semiconductor device design method according to the first embodiment. FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 11 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment; It is process sectional drawing (the 7) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 8) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 9) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 10) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 11) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 12) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 13) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 14) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is process sectional drawing (the 15) which shows the manufacturing method of the semiconductor device by 1st Embodiment. It is a figure which shows the level | step difference of the surface of the interlayer insulation film corresponding to the GG 'cross section of FIG. It is a top view which shows the design method of the semiconductor device by the modification of 1st Embodiment. It is a top view which shows the design method of the semiconductor device by 2nd Embodiment. It is a top view which shows the design method of the semiconductor device by 3rd Embodiment. 10 is a flowchart showing a method for designing a semiconductor device according to a third embodiment.

  FIG. 1 is a plan view (No. 1) showing an example of arrangement of dummy patterns. FIG. 1A shows an arrangement of a region 100 in which the density of the wiring pattern 106 is relatively high (high-density region), a region 102 in which the density of the wiring pattern 108 is relatively low (low-density region) 102, and the dummy pattern region 104. It is a top view which shows an example. FIG. 1B is an enlarged view of a part of the high-density region 100 in FIG. FIG. 1C is an enlarged view of a part of the dummy pattern region 104 in FIG. FIG. 1D is an enlarged view of a part of the low density region 102 in FIG.

  As shown in FIG. 1, a dummy pattern 110 is disposed at a medium density in the dummy pattern region 104 between the high density region 100 and the low density region 102. The density of the wiring patterns 106 and 108 is an existing ratio of the wiring patterns 106 and 108 in the wiring pattern areas 100 and 102, and the density of the dummy pattern 110 is an existing ratio of the dummy patterns 110 in the dummy pattern area 104. is there.

  As shown in FIGS. 1A and 1D, linear wiring patterns 106 and 108 are arranged in parallel in both the high-density region 100 and the low-density region 102. The width of the wiring pattern 106 in the high-density region 100 was 70 nm. Further, the interval between the wiring patterns 106 in the high-density region 100 was set to 70 nm. The density of the wiring pattern 106 in the high-density region 100 is 50%. The width of the wiring pattern 108 in the low density region 102 was 70 nm. The interval between the wiring patterns in the low density region 102 was 280 nm. The density of the wiring pattern 108 in the low density region 102 is 20%.

  As shown in FIG. 1C, a plurality of square dummy patterns 106 are arranged in the dummy pattern region 104 between the high density region 100 and the low density region 102. The dummy patterns 106 adjacent to each other are shifted from each other. The reason why the dummy patterns 106 are shifted from each other is to make the crosstalk between the wirings uniform. The size of the dummy pattern 106 was 500 nm × 500 nm. The interval between the adjacent dummy patterns 106 was 300 nm. The density of the dummy pattern in the dummy pattern region is 39%.

  When such wiring patterns 106 and 108 and the dummy pattern 110 are embedded in a groove (not shown) formed in an interlayer insulating film (not shown) by a damascene method, as shown in FIG. A relatively deep recess was formed on the surface of the interlayer insulating film. FIG. 2 is a view showing a step on the surface of the interlayer insulating film in the AA ′ cross section of FIG. 1. As shown in FIG. 2, a relatively deep recess 112 of about 75 nm was formed in the vicinity of the boundary between the high density region 100 and the dummy pattern region 104.

  As described above, the density of the wiring pattern 106 in the high-density region 110 in FIG. 1 is 50%, and the density of the dummy pattern 110 in the dummy pattern region 104 in FIG. 1 is 39% as described above. In the case of FIG. 1, a relatively deep recess 112 as shown in FIG. 2 was formed, although the pattern density was only 11% different.

  When another interlayer insulating film (not shown) is formed on the interlayer insulating film having such a relatively deep recess 112, the recess 112 generated in the interlayer insulating film is reflected in the other interlayer insulating film. As a result, a relatively deep recess (not shown) is also formed on the surface of the other interlayer insulating film. When wiring is embedded in another interlayer insulating film having a relatively deep recess on the surface by the damascene method, a conductive film (not shown) remains in the recess on the surface of the other interlayer insulating film. The adjacent wiring patterns may be short-circuited by the conductive film remaining in the recess.

  As described above, when attention is paid to the density of the wiring patterns 106 and 108 and the dummy pattern 110 is arranged at a medium density in a region between the high-density region 100 and the low-density region 102, the surface of the interlayer insulating film It was found that the concave portion 112 generated in the above could not be sufficiently suppressed.

  The inventor of the present application paid attention to the total perimeter of the wiring patterns 106 and 108 per unit area and conducted the following experiment.

  FIG. 3 is a plan view (No. 2) showing an example of arrangement of dummy patterns. As shown in FIG. 3A, a dummy pattern region 116 is provided around the wiring pattern region 114. The total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114 is set to be relatively large. The total perimeter of the dummy pattern 110 per unit area in the dummy pattern region 116 is set to be relatively small. FIG. 3B is an enlarged view of a part of the region 114 in FIG. FIG. 3C is an enlarged view of a part of the region 116 in FIG. The total perimeter of the pattern per unit area is the sum of the lengths of the sides around the pattern extracted from the pattern located in the region of the predetermined unit area.

  As shown in FIG. 3B, a plurality of wiring patterns 106 having a width of 70 nm are arranged in parallel in the wiring pattern region 114. The interval between the wiring patterns 106 adjacent to each other was set to 70 nm. The density of the wiring pattern 106 in the wiring pattern region 114 is 50%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the wiring pattern 114 in the unit region is 5714 μm.

  The total perimeter of the wiring pattern 114 in the unit area can be obtained by the following equation.

20 μm ÷ (0.07 μm × 2) × 20 μm × 2 = 5714 μm
Further, as shown in FIG. 3C, a plurality of square dummy patterns 110 are arranged in the dummy pattern region 116. The dummy patterns 110 adjacent to each other are shifted from each other. The size of the dummy pattern 110 was 500 nm × 500 nm. The interval between the dummy patterns 110 adjacent to each other was set to 300 nm. The density of the dummy pattern 110 in the dummy pattern region 116 is 39%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the dummy pattern 110 in the unit region is about 1250 μm.

  Note that the total perimeter of the dummy pattern 110 in the unit region 116 is obtained by the following equation.

{20 μm ÷ (0.5 μm + 0.3 μm)} ² × (0.5 μm × 4) = 1250 μm
When such a wiring pattern 106 and dummy pattern 110 are embedded in a groove formed in the interlayer insulating film by a damascene method, a relatively deep recess 118 is formed on the surface of the interlayer insulating film as shown in FIG. It was. FIG. 4 is a diagram showing a step on the surface of the interlayer insulating film in the BB ′ section of FIG. 3. As shown in FIG. 4, a relatively deep recess 118 of about 70 nm was formed in the vicinity of the boundary between the wiring pattern region 114 and the dummy pattern region 116.

  From this, it can be seen that when the total perimeter of the pattern per unit area is significantly different, a relatively deep recess 118 is formed on the surface of the interlayer insulating film.

  FIG. 5 is a plan view (No. 3) showing an example of arrangement of dummy patterns. As shown in FIG. 5A, a dummy pattern region 116 is provided around the wiring pattern region 114. The total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114 is set to be relatively large. The total perimeter of the dummy pattern 120 per unit area in the dummy pattern region 116 is set to be relatively small. FIG. 5B is an enlarged view of a part of the region 114 in FIG. FIG. 5C is an enlarged view of a part of the region 116 in FIG.

  As shown in FIG. 5B, a plurality of wiring patterns 106 having a width of 70 nm are arranged in parallel in the wiring pattern region 114. The interval between the wiring patterns 106 adjacent to each other was set to 70 nm. The density of the wiring pattern 106 in the wiring pattern region 114 is 50%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the wiring pattern 106 in the unit region is 5714 μm.

  As shown in FIG. 5C, a plurality of linear dummy patterns 120 having a width of 500 nm are arranged in parallel in the dummy pattern region 116. The longitudinal direction of the dummy pattern 120 was the same as the longitudinal direction of the wiring pattern 106. The interval between the adjacent dummy patterns 120 was 779 nm. The density of the dummy patterns 120 in the dummy pattern region 116 is 39%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the dummy pattern 120 in the unit region is 625 μm.

  Note that the sum of the perimeters of the dummy patterns 120 in the unit area can be obtained by the following equation.

20 μm ÷ (0.5 μm + 0.779 μm) × 20 μm × 2 = 625 μm
When such a wiring pattern 106 and dummy pattern 120 are embedded in a groove formed in an interlayer insulating film by a damascene method, a relatively deep recess 122 is formed on the surface of the interlayer insulating film as shown in FIG. It was. FIG. 6 is a view showing a step on the surface of the interlayer insulating film in the CC ′ cross section of FIG. 5. As shown in FIG. 6, a relatively deep recess 122 of about 53 nm was formed in the vicinity of the boundary between the wiring pattern region 114 and the dummy pattern region 116.

  Therefore, even when the dummy pattern 120 is formed in a linear shape, if the total perimeter of the pattern per unit area is significantly different, a relatively deep recess 122 is formed on the surface of the interlayer insulating film. I understand.

  FIG. 7 is a plan view (part 4) showing an example of arrangement of dummy patterns. As shown in FIG. 7A, a dummy pattern region 116 is provided around the wiring pattern region 114. The total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114 is set to be relatively large. The total perimeter of the dummy pattern 120 per unit area in the dummy pattern region 116 is set slightly smaller than the total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114. That is, in FIG. 7, in the dummy pattern region 116, the difference between the total perimeter of the wiring pattern 106 per unit area and the total perimeter of the dummy pattern 120 per unit area is relatively small. A linear dummy pattern 124 is arranged. FIG. 7B is an enlarged view of a part of the region 114 in FIG. FIG. 7C is an enlarged view of a part of the region 116 in FIG.

  As shown in FIG. 7B, a plurality of wiring patterns 106 having a width of 70 nm are arranged in parallel in the wiring pattern region 114. The interval between the wiring patterns 106 adjacent to each other was set to 70 nm. The density of the wiring pattern 106 in the wiring pattern region 114 is 50%. When a region having a size of 20 μm × 20 μm is defined as a unit region, the total perimeter of the wiring pattern 106 in the unit region is 5714 μm.

  As shown in FIG. 7C, a plurality of linear dummy patterns 124 having a width of 70 nm are arranged in parallel in the dummy pattern region 116. The longitudinal direction of the dummy pattern 124 was the same as the longitudinal direction of the wiring pattern 106. The interval between the adjacent dummy patterns 124 was 109 nm. The density of the dummy pattern 124 in the dummy pattern region 116 is 39%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the dummy patterns in the unit region is 4469 μm.

  Note that the sum of the perimeters of the dummy patterns in the unit area is obtained by the following equation.

20 μm ÷ (0.07 μm × 0.109 μm) × 20 μm × 2 = 4469 μm
When such a wiring pattern 106 and dummy pattern 124 are buried in a groove formed in the interlayer insulating film by a damascene method, the recess 126 formed on the surface of the interlayer insulating film is relatively shallow as shown in FIG. It was. FIG. 8 is a diagram showing a step on the surface of the interlayer insulating film in the section DD ′ in FIG. 7. As shown in FIG. 8, the recess 126 formed on the surface of the interlayer insulating film in the vicinity of the boundary between the wiring pattern region 114 and the dummy pattern region 116 was relatively shallow at about 10 nm.

  Therefore, if the total perimeters of the patterns 106 and 124 per unit area in the adjacent regions 114 and 116 are not significantly different, the recess 126 generated on the surface of the interlayer insulating film can be made relatively shallow. I understand.

  However, as shown in FIG. 7, when the longitudinal direction of the linear dummy pattern 124 and the longitudinal direction of the wiring pattern 106 are the same, the amount of crosstalk becomes large.

  FIG. 9 is a graph showing the standardized wiring capacity. Comparative Example 1 shows a standardized wiring capacity when a square dummy pattern is formed. Comparative Example 2 shows a standardized wiring capacity when a linear dummy pattern 124 is formed in parallel with the wiring pattern 106.

  As shown in FIG. 9, when the linear dummy pattern 124 is arranged in parallel with the wiring pattern 106, the wiring capacity increases by about 10%. Since the amount of crosstalk increases with an increase in wiring capacitance, arranging the linear dummy pattern 124 in parallel with the wiring pattern 106 becomes an impediment to improving the operating speed of the semiconductor device.

  FIG. 10 is a plan view (part 5) showing an example of the arrangement of dummy patterns. As shown in FIG. 10A, a dummy pattern region 116 is provided around the wiring pattern region 114. The total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114 is set to be relatively large. The total perimeter of the dummy pattern 128 per unit area in the dummy pattern region 116 is set slightly smaller than the total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114. That is, in FIG. 10, in the dummy pattern region 116, the difference between the total perimeter of the wiring pattern 106 per unit area and the total perimeter of the dummy pattern 128 per unit area is relatively small. A square dummy pattern 128 is arranged. FIG. 10B is an enlarged view of a part of the region 114 in FIG. FIG. 10C is an enlarged view of a part of the region 116 in FIG.

  As shown in FIG. 10B, in the wiring pattern region 114, a plurality of wiring patterns 106 having a width of 70 nm are arranged in parallel. The interval between the wiring patterns 106 adjacent to each other was set to 70 nm. The density of the wiring pattern 106 in the wiring pattern region 114 is 50%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the wiring pattern 114 in the unit region is 5714 μm.

  As shown in FIG. 10C, a plurality of square dummy patterns 128 are arranged in the dummy pattern region 116. The dummy patterns 128 adjacent to each other are arranged so as to be shifted from each other. The size of the dummy pattern 128 was set to 125 nm × 125 nm. The interval between the adjacent dummy patterns 128 was set to 75 nm. The density of the dummy patterns 128 in the dummy pattern region 116 is 39%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the dummy pattern 128 in the unit region is 5000 μm.

  Note that the sum of the perimeters of the dummy patterns 128 in the unit area is obtained by the following equation.

{20 μm ÷ (0.125 μm + 0.075 μm)} ² × (0.125 μm × 4)
= 5000μm
When such a wiring pattern 106 and dummy pattern 128 are embedded in a groove formed in the interlayer insulating film by the damascene method, the recess 130 formed on the surface of the interlayer insulating film is relatively shallow as shown in FIG. It was. FIG. 11 is a view showing a step on the surface of the interlayer insulating film in the section EE ′ of FIG. As shown in FIG. 11, the recess 130 formed on the surface of the interlayer insulating film in the vicinity of the boundary between the wiring pattern region 114 and the dummy pattern region 116 was relatively shallow, about 11 nm.

  In this way, if the dummy pattern 128 is square while keeping the sum of the perimeters of the patterns 106 and 128 per unit area in the regions 114 and 116 adjacent to each other, the concave portion can be suppressed while suppressing crosstalk. It can be seen that 130 can be shallow.

  The dummy pattern 128 is not limited to a square. A rectangular dummy pattern 128 in which the length of the long side relative to the length of the short side is not significantly long may be appropriately arranged in the dummy pattern region 116.

  FIG. 12 is a plan view (No. 6) showing an example of arrangement of dummy patterns. As shown in FIG. 12A, a dummy pattern region 116 is provided around the wiring pattern region 114. The total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114 is set to be relatively large. The total perimeter of the dummy pattern 132 per unit area in the dummy pattern region 116 is set slightly smaller than the total perimeter of the wiring pattern 106 per unit area in the wiring pattern region 114. That is, in FIG. 12, in the dummy pattern region 116, the difference between the total perimeter of the wiring pattern 106 per unit area and the total perimeter of the dummy pattern 132 per unit area is relatively small. Linear dummy patterns 128 are arranged obliquely. FIG. 12B is an enlarged view of a part of the region 114 in FIG. FIG. 12C is an enlarged view of a part of the region 116 in FIG.

  As shown in FIG. 12A, in the wiring pattern region 114, a plurality of wiring patterns 106 having a width of 70 nm are arranged in parallel. The interval between the wiring patterns 106 adjacent to each other was set to 70 nm. The density of the wiring pattern 106 in the wiring pattern region 106 is 50%. When a region having a size of 20 μm × 20 μm is defined as a unit region, the total perimeter of the wiring pattern 106 in the unit region is 5714 μm.

  As shown in FIG. 12B, in the dummy pattern region 116, a plurality of dummy patterns 132 having a width of 70 nm are arranged in parallel. The interval between adjacent dummy patterns was 109 nm. The longitudinal direction of the dummy pattern 132 was oblique to the longitudinal direction of the wiring pattern 106. More specifically, the angle formed by the longitudinal direction of the dummy pattern 132 and the longitudinal direction of the wiring pattern 106 is 45 degrees. The reason why the dummy pattern 132 is disposed obliquely with respect to the wiring pattern 106 is to suppress crosstalk with wiring (not shown) provided on the upper layer side or the lower layer side with respect to the dummy pattern 132. The density of the dummy patterns 132 in the dummy pattern region 116 is 39%. When a region having a size of 20 μm × 20 μm is used as a unit region, the total perimeter of the dummy pattern 132 in the unit region is 4469 μm, similar to the dummy pattern 124 described above with reference to FIG.

  When such a wiring pattern 106 and a dummy pattern 132 are embedded in a groove formed in the interlayer insulating film by a damascene method, as shown in FIG. 13, the concave portion 134 generated on the surface of the interlayer insulating film is relatively shallow. It was. FIG. 13 is a view showing a step on the surface of the interlayer insulating film in the section FF ′ in FIG. As shown in FIG. 13, the recess 134 formed on the surface of the interlayer insulating film in the vicinity of the boundary between the wiring pattern region 114 and the dummy pattern region 116 was relatively shallow, about 9 nm.

  In this way, crosstalk is also suppressed by forming the linear dummy pattern 132 obliquely while keeping the sum of the perimeters of the patterns 106 and 132 per unit area in regions adjacent to each other significantly different. However, the recess 134 can be shallow.

  Thus, the inventor of the present application can reduce the interlayer insulating film by making the difference between the total perimeter of the wiring pattern 106 per unit area and the total perimeter of the dummy patterns 128 and 132 per unit area relatively small. The inventors have conceived that it is possible to suppress the formation of deep recesses on the surface. Furthermore, it has been conceived that by forming the dummy pattern 128 into a rectangle such as a square, it is possible to suppress the occurrence of deep recesses on the surface of the interlayer insulating film while suppressing crosstalk. It has also been conceived that forming the dummy pattern 132 obliquely with respect to the wiring pattern 106 can suppress the formation of deep recesses on the surface of the interlayer insulating film while preventing crosstalk.

[First Embodiment]
A semiconductor device design method and a semiconductor device manufacturing method according to the first embodiment will be described with reference to FIGS.

(Semiconductor device design method)
First, the semiconductor device design method according to the present embodiment will be explained with reference to FIGS. FIG. 14 is a plan view of the semiconductor device design method according to the present embodiment. FIG. 14B is an enlarged view of a part of the region 12 in FIG. FIG. 14C is an enlarged view of a part of the region 16 in FIG. FIG. 14D is an enlarged view of a part of the region 14a in FIG. FIG. 14E is an enlarged view of a part of the region 14c in FIG. FIG. 14F is an enlarged view of a part of the region 14b in FIG. FIG. 15 is a flowchart showing the semiconductor device design method according to the present embodiment.

  When designing a semiconductor device, a semiconductor design device (CAD: Computer Aided Design) (not shown) is used to lay out various components of the semiconductor device. For example, the layout of the element isolation region, the layout of the gate electrode, the layout of the contact hole, the layout of the wiring, and the like are appropriately performed by an operation input of the semiconductor design apparatus by the designer. Thereby, design data of the semiconductor device is created, and a photomask for transferring the pattern to the photoresist film is created based on the design data.

  The semiconductor design apparatus used in the present embodiment has a function of calculating the sum of the perimeters of patterns in a unit area. As software for realizing such a function, for example, Caliber YieldAnalyzer (product name) manufactured by Mentor Graphics Corporation can be cited. Such software is installed and used in a semiconductor design apparatus. Note that the software for calculating the sum of the perimeters of the patterns in the unit area is not limited to such software. Any other software that can calculate the total perimeter of the wiring pattern in the unit area can be used as appropriate. Further, the semiconductor design apparatus may have such a function in advance without installing such software separately in the semiconductor design apparatus.

  In the present embodiment, the layout of the wiring pattern and the dummy pattern embedded in the groove formed in the interlayer insulating film is performed as follows.

  First, a wiring pattern is arranged in a predetermined layout area (device area) (step S1). Arrangement of the wiring pattern is performed by an operation input of the semiconductor design apparatus by the designer.

  Next, the size of a unit area (unit section, divided area, mesh, window) (not shown) is set (step S2). The unit area is for virtually dividing the layout area into a plurality of small areas having an equal area. In this specification, the area of a unit region is defined as a unit area. The size of the unit area is set by, for example, an operation input of the semiconductor design apparatus by the designer. The size of the unit region is, for example, 20 μm × 20 μm.

  The size of the unit region is not limited to 20 μm × 20 μm, and can be appropriately set according to the size of the wiring pattern and the like.

  Next, the layout area where the wiring pattern is arranged is virtually divided into a plurality of unit areas (not shown) (step S3). In the present embodiment, the reason why the layout area is virtually divided into a plurality of unit areas is to perform various analyzes for each unit area. More specifically, it is for calculating the sum total of the perimeters of the wiring patterns in the unit area for each unit area.

  Next, a predetermined upper limit value (first reference value, first value) for extracting a region having a relatively large total perimeter of the wiring pattern 10 in the unit region is set (step S4). The predetermined upper limit value is set, for example, by an operation input of the semiconductor design apparatus by a designer. The predetermined upper limit value is, for example, 5000 μm.

  Next, a predetermined lower limit value (second reference value, second value) for extracting a region where the sum of the perimeters of the wiring patterns in the unit region is relatively small is set (step S5). The second value is smaller than the first value. The predetermined upper limit value is set, for example, by an operation input of the semiconductor design apparatus by a designer. The predetermined lower limit value is, for example, 2000 μm.

  Next, the total perimeter of the wiring pattern 10 in the unit area is calculated for each unit area (step S6). The total perimeter of the wiring pattern 10 in the unit area is the total length of the sides of the wiring pattern 10 extracted from the wiring pattern 10 located in the unit area. Only the length of the side of the wiring pattern 10 in the part located in the unit region is the peripheral length of the wiring pattern 10 in the unit region. The perimeter is also referred to as a perimeter. When a plurality of wiring patterns 10 are present in the unit area, the sum of the lengths of the sides of the plurality of wiring patterns 10 located in the unit area is the unit area. The total perimeter of the wiring pattern 10 in FIG.

  Next, a unit region (unit region group) whose total perimeter of the wiring pattern 10 per unit area is equal to or greater than a predetermined upper limit value is extracted (step S7). When the predetermined upper limit value is 5000 μm, a unit region group (first region) 12 having a total sum of peripheral lengths of wiring patterns per unit area of 5000 μm or more is extracted. The first region 12 is formed by a plurality of unit region groups in which the total perimeter of the wiring pattern per unit area is equal to or greater than a predetermined upper limit value. In FIG. 14A, only a part of the first area 12 extracted in the layout area is shown.

  Next, a unit region (unit region group) whose total perimeter of the wiring pattern 10 per unit area is equal to or smaller than a predetermined lower limit value is extracted (step S8). When the predetermined lower limit value is 1000 μm, a unit region group (second region) 16 in which the total perimeter of the wiring pattern 10 per unit area is 1000 μm or less is extracted. The second region 16 is formed of a plurality of unit region groups in which the total perimeter of the wiring pattern per unit area is equal to or less than a predetermined lower limit value. In FIG. 14A, only a part of the second area 16 extracted in the layout area is shown.

  Next, the first region 12 in which the total perimeter of the wiring pattern 10 per unit area is equal to or greater than a predetermined upper limit, and the total perimeter of the wiring pattern 10 per unit area is equal to or less than a predetermined lower limit. In the dummy pattern region 14 between the second region 16, dummy patterns 18, 20 and 22 are arranged as follows.

  First, of the region (dummy pattern region) 14 between the first region 10 and the second region 12, the third region 14a adjacent to the first region 12 has a perimeter per unit area. A first dummy pattern (first dummy pattern group) 18 whose sum is a third value is arranged (step S9). A template of the first dummy pattern 18 whose total perimeter per unit area is the third value is created in advance and stored in a storage unit (not shown) in the semiconductor design apparatus. When the first dummy pattern 18 is arranged in the third region 14a, the first dummy pattern 18 is arranged using a template of the first dummy pattern 18 created in advance. The third region 14a is a region where a dummy pattern 18 having a relatively large total perimeter per unit area is disposed. The total perimeter length (third value) of the dummy pattern 18 per unit area in the third region 14 a may not be significantly different from the total perimeter length of the wiring pattern 10 per unit area in the first region 12. preferable. For this reason, the difference between the first value (predetermined upper limit value) and the third value is set smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Is done.

The first dummy pattern 18 is, for example, a rectangular dummy pattern. More specifically, the first dummy pattern 18 is a square dummy pattern. The size (a ₁ × b ₁ ) of the first dummy pattern 18 is, for example, 125 nm × 125 nm. a ₁ is the length of the first dummy pattern 18 in the X direction, and b ₁ is the length of the first dummy pattern 18 in the Y direction. The intervals c ₁ and d ₁ between the first dummy patterns 18 adjacent to each other are, for example, about 75 nm. c ₁ is an interval between the first dummy patterns 18 in the X direction, and d ₁ is an interval between the first dummy patterns 18 in the Y direction.

The shape of the first dummy pattern 18 is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the first dummy pattern 18. In other words, the ratio of the length a ₁ to the length b ₁ in the first dummy pattern 18 may be set as appropriate within a range of 1: 0.2 to 1: 5. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  A total sum (third value) of the perimeters of the first dummy pattern 18 per unit area is set to about 5000 μm, for example. When the width of the dummy pattern region 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm.

  Next, in the region (dummy pattern region) 14 between the first region 12 and the second region 16, the fourth region 14b adjacent to the second region 16 has a perimeter per unit area. A second dummy pattern 20 having a sum total of the fourth value is arranged (step S10). A template of the second dummy pattern 20 is created in advance and stored in a storage unit in the semiconductor design apparatus. When the second dummy pattern 20 is arranged in the fourth region 14b, the second dummy pattern 20 is arranged using a template of the second dummy pattern 20 created in advance. The fourth region 14b is a region where the dummy pattern 20 having a relatively small total perimeter per unit area is disposed. The total perimeter length (fourth value) of the dummy pattern 20 per unit area in the fourth region 14 b may not be significantly different from the total perimeter length of the wiring pattern 10 per unit area in the second region 16. preferable. For this reason, the difference between the second value (predetermined lower limit value) and the fourth value is set smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Is done.

The second dummy pattern 20 is, for example, a rectangular dummy pattern. More specifically, the second dummy pattern 20 is a square dummy pattern. The size (a ₂ × b ₂ ) of the second dummy pattern 20 is, for example, 625 nm × 625 nm. a ₂ is the length of the second dummy pattern 20 in the X direction, and b ₂ is the length of the second dummy pattern 20 in the Y direction. The intervals c ₂ and d ₂ between the second dummy patterns 20 adjacent to each other are, for example, about 375 nm. c ₂ is an interval between the second dummy patterns 20 in the X direction, and d ₂ is an interval between the second dummy patterns 20 in the Y direction.

The shape of the second dummy pattern 20 is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the second dummy pattern 20. In other words, the ratio between the length a ₂ and the length b ₂ in the second dummy pattern 20 may be set as appropriate within a range of 1: 0.2 to 1: 5. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  A total sum (fourth value) of the perimeter of the second dummy pattern 20 per unit area is, for example, about 1000 μm. When the width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is about 100 μm, for example, the width of the fourth region 14b is about 20 μm, for example.

  Next, the third dummy pattern 22 in which the total perimeter per unit area is the fifth value is added to the fifth region 14c, which is the region between the third region 14a and the fourth region 14b. Arrange (step S11). The template of the third dummy pattern 22 is created in advance and stored in the storage unit in the semiconductor design apparatus. When the third dummy pattern 22 is arranged in the fifth region 14c, the third dummy pattern 22 is arranged using a template of the third dummy pattern 22 created in advance. The fifth region 14c is a region where the dummy pattern 22 having a medium total perimeter per unit area is disposed. In the fifth region 14c, the total perimeter length (fifth value) of the dummy pattern 22 per unit area is a value between the third value and the fourth value. For this reason, the difference between the third value and the fifth value is smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Further, the difference between the fourth value and the fifth value is smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value).

The third dummy pattern 22 is, for example, a rectangular dummy pattern. More specifically, the third dummy pattern 22 is a square dummy pattern. The size (a ₃ × b ₃ ) of the third dummy pattern 22 is, for example, 208 nm × 208 nm. a ₃ is the length of the third dummy pattern 22 in the X direction, and b ₃ is the length of the third dummy pattern 22 in the Y direction. The intervals c ₃ and d ₃ between the third dummy patterns 22 adjacent to each other are set to 124.8 nm, for example. c ₂ is the third dummy pattern 22 distance between the X-direction, d ₃ is the third dummy pattern 22 interval between the Y-direction.

The shape of the third dummy pattern 22 is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the third dummy pattern 22. In other words, the ratio of the length a ₃ and the length b ₃ in the third dummy pattern 22 may be set as appropriate within a range of 1: 0.2 to 1: 5. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  The total perimeter length (third value) of the third dummy pattern 22 per unit area is, for example, about 3000 μm. The width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm, and the width of the fourth region 14 b is, for example, In the case of about 20 μm, the width of the fifth region 14 c is about 60 μm, for example.

  Thus, the wiring pattern 10 and the dummy patterns 18, 20, 22 are laid out.

  Thereafter, the layout of contact holes formed in other insulating films, wiring patterns embedded in other insulating films, dummy patterns, and the like is performed.

  Thus, the semiconductor device according to the present embodiment is designed.

  A photomask (not shown) for forming the wiring pattern 10 and the dummy patterns 18, 20, and 22 is created based on the design data obtained in this way. Such a photomask is formed for each wiring layer. Since the wiring pattern 10 differs for each wiring layer, the positions and widths of the first region 12, the second region 16, the third region 14a, the fourth region 14b, and the fifth region 14c are photomasks. Different for each. Then, using such a photomask, a semiconductor device is manufactured as described later.

As described above, according to the present embodiment, a dummy pattern having a medium total perimeter per unit area is arranged between a region where the total perimeter of the wiring pattern per unit area is large and a small region. . For this reason, according to the present embodiment, it is possible to prevent a portion where the total perimeter per unit area is remarkably different from occurring, and to achieve uniform polishing progress. For this reason, according to the present embodiment, it is possible to prevent deep recesses from being formed on the surface of the interlayer insulating film when the wiring is embedded in the groove formed in the interlayer insulating film by polishing.
(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 14 and 16 to 30. 16 to 30 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment. 16 to 30 correspond to the regions 12 and 16 where the wiring pattern is formed in FIG. 14A. 16 to 30 correspond to the region 14 where the dummy pattern is formed in FIG. 14A.

  First, for example, a SiOC film (insulating film) 220 is formed on the entire surface of the semiconductor substrate 200 on which the element isolation region 202, the transistor 212, the conductor plug 218, the interlayer insulating film 214, and the like are formed. The SiOC film 220 is formed on the interlayer insulating film 214 in which the conductor plug 216 is embedded. The element isolation region 202 is formed by, for example, an STI (Shallow Trench Isolation) method. The transistor has a gate electrode 206 formed on a semiconductor substrate 200 via a gate insulating film 204, and source / drain diffusion layers 208 formed on both sides of the gate electrode 206. A sidewall insulating film 210 is formed on the side wall portion of the gate electrode 206. A contact hole 216 reaching the source / drain diffusion layer 208 is formed in the interlayer insulating film 214. A conductor plug 218 is embedded in the contact hole 216. For example, tungsten is used as the material of the conductor plug 218. As a material of the interlayer insulating film 214, for example, a silicon oxide film is used. The film thickness of the interlayer insulating film 214 is about 300 nm, for example. The film thickness of the SiOC film 220 is about 200 nm, for example.

  Next, a silicon oxide film (insulating film) 222 is formed on the entire surface by, eg, plasma CVD. The film thickness of the silicon oxide film 222 is, eg, about 100 nm. The silicon oxide film 222 functions as a polishing stopper in a subsequent process. Thus, the interlayer insulating film 224 is formed by the SiOC film 220 and the silicon oxide film 222.

  Next, a photoresist film 226 is formed on the entire surface by spin coating (see FIG. 16A).

  Next, the wiring pattern 10 (see FIG. 14B and FIG. 14C) and the dummy patterns 18, 20, and 22 (see FIG. 14D to FIG. 14F) are photolithographed by photolithography. Transfer to the resist film 226 (exposure). When the wiring pattern 10 and the dummy patterns 18, 20, and 22 are transferred to the photoresist film 226, a photomask (not shown) is used. Such a photomask is created using design data obtained by the semiconductor device design method according to the first embodiment described above with reference to FIGS.

  Next, the photoresist film 226 is developed to form openings 228 and 230 in the photoresist film 226 (see FIG. 16B). The opening 228 is for forming a wiring groove (wiring pattern groove) 232 in the interlayer insulating film 224. The opening 230 is for forming the dummy pattern groove 234 in the interlayer insulating film 224.

  Next, the interlayer insulating film 224 is etched using the photoresist film 226 as a mask. As a result, a wiring pattern groove 232 and a dummy pattern groove 234 are formed. In the first region 12 (see FIG. 14A), a wiring pattern groove 232 in which the total perimeter per unit area is equal to or greater than a predetermined upper limit (first value) is formed. In the second region 16 (see FIG. 14A), a wiring pattern groove 232 in which the total perimeter per unit area is equal to or smaller than a predetermined lower limit (second value) is formed. Of the dummy pattern region 14 between the first region 14 and the second region 16, the third region 14a (see FIG. 14A) adjacent to the first region 14 has a unit area. A dummy pattern groove 234 is formed in which the total perimeter of the hit is the third value. Among the regions between the first region 12 and the second region 14, the fourth region 14b adjacent to the second region 14 (see FIG. 14A) includes a per unit area. A dummy pattern groove 234 whose total length is a fourth value smaller than the third value is formed. In the fifth region 14c (see FIG. 14A) between the third region 14a and the fourth region 14b, the total perimeter per unit area is smaller than the third value, A dummy pattern groove 234 having a fifth value larger than 4 is formed.

  Thereafter, the photoresist film 226 is peeled off (see FIG. 17A).

  Next, a barrier film 236 is formed on the entire surface by, eg, sputtering. As the barrier film 236, for example, a Ta film is formed. The film thickness of the barrier film 236 is, for example, about 5 nm.

  Next, a seed layer 238 is formed on the entire surface by, eg, sputtering. As the seed layer 238, for example, a Cu film is formed. The thickness of the seed layer 238 is, for example, about 20 nm (see FIG. 17B).

  Next, a conductive film 240 is formed by electroplating (see FIG. 18). For example, a Cu film is formed as the conductive film 240. The film thickness of the conductive film 240 is about 700 nm, for example. Note that since the seed layer 238 becomes a part of the conductive film 240, the seed layer 238 is not illustrated in FIGS.

  Next, the conductive film 240 is polished by, eg, CMP. The polishing of the conductive film 240 is terminated when, for example, the upper layer portion of the silicon oxide film (insulating film) 222 is polished. Since the upper layer portion of the silicon oxide film 222 is polished, the thickness of the silicon oxide film 222 is about 30 nm, for example. Thus, the wiring (wiring pattern, first metal wiring layer) 242 formed by the conductive film 240 is embedded in the wiring pattern groove 232 (see FIG. 19). The wiring 242 corresponds to the wiring pattern 10 described above with reference to FIG. In the wiring 242, a dummy pattern 244 formed by the conductive film 240 is embedded in the dummy pattern groove 234. The dummy pattern 244 corresponds to the dummy patterns 18, 20, and 22 described above with reference to FIG.

  According to the present embodiment, a dummy pattern having a medium sum of perimeters per unit area is arranged between a region where the sum of perimeters of wiring patterns per unit area is large and a region where the sum is small. For this reason, according to this embodiment, it is possible to prevent a portion where the sum of the perimeters per unit area is significantly different from occurring. For this reason, according to the present embodiment, when the wiring 242 is embedded in the wiring pattern groove 232 formed in the interlayer insulating film by polishing, it is prevented that a deep recess is formed on the surface of the interlayer insulating film 22. be able to.

  Next, a cap film (insulating film) 246 is formed on the entire surface by, eg, CVD. For example, a SiCN film is formed as the cap film 246. The film thickness of the cap film 246 is about 20 nm, for example.

  Next, an SiOC film (insulating film) 248 is formed on the entire surface by, eg, CVD. The film thickness of the SiOC film 248 is about 400 nm, for example.

  Next, a silicon oxide film (insulating film) 250 is formed on the entire surface by, eg, plasma CVD. The film thickness of the silicon oxide film 250 is about 100 nm, for example. The silicon oxide film 250 functions as a polishing stopper in a subsequent process. Thus, the interlayer insulating film 252 is formed by the cap film 246, the SiOC film 248, and the silicon oxide film 250.

  Next, a photoresist film 254 is formed on the entire surface by spin coating (see FIG. 20). The film thickness of the photoresist film 254 is about 350 nm, for example.

  Next, an opening 256 having a shape of a contact hole 258 (see FIG. 22) is formed in the photoresist film 254 by using a photolithography technique (see FIG. 21).

  Next, the silicon oxide film 250 and the SiOC film 248 are etched using the photoresist film 254 as a mask and the cap film 246 as an etching stopper. Thereby, a contact hole reaching the cap film 246 is formed.

  Thereafter, the photoresist film 254 is removed (see FIG. 22).

  Next, a photoresist film 260 is formed on the entire surface by spin coating (see FIG. 23). The film thickness of the photoresist film 260 is about 300 nm, for example.

  Next, the wiring pattern and the dummy pattern are transferred to the photoresist film 260 by photolithography (exposure). When the wiring pattern and the dummy pattern are transferred to the photoresist film 260, a photomask (not shown) is used. Such a photomask is created using design data created by the semiconductor device design method according to the first embodiment described above with reference to FIGS. Note that the photomask used when transferring the wiring pattern or the like to the photoresist film 260 is different from the photomask used when transferring the wiring pattern or the like to the photoresist film 226 (see FIG. 16).

  Next, the photoresist film 260 is developed to form openings 262 and 264 in the photoresist film (see FIG. 24). The opening 262 is for forming a wiring pattern groove in the interlayer insulating film 252. The opening 264 is for forming a dummy pattern groove in the interlayer insulating film 252.

  Next, the interlayer insulating film 252 is etched using the photoresist film 260 as a mask (see FIG. 25). As a result, a wiring pattern groove (wiring groove) 266 and a dummy pattern groove 268 are formed. In the first region 12 (see FIG. 14A), a wiring pattern groove 266 in which the total perimeter per unit area is equal to or greater than a predetermined upper limit (first value) is formed. Since the pattern of the second metal wiring layer is different from the pattern of the first metal wiring layer, the first region 12 and the second layer of the first metal wiring layer are different. It does not necessarily coincide with the first region 12 in the metal wiring layer. In the second region 16 (see FIG. 14A), a wiring pattern groove 266 in which the total perimeter per unit area is equal to or less than a predetermined lower limit (second value) is formed. Since the pattern of the second metal wiring layer is different from the pattern of the first metal wiring layer, the second region 16 in the first metal wiring layer (FIG. 14A). And the second region 16 (see FIG. 14A) in the second metal wiring layer do not necessarily match.

  Of the regions between the first region 12 and the second region 16, the third region 14a (see FIG. 14A) adjacent to the first region 12 has a per unit area. A dummy pattern groove 268 whose total length is the third value is formed. Among the regions between the first region 12 and the second region 16, the fourth region 14b adjacent to the second region 16 (see FIG. 14A) has a per unit area. A dummy pattern groove 268 having a fourth sum whose total length is smaller than the third value is formed. In the fifth region 14c (see FIG. 14A) between the third region 14a and the fourth region 14b, the total perimeter per unit area is smaller than the third value, A dummy pattern groove 268 having a fifth value larger than 4 is formed.

  Thereafter, the photoresist film 260 is peeled off (see FIG. 26).

  Next, the cap film 246 is etched using the silicon oxide film 250 as a mask. As a result, the contact hole 258 is formed to reach the wiring 242 (see FIG. 27).

  Next, a barrier film 270 is formed on the entire surface by, eg, sputtering. As the barrier film 270, for example, a Ta film is formed. The film thickness of the barrier film 270 is about 5 nm, for example.

  Next, a seed layer 272 is formed on the entire surface by, eg, sputtering (see FIG. 28). As the seed layer 272, for example, a Cu film is formed. The thickness of the seed layer 272 is about 20 nm, for example.

  Next, a conductive film 274 is formed by electroplating (see FIG. 29). For example, a Cu film is formed as the conductive film 274. The film thickness of the conductive film 274 is, for example, about 700 nm. Note that the seed layer 272 is part of the conductive film 274, and thus the seed layer 272 is not illustrated in FIGS.

  Next, the conductive film 274 is polished by, eg, CMP (see FIG. 30). The polishing of the conductive film 274 is terminated when, for example, a part of the silicon oxide film 250 is polished. Since a part of the silicon oxide film 250 is polished, the thickness of the silicon oxide film 250 is, for example, about 30 nm. Thus, the wiring (wiring pattern, second metal wiring layer) 276 and the conductor plug 278 formed by the conductive film 274 are embedded in the wiring pattern groove 266 and the contact hole 258. The wiring 276 corresponds to the wiring pattern 10 described above with reference to FIG. A dummy pattern 280 formed of a conductive film 274 is embedded in the dummy pattern groove 268. The dummy pattern 280 corresponds to the dummy patterns 18, 20, and 22 described above with reference to FIG.

  According to the present embodiment, a dummy pattern having a medium total perimeter per unit area is arranged between a region where the total perimeter of the wiring pattern per unit area is large and a small region. For this reason, according to this embodiment, it is possible to prevent a portion where the sum of the perimeters per unit area is significantly different from occurring. Therefore, according to the present embodiment, when the wiring 276 is embedded in the wiring pattern groove 266 formed in the interlayer insulating film 252 by polishing, the formation of a deep recess in the surface of the interlayer insulating film 252 is prevented. can do.

  Thus, the semiconductor device according to the present embodiment is manufactured.

(Evaluation results)
Next, the evaluation results of the semiconductor device manufacturing method according to the present embodiment will be explained with reference to FIG. FIG. 31 is a diagram showing a step on the surface of the interlayer insulating film corresponding to the section GG ′ in FIG. 14.

  As shown in FIG. 31, the recesses formed on the surfaces of the interlayer insulating films 224 and 252 were relatively shallow, about 12 nm.

  From this, it can be seen that according to the present embodiment, it is possible to prevent the formation of deep recesses on the surfaces of the interlayer insulating films 224 and 252.

  As described above, according to the present embodiment, a dummy pattern having a medium total perimeter per unit area is arranged between a region where the total perimeter of the wiring pattern per unit area is large and a small region. . For this reason, according to this embodiment, it is possible to prevent a portion where the sum of the perimeters per unit area is significantly different from occurring. For this reason, according to the present embodiment, it is possible to prevent deep recesses from being formed on the surface of the interlayer insulating film when the wiring is embedded in the groove formed in the interlayer insulating film by polishing.

(Modification)
A semiconductor device design method and a semiconductor device manufacturing method according to a modification of the present embodiment will be described.

  First, a method for designing a semiconductor device according to this modification will be described with reference to FIGS. FIG. 32 is a plan view showing a method for designing a semiconductor device according to this modification. FIG. 32B is an enlarged view of a part of the region 12 in FIG. FIG. 32C is an enlarged view of a part of the region 16 in FIG. FIG. 32D is an enlarged view of a part of the region 14a in FIG. FIG. 32 (e) is an enlarged view of a part of the region 14c of FIG. 32 (a). FIG. 32F is an enlarged view of a part of the region 14b in FIG.

  The semiconductor device design method and the semiconductor device manufacturing method according to this modification are mainly characterized in that the linear dummy pattern is formed obliquely with respect to the wiring pattern.

  In this modification, the layout of the wiring pattern and dummy pattern embedded in the groove formed in the interlayer insulating film is performed as follows.

  First, the steps from the step of arranging the wiring pattern (step S1) to the step of extracting the second region (step S8) are the same as the method for designing a semiconductor device described above with reference to FIG. .

  Next, the first region 12 in which the total perimeter of the wiring pattern 10 per unit area is equal to or greater than a predetermined upper limit, and the total perimeter of the wiring pattern 10 per unit area is equal to or less than a predetermined lower limit. In the dummy pattern region 14 between the second region 16, dummy patterns 18, 20 and 22 are arranged as follows.

  First, of the region (dummy pattern region) 14 between the first region 12 and the second region 16, the third region 14a adjacent to the first region 12 has a perimeter per unit area. A first dummy pattern (first dummy pattern group) 18a whose sum is a third value is arranged (step S9). A template of the first dummy pattern 18a whose total perimeter per unit area is the third value is created in advance and stored in a storage unit (not shown) in the semiconductor design apparatus. When the first dummy pattern 18a is arranged in the third region 14a, the first dummy pattern 18 is arranged using a template of the first dummy pattern 18a created in advance. The third region 14a is a region where a dummy pattern 18a having a relatively large total perimeter per unit area is disposed. The total perimeter length (third value) of the dummy pattern 18a per unit area in the third region 14a may not be significantly different from the total perimeter length of the wiring pattern 10 per unit area in the first region 12. preferable. For this reason, the difference between the first value (predetermined upper limit value) and the third value is set smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Is done.

The first dummy pattern 18a is a linear dummy pattern. The width L1 of the _first dummy pattern 18a is, for example, 70 nm. Mutually spacing _{S 1} between the first dummy patterns 18a to adjacent, and each example 90nm or so. The angle formed between the longitudinal direction of the first dummy pattern 18a and the longitudinal direction of the wiring pattern 10 is, for example, 45 degrees. The reason why the dummy pattern 18a is arranged obliquely with respect to the wiring pattern 10 is to suppress crosstalk with the wiring pattern 10 provided on the upper layer side, the lower layer side or the same layer with respect to the dummy pattern 18a.

  The total perimeter of the first dummy pattern 18a per unit area (third value) is, for example, about 5000 μm. When the width of the dummy pattern region 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm.

  Next, in the region (dummy pattern region) 14 between the first region 12 and the second region 16, the fourth region 14b adjacent to the second region 16 has a pattern per unit area. A second dummy pattern 20a whose total length is the fourth value is arranged (step S10). The template of the second dummy pattern 20a is created in advance and stored in the storage unit in the semiconductor design apparatus. When the second dummy pattern 20a is arranged in the fourth region 14b, the second dummy pattern 20a is arranged using a template of the second dummy pattern 20a created in advance. The fourth region 14b is a region where a dummy pattern 20a having a relatively small total perimeter per unit area is disposed. The total perimeter length (fourth value) of the dummy pattern 20 per unit area in the fourth region 14 b may not be significantly different from the total perimeter length of the wiring pattern 10 per unit area in the second region 16. preferable. For this reason, the difference between the second value (predetermined lower limit value) and the fourth value is set smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Is done.

The second dummy pattern 20a is a linear dummy pattern. The width L2 of the _second dummy pattern 20a is, for example, 70 nm. Mutually spacing _{S 2} between the second dummy patterns 20a to adjacent, and each example 730nm approximately. The angle formed between the longitudinal direction of the second dummy pattern 20a and the longitudinal direction of the wiring pattern 10 is, for example, 45 degrees. The reason why the dummy pattern 20a is arranged obliquely with respect to the wiring pattern 10 is to suppress crosstalk with the wiring pattern 10 provided on the upper layer side, the lower layer side or the same layer with respect to the dummy pattern 20a.

  The total perimeter of the second dummy pattern 20a per unit area (fourth value) is, for example, about 1000 μm. When the width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is about 100 μm, for example, the width of the fourth region 14b is about 20 μm, for example.

  Next, a third dummy pattern 22a having a total sum of perimeters per unit area of a fifth value is added to the fifth region 14c, which is a region between the third region 14a and the fourth region 14b. Arrange (step S11). A template of the third dummy pattern 22a is created in advance and stored in a storage unit in the semiconductor design apparatus. When the third dummy pattern 22a is arranged in the fifth region 14c, the third dummy pattern 22a is arranged using a template of the third dummy pattern 22a created in advance. The fifth region 14c is a region where a dummy pattern 22a having a medium sum of perimeters per unit area is disposed. In the fifth region 14c, the total perimeter length (fifth value) of the dummy pattern 22a per unit area is a value between the third value and the fourth value. For this reason, the difference between the third value and the fifth value is smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value). Further, the difference between the fourth value and the fifth value is smaller than the difference between the first value (predetermined upper limit value) and the second value (predetermined lower limit value).

The third dummy pattern 22a is a linear dummy pattern. The width L3 of the _third dummy pattern 22a is, for example, 70 nm. Mutually spacing _{S 3} between the third dummy pattern 22a of the adjacent, and each example 197nm approximately. The angle formed between the longitudinal direction of the third dummy pattern 22a and the longitudinal direction of the wiring pattern 10 is, for example, 45 degrees. The reason why the dummy pattern 22a is arranged obliquely with respect to the wiring pattern 10 is to suppress crosstalk with the wiring pattern 10 provided on the upper layer side, the lower layer side or the same layer with respect to the dummy pattern 22a.

  The total perimeter length (third value) of the third dummy pattern 22a per unit area is, for example, about 3000 μm. The width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm, and the width of the fourth region 14 b is, for example, In the case of about 20 μm, the width of the fifth region 14 c is about 60 μm, for example.

  Thus, the wiring pattern 10 and the dummy patterns 18a, 20a, and 22a are laid out.

  Thereafter, the layout of contact holes formed in other insulating films, wiring patterns embedded in other insulating films, dummy patterns, and the like is performed.

  Thus, the semiconductor device according to the present embodiment is designed.

  Based on the design data obtained in this manner, a photomask (not shown) for forming the wiring pattern 10 and the dummy patterns 18a, 20a, and 22a is created. Such a photomask is formed for each wiring layer. Since the wiring pattern 10 differs for each wiring layer, the positions and widths of the first region 12, the second region 16, the third region 14a, the fourth region 14b, and the fifth region 14c are photomasks. Different for each.

  Then, using such a photomask as appropriate, the semiconductor device according to the present modification is manufactured in the same manner as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

[Second Embodiment]
A semiconductor device design method and a semiconductor device manufacturing method according to the second embodiment will be described with reference to FIGS. The same components as those in the semiconductor device designing method and the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 14 to 32 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device design method and the semiconductor device manufacturing method according to the present embodiment are mainly arranged such that the dummy patterns 18b, 20b, and 22b are arranged so that the difference in the total perimeter of the pattern per unit area becomes smaller. There is a special feature.

  First, the semiconductor device design method according to the present embodiment will be explained with reference to FIGS. FIG. 33 is a plan view of the semiconductor device design method according to the present embodiment. FIG. 33B is an enlarged view of a part of the region 12 in FIG. FIG. 33C is an enlarged view of a part of the region 16 in FIG. FIG. 33 (d) is an enlarged view of a part of the region 14a of FIG. 33 (a). FIG. 33 (e) is an enlarged view of a part of the region 14c of FIG. 33 (a). FIG. 33 (f) is an enlarged view of a part of the region 14b of FIG. 33 (a).

  In the present embodiment, the layout of the wiring pattern and the dummy pattern embedded in the groove formed in the interlayer insulating film is performed as follows.

  First, the steps from the step of arranging the wiring pattern (step S1) to the step of extracting the second region (step S8) are the same as the method for designing a semiconductor device described above with reference to FIG. .

  Next, the first region 12 in which the total perimeter of the wiring pattern 10 per unit area is equal to or greater than a predetermined upper limit, and the total perimeter of the wiring pattern 10 per unit area is equal to or less than a predetermined lower limit. Dummy patterns 18b, 20b, and 22b are arranged in the dummy pattern region 14 between the second region 16 as follows.

  First, in the region (dummy pattern region) 14 between the first region 12 and the second region 16, the third region 14a adjacent to the first region 12 has a perimeter per unit area. A first dummy pattern (first dummy pattern group) 18b whose sum is a third value is arranged (step S9). A template of the first dummy pattern 18b whose total perimeter per unit area is a third value is created in advance and stored in a storage unit (not shown) in the semiconductor design apparatus. When the first dummy pattern 18b is arranged in the third region 14a, the first dummy pattern 18 is arranged using a template of the first dummy pattern 18b created in advance. The third region 14a is a region where a dummy pattern 18b having a relatively large total perimeter per unit area is disposed. In order to further reduce the difference in the total perimeter of the pattern per unit area, the total perimeter (third value) of the dummy pattern 18b per unit area in the third region 14a is set to the first value. It is preferably smaller and larger than the fifth value. The first value is the total sum of the perimeters of the wiring pattern 10 per unit area in the first region 12. The fifth value is the sum of the perimeters of the wiring pattern 22b per unit area in the fifth region 14c. For this reason, the difference between the first value (predetermined upper limit value) and the third value is set smaller than the difference between the first value (predetermined upper limit value) and the fifth value.

The first dummy pattern 18b is, for example, a rectangular dummy pattern. More specifically, the first dummy pattern 18b is a square dummy pattern. The size (a ₄ × b ₄ ) of the first dummy pattern 18b is, for example, 100 nm × 100 nm. a ₄ is the length of the first dummy pattern 18b in the X-direction, _{b 4} is the length of the first dummy pattern 18b in the Y direction. The intervals c ₄ and d ₄ between the first dummy patterns 18b adjacent to each other are set to, for example, about 100 nm. c ₄ is the distance between the first dummy pattern 18b in the X-direction, _{d 4} is the first dummy pattern 18b interval between the Y-direction.

The shape of the first dummy pattern 18b is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the first dummy pattern 18b. In other words, the ratio of the first length of the dummy pattern 18b _{a 4} and a length _{b 4,} 1: 0.2 to 1: in the range of 5 may be set as appropriate. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  The total sum (third value) of the perimeter of the first dummy pattern 18b per unit area is, for example, about 4000 μm. When the width of the dummy pattern region 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm.

  Next, in the region (dummy pattern region) 14 between the first region 12 and the second region 16, the fourth region 14b adjacent to the second region 16 has a pattern per unit area. A second dummy pattern 20b whose total length is the fourth value is arranged (step S10). The template of the second dummy pattern 20b is created in advance and stored in the storage unit in the semiconductor design apparatus. When the second dummy pattern 20b is arranged in the fourth region 14b, the second dummy pattern 20b is arranged using a template of the second dummy pattern 20b created in advance. The fourth region 14b is a region where a dummy pattern 20b having a relatively small total perimeter per unit area is disposed. In order to further reduce the difference in the total perimeter of the pattern per unit area, the total perimeter (fourth value) of the dummy pattern 20b per unit area in the fourth region 14b is set to the second value. It is preferably larger and smaller than the fifth value. The second value is the total sum of the perimeters of the wiring pattern 10 per unit area in the second region 16. For this reason, the difference between the second value (predetermined lower limit value) and the fourth value is set smaller than the difference between the second value (predetermined lower limit value) and the fifth value.

The second dummy pattern 20b is, for example, a rectangular dummy pattern. More specifically, the second dummy pattern 20b is a square dummy pattern. The size (a ₅ × b ₅ ) of the second dummy pattern 20b is, for example, 100 nm × 100 nm. a ₅ is the length of the second dummy pattern 20b in the X-direction, _{b 5} is the length of the second dummy pattern 20b in the Y direction. The intervals c ₅ and d ₅ between the second dummy patterns 20b adjacent to each other are, for example, about 300 nm. c ₅ is the spacing between the second dummy pattern 20b in the X-direction, _{d 5} is the distance between the second dummy pattern 20b in the Y direction.

The shape of the second dummy pattern 20b is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the second dummy pattern 20b. In other words, the ratio of the length _{a 5} and a length _{b 5} of the second dummy pattern 20b, 1: 0.2 to 1: in the range of 5 may be set as appropriate. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  The total sum (fourth value) of the perimeter of the second dummy pattern 20b per unit area is, for example, about 4000 μm. When the width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is about 100 μm, for example, the width of the fourth region 14b is about 20 μm, for example.

  Next, a third dummy pattern 22b whose total perimeter per unit area is a fifth value is added to the fifth region 14c, which is a region between the third region 14a and the fourth region 14b. Arrange (step S11). The template of the third dummy pattern 22b is created in advance and stored in the storage unit in the semiconductor design apparatus. When the third dummy pattern 22b is arranged in the fifth region 14c, the third dummy pattern 22b is arranged using a template of the third dummy pattern 22a created in advance. In order to further reduce the difference in the total perimeter of the pattern per unit area, the total perimeter (fifth value) of the dummy pattern 22b per unit area in the fifth region 14c is set to the third value. It is preferably smaller and larger than the fourth value. For this reason, the difference between the third value and the fifth value is smaller than the difference between the third value and the fourth value. Further, the difference between the fourth value and the fifth value is smaller than the difference between the third value and the fourth value.

The third dummy pattern 22b is, for example, a rectangular dummy pattern. More specifically, the third dummy pattern 22b is a square dummy pattern. The size (a ₅ × b ₅ ) of the third dummy pattern 22b is, for example, 100 nm × 100 nm. a ₆ is the length of the third dummy pattern 22b in the X-direction, _{b 6} is a length of the third dummy pattern 22b in the Y direction. The intervals c ₆ and d ₆ between the third dummy patterns 22b adjacent to each other are, for example, about 130 nm. c ₆ is an interval between the third dummy pattern 22b in the X-direction, _{d 6} is the third dummy pattern 22b interval between the Y-direction.

The shape of the third dummy pattern 22b is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the third dummy pattern 22b. In other words, the ratio of the third length of the dummy pattern 22b _{a 6} and length _{b 6,} 1: _0.2~1: in the range of 5 may be set as appropriate. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  A total sum (fifth value) of the perimeter of the third dummy pattern 22b per unit area is, for example, about 3000 μm. The width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 20 μm, and the width of the fourth region 14 b is, for example, In the case of about 20 μm, the width of the fifth region 14 c is about 60 μm, for example.

  Thus, the wiring pattern 10 and the dummy patterns 18b, 20b, and 22b are laid out.

  Thereafter, the layout of contact holes formed in other insulating films, wiring patterns embedded in other insulating films, dummy patterns, and the like is performed.

  Thus, the semiconductor device according to the present embodiment is designed.

  Based on the design data thus obtained, a photomask (not shown) for forming the wiring pattern 10 and the dummy patterns 18b, 20b, and 22b is created. Such a photomask is formed for each wiring layer. Since the wiring pattern 10 differs for each wiring layer, the positions and widths of the first region 12, the second region 16, the third region 14a, the fourth region 14b, and the fifth region 14c are photomasks. Different for each.

  Then, using the photomask as appropriate, the semiconductor device according to the present embodiment is manufactured in the same manner as the method for manufacturing the semiconductor device according to the first embodiment described above with reference to FIGS.

  As described above, the dummy patterns 18b, 20b, and 22b may be arranged so that the difference in the total perimeter of the pattern per unit area becomes smaller. According to the present embodiment, since the difference in the total perimeter of the pattern per unit area becomes smaller, it is possible to more reliably prevent deep recesses from being formed on the surface of the interlayer insulating film.

[Third Embodiment]
A semiconductor device design method and a semiconductor device manufacturing method according to the third embodiment will be described with reference to FIGS. The same components as those in the semiconductor device designing method and the semiconductor device manufacturing method according to the first or second embodiment shown in FIGS. 14 to 33 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device design method and the semiconductor device manufacturing method according to the present embodiment are mainly characterized in that the dummy pattern region 14 is formed by the third region 14d and the fourth region 14e. In the third region 14d adjacent to the first region 12, a dummy pattern 18c having a total value of the perimeter per unit area smaller than the first value and a third value larger than the second value is arranged. Is done. In the fourth region 14e between the third region 14d and the second region 16, the total perimeter per unit area is smaller than the third value and larger than the second value. A dummy pattern 20c having a value of is arranged. The first value is the total sum of the perimeters of the wiring pattern 10 per unit area in the first region 12. The second value is the sum of the perimeters of the wiring pattern 10 per unit area in the second region 16.

(Semiconductor device design method)
First, the semiconductor device design method according to the present embodiment will be explained with reference to FIGS. FIG. 34 is a plan view of the semiconductor device design method according to the present embodiment. FIG. 34 (b) is an enlarged view of a part of the region 12 in FIG. 34 (a). FIG. 34C is an enlarged view of a part of the region 16 in FIG. FIG. 34 (d) is an enlarged view of a part of the region 14d of FIG. 34 (a). FIG. 34 (e) is an enlarged view of a part of the region 14e of FIG. 34 (a).

  In the present embodiment, the layout of the wiring pattern and the dummy pattern embedded in the groove formed in the interlayer insulating film is performed as follows.

  First, the steps from the step of arranging the wiring pattern (step S21) to the step of extracting the second region (step S28) are the same as steps S1 to S8 of the semiconductor device design method described above with reference to FIG. Therefore, the description is omitted.

  Next, the first region 12 in which the total perimeter of the wiring pattern 10 per unit area is equal to or greater than a predetermined upper limit, and the total perimeter of the wiring pattern 10 per unit area is equal to or less than a predetermined lower limit. In the dummy pattern region 14 between the second region 16, dummy patterns 18 c and 20 c are arranged as follows.

  First, in the region (dummy pattern region) 14 between the first region 10 and the second region 12, the third region 14d adjacent to the first region 12 has a perimeter per unit area. A first dummy pattern (first dummy pattern group) 18c whose sum is a third value is arranged (step S29). A template of the first dummy pattern 18c in which the total perimeter per unit area is a third value is created in advance and stored in a storage unit (not shown) in the semiconductor design apparatus. When the first dummy pattern 18c is arranged in the third region 14d, the first dummy pattern 18c is arranged using a template of the first dummy pattern 18c created in advance. In the third region 14d, the total perimeter per unit area is set to a third value that is smaller than the first value and larger than the fourth value. The first value is the total sum of the perimeters of the wiring pattern 10 per unit area in the first region 12. The fourth value is the total sum of the perimeters of the dummy patterns 20c per unit area in the fourth region 14e.

The first dummy pattern 18c is, for example, a rectangular dummy pattern. More specifically, the first dummy pattern 18c is a square dummy pattern. The size (a ₇ × b ₇ ) of the first dummy pattern 18 is, for example, 100 nm × 100 nm. a ₇ is a length of the first dummy patterns 18c in the X-direction, _{b 7} is the length of the first dummy patterns 18c in the Y direction. The intervals c ₇ and d ₇ between the first dummy patterns 18c adjacent to each other are set to, for example, about 114 nm. c ₇ is a first dummy pattern 18c interval between the X-direction, _{d 7} is a first dummy pattern 18c interval between the Y-direction.

Note that the shape of the first dummy pattern 18c is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the first dummy pattern 18c. In other words, the ratio of the first dummy pattern length _{a 7} in 18c and length _{b 7,} 1: 0.2 to 1: in the range of 5 may be set as appropriate. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  The total perimeter of the first dummy pattern 18c per unit area (third value) is, for example, about 3500 μm. When the width of the dummy pattern region 14 between the first region 12 and the second region 16 is, for example, about 100 μm, the width of the third region 14 a is, for example, about 50 μm.

  Next, of the region (dummy pattern region) 14 between the first region 12 and the second region 16, the fourth region 14e adjacent to the second region 16 has a perimeter per unit area. The second dummy pattern 20c having the fourth sum is arranged (step S30). A template of the second dummy pattern 20c is created in advance and stored in a storage unit in the semiconductor design apparatus. When the second dummy pattern 20c is arranged in the fourth region 14e, the second dummy pattern 20c is arranged using a template of the second dummy pattern 20c created in advance. In the fourth region 14e, the sum of the perimeters per unit area is set to a fourth value that is smaller than the third value and larger than the second value.

The second dummy pattern 20c is, for example, a rectangular dummy pattern. More specifically, the second dummy pattern 20c is a square dummy pattern. The size (a ₈ × b ₈ ) of the second dummy pattern 20c is, for example, 100 nm × 100 nm. a ₈ is the length of the second dummy patterns 20c in the X-direction, _{b 8} is the length of the second dummy patterns 20c in the Y direction. The intervals c ₈ and d ₈ between the second dummy patterns 20c adjacent to each other are, for example, about 180 nm. c ₈ is the spacing between the second dummy patterns 20c in the X-direction, _{d 8} is the spacing between the second dummy patterns 20c in the Y direction.

Note that the shape of the second dummy pattern 20c is not limited to a square. For example, a rectangular pattern in which the ratio of the short side to the long side is 1: 1 to 1: 5 may be appropriately used as the second dummy pattern 20c. In other words, the ratio of the second dummy length in the pattern 20c _{a 8} and length _{b 8,} 1: _0.2~1: in the range of 5 may be set as appropriate. Thus, if the ratio between the short side and the long side is set to be relatively small, crosstalk can be sufficiently suppressed.

  The total perimeter of the second dummy pattern 20c per unit area (fourth value) is, for example, about 2000 μm. When the width of the region (dummy pattern region) 14 between the first region 12 and the second region 16 is about 100 μm, for example, the width of the fourth region 14b is about 50 μm, for example.

  Thus, the wiring pattern 10 and the dummy patterns 18c and 20c are laid out.

  Thereafter, the layout of contact holes formed in other insulating films, wiring patterns embedded in other insulating films, dummy patterns, and the like is performed.

  Thus, the semiconductor device according to the present embodiment is designed.

  Based on the design data thus obtained, a photomask (not shown) for forming the wiring pattern 10 and the dummy patterns 18c and 20c is created. Such a photomask is formed for each wiring layer. Since the wiring pattern 10 differs for each wiring layer, the positions and widths of the first region 12, the second region 16, the third region 14d, and the fourth region 14ec differ for each photomask. Then, using such a photomask, a semiconductor device is manufactured as described later.

  As described above, the dummy pattern region 14 may be formed by the third region 14d and the fourth region 14e. Also in this embodiment, since the difference in the total perimeter of the pattern per unit area can be made relatively small, it is possible to prevent deep recesses from being formed on the surface of the interlayer insulating film.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the second and third embodiments, the case where the rectangular dummy patterns 18b, 18c, 20b, 20c, and 22b are formed has been described as an example. However, the rectangular dummy patterns 18b, 18c, 20b, 20c, and 22b are limited. Is not to be done. Also in the second and third embodiments, as in the modification of the first embodiment, the dummy pattern may be linear, and the linear dummy pattern may be arranged obliquely with respect to the wiring pattern.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
Placing a wiring pattern within a predetermined layout area;
Dividing the layout region into unit regions of a predetermined unit area;
Calculating the total perimeter of the wiring pattern per unit area for each unit region;
Extracting a first region in which the sum of the perimeters of the wiring pattern in the unit region is equal to or greater than a first value which is a predetermined upper limit value;
Extracting a second region in which the total perimeter of the wiring pattern in the unit region is equal to or less than a second value which is a predetermined lower limit;
Of the regions between the first region and the second region, the third region adjacent to the first region has a third sum of the perimeters per unit area. Placing a first dummy pattern;
A total sum of perimeters per unit area in the fourth region adjacent to the second region in the region between the first region and the second region is the third value. Placing a second dummy pattern having a smaller fourth value;
In a fifth region between the third region and the fourth region, a total sum of perimeters per unit area is smaller than the third value and larger than the fourth value. And a step of arranging a third dummy pattern having a value of.

(Appendix 2)
In the method for designing a semiconductor device according to attachment 1,
The third value is less than the first value;
The method for designing a semiconductor device, wherein the fourth value is greater than the second value.

(Appendix 3)
In the method for designing a semiconductor device according to attachment 1 or 2,
The difference between the first value and the third value is smaller than the difference between the first value and the second value,
The difference between the second value and the fourth value is smaller than the difference between the first value and the second value,
The difference between the third value and the fifth value is smaller than the difference between the first value and the second value,
The difference between the fourth value and the fifth value is smaller than the difference between the first value and the second value.

(Appendix 4)
In the method for designing a semiconductor device according to any one of appendices 1 to 3,
The method for designing a semiconductor device, wherein the first dummy pattern, the second dummy pattern, and the third dummy pattern are rectangular dummy patterns, respectively.

(Appendix 5)
In the method for designing a semiconductor device according to any one of appendices 1 to 3,
The first dummy pattern, the second dummy pattern, and the third dummy pattern are each a linear dummy pattern,
The longitudinal direction of the first dummy pattern, the longitudinal direction of the second dummy pattern, and the longitudinal direction of the third dummy pattern are each oblique to the longitudinal direction of the wiring pattern. Device design method.

(Appendix 6)
Placing a wiring pattern within a predetermined layout area;
Dividing the layout region into unit regions of a predetermined unit area;
Calculating the total perimeter of the wiring pattern per unit area for each unit region;
Extracting a first region in which the sum of the perimeters of the wiring pattern in the unit region is equal to or greater than a first value which is a predetermined upper limit value;
Extracting a second region in which the total perimeter of the wiring pattern in the unit region is equal to or less than a second value which is a predetermined lower limit;
Of the regions between the first region and the second region, a third region adjacent to the first region has a sum of perimeters per unit area as the first region. Placing a first dummy pattern that is less than a value and a third value greater than the second value;
In a fourth region between the third region and the second region, a total sum of perimeters per unit area is smaller than the third value and larger than the second value. And a step of arranging a second dummy pattern having a value of.

(Appendix 7)
In the method for designing a semiconductor device according to attachment 7,
The method for designing a semiconductor device, wherein the first dummy pattern and the second dummy pattern are rectangular dummy patterns, respectively.

(Appendix 8)
In the method for designing a semiconductor device according to any one of appendices 1 to 7,
Each of the first dummy pattern and the second dummy pattern is a linear dummy pattern,
The method of designing a semiconductor device, wherein a longitudinal direction of the first dummy pattern and a longitudinal direction of the second dummy pattern are respectively inclined with respect to a longitudinal direction of the wiring pattern.

(Appendix 9)
Forming a wiring groove for embedding the wiring and a dummy pattern groove for embedding the dummy pattern in the insulating film;
Forming a conductive film in the wiring groove, in the dummy pattern groove and on the insulating film;
The conductive film is polished until the insulating film is exposed, and the wiring of the conductive film embedded in the wiring groove and the dummy pattern of the conductive film embedded in the dummy pattern groove are formed. A process,
In the step of forming the wiring groove and the dummy pattern groove, the wiring groove whose total perimeter per unit area is equal to or greater than a first value which is a predetermined upper limit value is in the first region. The wiring groove is formed in a second region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value, and is formed in the second region. The dummy pattern groove having a total perimeter of the unit area of a third value is formed in a third region adjacent to the first region among regions between the two regions. In the fourth region adjacent to the second region among the regions between the first region and the second region, the total perimeter per unit area is the third region. Forming the dummy pattern groove having a fourth value smaller than the value of the third region and the fourth region. In the fifth region between the regions, the dummy pattern groove in which the total perimeter per unit area is a fifth value smaller than the third value and larger than the fourth value. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device.

(Appendix 10)
In the method for manufacturing a semiconductor device according to attachment 9,
The third value is less than the first value;
The method for manufacturing a semiconductor device, wherein the fourth value is greater than the second value.

(Appendix 11)
Forming a wiring groove for embedding the wiring and a dummy pattern groove for embedding the dummy pattern in the insulating film;
Forming a conductive film in the wiring groove, in the dummy pattern groove and on the insulating film;
The conductive film is polished until the insulating film is exposed, and the wiring of the conductive film embedded in the wiring groove and the dummy pattern of the conductive film embedded in the dummy pattern groove are formed. A process,
In the step of forming the wiring groove and the dummy pattern groove, the wiring groove whose total perimeter per unit area is equal to or greater than a first value which is a predetermined upper limit value is in the first region. The wiring groove is formed in a second region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value, and is formed in the second region. In a third region adjacent to the first region among the regions between the two regions, a total perimeter per unit area is smaller than the first value, and the second region Forming the dummy pattern groove having a third value larger than the value, and in the fourth region between the third region and the second region, the total perimeter of the unit area is Forming the dummy pattern groove having a fourth value smaller than the third value and larger than the second value; The method of manufacturing a semiconductor device, characterized in that that.

DESCRIPTION OF SYMBOLS 10 ... Wiring pattern 12 ... 1st area | region 14 ... Dummy pattern area | region 14a ... 3rd area | region 14b ... 4th area | region 14c ... 5th area | region 14d ... 3rd area | region 14e ... 4th area | region 16 ... 2nd Regions 18, 18a to 18c ... Dummy patterns 20, 20a to 20c ... Dummy patterns 22, 22a, 22b ... Dummy pattern 100 ... High density region 102 ... Low density region 104 ... Dummy pattern region 106 ... Wiring pattern 108 ... Wiring pattern 110 ... Dummy pattern 112 ... recess 114 ... wiring pattern region 116 ... dummy pattern region 118 ... recess 120 ... dummy pattern 122 ... recess 124 ... dummy pattern 126 ... recess 128 ... dummy pattern 130 ... recess 132 ... dummy pattern 134 ... recess 200 ... semiconductor substrate 202 ... Element isolation region 204 ... Gate insulating film 2 6 ... Gate electrode 208 ... Source / drain diffusion layer 210 ... Side wall insulating film 212 ... Transistor 214 ... Interlayer insulating film 216 ... Contact hole 218 ... Conductor plug 220 ... SiOC film 222 ... Silicon oxide film 224 ... Interlayer insulating film 226 ... Photo Resist film 228 ... opening 230 ... opening 232 ... wiring pattern groove 234 ... dummy pattern groove 236 ... barrier film 238 ... seed layer 240 ... conductive film 242 ... wiring 244 ... dummy pattern 246 ... cap film 248 ... SiOC film 250 ... Silicon oxide film 252 ... Interlayer insulating film 254 ... Photoresist film 256 ... Opening portion 258 ... Contact hole 260 ... Photoresist film 262 ... Opening portion 264 ... Opening portion 266 ... Wiring groove 268 ... Dummy pattern groove 270 ... Barrier film 272 ... Seed layer 274 ... Film 276 ... wiring 278 ... conductor plug 280 ... dummy pattern

Claims (5)

Placing a wiring pattern within a predetermined layout area;
Dividing the layout region into unit regions of a predetermined unit area;
Calculating the total perimeter of the wiring pattern per unit area for each unit region;
Extracting a first region in which the sum of the perimeters of the wiring pattern in the unit region is equal to or greater than a first value which is a predetermined upper limit value;
Extracting a second region in which the total perimeter of the wiring pattern in the unit region is equal to or less than a second value which is a predetermined lower limit;
Of the regions between the first region and the second region, the third region adjacent to the first region has a third sum of the perimeters per unit area. Placing a first dummy pattern;
A total sum of perimeters per unit area in the fourth region adjacent to the second region in the region between the first region and the second region is the third value. Placing a second dummy pattern having a smaller fourth value;
In a fifth region between the third region and the fourth region, a total sum of perimeters per unit area is smaller than the third value and larger than the fourth value. And a step of arranging a third dummy pattern having a value of. The method of designing a semiconductor device according to claim 1,
The third value is less than the first value;
The method for designing a semiconductor device, wherein the fourth value is greater than the second value. Placing a wiring pattern within a predetermined layout area;
Dividing the layout region into unit regions of a predetermined unit area;
Calculating the total perimeter of the wiring pattern per unit area for each unit region;
Extracting a first region in which the sum of the perimeters of the wiring pattern in the unit region is equal to or greater than a first value which is a predetermined upper limit value;
Extracting a second region in which the total perimeter of the wiring pattern in the unit region is equal to or less than a second value which is a predetermined lower limit;
Of the regions between the first region and the second region, a third region adjacent to the first region has a sum of perimeters per unit area as the first region. Placing a first dummy pattern that is less than a value and a third value greater than the second value;
In a fourth region between the third region and the second region, a total sum of perimeters per unit area is smaller than the third value and larger than the second value. And a step of arranging a second dummy pattern having a value of. Forming a wiring groove for embedding the wiring and a dummy pattern groove for embedding the dummy pattern in the insulating film;
Forming a conductive film in the wiring groove, in the dummy pattern groove and on the insulating film;
The conductive film is polished until the insulating film is exposed, and the wiring of the conductive film embedded in the wiring groove and the dummy pattern of the conductive film embedded in the dummy pattern groove are formed. A process,
In the step of forming the wiring groove and the dummy pattern groove, the wiring groove whose total perimeter per unit area is equal to or greater than a first value which is a predetermined upper limit value is in the first region. The wiring groove is formed in a second region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value, and is formed in the second region. The dummy pattern groove having a total perimeter of the unit area of a third value is formed in a third region adjacent to the first region among regions between the two regions. In the fourth region adjacent to the second region among the regions between the first region and the second region, the total perimeter per unit area is the third region. Forming the dummy pattern groove having a fourth value smaller than the value of the third region and the fourth region. In the fifth region between the regions, the dummy pattern groove in which the total perimeter per unit area is a fifth value smaller than the third value and larger than the fourth value. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. Forming a wiring groove for embedding the wiring and a dummy pattern groove for embedding the dummy pattern in the insulating film;
Forming a conductive film in the wiring groove, in the dummy pattern groove and on the insulating film;
The conductive film is polished until the insulating film is exposed, and the wiring of the conductive film embedded in the wiring groove and the dummy pattern of the conductive film embedded in the dummy pattern groove are formed. A process,
In the step of forming the wiring groove and the dummy pattern groove, the wiring groove whose total perimeter per unit area is equal to or greater than a first value which is a predetermined upper limit value is in the first region. The wiring groove is formed in a second region, and the sum of the perimeters per unit area is equal to or less than a second value that is a predetermined lower limit value, and is formed in the second region. In a third region adjacent to the first region among the regions between the two regions, a total perimeter per unit area is smaller than the first value, and the second region Forming the dummy pattern groove having a third value larger than the value, and in the fourth region between the third region and the second region, the total perimeter of the unit area is Forming the dummy pattern groove having a fourth value smaller than the third value and larger than the second value; The method of manufacturing a semiconductor device, characterized in that that.

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