JP2011054772A - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of reducing a soft error rate without increasing parasitic capacitance is provided.
A first conductivity type well formed on a main surface of a semiconductor substrate; a transistor formed on the surface of the first conductivity type well; an element isolation insulating region formed on the main surface of the semiconductor substrate; The first conductivity type is formed on the surface of the one conductivity type well with the transistor and the element isolation insulating region being spaced apart, the depth of the bottom surface is approximately equal to the bottom surface of the element isolation insulation region, and the impurity concentration is higher than that of the first conductivity type well. A high concentration region, and a well contact electrode formed on a surface of the first conductivity type high concentration region.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including a fine transistor that is affected by radiation irradiation or the like.

  In semiconductor devices and LSIs, ionized secondary particles generated by collision of α-rays generated by decay of radioactive elements in package fillers and neutrons falling from the universe onto the ground (for example, silicon) in semiconductor substrates It is known that soft errors are caused by charged particles. That is, when the charged particles travel in the semiconductor substrate, electron / hole pairs are generated along the tracks, and the electrons or holes are collected in the diffusion layer of the semiconductor device. At that time, in a logic circuit in the semiconductor device, a logic error occurs when bit “1” is inverted to “0” or “0” is “1”.

  At this time, for example, electrons are collected in the diffusion layer (source / drain region) of the nMOS, but holes stay in the channel region for a while to raise the well potential. Then, when there is a potential difference between the source and drain diffusion layers of the nMOS, a so-called parasitic bipolar effect occurs in which a leakage current flows even when the gate is off, increasing the amount of collected charge and causing a soft error. It becomes easy. Therefore, it is known that if a retrograde well that forms a high-concentration layer in a certain depth inside the well is added to lower the well resistance, the soft error resistance is improved.

  8A and 8B are cross-sectional views of a conventional semiconductor device provided with this retrograde well described in Patent Document 1. FIG. FIG. 8A is a cross-sectional view of the SRAM portion. The flat well PWLM (P-type well), the retrograde well BPM (P-type high-concentration well) and BNM (N-type high) having higher concentrations than the NMLM (N-type well). It is described that a concentration well) is provided at a position corresponding to the bottom of the separation unit 2 and the vicinity thereof. On the other hand, FIG. 8B is a cross-sectional view of the logic circuit portion, which is a retrograde well BPL (P type), BNL (N type) having a higher concentration than the flat wells PWLL and NWLL and a lower concentration than the retrograde well of the SRAM portion. ) Is provided only in the element isolation region to improve the element isolation capability. In addition, it is described that no retrograde well is provided below an active region in which a transistor of the logic circuit portion is formed so that a junction capacitance is not increased in a logic circuit that requires high speed.

  FIG. 8C is a cross-sectional view of the conventional semiconductor device described in Patent Document 2, in which the vertical conductor (vertically doped structure) 730 connected to the power source VSS reaches the P-bulk silicon substrate 740. It is described that the parasitic bipolar transistor operation caused by irradiation of radiation is prevented. Furthermore, Patent Document 3 describes a thyristor type electrostatic protection circuit that uses an NMOS transistor as a trigger element of a thyristor.

JP 2002-289696 A JP-T-2007-523481 JP 2003-203985 A

  The following analysis is given by the present invention. As a soft error, conventionally, bit inversion in memory circuits such as DRAM and SRAM holding information and sequential circuits such as flip-flops and latch circuits has attracted attention. The soft error phenomenon that occurs in Japan is also drawing attention. In the combinational circuit, when the charged particles pass nearby and charge collection occurs, the output potential of the logic cell temporarily varies, but eventually returns to the original state. However, a phenomenon called Single Event Transient, in which a potential pulse generated by a temporary potential fluctuation propagates through the combinational circuit, occurs. When the pulse finally reaches a sequential circuit such as a flip-flop, and the clock signal of the sequential circuit is input at the timing when the potential fluctuates, erroneous information is captured and held in the sequential circuit, causing an error. .

  The parasitic bipolar effect caused by radiation irradiation or the like is a problem particularly in an SRAM circuit that takes a well contact region only at a certain distance. In a combinational logic circuit that takes a well contact region in a cell, the influence is It has been considered limited. Here, a region in contact with the well contact electrode and a continuous region in the periphery of which the substrate surface has the same conductivity type are collectively referred to as a well contact region.

  With the recent reduction in device dimensions, it is considered that the parasitic bipolar effect becomes prominent even in combinational logic circuits. In the combinational logic circuit, the time during which charges are collected increases due to leakage current due to the parasitic bipolar effect. As a result, the pulse width of the error signal is increased. The probability that this error signal is latched in a sequential circuit synchronized with a clock such as a flip-flop is considered to be almost proportional to the pulse width of the error signal, so the soft error rate in the logic circuit increases due to the parasitic bipolar effect. .

  According to the inventor's study, the combinational logic circuit requires high-speed operation. Therefore, if the well resistance with respect to the transistor formation region can be reduced without increasing the parasitic capacitance of the transistor, the combinational logic circuit is also effective. It is considered that a structure capable of suppressing the parasitic bipolar effect can be obtained.

  On the other hand, Patent Document 1 does not describe a method for preventing the parasitic bipolar effect without disturbing the high-speed operation of the logic circuit. If a vertical conductor reaching the P-bulk silicon substrate 740 is provided as in Patent Document 2, the parasitic bipolar effect can be prevented. However, in order to form a vertical conductor reaching the P-bulk silicon substrate 740, a process is performed. It is considered that the parasitic capacitance of the transistor increases as the number increases and the distance between the vertical conductor and the transistor decreases.

  A semiconductor device according to an aspect of the present invention includes a first conductivity type well formed on a main surface of a semiconductor substrate, a transistor formed on the surface of the first conductivity type well, and a main surface of the semiconductor substrate. The device isolation insulating region is formed on the surface of the first conductivity type well with the transistor and the element isolation insulating region being separated from each other, and the depth of the bottom surface is approximately equal to the bottom surface of the element isolation insulating region. A first conductivity type high concentration region having an impurity concentration higher than that of the conductivity type well; and a well contact electrode formed on a surface of the first conductivity type high concentration region.

  According to the present invention, the first conductivity type high concentration region formed between the transistor and the element isolation insulating region and connected to the well contact electrode is formed at approximately the same depth as the element isolation insulating region. Well resistance to the transistor region can be reduced without increasing the capacitance. Thereby, the parasitic bipolar effect resulting from radiation irradiation etc. can be suppressed and a soft error can also be prevented.

1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along arrows I (b) -I (b) in FIG. 2A is a cross-sectional view taken along the arrow II (a) -II (a) and FIG. 2B is a cross-sectional view taken along the arrow II (b) -II (b) of the semiconductor device of FIG. . It is a schematic diagram of a charge collection current waveform when charged particles are incident on a transistor region. 5A is a plan view of a semiconductor device of a comparative example, and FIG. 4B is a cross-sectional view taken along arrows IV (b) -IV (b) in FIG. It is a graph which shows the relationship between the additional impurity density | concentration to a high concentration area | region, and a charge collection continuation time. FIG. 6A is a plan view of a semiconductor device according to another embodiment of the present invention, FIG. 6B is a cross-sectional view taken along arrows VI (b) -VI (b) in FIG. It is sectional drawing along the arrow VI (c) -VI (c) direction in (a). 8A is a plan view of a semiconductor device according to still another embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along arrows VII (b) -VII (b) in FIG. (A) (b) is sectional drawing of the SRAM part and logic circuit part of the conventional semiconductor device which are each described in patent document 1, (c) is another conventional technique described in patent document 2 It is sectional drawing of this semiconductor device.

  Before describing the examples in detail, an outline of an embodiment of the present invention will be described. It should be noted that the drawings cited in the outline of the embodiments and the reference numerals of the drawings are shown as examples of the embodiments, and do not limit the variations of the embodiments according to the present invention.

  A semiconductor device 100, 100 a, 100 b according to an embodiment of the present invention includes a first conductivity type well 105 formed on the main surface of a semiconductor substrate 108 and transistors 102, 103 formed on the surface of the first conductivity type well 105. And an element isolation insulating region 101 formed on the main surface of the semiconductor substrate 108, and a transistor 102, 103 and the element isolation insulating region 101 are formed on the surface of the first conductivity type well 105 with a depth of the bottom surface approximately A first conductivity type high concentration region 106 having an impurity concentration equal to the bottom surface of the element isolation insulating region (101 between 106 and 102) and having a higher impurity concentration than the first conductivity type well 105, and the surfaces of the first conductivity type high concentration region 106 And a well contact electrode 104 formed on the substrate.

  Since the well contact electrode 104 is formed on the surface of the first conductivity type high concentration region 106, the first conductivity type high concentration region 106 and the well contact electrode 104 are connected to a low resistance. Further, since the first conductivity type high concentration region 106 and the transistor (for example, the MIS transistor including the source / drain 102 and the gate 103) are formed with the element isolation insulating region 101 therebetween, the first conductivity type high concentration region 106 is formed. Even if the transistor is provided, the parasitic capacitance of the transistor does not increase. In particular, since the depth of the bottom surface of the first conductivity type high-concentration region 106 is approximately equal to the depth of the bottom surface of the element isolation insulating region 101 that separates the transistor, the peripheral region of the transistor is increased without increasing the parasitic capacitance of the transistor. Well resistance to can be reduced. It is the inventor's knowledge that the depth of the bottom surface of the first conductivity type high concentration region 106 is approximately equal to the depth of the bottom surface of the element isolation insulating region 101 separating the transistors. If the depth of the first conductivity type high-concentration region 106 is too shallow, the well resistance increases, and the depth of the first conductivity type high-concentration region 106 is too deep. If exposed from the bottom, the exposed side surface will increase the parasitic capacitance of the transistor. In particular, as the miniaturization progresses and the first conductivity type high concentration region 106 is provided near the transistor region, the parasitic capacitance of the transistor is increased.

  In other words, by the first conductivity type high-concentration region 106, the well contact electrode 104 has low resistance and is insulated by the element isolation insulating region 101 so as not to increase the parasitic capacitance due to the wiring, and is wired to the vicinity of the transistor.

  Further, since the depth of the first conductivity type high concentration region 106 is at most equal to the depth of the element isolation insulating region 101, it can be manufactured relatively easily by using a known manufacturing technique such as ion implantation. Since the one-conductivity type high-concentration region 106 is formed, the manufacturing process does not increase greatly.

  Although the depth of the element isolation insulating region 101 may vary depending on the location, the depth of the bottom surface of the first conductivity type high concentration region 106 is the same as the depth of the bottom surface of the element isolation insulating region 101 that separates the transistor. It is desirable to be approximately equal.

  The transistor may be a second conductivity type MIS (Metal-Insulator-Semiconductor) transistor. For example, if the first conductivity type well is a P type well, the transistor may be an N type MIS transistor, and if the first conductivity type well is an N type well, the transistor may be a P type MIS transistor. . Further, the gate insulating film 107 of the MIS transistor may be an oxide film or an insulating film other than the oxide film.

The first conductivity type high concentration region 106 may be a high concentration region having an impurity concentration of 1e17 cm ⁻³ or more. As indicated by 12 in FIG. 5, there is a correlation between the impurity concentration of the first conductivity type high concentration region 106 and the charge collection duration tcc (the shorter the tcc, the more the parasitic bipolar transistor effect is suppressed). According to knowledge, the impurity concentration of the first conductivity type high concentration region 106 is desirably 1e17 cm ⁻³ or more. 5 represents the impurity concentration of the first conductivity type added to the first conductivity type well, and does not represent the impurity concentration of the first conductivity type high concentration region 106 itself.

  The transistor may be a transistor for constituting a predetermined combinational circuit. The semiconductor devices 100, 100a, and 100b each include a combinational circuit such as a NAND gate, a NOR gate, and an inverter. The combinational circuit is a sequential circuit that operates in synchronization with a clock such as a latch, flip-flop, or memory, and a memory Connected to the circuit. When the combinational circuit generates a single event transient due to radiation irradiation or the like and overlaps with the clock edge, a soft error occurs. According to the above configuration, the occurrence of a single event transient can be prevented, or even if a single event transient occurs, the time is shortened and the probability of a soft error can be reduced.

  The bottom surface of the first conductivity type high concentration region 106 is formed deeper than the bottom surface of the source / drain region 102 of the second conductivity type MIS transistor. With such a configuration, the parasitic bipolar transistor effect can be effectively prevented.

  Further, as in the semiconductor device 100a of FIG. 6, the first conductivity type deep layer having a higher impurity concentration than the first conductivity type well 105 formed in a region deeper than the bottom surface of the element isolation insulating region 101 in the first conductivity type well 105. A high concentration region 116 may be further provided. In the case where the transistor is a memory circuit or a sequential circuit, the soft error can be more effectively prevented by providing the first conductivity type deep high concentration region 116 on the bottom surface thereof. The first conductivity type deep layer high concentration region 116 may be partially provided at a necessary place.

  Further, as in the semiconductor device 100b of FIG. 7, the second conductivity type well 125 formed on the main surface of the semiconductor substrate 108 and the surface of the second conductivity type well 125 are provided together with the second conductivity type MIS transistor. Are formed on the surface of the first conductivity type MIS transistor (source drain 122 and gate 103) and the second conductivity type well 125 with the element isolation insulating region 101 between them. The depth of the bottom surface is approximately equal to the bottom surface of the element isolation insulating region 101 and is formed on the surface of the second conductivity type high concentration region 126 having a higher impurity concentration than the second conductivity type well 125 and the surface of the second conductivity type high concentration region 126. The well contact electrode 104 may be provided.

  In the case of providing the first conductivity type MIS transistor, the second conductivity type high concentration region 126 connected to the well contact electrode 104 is formed by separating the element isolation insulating region 101 similarly to the second conductivity type MIS transistor. The well resistance of the second conductivity type well 125 in the vicinity of the back gate of the second conductivity type MIS transistor can be reduced, and the occurrence of a soft error due to radiation irradiation or the like can be suppressed. Further, if the second conductivity type high concentration region 126 is considered as a wiring connected to the well contact electrode 104, the parasitic capacitance does not increase because the second conductivity type high concentration region 126 is insulated by the element isolation insulating region 101. Of the element isolation insulating regions 101 provided on the surface of the semiconductor substrate 108, the depth of the bottom surface of the element isolation insulating region 101 provided on the surface of the second conductivity type well 125 is the element isolation insulating region 101 provided on the surface of another region. The depth of the bottom surface of the element isolation insulating region 101 separating the first conductivity type MIS transistor from the second conductivity type high concentration region 126 may be different from the depth of the bottom surface of the second conductivity type high concentration region 126. Desirably, the bottom and depth are approximately equal. Also, the formation of the second conductivity type high concentration region 126 can be performed by adding a relatively simple manufacturing process using a known ion implantation technique or the like.

  The first conductive type MIS transistor constitutes a predetermined logic circuit together with the second electric type MIS transistor. The logic circuit may be a combinational circuit in addition to a memory circuit and a sequential circuit. According to the inventor's knowledge, the combinational circuit also generates a single event transient due to radiation irradiation, etc., and causes a soft error. According to the above configuration, the combinational logic circuit is not hindered in high-speed operation. Can prevent the occurrence of soft errors.

  The description of the outline is finished above, and each embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 1A is a plan view of the semiconductor device 100 according to the first embodiment. 1 (b), 2 (a), and 2 (b) are arrows I (b) -I (b), II (a) -II (in the plan view of FIG. 1 (a), respectively. It is sectional drawing along a) and arrow II (b) -II (b). The structure of the semiconductor device 100 according to the first embodiment will be described with reference to these drawings.

  First, a planar structure viewed from the main surface of the semiconductor substrate 108 of the semiconductor device 100 will be described. In FIG. 1A, a MIS transistor having a source / drain region 102 is formed on the surface of a semiconductor substrate 108 with a gate electrode 103 interposed therebetween. The MIS transistor may be a P-type MIS transistor or an N-type MIS transistor, but the following description will be continued here assuming that it is an N-type MIS transistor. In the case of an N-type MIS transistor, the source / drain region 102 is an N-type region.

  In FIG. 1A, a well contact electrode 104 is provided in parallel with the direction of current flow of the source / drain and at a predetermined distance from the N-type source / drain region. In order to prevent the parasitic bipolar effect and increase the integration density of the layout, the well contact electrode 104 is formed in the channel region of the MIS transistor (the portion immediately below the gate electrode 103 of the source / drain region 102 partitioned by the gate electrode 103) or the drain region. It is desirable to provide it nearby. The arrangement of the well contact electrode 104 is not limited to the arrangement shown in FIG. 1A, and may be provided so as to surround the entire source / drain region 102, for example.

  Next, a cross-sectional structure of the semiconductor device 100 will be described. In the cross-sectional view of FIG. 1B, a P-type well 105 is formed on the main surface of the semiconductor substrate 108. The semiconductor substrate 108 may be either an N-type or P-type semiconductor substrate. Further, the P-type well 105 may be provided on the entire main surface of the semiconductor substrate 108 or may be provided on a partial region of the main surface of the semiconductor substrate 108. A gate insulating film 107 is formed on a part of the surface of the P-type well 105, and a gate electrode 103 is formed on the surface of the gate insulating film 107. The vicinity of the surface of the P-type well 105 sandwiching the gate insulating film 107 immediately below the gate electrode 103 becomes the channel region of the N-type MIS transistor.

  A P-type high concentration region 106 is provided immediately below the well contact electrode 104 to lower the well resistance of the P-type well from the well contact electrode 104 to the vicinity of the channel region of the N-type MIS transistor. An element isolation insulating region 101 is provided on the surface of the semiconductor substrate 108 except for the region where the N-type MIS transistor is formed and the P-type high concentration region 106. In FIG. 1B, since the P-type well 105 is provided on the entire surface of the semiconductor substrate 108, the element isolation insulating region 101 is provided on the surface of the P-type well 105. When the P-type well 105 is provided on the surface, the element isolation insulating region 101 may be formed also on the surface of the semiconductor substrate 108 where the P-type well 105 is not formed. Further, the element isolation insulating region 101 may be an insulating film formed by STI (Shallow Trench Isolation).

  By providing the element isolation insulating region 101 between the MIS transistors, the source / drain regions 102 of the MIS transistors can be insulated from each other. An element isolation insulating region 101 is also provided between the P-type high concentration region 106 and the channel region or source / drain region 102 of the MIS transistor. By providing the element isolation insulating region 101 between the P-type high concentration region 106 and the channel region or source / drain region of the MIS transistor, between the P-type high concentration region 106 and the channel region or source / drain region 102 of the MIS transistor. Can reduce the parasitic capacitance.

  The bottom surface of the P-type high concentration region 106 is substantially equal to the depth of the bottom surface of the element isolation insulating region 101 that separates from the transistor region (channel region or source / drain region 102). In the case where the bottom surface of the P-type high concentration region 106 is formed deeper than the bottom surface of the element isolation insulating region 101, the P-type high concentration region 106 exposed from the bottom surface of the element isolation insulating region 101 and the channel region or source / drain of the transistor This is not desirable because the parasitic capacitance with the region 102 increases. This parasitic capacitance is not a problem when there is a distance between the P-type high concentration region 106 exposed from the bottom surface of the element isolation insulating region 101 and the transistor region, but in order to reduce the well resistance and increase the degree of integration. This is a problem because it is necessary to shorten the distance from the bottom surface of the P-type high concentration region 106 to the transistor region. In this embodiment, since the side surface of the P-type high concentration region 106 separates the element isolation insulating region 101, it hardly affects the parasitic capacitance of the transistor.

  Further, when the depth of the bottom surface of the P-type high concentration region 106 is shallower than the bottom surface of the element isolation insulating region separating the transistor region, the P-well resistance to the channel region of the MIS transistor is increased and the bipolar effect is sufficiently obtained. Can not prevent. Ideally, it is desirable that the bottom surface of the P-type high concentration region 106 is aligned with the bottom surface of the peripheral element isolation insulating region 101, particularly the bottom surface of the element isolation insulating region 101 formed between the transistor region. According to a general manufacturing method of a semiconductor device, the process of manufacturing the element isolation insulating region 101 and the process of manufacturing the P-type high concentration region 106 are different. Although the depth of the bottom surface of the high-concentration region 106 cannot be completely matched, when the P-type high concentration region 106 is formed after the element isolation insulating region 101 is formed, It is desirable to form the P-type high concentration region 106 so that the bottom surface is substantially aligned with the bottom surface of the element isolation insulating region.

  2A, the depth of the bottom surface of the N-type source / drain region 102 of the N-type MIS transistor is the bottom surface of the element isolation insulating region 101. Shallow than the depth of. Accordingly, since the bottom surface of the P-type high concentration region 106 is substantially equal to the depth of the bottom surface of the element isolation insulating region 101, the resistance from the well contact electrode of the P-type well in the portion immediately below the channel of the N-type MIS transistor is reduced. be able to. Therefore, it is possible to prevent the MIS transistor from operating as a parasitic bipolar transistor due to radiation irradiation or the like. When the MIS transistor operates as a parasitic bipolar transistor, the channel region (the relatively shallow region of the P-type well just below the gate electrode) is the base, the drain of the N-type source / drain region 102 is the collector, and the source is the parasitic. Sometimes it operates as a bipolar transistor.

  Further, as shown in the cross-sectional view of the well contact electrode 104 portion of FIG. 2B, a P-type high concentration region 106 is formed on the entire surface immediately below the well contact electrode 104 formed in a rectangular shape. The well contact electrode 104 and the P-type well 105 are connected via the P-type high-concentration region 106 on the entire surface immediately below the 104.

  FIG. 3 is a schematic diagram of a charge collection current waveform when charged particles enter the transistor region. 3 shows, for example, the cross-sectional structure of the MIS transistor shown in FIG. 2A, in which the source region (one of the source / drain regions 102) and the gate electrode 103 are ground potential, and the drain region (the other of the source / drain regions 102) is the power source. It is the figure which showed the typical electric charge collection current waveform in the drain terminal when a charged particle injects into the center of a drain area | region fixed to an electric potential. Here, the time until the current is sufficiently attenuated is defined as a charge collection duration tcc.

  In the above case, since the gate electrode 103 is fixed to the ground potential, the N-type MIS transistor is turned off, and no current should flow between the drain region and the source region. However, when charged particles enter the center of the drain region and the charged particles travel through the semiconductor substrate, electron-hole pairs are generated along the tracks, and the electrons are collected in the drain. However, holes stay in the channel region for a while, raising the potential of the P-type well 105 in the vicinity of the source and drain regions. Then, since the potential of the P-type well 105 in the vicinity becomes higher than the potential of the source region, the NPN type having the N-type drain region as the collector, the P-type well 105 around the channel region as the base, and the N-type source region as the emitter. The parasitic bipolar transistor becomes a forward bias state, and current flows from the N-type drain (collector) region to the N-type source (emitter) region. This current continues until the potential of the P-type well 105 around the channel region becomes the same as that of the source region. This time is the charge collection duration tcc. This charge collection duration tcc depends on the resistance of the P-type well from the channel region to the well contact electrode 104. If the resistance from the P-type well 105 near the channel region to the well contact 104 is large, the charge collection duration tcc becomes long. If the resistance from the P-type well 105 near the channel region to the well contact 104 is small, the charge collection duration tcc. Becomes shorter.

  When the MIS transistor is a MIS transistor that forms a combinational circuit such as an inverter, the potential of the drain region is not fixed. However, when a current flows between the source and drain of the MIS transistor that forms the combinational circuit, the output of the combinational circuit Outputs a pulse. It has been found that the pulse width observed in the combinational circuit and the charge collection duration tcc are closely related. That is, the larger the tcc, the longer the pulse width that appears in the actual combinational circuit. If the pulse width is increased, the probability that a clock error and the above pulse overlap in a sequential circuit or a memory circuit to which the output signal of the combinational circuit is connected is increased.

  FIG. 5 is a graph showing the relationship between the additional impurity concentration in the high concentration region (FIG. 1B, 106, etc.) and the charge collection duration tcc. A broken line indicated by reference numeral 12 in FIG. 5 indicates the relationship between the additional impurity concentration of the P-type high concentration region 106 and the charge collection duration time tcc according to the embodiment of FIG. The horizontal axis in FIG. 5 is the impurity concentration of the P-type impurity added to the P-type well 105 in the P-type high concentration region 106, and the vertical axis is the charge collection duration time tcc. In FIG. 5, using the transistor structure of the 65 nm technology node, the relationship between the concentration value added by the device simulation and the charge collection duration tcc was obtained.

Since the impurity concentration of the P-type high concentration region 106 is made equal to the impurity concentration of the P-type well 105 without adding the impurity concentration to the P-type high concentration region 106, the value of the charge collection duration time tcc is about 100 ps. The parasitic bipolar effect can be suppressed by increasing the impurity concentration of the P-type high concentration region 106, and the charge collection duration tcc can be almost halved if the concentration value is increased by about 1e18 cm ⁻³ .

  Further, for the sake of comparison, the broken line indicated by reference numeral 11 in FIG. 5 assumes that the additional impurity concentration of the P-type high concentration region 206 and the charge collection duration tcc are calculated by device simulation assuming the semiconductor device 200 having the structure shown in FIG. This is a relationship. In the semiconductor device 200 of the comparative example of FIG. 4, the P-type high concentration region 106 in FIG. 1B is not provided, but instead formed in a deep layer of a P-type well as described in Patent Document 1. A P-type high concentration region 206 is provided. The other structure is the same as that of the semiconductor device 100 of the first embodiment shown in FIGS.

  That is, as can be understood from FIG. 5, the charge collection continuation time tcc can be shortened in the structure of FIG. 1 of the first embodiment compared to the structure of FIG. 4 shown as a comparative example. Further, in the structure of FIG. 4, since the P-type high concentration region is provided immediately below the N-type MIS transistor, the parasitic capacitance of the channel region and the drain region of the N-type MIS transistor increases, and the operation speed of the logic circuit decreases. Leads to. On the other hand, according to the structure of the first embodiment, the increase in parasitic capacitance due to the provision of the P-type high concentration region 106 is extremely limited, and the influence on the operation speed of the logic circuit is slight.

  In the first embodiment, an example in which an N-type MIS transistor is formed in the P-type well 105 and the P-type high concentration region 106 is provided in the P-type well 105 has been described. A P-type MIS transistor may be formed in the well, and an N-type high concentration region may be provided in the N-type well.

  In the semiconductor device 100 of the first embodiment, the P-type high concentration region 106 exposes only the well contact region by a photoresist development / exposure technique, for example, at an appropriate place in the manufacturing process of the semiconductor device 100. It can be formed by introducing impurities by ion implantation multiple times. At this time, since the depth for increasing the concentration is limited, the number of ion implantations can be minimized. In addition, the high concentration region may be formed using any available impurity introduction technique.

  FIG. 6 is a plan view of the semiconductor device 100a according to the second embodiment (FIG. 6A) and a cross-sectional view taken along arrows VI (b) -VI (b) in FIG. 6A (FIG. 6B). )) And a sectional view taken along arrows VI (c) -VI (c) in FIG. 6 (a) to 6 (c), portions that are substantially the same in structure and function as those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the semiconductor device 100 according to the first embodiment shown in FIGS. 1A and 2B, the well contact electrode 104 is provided on the entire surface of the P-type high concentration region 106, and the well contact is formed on the entire surface of the P-type high concentration region 106. Although connected to the electrode 104, in the semiconductor device 100 a of Example 2 shown in FIGS. 6A to 6C, the well contact electrode 104 is provided on a part of the surface of the P-type high concentration region 106, and the well contact The surface of the P-type high concentration region 106 whose surface is not covered with the electrode 104 is covered with a surface oxide film 109.

  In logic cells constituting a combinational circuit or sequential circuit, a well contact region is often formed in a strip shape along one side or a plurality of sides of a rectangular logic cell. In FIG. 6A as well, the P-type high concentration region 106 is provided long in a strip shape, but the well contact region does not necessarily extend long in a strip shape. The P-type high concentration region 106 may be provided only in a limited distance range around the well contact electrode 104. In FIG. 6A, only one well contact electrode 104 is shown on the surface (in the well contact region) of the belt-like P-type high concentration region 106, but a plurality of well contacts are formed along the belt-like region. An electrode 104 may be provided. The number of well contact electrodes can be determined as appropriate depending on the value of the required well resistance.

Further, as shown in FIGS. 6B and 6C, in Example 2, the high-concentration layer 116 having the same conductivity type as the P-type well 105 corresponding to the retrograde well of Patent Document 1 is formed from the element isolation insulating region 101. Deeply formed on the entire surface of the P-type well 105. However, the P-type deep high-concentration region 116 is formed to be sufficiently deep so as not to increase the junction capacitance with the source / drain region 102, for example, at a depth of 0.4 μm and a peak concentration of 5e17 cm ⁻³ . The P-type deep high-concentration region 116 may be provided only in a region where a storage circuit such as an SRAM is disposed, or may be provided on the entire surface of the semiconductor substrate. In addition, the P-type deep high-concentration region 116 does not need to be provided at a location where a logic circuit that requires high-speed operation and does not want to increase parasitic capacitance is disposed. With such a configuration, the well resistance can be suppressed by the P-type deep high-concentration region 116 in the region where the storage circuit such as the SRAM is arranged. Can be raised. On the other hand, in the region where the combinational circuit is arranged, the P-type deep high concentration region 116 is not provided, and the P-type high concentration region 106 is provided in the vicinity of the transistor, so that the high speed performance of the combinational circuit is not impaired. The effect can also be suppressed.

Further, the P-type high concentration region 106 directly connected to the well contact electrode 104 forms a high concentration layer so as to have a concentration value of about 1e18 cm ⁻³ even in a thin area from the substrate surface to the bottom of the element isolation insulating region 101. To do. The impurity concentration of the P-type high-concentration region 106, is higher than the impurity concentration of the P-type well 105, the effect is obtained, the impurity concentration of the P-type high-concentration region 106 1e18 cm ^-3 longitudinal (5e17cm ^-3 least 2E18 cm ^-3 The following effects can be obtained.

  Although the second embodiment has been described as an example in which the N-type MIS transistor, the P-type high concentration region 106, and the P-type deep high concentration region 116 are provided in the P-type well 105 as in the first embodiment, Similarly, it is also possible to reverse all of the N type and the P type.

  7A and 7B are plan views of the semiconductor device 100b according to the third embodiment (FIG. 7A) and arrows VII (b) -VII (b) in FIG. 7A. It is sectional drawing (FIG.7 (b)). 7 (a) and 7 (b) of the third embodiment, parts having substantially the same structure and function as those of the first or second embodiment are denoted by the same reference numerals, and the first and second embodiments are the same as those of the first or second embodiment. A duplicate description is omitted.

  In the first and second embodiments, when a transistor is provided in either P-type or N-type well, the well resistance for the transistor region is reduced without increasing the parasitic capacitance of the transistor. Met. The third embodiment is a CMOS semiconductor device in which an N-type MIS transistor is provided in the P-type well 105 and a P-type MIS transistor is provided in the N-type well 125. Both wells of the P-type well 105 and the N-type well 125 are used. This is an example of the semiconductor device 100b that prevents the parasitic bipolar effect caused by radiation irradiation and the like and suppresses the increase in parasitic capacitance so as not to hinder the high-speed switching operation of the logic circuit. In the third embodiment, an N-type well 125 is provided on the surface of the semiconductor substrate 108 in addition to the P-type well 105. Further, a P-type source / drain region 122 is provided on the surface of the N-type well 125, and a gate electrode 103 is provided in an upper layer with the gate insulating film 107 interposed between the N-type well 125 and the gate electrode 103 as a gate. , A P-type MIS transistor having one of the P-type source / drain regions 122 as a source and the other as a drain is provided. This gate electrode 103 is also connected to the gate of an N-type MIS transistor provided in the P-type well 105, and together with the P-type MIS transistor provided in the N-type well 125, a CMOS gate circuit (typically CMOS Inverter). Similarly to the P-type well 105, the N-type well 125 is arranged with the element isolation insulating region 101 sandwiched between the N-type high concentration region 126 and the P-type MIS transistor, so that the N-type well 125 can be formed at the periphery of the P-type MIS transistor. Prevents parasitic bipolar effects.

  Further, since the depth of the bottom surface of the N-type high concentration region 126 is approximately the same as the bottom surface of the element isolation insulating region 101 that separates the N-type high concentration region 126 and the transistor region, it is provided on the surface of the N-type well 125. The well resistance from the N well contact electrode 104 of the P-type MIS transistor to the channel region of the P-type MIS transistor is reduced while preventing an increase in the parasitic capacitance of the P-type MIS transistor. As a result, it is possible to prevent a parasitic bipolar operation caused by radiation irradiation or the like and prevent a soft error from occurring without interfering with the high-speed operation of the CMOS logic circuit.

  Although not particularly shown in FIG. 7, a deep P-type high layer is formed in a sufficiently deep region so as not to increase the junction capacitance with the source / drain region 102 in the P-type well 105 as in the second embodiment. A concentration region 116 (see FIG. 6) is provided, and a deep N-type high concentration region (not shown) is provided in a sufficiently deep region so as not to increase the junction capacitance with the source / drain region 122 in the N-type well 125. You can also. In addition, the well contact electrode 104 can be provided not only in a strip shape parallel to the direction in which the channel current flows as shown in FIG.

  Although the embodiments have been described above, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is.

100, 100a, 100b, 200: Semiconductor device 101: Element isolation insulating region 102: N-type source / drain region 103: Gate electrode 104: Well contact electrode 105: P-type well 106, 206: P-type high concentration region 116: P-type Deep layer high concentration region 107: Gate insulating film 108: Semiconductor substrate 109: Surface oxide film 122: P type source / drain region 125: N type well 126: N type high concentration region 11: P type high concentration region according to the comparative example of FIG. 206 impurity concentration and charge collection duration tcc
12: Impurity concentration and charge collection duration tcc of the P-type high concentration region 106 according to the embodiment of FIG.

Claims (11)

A first conductivity type well formed on the main surface of the semiconductor substrate;
A transistor formed on a surface of the first conductivity type well;
An element isolation insulating region formed on the main surface of the semiconductor substrate;
Formed on the surface of the first conductivity type well with the transistor and the element isolation insulating region in between, the depth of the bottom surface is approximately equal to the bottom surface of the element isolation insulating region, and the impurity concentration is higher than that of the first conductivity type well. A first conductivity type high concentration region;
A well contact electrode formed on a surface of the first conductivity type high concentration region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the transistor is a second conductivity type MIS transistor. The semiconductor device according to claim 1, wherein the first conductivity type high concentration region is a high concentration region having an impurity concentration of 1e17 cm ⁻³ or more.   The semiconductor device according to claim 1, wherein the transistor is a transistor for forming a predetermined combinational circuit.   3. The semiconductor device according to claim 2, wherein a bottom surface of the first conductivity type high concentration region is formed deeper than a bottom surface of a source / drain region of the second conductivity type MIS transistor.   The semiconductor device further comprises a first conductivity type deep layer high concentration region having a higher impurity concentration than the first conductivity type well formed in a region deeper than a bottom surface of the element isolation insulating region in the first conductivity type well. Item 6. The semiconductor device according to any one of Items 1 to 5. A second conductivity type well formed on the main surface of the semiconductor substrate;
A first conductivity type MIS transistor provided on a surface of the second conductivity type well and constituting a predetermined logic circuit together with the second conductivity type MIS transistor;
The second conductivity type well is formed on the surface of the first conductivity type MIS transistor with the element isolation insulating region therebetween, and the depth of the bottom surface is approximately equal to the bottom surface of the element isolation insulating region, and the second conductivity type A second conductivity type high concentration region having a higher impurity concentration than the well;
A well contact electrode formed on the surface of the second conductivity type high concentration region;
The semiconductor device according to claim 2, further comprising: 8. The semiconductor device according to claim 7, wherein each of the first conductivity type high concentration region and the second conductivity type high concentration region is a high concentration region having an impurity concentration of 1e17 cm ⁻³ or more.   9. The semiconductor device according to claim 7, wherein the predetermined logic circuit is a combinational circuit. A first conductivity type deep layer high concentration region having an impurity concentration higher than that of the first conductivity type well formed in a region deeper than the bottom surface of the element isolation insulating region in the first conductivity type well;
A second conductivity type deep high concentration region having a higher impurity concentration than the second conductivity type well formed in a region deeper than the bottom surface of the element isolation insulating region in the second conductivity type well;
The semiconductor device according to claim 7, further comprising:   6. The first conductivity type well is a P well, the first conductivity type high concentration region is a P type high concentration region, and the second conductivity type MIS transistor is an N type MIS transistor. The semiconductor device according to any one of 7 to 10.

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