JP2011055345A - Imaging apparatus - Google Patents

Abstract

An imaging apparatus having a high S / N ratio and a wide dynamic range is provided.
An imaging apparatus includes a plurality of pixels configured to include a photoelectric conversion unit, a plurality of color filters provided for each color corresponding to each of the plurality of pixels, and a photographing sensitivity for setting a photographing sensitivity. A setting unit, a second conductivity type charge absorption layer, and a voltage application unit; The photoelectric conversion unit is composed of a well made of a first conductivity type semiconductor and a charge accumulation unit made of a second conductivity type semiconductor and provided on the light receiving surface side of the first conductivity type semiconductor, and photoelectrically converts incident light. Generate charge. The second conductivity type charge absorption layer is disposed below the charge storage portion with the first conductivity type semiconductor interposed between pixels provided with at least one color filter. The voltage application unit applies a voltage to the charge absorption layer based on the imaging sensitivity set by the imaging sensitivity setting unit.
[Selection] Figure 5

Description

  The present invention relates to an imaging apparatus.

  In general, a CCD type or CMOS type solid-state imaging device is used in an imaging apparatus such as a digital camera. In this type of solid-state imaging device, a plurality of pixels having photoelectric conversion units are arranged in a matrix. For example, in a CMOS type solid-state imaging device, each pixel includes a photoelectric conversion unit such as a photodiode, a floating diffusion region, an amplification transistor, and the like. The electric charge generated in the photoelectric conversion unit according to the amount of incident light is transferred to the floating diffusion region. The amplification transistor receives a signal voltage based on the electric charge accumulated in the floating diffusion region at the gate, and outputs a pixel signal corresponding to the amount of incident light.

  For example, in shooting in a dark place or shooting using a high-speed shutter, the SN ratio decreases because the amount of incident light is small. For this reason, it is necessary to improve the SN ratio in high-sensitivity imaging. On the other hand, in shooting a high-luminance subject or long-second shooting, it is necessary to widen the dynamic range in order to prevent blackout and whiteout. In recent years, a solid-state imaging device in which two photoelectric conversion units having different saturation light amounts are provided in the same pixel has been proposed (for example, Patent Document 1). In the solid-state imaging device of Patent Literature 1, the two photoelectric conversion units of each pixel are arranged at different depths of the semiconductor substrate. For example, a photoelectric conversion unit arranged at a deep position has a wider dynamic range than a photoelectric conversion unit arranged at a shallow position.

Japanese Patent Laid-Open No. 2005-12007

  In the configuration in which the two photoelectric conversion units are arranged at different depths of the semiconductor substrate, it is difficult to completely transfer the charges of the photoelectric conversion units arranged in the deeper side to the floating diffusion region. When the charge of the photoelectric conversion unit is not completely transferred, the charge remains in the photoelectric conversion unit until the next photoelectric conversion (next frame), and an afterimage is generated. In this case, the image quality decreases.

  An object of the present invention is to provide an imaging device having a high SN ratio and a wide dynamic range.

  The imaging device includes a plurality of pixels configured to include a photoelectric conversion unit, a plurality of color filters provided for each color corresponding to each of the plurality of pixels, a shooting sensitivity setting unit that sets shooting sensitivity, It has a second conductivity type charge absorption layer and a voltage application section. The photoelectric conversion unit is composed of a well made of a first conductivity type semiconductor and a charge accumulation unit made of a second conductivity type semiconductor and provided on the light receiving surface side of the first conductivity type semiconductor, and photoelectrically converts incident light. Generate charge. The second conductivity type charge absorption layer is disposed below the charge storage portion with the first conductivity type semiconductor interposed between pixels provided with at least one color filter. The voltage application unit applies a voltage to the charge absorption layer based on the imaging sensitivity set by the imaging sensitivity setting unit.

  According to the present invention, it is possible to provide an imaging device having a high SN ratio and a wide dynamic range.

It is a figure which shows the outline | summary of the imaging device in one Embodiment. It is a figure which shows an example of the solid-state image sensor shown in FIG. FIG. 3 is a diagram illustrating an example of a circuit configuration of a pixel illustrated in FIG. 2. It is a figure which shows an example of the planar structure of the pixel shown in FIG. FIG. 5 is a diagram showing a cross section taken along line A-A ′ of the pixel shown in FIG. 4. FIG. 6 is a diagram illustrating a net impurity concentration distribution at a B-B ′ position of the pixel illustrated in FIG. 5. It is a figure which shows an example of the spectral sensitivity of a pixel when there is no color filter. It is a figure which shows an example of the spectral sensitivity of the pixel shown in FIG. It is a figure which shows an example of operation | movement of the solid-state image sensor shown in FIG. It is a figure which shows the cross section of the pixel of the imaging device in another embodiment. It is a figure which shows an example of the solid-state image sensor of the imaging device in another embodiment. It is a figure which shows an example of the planar structure of the pixel shown in FIG. It is a figure which shows the cross section which follows the C-C 'line of the pixel shown in FIG. It is a figure which shows an example of the solid-state image sensor of the imaging device in another embodiment. It is a figure which shows an example of the circuit structure of the pixel shown in FIG. It is a figure which shows an example of the planar structure of the pixel shown in FIG. It is a figure which shows an example of the spectral sensitivity of the pixel shown in FIG. It is a figure which shows the cross section of the pixel in the modification of the solid-state image sensor shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. The imaging apparatus of this embodiment is, for example, a digital camera, and includes a solid-state imaging device 10, an optical system 20, a control unit 30, a timing generator 40, a memory 50, a storage medium 60, a monitor 70, and an operation unit 80. Yes. The solid-state imaging device 10 is, for example, a CMOS type solid-state imaging device, and converts an image of a subject incident through a photographing lens 22 provided in the optical system 20 into an electrical signal (hereinafter also referred to as an image signal). .

  The optical system 20 includes a photographing lens 22 that forms an image of a subject on the light receiving surface of the solid-state imaging device 10. The optical system 20 may include a zoom lens and a focus lens in addition to the photographing lens 22. The control unit 30 is, for example, a microprocessor, and controls the operation of the imaging device based on a program (not shown). For example, the control unit 30 performs autofocus control, aperture control, exposure control to the solid-state imaging device 10, recording of image data, and the like. Further, the control unit 30 includes a photographing sensitivity setting unit 34, which will be described later, and a sensitivity adjusting unit 32 as a voltage applying unit that variably applies a voltage to the charge absorption layer, and the dynamic range of the solid-state imaging device 10 is set according to the photographing sensitivity. Adjust.

  For example, the sensitivity adjustment unit 32 variably applies the adjustment voltage VA to the charge absorption layer ABL1 shown in FIG. Specifically, the sensitivity adjustment unit 32 applies a voltage corresponding to the imaging sensitivity set by the imaging sensitivity setting unit 34 to the charge absorption layer ABL1. Note that the setting of the photographing sensitivity in the photographing sensitivity setting unit 34 may be set by the user, or may be automatically set based on information obtained by photometry or the like (for example, information on the amount of incident light). . Here, the sensitivity adjustment unit 32 and the imaging sensitivity setting unit 34 may be provided outside the control unit 30. For example, the sensitivity adjustment unit 32 and the imaging sensitivity setting unit 34 may be provided in the solid-state imaging device 10.

  The timing generator 40 is controlled by the control unit 30 and supplies a driving clock to the solid-state imaging device 10. For example, the timing generator 40 supplies drive clocks and control signals TN and TS for the vertical scanning circuit 11 and the horizontal scanning circuit 15 shown in FIG. Note that the timing generator 40 may be provided in the control unit 30 or may be provided in the solid-state imaging device 10.

  The memory 50 is a buffer memory formed by, for example, DRAM (Dynamic RAM), SRAM (Static RAM), or the like, and temporarily stores image data and the like. The storage medium 60 stores image data of captured images. The monitor 70 is a liquid crystal display, for example, and displays captured images, images stored in the storage medium 60, menu screens, and the like. The operation unit 80 includes a release button and other various switches, and is operated by the user in order to operate the imaging apparatus.

  FIG. 2 shows an example of the solid-state imaging device 10 shown in FIG. The solid-state imaging device 10 includes, for example, a pixel array ARY, a vertical signal line VL, a constant current source IS, a column amplifier CA, a vertical scanning circuit 11, an accumulation signal selection unit 12, a signal accumulation unit 13, a horizontal selection switch unit 14, and a horizontal scan. A circuit 15 is provided.

  The pixel array ARY has pixels PX1 arranged in a matrix in the row direction (horizontal direction in the figure) and the column direction (vertical direction in the figure). Each pixel PX1 includes, for example, a photoelectric conversion unit, which will be described later, and a color filter CFL shown in FIG. 5 provided for each color corresponding to the photoelectric conversion unit, and according to the amount of incident light that has passed through the color filter CFL. Generate electrical signals. Hereinafter, the pixel PX1 having the red (R), green (G), and blue (B) color filters CFL is also referred to as a red pixel PX1 (R), a green pixel PX1 (G), and a blue pixel PX1 (B). Further, the pixels PX1 having the red (R), green (G), and blue (B) color filters CFL in the pixel array ARY are collectively referred to as a red pixel PX1 (R) group, a green pixel PX1 (G) group, Also referred to as a blue pixel PX1 (B) group.

  The arrangement of the color filters CFL is not particularly limited, but a Bayer arrangement is exemplified in the present embodiment. When attention is paid to the row direction, for example, the red pixel PX1 (R) and the green pixel PX1 (G) are alternately arranged in the nth row of the pixel array ARY, and the green pixel PX1 (G) is arranged in the n + 1th row. The blue pixels PX1 (B) are alternately arranged. When attention is paid to the column direction, for example, in the m-th column of the pixel array ARY, the green pixel PX1 (G) and the red pixel PX1 (R) are alternately arranged, and in the m + 1-th column, the blue pixel PX1 (B ) And green pixels PX1 (G) are alternately arranged.

  The plurality of pixels PX1 arranged in the column direction are connected to the vertical signal line VL provided for each column. A constant current source IS is connected to each vertical signal line VL.

  The vertical scanning circuit 11 controls the pixels PX1 of the pixel array ARY for each row using the control signals SEL, RES, and TX. For example, the vertical scanning circuit 11 controls the control signals SEL (n), RES (n), and TX (n), and outputs the signal of each pixel PX1 in the nth row to each vertical signal line VL. For example, the vertical scanning circuit 11 controls the control signals SEL (n + 1), RES (n + 1), and TX (n + 1), and outputs the signal of each pixel PX1 in the (n + 1) th row to each vertical signal line VL. Hereinafter, the control signals SEL, RES, and TX are also referred to as a selection signal SEL, a reset signal RES, and a transfer signal TX, respectively.

  The column amplifier CA is, for example, an inverting amplifier configured using an operational amplifier, and is provided for each vertical signal line VL. Each column amplifier CA inverts and amplifies a signal read from each pixel PX1 via each vertical signal line VL.

  The accumulated signal selection unit 12 includes a pixel signal selection switch MS1 and a noise signal selection switch MN1 provided for each vertical signal line VL. For example, the pixel signal selection switch MS1 is an nMOS transistor, and is turned on when the control signal TS applied to the gate is at a high level, and the pixel signal input from the column amplifier CA is supplied to the pixel signal storage unit of the signal storage unit 13. Output to CS.

  Further, for example, the noise signal selection switch MN1 is an nMOS transistor and is turned on when the control signal TN applied to the gate is at a high level, and the noise signal input from the column amplifier CA is used as the noise signal of the signal storage unit 13. Output to the storage unit CN. Hereinafter, the pixel signal selection switch MS1 and the noise signal selection switch MN1 are also referred to as transistors MS1 and MN1, respectively.

  The signal storage unit 13 includes a pixel signal storage unit CS and a noise signal storage unit CN provided for each vertical signal line VL. For example, the pixel signal storage unit CS is a capacitor, one terminal is connected to the source of the transistor MS1, and the other terminal is grounded. Further, for example, the noise signal storage unit CN is a capacitor, one terminal is connected to the source of the transistor MN1, and the other terminal is grounded. Hereinafter, the pixel signal storage unit CS and the noise signal storage unit CN are also referred to as capacitors CS and CN, respectively.

  The horizontal selection switch unit 14 includes a pixel signal output switch MS2 and a noise signal output switch MN2 provided for each vertical signal line VL. For example, the pixel signal output switch MS2 is an nMOS transistor, and is turned on when the control signal GH applied to the gate is at a high level, and outputs the voltage held in the capacitor CS as the pixel signal OUTS. Further, for example, the noise signal output switch MN2 is an nMOS transistor, and is turned on when the control signal GH applied to the gate is at a high level, and outputs the voltage held in the capacitor CN as the noise signal OUTN. Hereinafter, the pixel signal output switch MS2 and the noise signal output switch MN2 are also referred to as transistors MS2 and MN2, respectively. Note that the gates of the transistors MS2 and MN2 are connected to each other.

  Here, the noise signal OUTN is a signal indicating a fixed noise component including a reset noise component of the pixel PX1, for example. The pixel signal OUTS is a signal including the above-described noise component and a signal component corresponding to the electric charge generated by photoelectric conversion in the photodiode in the pixel PX1. Therefore, for example, by CDS (correlated double sampling), a fixed noise component such as a reset noise component of the pixel PX1 included in the pixel signal OUTS is removed by subtracting the noise signal OUTN from the pixel signal OUTS.

  The horizontal scanning circuit 15 sequentially turns on the transistors MS2 and MN2 for each column using the control signal GH, and sequentially outputs signals OUTS and OUTN held in the capacitors CS and CN of the signal storage unit 13, respectively. For example, when outputting the pixel signal OUTS and the noise signal OUTN corresponding to the signal read from the pixel PX1 in the m-th column, the horizontal scanning circuit 15 controls the control signal GH (m) to a high level and performs control. Other control signals GH including the signal GH (m + 1) are controlled to a low level.

  FIG. 3 illustrates an example of a circuit configuration of the pixel PX1 illustrated in FIG. The pixel PX1 includes a photodiode PD as a photoelectric conversion unit, a diode D1, a transfer transistor MTR, an amplification transistor MAM, a pixel selection transistor MSE, a reset transistor MRS, and a floating diffusion FD (floating diffusion region) as a charge-voltage conversion unit. ing. Since the pixel PX1 includes the photodiode PD, the above-described red (R), green (G), and blue (B) color filters CFL correspond to the respective colors of the photodiode PD. It will be provided every time. In addition, in the pixel array ARY, the photodiode PD constituting each pixel PX1 includes a photodiode PD group (R) provided with a red filter, a photodiode PD group (G) provided with a green filter, and a photo provided with a blue filter. A diode PD group (B) is formed.

  The floating diffusion FD includes a region where a parasitic capacitance CFD for accumulating charges transferred from the photodiode PD is formed (a drain region of the transistor MTR, a wiring region between the transistors MTR and MAM, a gate region of the transistor MAM, and a reset transistor MRS). Source region, etc.). Further, the transistors MTR, MAM, MSE, and MRS formed in the pixel PX1 are all nMOS transistors.

  The photodiode PD is a photoelectric conversion unit that photoelectrically converts incident light to generate charges, and has an anode grounded and a cathode connected to the source of the transfer transistor MTR. The diode D1 has an anode grounded and an adjustment voltage VA applied to the cathode. As shown in FIG. 5 described later, the anode of the diode D1 (the region PA1 in FIG. 5) is also the anode of the photodiode PD. Therefore, for example, the diode D1 absorbs part of the electric charge generated by the photodiode PD when the adjustment voltage VA is applied to the cathode.

  Of the charge generated by the photodiode PD, the signal charge remaining without being absorbed by the diode D1 is accumulated in an n-type region (for example, an n-type region NA1 shown in FIG. 5 described later) of the photodiode PD. The Therefore, in this embodiment, the quantum efficiency (light receiving sensitivity) of the photodiode PD can be adjusted by adjusting the adjustment voltage VA.

  The transfer transistor MTR is turned on while the transfer signal TX applied to the gate is at a high level, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD. Note that the signal charges transferred to the floating diffusion FD are accumulated in the capacitor CFD.

  The amplification transistor MAM has a source connected to the drain of the pixel selection transistor MSE, a drain connected to the power supply VDD, and a gate connected to the drain of the transfer transistor MTR. That is, the voltage of the floating diffusion FD (the voltage of the capacitor CFD) is input to the gate of the amplification transistor MAM. For example, the amplification transistor MAM outputs, from the source, a voltage obtained by dropping the gate voltage by the threshold voltage of the amplification transistor MAM. As described above, the amplification transistor MAM generates a signal corresponding to the signal charge transferred to the floating diffusion FD.

  The pixel selection transistor MSE is turned on when the selection signal SEL applied to the gate is at a high level, and conducts between the vertical signal line VL connected to the source and the source of the amplification transistor MAM. Therefore, during the period in which the pixel selection transistor MSE is on, the amplification transistor MAM, the pixel selection transistor MSE, and the constant current source IS connected to the vertical signal line VL constitute a source follower circuit. Accordingly, the signal of the pixel PX1 selected by the pixel selection transistor MSE is output to the vertical signal line VL.

  The reset transistor MRS has a source connected to the gate of the amplification transistor MAM and a drain connected to the power supply VDD. The reset transistor MRS is turned on while the reset signal RES applied to the gate is at a high level, and resets the charge of the floating diffusion FD (charge accumulated in the capacitor CFD) to the initial state.

  FIG. 4 shows an example of a planar structure of the pixel PX1 shown in FIG. The shaded area in the figure indicates the gate of the transistor, and the rectangle with a cross indicates the contact area. Regions NA1, NA2, NA3, NA4, NA5, and NA6 indicate n-type regions. For example, the n-type regions NA1, NA2, NA3, NA4, NA5, and NA6 are formed by introducing an n-type impurity into a p-type well region PWELL shown in FIG.

  The transfer transistor MTR includes an n-type region NA1, a gate GT1, and an n-type region NA2. The n-type region NA1 is also a source of the transfer transistor MTR and a charge storage portion (n-type region) of the photodiode PD. Hereinafter, the n-type region NA1 is also referred to as a charge storage unit NA1. The n-type region NA2 is also the drain of the transfer transistor MTR and is a part of the floating diffusion FD shown in FIG. A transfer signal TX is applied to the gate GT1 of the transfer transistor MTR via the wiring LN1.

  The pixel selection transistor MSE includes an n-type region NA3, a gate GT2, and an n-type region NA4. A vertical signal line VL is connected to the n-type region NA3 which is the source of the pixel selection transistor MSE. The selection signal SEL is applied to the gate GT2 of the pixel selection transistor MSE via the wiring LN2. The amplification transistor MAM includes an n-type region NA4, a gate GT3, and an n-type region NA5. The n-type region NA4 is also the drain of the pixel selection transistor MSE and the source of the amplification transistor MAM.

  The reset transistor MRS includes an n-type region NA5, a gate GT4, and an n-type region NA6. The n-type region NA5 is also the drain of the amplification transistor MAM and the drain of the reset transistor MRS, and is connected to the power supply VDD. In FIG. 4, the wiring of the power supply VDD, the ground line, and the like are omitted for easy understanding of the drawing. A reset signal RES is applied to the gate GT4 of the reset transistor MRS via the wiring LN3.

  The n-type region NA6 that is the source of the reset transistor MRS is connected to the gate GT3 of the amplification transistor MAM and the n-type region NA2 that is the drain of the transfer transistor MTR by the wiring LN4. Here, the capacitance CFD shown in FIG. 3 described above is a parasitic capacitance formed in the n-type region NA2 of the transistor MTR, the n-type region NA6 of the transistor MRS, the gate GT3 of the transistor MAM, the wiring LN4, and the like.

  The charge absorption layer ABL1 is formed on the entire surface of the pixel array ARY, and is not formed in a peripheral circuit region (not shown) (a region where the peripheral circuit such as the vertical scanning circuit 11 shown in FIG. 2 described above is formed). That is, the charge absorption layer ABL1 is formed in common over the entire surface of the pixels PX1 having a plurality of colors. For example, the charge absorption layer ABL1 is an n-type region formed below the photodiode PD as described later, and is a part of the diode D1 shown in FIG. 3 described above. Here, the lower side of the photodiode PD refers to the side opposite to the light receiving surface of the photodiode PD. Note that the adjustment voltage VA is applied to the charge absorption layer ABL1 through the wiring LVA.

  FIG. 5 shows a cross section taken along line A-A ′ of the pixel PX <b> 1 shown in FIG. 4. Note that in FIG. 5, illustration of a light shielding film, a microlens, and the like is omitted for easy understanding of the drawing. The pixel PX1 is configured by forming a p-type well region PWELL made of a p-type semiconductor as a first conductivity type semiconductor on an n-type silicon substrate NSUB. For example, by introducing an n-type impurity into the p-type well region PWELL, the charge absorption layer ABL1, the n-type regions NA1, NA2, and the like are formed. The p-type well region PWELL is grounded.

  On the light receiving surface side (upper side in the figure) of the p-type well region PWELL, a charge storage portion NA1 (n-type region NA1) made of an n-type semiconductor as a second conductivity type semiconductor is formed. That is, the charge storage portion NA1 made of the second conductivity type semiconductor is provided on the light receiving surface side of the well region PWELL made of the first conductivity type semiconductor to form the photodiode PD. Note that the photodiode PD according to the present embodiment has a junction JCP (pn junction) between the region PA1 (p-type region PA1) made of the first conductivity type semiconductor and the charge storage portion NA1 (n-type region NA1).

  Above the light receiving surface of the photodiode PD corresponding to the pixel PX1, a color filter CFL is arranged for each color corresponding to each photodiode PD. For example, a red color filter CFL (R) is provided on the light receiving surface of the photodiode PD of the red pixel PX1 (R), and a green color is provided on the light receiving surface of the photodiode PD of the green pixel PX1 (G). A blue color filter CFL (B) is disposed on the light receiving surface of the photodiode PD of the blue pixel PX1 (B) (not shown). As described above, since the color filters CFL of a plurality of colors having different spectral characteristics are provided corresponding to the photodiodes PD, the photodiodes PD correspond to the amount of incident light that has passed through the arranged color filters CFL. Generate a charge.

  A charge absorption layer ABL1 is disposed at a distance from the charge storage portion NA1 below the charge storage portion NA1 (that is, on the n-type silicon substrate NSUB side opposite to the light receiving surface). Here, the p-type semiconductor region PA1 interposed between the charge storage portion NA1 and the charge absorption layer ABL1 is a part of the p-type well region PWELL. The diode D1 is a pn junction diode, and has a junction (pn junction) between the p-type semiconductor region PA1 and the n-type semiconductor charge absorption layer ABL1.

  Therefore, a depletion layer is formed in the vicinity of the junction between the region PA1 and the charge absorption layer ABL1. Due to this depletion layer, a part of the charge generated in the photodiode PD (for example, a charge generated in a region near the depletion layer) is absorbed by the charge absorption layer ABL1. Of the charge generated by the photodiode PD, the signal charge remaining without being absorbed by the charge absorption layer ABL1 is accumulated in the charge accumulation unit NA1.

  Here, the impurity concentration of the charge absorption layer ABL1 is higher than the impurity concentration of the region PA1 interposed between the charge storage portion NA1 and the charge absorption layer ABL1, as shown in FIG. For this reason, for example, when the adjustment voltage VA that reverse biases the diode D1 is applied to the charge absorption layer ABL1, the depletion layer of the diode D1 spreads to the region PA1 side. That is, the depletion layer formed in the vicinity of the junction between the region PA1 and the charge absorption layer ABL1 spreads toward the charge storage unit NA1 as the adjustment voltage VA is increased.

  Therefore, in this embodiment, the quantum efficiency of the photodiode PD can be adjusted by adjusting the adjustment voltage VA. Further, in this embodiment, even when the charge absorption layer ABL1 is formed in a deep region where the incident light hardly reaches, the depletion layer is changed to the charge storage portion NA1 by applying an appropriate adjustment voltage VA to the charge absorption layer ABL1. The quantum efficiency of the photodiode PD can be adjusted. When incident light reaches the charge absorption layer ABL1, the charge generated in the vicinity of the junction between the region PA1 and the charge absorption layer ABL1 is absorbed by the charge absorption layer ABL1.

  In this embodiment, it is not necessary to read out the charge absorbed by the charge absorption layer ABL1. In the transfer transistor MTR, since the charge storage portion NA1 is formed at substantially the same depth as the n-type region NA2 (drain of the transfer transistor MTR), the signal charge stored in the charge storage portion NA1 is transferred to the floating diffusion FD. It can be transferred efficiently. Thereby, in this embodiment, it is possible to prevent an afterimage from occurring in the image of the next frame, and it is possible to prevent the image quality from deteriorating.

  FIG. 6 shows a net impurity concentration distribution at the B-B ′ position of the pixel shown in FIG. 5. The horizontal axis of the figure indicates the depth (unit: μm) from the light receiving surface of the photodiode PD shown in FIG. 5, and the vertical axis of the figure indicates the net impurity concentration. The impurity concentration of the charge storage portion NA1 (for example, a depth of 0.3 to 0.5 μm in FIG. 6) is about 1E17 per cubic cm. Further, the impurity concentration in the region PA1 (in FIG. 6, for example, a depth of 0.7 to 3.6 μm) between the charge storage portion NA1 and the charge absorption layer ABL1 is about 1E15 per cubic cm. The impurity concentration of the charge absorption layer ABL1 (in FIG. 6, for example, a depth of 4.2 to 6.0 μm) is about 1E16 per cubic cm.

  Thus, the impurity concentration of the charge absorption layer ABL1 is higher by one digit or more than the impurity concentration of the region PA1 between the charge storage portion NA1 and the charge absorption layer ABL1. Thereby, in this embodiment, the extension to the region PA1 side of the depletion layer formed in the vicinity of the junction between the region PA1 and the charge absorption layer ABL1 can be increased. Therefore, the charge absorption layer ABL1 can efficiently absorb the charge generated in the region PA1 through the depletion layer. Thereby, in this embodiment, the quantum efficiency of the photodiode PD can be efficiently reduced, and the dynamic range of the photodiode PD can be easily expanded.

  FIG. 7 shows an example of the spectral output of the pixel PX1 when there is no color filter CFL. The horizontal axis in the figure indicates the wavelength of incident light (unit: nm), and the vertical axis in the figure indicates the output value of the pixel PX1 relative to the incident light as a relative value. For example, when the wavelength of incident light is 450 nm or more, the output value of the pixel PX1 when the adjustment voltage VA applied to the charge absorption layer ABL1 is 6V is lower than when the adjustment voltage VA is 1V, and the adjustment voltage VA is 10V. Higher than when. That is, the output value of the pixel PX1 varies depending on the quantum efficiency of the photodiode PD. For example, the output value of the pixel PX1 decreases as the adjustment voltage VA increases, and increases as the adjustment voltage VA decreases. Note that the output value of the pixel PX1 is an output value output from the solid-state imaging device 10.

  FIG. 8 shows an example of the spectral output of the pixel PX1 shown in FIG. The horizontal axis in the figure indicates the wavelength of incident light (unit: nm), and the vertical axis in the figure indicates the output value of the pixel PX1 relative to the incident light as a relative value. Since the gain for the pixel signal is constant (the circuit gain including the column amplifier CA is fixed and the capacitance of the floating diffusion FD of the pixel PX1 is fixed), the output value of the pixel PX1 indicated by the vertical axis in FIG. The sensitivity may be read as the sensitivity (relative value) of the pixel PX1.

  As shown in FIG. 8, in the blue pixel PX1 (B), the dependence of the output value of the pixel PX1 on the adjustment voltage VA is smaller than that of the green pixel PX1 (G) and the red pixel PX1 (R). . That is, in the green pixel PX1 (G) and the red pixel PX1 (R), the output value of the pixel PX1 can be adjusted by adjusting the adjustment voltage VA. For example, in the green pixel PX1 (G) and the red pixel PX1 (R), their output values decrease as the adjustment voltage VA is increased.

  Therefore, in high-sensitivity imaging, for example, the sensitivity adjustment unit 32 illustrated in FIG. 1 applies the adjustment voltage VA of 1 V to the charge absorption layer ABL1, thereby increasing the quantum efficiency of the photodiode PD. In this case, even when the amount of incident light is small, the pixel PX1 can output a signal with a high SN ratio.

  On the other hand, in low-sensitivity imaging, for example, the sensitivity adjustment unit 32 applies an adjustment voltage VA of 6 V or 10 V to the charge absorption layer ABL1, thereby reducing the quantum efficiency of the photodiode PD. In this case, the dynamic range of the photodiode PD can be expanded. Therefore, it is possible to capture a large amount of light without whiteout without increasing the area of the light receiving surface of the charge storage unit NA1. This is because the number of charges stored in the charge storage unit NA1 decreases as the quantum efficiency of the photodiode PD decreases.

  Note that in low-sensitivity imaging, since the amount of incident light is large, even if the quantum efficiency of the photodiode PD is lowered, a large amount of charge is accumulated in the charge accumulation unit NA1. Therefore, in low-sensitivity imaging, the pixel PX1 can output a signal with a high SN ratio even if the quantum efficiency of the photodiode PD is lowered. Further, the circuit gain of the amplification transistor MAM, the column amplifier CA, and the like has a maximum allowable signal value. Therefore, if the quantum efficiency of the photodiode PD is high, problems such as saturation may occur in those circuits. In this embodiment, since the quantum efficiency of the photodiode PD can be easily reduced, such a problem does not occur.

  Further, as shown in FIG. 8, the sensitivity of the photodiode PD of the green pixel PX1 (G) is higher than that of the blue pixel PX1 (B) and the red pixel PX1 (R). For this reason, for example, the dynamic range of the imaging device depends on the dynamic range of the photodiode PD of the green pixel PX1 (G). In this embodiment, by setting a large adjustment voltage VA that reversely biases the diode D1 corresponding to the green pixel PX1 (G), the green pixel PX1 (G) that is a constraint condition of the dynamic range of the imaging device is set. The quantum efficiency of the photodiode PD can be reduced. Thereby, in this embodiment, the dynamic range of an imaging device can be expanded easily.

  FIG. 9 shows an example of the operation of the solid-state imaging device 10 shown in FIG. FIG. 9 shows the operation of the solid-state imaging device 10 when the pixel signal OUTS and the noise signal OUTN are read from each pixel PX1 in the n-th row of the pixel array ARY shown in FIG.

  The period T1 is a period for accumulating the pixel signal OUTS and the noise signal OUTN of each pixel PX1 in the capacitors CS and CN of the signal accumulation unit 13, respectively. The period T2 is a horizontal scanning period for sequentially outputting the pixel signal OUTS and the noise signal OUTN stored in the capacitors CS and CN of the signal storage unit 13, respectively. For example, a period T1 (n) and a period T2 (n) indicate periods T1 and T2 for reading out the signal of the pixel PX1 in the n-th row, respectively. Hereinafter, the elements shown in FIG. 3 of each pixel PX1 in the n-th row may be referred to by adding n to the end of the code. For example, the amplification transistor MAM of each pixel PX1 in the nth row is also referred to as an amplification transistor MAMn.

  For example, the sensitivity adjustment unit 32 illustrated in FIG. 1 described above applies the adjustment voltage VA corresponding to the imaging sensitivity to the charge absorption layer ABL1 illustrated in FIG. 5 before the period T1. Further, before the period T1 (n) starts, the reset signal RES (n) is maintained at a high level (FIG. 9A), and the reset transistor MRSn is turned on, so that the voltage of the floating diffusion FDn is initially It has been reset to a state (hereinafter also referred to as a reset state).

  In the period T1 (n), first, the reset signal RES (n) changes from the high level to the low level (FIG. 9B), and the reset transistor MRSn is turned off. Thereby, the floating diffusion FDn can accumulate the signal charge from the photodiode PDn when the transfer transistor MTRn is turned on. Note that the voltage of the floating diffusion FDn is maintained in the reset state until the signal charge is transferred from the photodiode PDn.

  Next, the selection signal SEL (n) changes from the low level to the high level (FIG. 9C), and the pixel selection transistor MSEn is turned on. As a result, a signal is output from the source of the amplification transistor MMAn. That is, the amplification transistor MAMn outputs a voltage corresponding to the voltage of the floating diffusion FDn (reset voltage) to the vertical signal line VL via the pixel selection transistor MSEn. Note that the voltage output to the vertical signal line VL is inverted and amplified by the column amplifier CA.

  Then, the control signal TN changes from the low level to the high level (FIG. 9 (d)), and the transistor MN1 is turned on. As a result, a signal (noise signal OUTN) corresponding to the reset state of the pixel PX1 in the n-th row is accumulated in the capacitor CN of the signal accumulation unit 13. Thereafter, the control signal TN changes from a high level to a low level (FIG. 9 (e)), and the transistor MN1 is turned off. Thereby, the noise signal OUTN of the pixel PX1 in the n-th row is held in the capacitor CN.

  After the control signal TN changes from the high level to the low level, the transfer signal TX (n) changes from the low level to the high level (FIG. 9 (f)). Then, after a certain period of time, the transfer signal TX (n) changes from a high level to a low level (FIG. 9 (g)). As a result, the transfer transistor MTRn is turned on for a certain period, and the signal charge stored in the charge storage portion NA1 of the photodiode PDn is transferred to the floating diffusion FDn through the transfer transistor MTRn. Then, a signal voltage corresponding to the voltage of the floating diffusion FDn (the voltage of the capacitor CFD in which signal charges are accumulated) is output from the amplification transistor MAMn to the vertical signal line VL via the pixel selection transistor MSEn. The voltage output to the vertical signal line VL is inverted and amplified by the column amplifier CA shown in FIG.

  After the transfer signal TX (n) changes from the high level to the low level, the control signal TS changes from the low level to the high level (FIG. 9 (h)), and the transistor MS1 is turned on. Accordingly, a signal (pixel signal OUTS) including a signal component corresponding to the signal charge accumulated in the charge accumulation unit NA1 of the photodiode PD of the pixel PX1 in the n-th row is accumulated in the capacitor CS of the signal accumulation unit 13. . Thereafter, the control signal TS changes from the high level to the low level (FIG. 9 (i)), and the transistor MS1 is turned off. Thereby, the pixel signal OUTS of the pixel PX1 in the n-th row is held in the capacitor CS.

  In the horizontal scanning period T2 (n), the control signal GH sequentially changes to a high level (FIG. 9 (j, k)). For example, when the control signal GH corresponding to the output target column is changed to a high level, the horizontal scanning circuit 15 changes the other control signal GH to a low level. Accordingly, the transistors MS2 and MN2 are sequentially turned on, and the signals OUTS and OUTN held in the capacitors CS and CN of the signal storage unit 13 are sequentially output. In the horizontal scanning period T2, for example, the control signal RES is maintained at a high level, and the control signals SEL, TX, TN, and TS are maintained at a low level.

  As described above, in this embodiment, the pixel PX1 has the charge absorption layer ABL1 to which the adjustment voltage VA is applied. The charge absorption layer ABL1 formed over the pixel array ARY is disposed below the charge accumulation portion NA1 of the photodiode PD and spaced from the charge accumulation portion NA1. For this reason, in this embodiment, the quantum efficiency of the photodiode PD can be adjusted by adjusting the adjustment voltage VA applied to the charge absorption layer ABL1. Therefore, in this embodiment, in the case of high-sensitivity imaging, the quantum efficiency of the photodiode PD can be increased and the SN ratio can be increased by reducing the adjustment voltage VA applied to the charge absorption layer ABL1. In the case of low-sensitivity imaging, the quantum efficiency of the photodiode PD can be lowered and the dynamic range can be expanded by increasing the adjustment voltage VA applied to the charge absorption layer ABL1. That is, in this embodiment, an imaging apparatus with a high SN ratio and a wide dynamic range can be provided.

  FIG. 10 shows a cross section of the pixel PX1 of the imaging apparatus according to another embodiment. FIG. 10 corresponds to a cross section taken along the line A-A ′ of the pixel PX <b> 1 shown in FIG. 4. Further, in FIG. 10, description of a light shielding film, a microlens, and the like is omitted for easy understanding of the drawing. The imaging device of this embodiment is provided with a charge absorption layer ABL2 instead of the charge absorption layer ABL1 shown in FIG. Other configurations are the same as those of the embodiment described with reference to FIGS. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the imaging device shown in FIGS. 4 and 5, the charge absorption layer ABL1 is arranged over the pixel array ARY, and the distance from the light receiving surface to the charge absorption layer ABL1 is constant. In the image pickup apparatus according to the present embodiment, the charge absorption layer ABL2 has the same configuration arranged over the pixel array ARY, but the interval from the light receiving surface to the charge absorption layer ABL2, that is, the charge accumulation unit NA1 and the charge absorption layer. The distance DIS with respect to ABL2 is formed to be different from each other corresponding to the color of the color filter CFL arranged in the pixel PX1. For example, the distance DISg between the charge storage portion NA1 and the charge absorption layer ABL2 in the green pixel PX1 (G) is shorter than the distance DISr between the charge storage portion NA1 and the charge absorption layer ABL2 in the red pixel PX1 (R). Thereby, the quantum efficiency of the photodiode PD when the adjustment voltage VA is applied to the charge absorption layer ABL2 can be made different between the red pixel PX1 (R) and the green pixel PX1 (G). For example, in this embodiment, the decrease in the quantum efficiency of the photodiode PD of the red pixel PX1 (R) when the adjustment voltage VA is increased can be made smaller than that of the green pixel PX1 (G).

  Since the quantum efficiency of the photodiode PD of the green pixel PX1 (G) is a limiting condition of the dynamic range of the imaging device, even if the quantum efficiency of the photodiode PD of the red pixel PX1 (R) is high, it does not cause a big problem. . Further, the distance DIS between the charge storage portion NA1 and the charge absorption layer ABL2 of the pixel PX1 of a plurality of colors (for example, red, green, and blue) is adjusted according to the color of the arranged color filter CFL, and the photodiode PD The quantum efficiency may be set appropriately for each color. In that case, although not shown, the distance DISb between the charge storage portion NA1 of the blue pixel PX1 (B) and the charge absorption layer ABL2 is such that the quantum efficiency of the photodiode PD in the blue pixel PX1 (B) is a desired value. It is set separately as follows.

  Note that the configuration according to the present embodiment can be suitably employed for each of the red pixel PX1 (R) group, the green pixel PX1 (G) group, and the blue pixel PX1 (B) group that constitute the pixel array ARY. For example, for all the green pixels PX1 (G) belonging to the green pixel PX1 (G) group, the distance DISg between the charge storage portion NA1 and the charge absorption layer ABL2 is set to the distance DISg, and the red pixels belonging to the red pixel PX1 (R) group. For all of PX1 (R), the distance between the charge storage portion NA1 and the charge absorption layer ABL2 can be a distance DISr shorter than the distance DISg. Thereby, the quantum efficiency of the photodiode PD when the adjustment voltage VA is applied to the charge absorption layer ABL2 can be made different between the red pixel PX1 (R) group and the green pixel PX1 (G) group. Note that the interval between the charge storage portion NA1 and the charge absorption layer ABL2 need not be constant for all the pixels PX1 belonging to the same pixel group. Even for the pixel PX1 in the same pixel group, for example, the distance DIS may be changed between the central portion and the peripheral portion of the pixel array ARY as necessary.

  As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 9 can be obtained.

  11 to 13 show an example of the solid-state imaging device 10 of the imaging apparatus according to another embodiment. In the solid-state imaging device 10 of this embodiment, a pixel PX2 is provided instead of the pixel PX1 shown in FIG. Further, in the red pixel PX2 (R), the green pixel PX2 (G), and the blue pixel PX2 (B), a charge absorption layer ABL3 is provided for each pixel PX2 instead of the charge absorption layer ABL1 shown in FIG. Yes. Adjustment voltages VAr, VAg, and VAb are supplied to the charge absorption layer ABL3 provided for each pixel PX2 in accordance with the color filter CFL that is arranged. For example, the sensitivity adjustment unit 32 illustrated in FIG. 1 supplies adjustment voltages VAr, VAg, and VAb corresponding to the imaging sensitivity to the red pixel PX2 (R), the green pixel PX2 (G), and the blue pixel PX2 (B), respectively. To do. Other configurations are the same as those of the embodiment described with reference to FIGS. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The circuit configuration of the pixel PX2 shown in FIG. 11 is different from the cathode of the diode D2 according to the color of the color filter CFL provided, with the diode D2 provided for each pixel PX2 instead of the diode D1 shown in FIG. The adjustment voltages VAr, VAg, and VAb are applied. The other circuit configuration of the pixel PX2 is the same as that of the pixel PX1. For example, the diode D2 of the green pixel PX2 (G) absorbs a part of the charge generated by the photodiode PD when the adjustment voltage VAg is applied to the cathode. Similarly, adjustment voltages VAr and VAb are applied to the cathodes of the diodes D2 of the red pixel PX2 (R) and the blue pixel PX2 (B), respectively, and a part of the charge generated by the photodiode PD is absorbed. . That is, in this embodiment, the adjustment voltages VAr, VAg, and VAb applied to the cathode of the diode D2 can be set for each color.

  FIG. 12 shows an example of a planar structure of the pixel PX2 shown in FIG. The shaded area in the figure indicates the gate of the transistor, and the rectangle with a cross indicates the contact area. In FIG. 12, the wiring of the power supply VDD, the grounding line, and the like are omitted for easy understanding of the drawing. The pixel array ARY of this embodiment includes a charge absorption layer ABL3 instead of the charge absorption layer ABL1 shown in FIG. 4, and wirings LVAr, LVAg, and LVAb instead of the wiring LVA. The other configuration of the pixel array ARY of this embodiment is the same as the pixel array ARY shown in FIG.

  The charge absorption layer ABL3 is an n-type region provided separately for each pixel PX2, and is a part of the diode D2 described above. Note that the adjustment voltages VAr, VAg, and VAb are respectively supplied to the charge absorption layers ABL3 of the red pixel PX2 (R), the green pixel PX2 (G), and the blue pixel PX2 (B) through the wirings LVAr, LVAg, and LVAb, respectively. Applied.

  FIG. 13 shows a cross section taken along line C-C ′ of the pixel PX <b> 2 shown in FIG. 12. Note that in FIG. 13, illustration of a light shielding film, a microlens, and the like is omitted for easy understanding of the drawing. A red color filter CFL (R) is disposed on the light receiving surface of the photodiode PD of the red pixel PX2 (R), and a green color filter is disposed on the light receiving surface of the photodiode PD of the green pixel PX2 (G). CFL (G) is arranged. A blue color filter CFL (B) is disposed on the light receiving surface of the photodiode PD of the blue pixel PX2 (B) (not shown).

  On the n-type silicon substrate NSUB side of the charge storage portion NA1 of each pixel PX2, a charge absorption layer ABL3 provided separately for each pixel PX2 is disposed at a distance from the charge storage portion NA1. A region between the charge absorption layers ABL3 adjacent to each other and a region PA1 between the charge storage portion NA1 and the charge absorption layer ABL3 are p-type semiconductors and constitute a part of the p-type well region PWELL. The region PA1 is a part of the diode D2. That is, the diode D2 is a pn junction diode, and has a junction (pn junction) between the p-type semiconductor region PA1 and the n-type semiconductor charge absorption layer ABL3.

  As shown in FIG. 13, each pixel PX2 has an n-type region NA7 electrically connected to the charge absorption layer ABL3. For example, the n-type region NA7 is formed integrally with the charge absorption layer ABL3 by introducing an n-type impurity into the p-type well region PWELL. The n-type region NA7 only needs to be electrically connected to the charge absorption layer ABL3 and may not be formed integrally with the charge absorption layer ABL3.

  For example, in the red pixel PX2 (R), the n-type region NA7 is formed to extend from the charge absorption layer ABL3 to the surface of the p-type well region PWELL (light receiving surface side in the drawing) and is electrically connected to the wiring LVAr Has been. For example, in the green pixel PX2 (G), the n-type region NA7 is formed to extend from the charge absorption layer ABL3 to the surface of the p-type well region PWELL, and is electrically connected to the wiring LVAg. In the blue pixel PX2 (B) (not shown), the n-type region NA7 is formed extending from the charge absorption layer ABL3 to the surface of the p-type well region PWELL, and is electrically connected to the wiring LVAb.

  Accordingly, for example, the sensitivity adjustment unit 32 illustrated in FIG. 1 uses the adjustment voltages VAr, VAg, and VAb that are set according to the imaging sensitivity as illustrated in FIG. 11 to the red pixel PX2 (R) and the green pixel PX2, respectively. (G), and can be applied to the charge absorption layer ABL3 of the blue pixel PX2 (B). For example, the sensitivity adjustment unit 32 applies the adjustment voltage VAr of 1V to the charge absorption layer ABL3 of the red pixel PX2 (R) in the low-sensitivity imaging, and absorbs the charge of the green pixel PX2 (G) and the blue pixel PX2 (B). Adjustment voltages VAg and VAb of 10 V are applied to the layer ABL3, respectively. For example, the adjustment voltage VAb may be set to a voltage value different from the adjustment voltages VAg and VAr, or may be set to the same voltage value as the adjustment voltage VAr. That is, the sensitivity adjustment unit 32 individually applies the adjustment voltages VAr, VAg, and VAb corresponding to the color of the color filter CFL to the charge absorption layer ABL3 of each pixel PX2.

  As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 9 can be obtained. Further, in this embodiment, since the charge absorption layer ABL3 is provided separately for each pixel PX2, the charge absorption layer ABL3 of the red pixel PX2 (R), the green pixel PX2 (G), and the blue pixel PX2 (B). The adjustment voltages VAr, VAg, and VAb to be applied to can be set for each color. Thereby, the quantum efficiency of the photodiode PD can be adjusted for each color.

  Note that the configuration according to the present embodiment can be suitably employed for each of the red pixel PX2 (R) group, the green pixel PX2 (G) group, and the blue pixel PX2 (B) group constituting the pixel array ARY. For example, the charge absorption layer ABL3 is provided for all the green pixels PX2 (G) belonging to the green pixel PX2 (G) group, and the adjustment voltage VAg is applied. The same applies to the red pixel PX2 (R) and the blue pixel PX2 (B). Thereby, the quantum efficiency of the photodiode PD can be adjusted for each color over the entire pixel array ARY. Note that the adjustment voltage VA does not have to be constant for all the pixels PX2 belonging to the same pixel group. Even in the pixel PX2 in the same pixel group, for example, the adjustment voltage VA may be changed between the central portion and the peripheral portion of the pixel array ARY as necessary.

  FIG. 14 shows an example of the solid-state imaging element 10 of the imaging apparatus according to another embodiment. The solid-state imaging device 10 of this embodiment is configured by providing a pixel PX3 instead of the pixel PX1 shown in FIG. 2, and adding a capacitance control unit 16 to the solid-state imaging device 10 shown in FIG. Other configurations are the same as those of the embodiment described with reference to FIGS. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The capacity control unit 16 supplies control signals VCr, VCg, and VCb corresponding to the photographing sensitivity to the red pixel PX2 (R), the green pixel PX2 (G), and the blue pixel PX2 (B), respectively. Note that the control signals VCr, VCg, and VCb are signals for controlling the capacitance value of the floating diffusion FD as a charge-voltage converter shown in FIG. Hereinafter, the control signals VCr, VCg, and VCb are also referred to as control signals VC, for example, when they are not distinguished for each color. Here, the capacitance control unit 16 is formed on the same substrate as the solid-state imaging device 10, but is not limited thereto, and may be separately provided outside the solid-state imaging device 10. For example, the capacity control unit 16 may be provided in the control unit 30.

  FIG. 15 illustrates an example of a circuit configuration of the pixel PX3 (R) illustrated in FIG. The green pixel PX3 (G) and the blue pixel PX3 (B) are the same as the red pixel PX3 (R) except for the supplied control signals VCg and VCb. The pixel PX3 includes a capacitor CFD ′ for variably controlling the capacitance value of the floating diffusion FD. The capacitor CFD ′ includes the parasitic capacitor CFD shown in FIG. Other configurations of the pixel PX3 are the same as those of the pixel PX1 shown in FIG.

  The capacitor CFD ′ includes, for example, an nMOS transistor having a gate formed on the p-type well region PWELL illustrated in FIG. 5 via an oxide film (insulating film), and electrically connects to the floating diffusion FD. Connected. For example, the capacitance value of the capacitor CFD 'when the high level control signal VC is applied to the gate is larger than that when the low level control signal VC is applied to the gate. Thus, the capacitance value of the capacitor CFD ′ changes according to the control signal VC.

  Since the capacitor CFD ′ is electrically connected to the floating diffusion FD, the total capacitance value of the floating diffusion FD including the parasitic capacitor CFD changes according to the control signal VC. Therefore, in this embodiment, the conversion gain in the floating diffusion FD can be adjusted by adjusting the control signal VC. Here, the conversion gain in the floating diffusion FD is a conversion ratio between the signal charge transferred from the photodiode PD and the signal voltage input to the gate of the amplification transistor MAM.

  FIG. 16 illustrates an example of a planar structure of the pixel PX3 illustrated in FIG. The shaded area in the figure indicates the gate of the transistor, and the rectangle with a cross indicates the contact area. In FIG. 16, the wiring of the power supply VDD, the ground line, and the like are omitted for easy understanding of the drawing. The pixel array ARY of this embodiment is configured by adding wirings LVCr, LVCg, and LVb to the pixel array ARY shown in FIG. 4 and providing a pixel PX3 instead of the pixel PX1. The other configuration of the pixel array ARY of this embodiment is the same as the pixel array ARY shown in FIG. For example, the cross section taken along the line A-A ′ of the pixel PX <b> 3 shown in FIG. 16 is the same as FIG. 5 described above.

  The gate GT5 to which the control signal VC is applied is the gate of the nMOS transistor that forms the capacitor CFD ', and is disposed adjacent to the source (n-type region NA6) of the reset transistor MRS. Further, control signals VCr, VCg, and VCb are respectively applied to the gates GT5 of the red pixel PX3 (R), the green pixel PX3 (G), and the blue pixel PX3 (B) through wirings LVCr, LVCg, and LVCb, respectively. The That is, in this embodiment, the control signal VC applied to the gate GT5 of the pixel PX3 can be set for each color.

  When the control signal VC is applied to the gate GT5 arranged adjacent to the n-type region NA6, the gate signal is inverted to the vicinity of the surface of the p-type well region PWELL on the lower side of the gate GT5 (position overlapping the gate GT5 in the figure). A layer is formed. This inversion layer is electrically connected to the n-type region NA6, which is one of the regions for forming the parasitic capacitance CFD, and functions as a further region for forming the capacitance CFD 'of the floating diffusion FD. As a result, the capacitance value of the floating diffusion FD can be increased as compared with the above-described embodiment having only the parasitic capacitance CFD. Note that the capacitance in the inversion layer changes according to the magnitude (level) of the control signal VC applied to the gate GT5. Therefore, the capacitance value of the floating diffusion FD can be adjusted by variably controlling the level of the control signal VC.

  Thereby, in this embodiment, the total capacity value of the floating diffusion FD can be adjusted by adjusting the control signal VC, and the conversion gain in the floating diffusion FD can be adjusted. That is, in this embodiment, the sensitivity of the pixel PX3 can be adjusted by adjusting the conversion gain in the floating diffusion FD. For example, the sensitivity of the pixel PX3 is a conversion ratio between the amount of incident light and the signal voltage output from the pixel PX3.

  Here, as shown in FIG. 8, the sensitivity of the red pixel PX3 (R) is higher than the sensitivity of the green pixel PX3 (G) and the blue pixel PX3 (B) when the conversion gain of the floating diffusion FD is the same. Low. Therefore, for example, in the case of low-sensitivity imaging in which the adjustment voltage VA of 10 V is applied to the charge absorption layer ABL1, when it is not desired to reduce the sensitivity of the red pixel PX3 (R), the capacitance adjustment unit 16 shown in FIG. May be operated as follows, for example.

  In the low sensitivity shooting, the capacity adjustment unit 16 applies the low level control signal VCr to the gate GT5 of the red pixel PX3 (R), and applies the high level control signals VCg and VCb to the green pixel PX3 (G) and the blue pixel PX3. Each is applied to the gate GT5 of (B). In this case, the capacitance value of the floating diffusion FD of the red pixel PX3 (R) is smaller than that of the green pixel PX3 (G) and the blue pixel PX3 (B). Alternatively, the control signal VCr is not applied to the gate GT5 of the red pixel PX3 (R), and the control signals VCg and VCb are respectively applied to the gate GT5 of the green pixel PX3 (G) and the blue pixel PX3 (B). Good.

  For this reason, the conversion gain in the floating diffusion FD of the red pixel PX3 (R) is larger than the conversion gain in the floating diffusion FD of the green pixel PX3 (G) or the blue pixel PX3 (B). As a result, for example, as shown in FIG. 17 described later, the sensitivity of the red pixel PX3 (R) when the adjustment voltage VA is 10V is almost the same as the sensitivity of the red pixel PX3 (R) when the adjustment voltage VA is 1V. Maintained at the same value. Thus, in this embodiment, the capacitance of the floating diffusion FD of the red pixel PX3 (R) is made smaller than that of the green pixel PX3 (G) and the blue pixel PX3 (B) by using the variable capacitor CFD ′. As a result, the sensitivity of the red pixel PX3 (R) can be increased, and the signal voltage output from the red pixel PX3 (R) can be increased.

  For example, in high-sensitivity imaging in which the adjustment voltage VA of 1 V is applied to the charge absorption layer ABL1, the capacitance adjustment unit 16 applies the high level control signals VCr, VCg, and VCb to the red pixel PX3 (R) and the green pixel. The voltage is applied to the gate GT5 of PX3 (G) and the blue pixel PX3 (B), respectively. As described above, the capacity adjustment unit 16 controls the control signal VC according to the photographing sensitivity. Further, the capacity adjustment unit 16 may adjust the control signals VCr, VCg, and VCb for each color in order to adjust the color balance of the image sensor 10.

  FIG. 17 shows an example of the spectral output of the pixel PX3 shown in FIG. The horizontal axis in the figure indicates the wavelength of incident light (unit: nm), and the vertical axis in the figure indicates the output value of the pixel PX3 relative to the incident light as a relative value. The thin line in the figure indicates the output value of the pixel PX3 when the adjustment voltage VA is set to 1 V and the control signals VCr, VCg, and VCb are all set to a high level. For example, it is applied during high-sensitivity shooting. The thick line in the figure shows the output value of the pixel PX3 when the adjustment voltage VA is set to 10 V and the control signals VCr, VCg, and VCb are respectively set to the low level, the high level, and the high level. This setting is applied at the time of low-sensitivity shooting, for example.

  The output value of the red pixel PX3 (R) when the adjustment voltage VA is 10V is substantially the same as the output value of the red pixel PX3 (R) when the adjustment voltage VA is 1V. As described above, in this embodiment, when the adjustment voltage VA is 10 V, the low level control signal VCr is applied to the gate GT5 of the red pixel PX3 (R). The output value of the red pixel PX3 (R) that has shown the value can be increased.

  As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 9 can be obtained. Further, in this embodiment, each pixel PX3 has a variable capacitor CFD 'whose capacitance value is variably set by the control signals VCr, VCg, and VCb. Thereby, in this embodiment, the total capacity value of the floating diffusion FD can be set for each color, and the color balance of the image sensor 10 can be adjusted.

  Note that the configuration according to the present embodiment can be suitably employed for each of the red pixel PX3 (R) group, the green pixel PX3 (G) group, and the blue pixel PX3 (B) group that constitute the pixel array ARY. For example, the floating diffusion FD having the variable capacitance CFD ′ is provided for all the green pixels PX3 (G) belonging to the green pixel PX3 (G) group, and the control signal VCg is applied. The same applies to the red pixel PX3 (R) and the blue pixel PX3 (B). Note that the control signal VC need not be constant for all the pixels PX3 belonging to the same pixel group. Even for the pixel PX3 in the same pixel group, for example, the control signal VC may be changed between the central portion and the peripheral portion of the pixel array ARY as necessary.

  In the embodiment described with reference to FIGS. 1 to 9, the example in which the charge absorption layer ABL1 is formed in the p-type well region PWELL has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 18, an n-type silicon substrate NSUB may be used as the charge absorption layer ABL1. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiments described with reference to FIGS. 11 to 13, the example in which the charge absorption layer ABL3 is provided in each pixel PX2 has been described. The present invention is not limited to such an embodiment. For example, the charge absorption layer ABL3 is not particularly limited, but may be provided only in the green pixel PX2 (G). In this case, the charge absorption layer ABL3 is provided only for the group of photoelectric conversion units (photodiodes PD) in which the green color filter CFL is provided among the pixels PX2 constituting the pixel array ARY. Also in this case, it is possible to reduce the quantum efficiency of the photodiode PD of the green pixel PX2 (G) that is a constraint condition of the dynamic range of the imaging device. Alternatively, the charge absorption layer ABL3 is not particularly limited, but may be provided only in the green pixel PX2 (G) and the blue pixel PX2 (B). In this case, among the pixels PX2 constituting the pixel array ARY, a group of photoelectric conversion units (photodiode PD) provided with the green color filter CFL and a photoelectric conversion unit (photodiode PD) provided with the blue color filter CFL. The charge absorption layer ABL3 is provided for each of the groups. In this case, compared to the quantum efficiency of the red pixel PX2 (R), the quantum efficiency of the photodiode PD of the green pixel PX2 (G) and the blue pixel PX2 (B) can be reduced. Therefore, also in this case, the same effect as that of the above-described embodiment can be obtained.

  In the embodiments described with reference to FIGS. 14 to 17, the example in which the capacitance value related to the capacitance CFD ′ of the floating diffusion FD is adjusted by the control signal VC has been described. The present invention is not limited to such an embodiment. For example, the capacitor CFD ′ may not be configured to include the gate GT5, but may be fixed to a capacitor value at which the color balance of the image sensor 10 is optimized. That is, the capacitance CFD ′ may be fixed to different capacitance values corresponding to the color filters CFL of a plurality of colors. In this case, for example, if the size of the n-type region NA6 forming the capacitance is changed for each group of the pixels PX in which the color filters CFL of the same color are arranged so as to have different capacitance values corresponding to the color filter CFL. Good. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiment described with reference to FIGS. 14 to 17, the gates GT5 of the red pixel PX3 (R), the green pixel PX3 (G), and the blue pixel PX3 (B) are respectively connected to the gates LVCr, LVCg, and LVCb. The example in which the control signals VCr, VCg, and VCb are applied has been described. The present invention is not limited to such an embodiment. For example, the wiring LVCr may be also used as the wiring LVCb. In this case, for example, when a signal is read from the pixel PX3 in the row including the red pixel PX3 (R), the control signal VCr is applied to the gate GT5 of the red pixel PX3 (R) via the wiring LVCr. When a signal is read from the pixel PX3 in the row including the blue pixel PX3 (B), the control signal VCb is applied to the gate GT5 of the blue pixel PX3 (B) through the wiring LVCr. Also in this case, the same effect as the above-described embodiment can be obtained.

  Alternatively, the capacitor CFD ′ is controlled by applying a control signal to the gates GT5 of the plurality of pixels PX3 arranged in the same column via a common wiring as disclosed in Japanese Patent Application Laid-Open No. 2008-305983. May be. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiments described with reference to FIGS. 14 to 17, the example in which the control signal VC is set to either the high level or the low level has been described. The present invention is not limited to such an embodiment. For example, the control signal VC may be selectively set from three or more voltage values. In this case, the capacitance value of the capacitor CFD 'can be adjusted in multiple stages, and the conversion gain in the floating diffusion FD can be optimally adjusted. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiment described with reference to FIGS. 14 to 17, the example in which the capacitor CFD ′ is added to the pixel PX <b> 1 illustrated in FIG. 3 has been described. The present invention is not limited to such an embodiment. For example, the capacitor CFD ′ may be added to the pixel PX2 in the embodiment described with reference to FIGS. Also in this case, the same effect as the above-described embodiment can be obtained.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  It can be used for an imaging device.

  DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor; 11 ... Vertical scanning circuit; 12 ... Accumulation signal selection part; 13 ... Signal accumulation part; 14 ... Horizontal selection switch part; 15 ... Horizontal scanning circuit; Control unit 32 Sensitivity adjustment unit 40 Timing generator 50 Memory 60 Storage medium 70 Monitor 80 Operation unit ABL1, ABL2, ABL3 Charge absorption layer ARY Pixel array CA Column amplifier; CFD, parasitic capacitance; CFD ', floating capacitance; CFL, color filter; D1, diode, FD, floating diffusion, IS, constant current source, JCP, junction, MAM, amplification transistor, MRS, reset transistor, MSE ··· Pixel selection transistor; MTR · Transfer transistor; NA1 · Charge storage unit · PA1 · P-type half Areas of the body; PD ‥ photodiode; PX1, PX2, PX3 ‥ pixel; VL ‥ vertical signal line

Claims (7)

A well made of a first conductivity type semiconductor and a charge accumulation portion made of a second conductivity type semiconductor and provided on the light receiving surface side of the first conductivity type semiconductor are configured to generate charges by photoelectrically converting incident light. A plurality of pixels including a photoelectric conversion unit;
A plurality of color filters provided for each color corresponding to each of the plurality of pixels;
A shooting sensitivity setting section for setting the shooting sensitivity;
For a pixel provided with at least one color filter, a second conductivity type charge absorbing layer disposed with the first conductivity type semiconductor interposed below the charge storage portion;
An image pickup apparatus comprising: a voltage application unit configured to apply a voltage to the charge absorption layer based on the imaging sensitivity set by the imaging sensitivity setting unit. The imaging device according to claim 1,
The image pickup apparatus, wherein the charge absorption layer is provided in a plurality of pixels provided with color filters of different colors. The imaging apparatus according to claim 2, wherein
The image pickup apparatus, wherein an interval from the light receiving surface to the charge absorption layer is different in a plurality of pixels provided with the color filters of different colors. In the imaging device according to claim 2 or 3,
The charge absorption layer is provided separately for each pixel,
The image pickup apparatus, wherein the voltage application unit applies a voltage corresponding to a color of the color filter to the charge absorption layer. The imaging apparatus according to any one of claims 1 to 4,
The pixel includes a charge-voltage conversion unit to which the charge generated by the photoelectric conversion unit is transferred,
The image pickup apparatus, wherein the charge-voltage conversion unit has different capacitance values corresponding to colors of the color filters provided in the pixels. The imaging device according to claim 5.
An imaging apparatus comprising: a capacitance control unit that controls a capacitance value of the charge-voltage conversion unit based on imaging sensitivity set by the imaging sensitivity setting unit. The imaging device according to any one of claims 1 to 6,
The imaging apparatus according to claim 1, wherein an impurity concentration of the charge absorption layer is higher than an impurity concentration of the first conductivity type semiconductor interposed between the charge storage portion and the charge absorption layer.

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