JP2011097080A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a high breakdown voltage semiconductor device is provided.
A semiconductor layer is selectively ion-implanted using a mask, a first semiconductor region of a first conductivity type is formed in the semiconductor layer, and a first conductivity type impurity concentration is higher than that of the first semiconductor region. Forming a first conductive type second semiconductor region having a low conductivity at the same time, forming a second conductive type source region on the first semiconductor region, and forming a source on the second semiconductor region A step of forming a drain region of the second conductivity type at a position sandwiching the gate electrode between the region and the region of the semiconductor layer between the gate electrode and the drain region in contact with the drain region and having an impurity concentration higher than that of the drain region Forming a low drift region of the second conductivity type.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  There are known lateral diffusion metal-oxide-semiconductor (LDMOS) structures in various breakdown voltage systems according to required applications (for example, Patent Document 1). In recent years, in order to achieve low on-resistance and high speed for LDMOS, the same fine process and fine design rules as CMOS (Complementary Metal-Oxide-Semiconductor) have been increasingly applied. By applying fine design rules, it is possible to design an LDMOS with a short channel comparable to CMOS, the size of the entire device, and an LDMOS with low voltage drive, as well as a circuit design that incorporates fine CMOS and LDMOS together. Is also possible.

JP 2007-53257 A

  The present invention provides a method for manufacturing a high breakdown voltage semiconductor device.

According to one embodiment of the present invention, ion implantation is selectively performed on a semiconductor layer using a mask, and the first conductivity type first semiconductor region and the first semiconductor region are formed in the semiconductor layer. A step of simultaneously forming a second semiconductor region of a first conductivity type having a low first conductivity type impurity concentration, a step of forming a gate electrode on the semiconductor layer via an insulating film, and the first semiconductor region Forming a second conductivity type source region thereon; and forming a second conductivity type drain region on the second semiconductor region at a position sandwiching the gate electrode with the source region. Forming a drift region of a second conductivity type in contact with the drain region and having a lower impurity concentration than the drain region in a surface layer portion between the gate electrode and the drain region in the semiconductor layer. Features provided The method of manufacturing a semiconductor device that is provided.
According to another aspect of the present invention, the semiconductor layer is selectively ion-implanted using a mask, and the second conductive type first semiconductor region is formed in the semiconductor layer. A step of simultaneously forming a second conductivity type second semiconductor region having a second conductivity type impurity concentration higher than that of the semiconductor region; and ion implantation uniformly over the entire surface of the first semiconductor region and the second semiconductor region And forming a first conductivity type third semiconductor region on the first semiconductor region, and a first conductivity type fourth impurity having a first conductivity type impurity concentration lower than that of the third semiconductor region. A step of simultaneously forming a semiconductor region on the second semiconductor region, a step of forming a gate electrode on the semiconductor layer via an insulating film, and a second conductivity type on the third semiconductor region. Forming a source region of the second semiconductor region and a step of forming the source region on the fourth semiconductor region. Forming a drain region of a second conductivity type at a position sandwiching the gate electrode between the source region and the drain region in a surface layer portion of the semiconductor layer between the gate electrode and the drain region. Forming a second conductivity type drift region having an impurity concentration lower than that of the drain region. The method for manufacturing a semiconductor device is provided.

  According to the present invention, a method for manufacturing a high breakdown voltage semiconductor device is provided.

The schematic diagram which shows the principal part cross-section of the semiconductor device which concerns on embodiment of this invention. The schematic diagram which shows 1st Embodiment of LDMOS in the semiconductor device. The schematic diagram which shows the manufacturing method of LDMOS shown in FIG. FIG. 4 is a schematic diagram illustrating a process following FIG. 3. The schematic diagram which shows the process of following FIG. The schematic diagram which shows the example of a plane pattern of the mask for ion implantation used by this embodiment. The schematic diagram which shows 2nd Embodiment of LDMOS. FIG. 8 is a schematic diagram showing a method for manufacturing the LDMOS shown in FIG. 7. FIG. 9 is a schematic diagram illustrating a process following FIG. 8. FIG. 8 is a schematic diagram showing another method for manufacturing the LDMOS shown in FIG. 7. FIG. 11 is a schematic diagram illustrating a process following FIG. 10. The schematic diagram which shows 3rd Embodiment of LDMOS. The schematic diagram which shows the manufacturing method of LDMOS shown in FIG. FIG. 13 is a schematic diagram showing another method for manufacturing the LDMOS shown in FIG. 12. The schematic diagram which shows other embodiment of LDMOS. The schematic diagram which shows other embodiment of LDMOS.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is described as P type and the second conductivity type is described as N type. However, the present invention can be realized even when the first conductivity type is N type and the second conductivity type is P type. is there.

  In the semiconductor device according to this embodiment, a FET (Field Effect Transistor) having a LDMOS (Lateral Diffusion Metal-Oxide-Semiconductor) structure and a FET (Complementary Metal-Oxide-Semiconductor) structure FET are mixedly mounted on the same substrate. It has a one-chip structure. FIG. 1 shows a cross-sectional structure of the main part.

  For example, the LDMOS 10 is formed in the first transistor formation region 101 on the P-type substrate 11, and the CMOS 40 is formed in the second transistor formation region 102. A high concentration P-type well region 41 and a low concentration P-type well region 42 are formed in the first transistor formation region 101 of the substrate 11. A semiconductor layer 50 having a high concentration P-type well region 41 and a low concentration P-type well region 42 is formed in the first transistor formation region 101 of the substrate 11. A P-type well region 12 and an N-type well region 13 are formed in the second transistor formation region 102 in the substrate 11.

  The P-type well region 12 and the N-type well region 13 are isolated from each other by an insulating layer 6 having an STI (Shallow Trench Isolation) structure, for example. With respect to the P-type well region 12 and the N-type well region 13, the semiconductor layer 50 of the first transistor formation region 101 is also element-isolated by the insulating layer 6 having the STI structure.

  The CMOS 40 has an N-channel MOS 20 provided on the P-type well region 12 and a P-channel MOS 30 provided on the N-type well region 13.

In the surface layer portion of the P-type well region 12, an N ⁺ -type source region 14 and an N ⁺ -type drain region 16 are provided separately from each other. Further, an N-type LDD (Lightly Doped Drain) region 15 having an N-type impurity concentration lower than that of the source region 14 is provided adjacent to the source region 14 in the surface layer portion of the P-type well region 12. An N-type LDD region 17 having a lower N-type impurity concentration is provided adjacent to the drain region 16.

  A gate electrode 18 is provided on the P-type well region 12 between the LDD region 15 and the LDD region 17 with the insulating film 5 interposed therebetween. A sidewall insulating film 19 is provided on the sidewall of the gate electrode 18. The LDD region 15 and the LDD region 17 are located under the sidewall insulating film 19.

  On the source region 14, a source electrode 21 is provided that is electrically connected to the source region 14 through, for example, ohmic contact. On the drain region 16, a drain electrode 22 is provided that is electrically connected to the drain region 16 through, for example, ohmic contact.

  When a desired gate voltage is applied to the gate electrode 18, an N-type channel is formed in the surface layer portion of the P-type well region 12 below the gate electrode 18, and the source and drain are electrically connected.

On the other hand, in the surface layer portion of the N-type well region 13, a P ⁺ -type source region 24 and a P ⁺ -type drain region 26 are provided apart from each other. Further, a P-type LDD region 25 having a P-type impurity concentration lower than that of the source region 24 is provided adjacent to the source region 24 in the surface layer portion of the N-type well region 13, and further, P-type impurities are more than the drain region 26. A P-type LDD region 27 having a low concentration is provided adjacent to the drain region 26.

  A gate electrode 28 is provided on the N-type well region 13 between the LDD region 25 and the LDD region 27 via the insulating film 5. A sidewall insulating film 19 is provided on the side wall of the gate electrode 28. The LDD region 25 and the LDD region 27 are located under the sidewall insulating film 19.

  On the source region 24, a source electrode 31 that is electrically connected to the source region 24 through, for example, ohmic contact is provided. A drain electrode 32 is provided on the drain region 26 and is electrically connected to the drain region 26 in, for example, ohmic contact.

  When a desired gate voltage is applied to the gate electrode 28, a P-type channel is formed in the surface layer portion of the N-type well region 13 below the gate electrode 28, and the source and drain are electrically connected.

  At the same time as the formation of the CMOS 40, the LDMOS 10 is also formed using the process used in the CMOS formation.

  Hereinafter, the structure of the LDMOS 10 will be described.

[First Embodiment]
FIG. 2 is a schematic cross-sectional view of the LDMOS 10 according to the first embodiment of the present invention.

In the surface layer portion of the semiconductor layer 50, a P ⁺ -type contact region 43, an N ⁺ -type source region 44, an N-type LDD region 45, a P-type channel region 46, an N ⁻ -type drift region 47, and an N ⁺ -type Each impurity diffusion region of the drain region 48 is formed.

  The semiconductor layer 50 has a high-concentration P-type well region 41 and a low-concentration P-type well region 42 having a lower P-type impurity concentration. The high-concentration P-type well region 41 is formed by the same ion implantation process as the P-type well region 12 of the N-channel MOS 20 shown in FIG. 1, and the P-type impurity concentrations in the high-concentration P-type well region 41 and the P-type well region 12 are formed. And the profile is substantially the same. The low concentration P-type well region 42 is also formed by the same ion implantation process as the P-type well region 12 and the high concentration P-type well region 41. By using a mask described later, the low concentration P-type well region 42 is The P-type impurity concentration is made lower than that of the P-type well region 12 and the high concentration P-type well region 41.

  The contact region 43, the source region 44, the LDD region 45 and the channel region 46 are formed in the surface layer portion of the high concentration P-type well region 41. The drift region 47 and the drain region 48 are formed in the surface layer portion of the low concentration P-type well region 42.

  The inflection point of the P-type impurity concentration between the high-concentration P-type well region 41 and the low-concentration P-type well region 42 is schematically represented by a dotted line in FIG. That is, the source region 44 side has a higher effective P-type impurity concentration than the drain region 48 side than the dotted line, and conversely, the drain region 48 side more effective than the source region 44 side than the dotted line. Impurity concentration is low.

  An LDD region 45, a channel region 46, and a drift region 47 are formed in this order from the source region 44 side between the source region 44 and the drain region 48. The LDD region 45 is in contact with the source region 44, and the channel region 46 is in contact with the LDD region 45 on the opposite side of the source region 44. The LDD region 45 has a lower N-type impurity concentration than the source region 44 and the drain region 48. A contact region 43 is provided in contact with the source region 44 on the opposite side of the portion in contact with the LDD region 45. The drift region 47 has a lower N-type impurity concentration than the source region 44 and the drain region 48 and is in contact with the drain region 48.

  A source electrode 51 is provided on the contact region 43 and the source region 44. The source electrode 51 is electrically connected, for example, in ohmic contact with the contact region 43 and the source region 44. The high concentration P-type well region 41 is set to the source potential via the contact region 43. A drain electrode 52 is provided on the drain region 48, and the drain electrode 52 is electrically connected to the drain region 48 in, for example, ohmic contact.

  A gate electrode 53 is provided on the surface of the semiconductor layer 50 between the source region 44 and the drift region 47 with the insulating film 5 interposed therebetween. A sidewall insulating film 19 is provided on the side wall of the gate electrode 53. The channel region 46 is located under the gate electrode 53, and the LDD region 45 is located under the sidewall insulating film 19.

  Each impurity diffusion region and the gate electrode 53 are formed in, for example, a stripe pattern extending in a direction penetrating the paper surface. Alternatively, the contact region 43 and the source region 44 may have a structure in which the contact region 43 and the source region 44 are arranged alternately or at a certain interval in a direction penetrating the paper surface.

  When a desired gate voltage is applied to the gate electrode 53, an inversion layer is formed in the channel region 46, and the source electrode 51 is connected to the source electrode 51 through the source region 44, the LDD region 45, the inversion layer, the drift region 47 and the drain region 48. The drain electrodes 52 are electrically connected and turned on. The threshold voltage is adjusted by controlling the impurity concentration of the channel region 46.

  In the LDMOS, by providing the drift region 47 having a relatively low N-type impurity concentration, when a reverse bias is applied between the drain and the source, the drift region 47 is depleted, thereby relaxing the electric field, Maintain pressure resistance. Further, a desired breakdown voltage can be realized by adjusting the N-type impurity concentration and the lateral length of the drift region 47 in accordance with the breakdown voltage required for the element.

  In this embodiment, the CMOS 40 and the LDMOS 10 are formed on the same substrate 11 and made into one chip. For example, the CMOS 40 functions as a driver circuit that drives the gate of the LDMOS 10. In manufacturing a mixed chip of the CMOS 40 and the LDMOS 10, in order to reduce the cost by reducing the number of processes, the LDMOS is also formed using the process used in the CMOS manufacturing.

  In this case, the LDMOS well region is formed by the same ion implantation process as that of the CMOS well region. When the impurity concentration of the CMOS well region is high, the element breakdown voltage of the LDMOS is determined by the breakdown voltage of the junction between the drain region of the LDMOS and the high impurity concentration well region. In other words, the breakdown voltage of the LDMOS is determined by the breakdown voltage set in the CMOS. That is, it is not appropriate for the LDMOS that often requires a breakdown voltage higher than that of the CMOS to be a high impurity concentration well region under the drain region similar to the CMOS. In general, an LDMOS determines an element withstand voltage depending on a dose amount and a length of a drift region, whereas a structure in which an withstand voltage is determined immediately below a drain region cannot freely design an element withstand voltage.

  In contrast, in the present embodiment, the high concentration P-type well region 41 and the low concentration P-type well region 42 having relatively different impurity concentrations are formed in the LDMOS formation region, and the drain region 48 of the LDMOS 10 is formed in the low concentration P-type well. It is formed on the region 42. As a result, it is possible to suppress a decrease in breakdown voltage at the junction between the drain region 48 and the underlying low concentration P-type well region 42. That is, the breakdown voltage of the LDMOS 10 is not determined by the breakdown voltage of the CMOS 40, and a desired breakdown voltage higher than that of the CMOS 40 can be realized by adjusting the N-type impurity concentration and the lateral length of the drift region 47.

  In addition, by forming a high-concentration P-type well region 41 having a relatively high impurity concentration below the source region 44 side in the LDMOS 10, punch-through during reverse bias application can be suppressed.

  In the example shown in FIGS. 1 and 2, the impurity concentration inflection point (indicated by a dotted line) between the high concentration P-type well region 41 and the low concentration P-type well region 42 is located below the gate electrode 53. For example, it may be located under the drift region 47. In short, the high-concentration high-concentration P-type well region 41 designed for CMOS need not be in contact with the drain region 48.

  Next, a method for manufacturing the LDMOS 10 will be described with reference to FIGS.

  First, a high-concentration P-type well region 41 and a low-concentration P-type well region 42 are formed simultaneously by introducing a P-type impurity into the substrate 11 by ion implantation. Specifically, as shown in FIG. 3A, ion implantation is performed using a mask 60.

  A plan view of the mask 60 is shown in FIG. The mask 60 includes a first opening formation region 60a and a second opening formation region 60b having a lower opening ratio per unit area than the first opening formation region 60a. For example, a stripe-shaped shielding part 61 is formed in the second opening formation region 60 b, and the other part in the second opening formation region 60 b is an opening 62. The shielding portion pattern is not limited to a stripe shape, and may be a lattice shape as shown in FIG. 6B, or may be a plurality of island shapes as shown in FIG.

  The dose of ion implantation is substantially uniform in the surface direction. By performing the ion implantation using the mask 60, the amount of ion implantation into the lower portion of the second opening formation region 60b is relatively small, and a wide opening is formed next to the second opening formation region 60b. In addition, the amount of ion implantation into the lower portion of the first opening formation region 60a is relatively increased. That is, as shown in FIG. 3B, a high concentration P-type well region 41 having a relatively high impurity concentration and a low concentration P-type well region 42 having a relatively low impurity concentration are formed in one ion implantation step. Formed simultaneously.

  The position of the impurity concentration inflection point (represented by the dotted line in FIG. 3B) where the P-type impurity concentration greatly changes between the high-concentration P-type well region 41 and the low-concentration P-type well region 42 is shown in FIG. In the mask 60 shown in (a), the vicinity of the boundary between the second opening formation region 60b and the first opening formation region 60a.

  The ion implantation is performed a plurality of times (in a plurality of stages) at different acceleration voltages and at different depths, and the implanted impurities are activated and diffused in the substrate 11 by performing heat treatment after the ion implantation. Therefore, each of the high concentration P-type well region 41 and the low concentration P-type well region 42 has a plurality of impurity concentration peaks in the film thickness direction. Since the high-concentration P-type well region 41 and the low-concentration P-type well region 42 are formed by the same ion implantation process, the acceleration energy is also the same, and the high-concentration P-type well region 41 and the low-concentration P-type well region 42 , Have impurity concentration peaks at substantially the same depth.

  At the same time as the ion implantation for forming the high-concentration P-type well region 41 and the low-concentration P-type well region 42, the P-type well region 12 of the N-channel MOS 20 in the CMOS 40 shown in FIG. 1 is also formed. The P-type well region 12 is not covered with a shielding portion, like the high-concentration P-type well region 41 of the LDMOS 10, and therefore, the high-concentration P-type well region 41 of the LDMOS 10 and the P-type well region 12 of the N-channel type MOS 20 are different from each other. The impurity concentration is relatively high and almost the same.

  Further, at the time of the ion implantation of the P-type impurity, the portion of the substrate 11 where the P-channel MOS 30 is formed is covered with a mask and the P-type impurity is not implanted. The N-type well region 13 of the P-channel MOS 30 is covered with a mask before or after the implantation of the P-type impurity, except for the portion of the substrate 11 where the N-type well region 13 is to be formed. It is formed by injection.

  As described above, according to the present embodiment, the low impurity concentration well region for LDMOS is formed simultaneously by ion implantation using the mask 60 without changing the CMOS well region concentration condition applied by the fine rule. it can. That is, two well regions having relatively different effective impurity concentrations can be formed for LDMOS in accordance with the step of forming the CMOS well region. As a result, a CMOS process can be applied to manufacture a mixed chip of CMOS and LDMOS having a higher withstand voltage than this, and costs can be reduced without additional steps for LDMOS. Moreover, the LDMOS can be designed with a desired high breakdown voltage that does not depend on the set breakdown voltage of the CMOS.

  After the high-concentration P-type well region 41 and the low-concentration P-type well region 42 are formed, next, as shown in FIG. A P-type region 46 is formed by selective ion implantation and subsequent heat treatment. The P-type impurity concentration in the P-type region 46 is set so as to obtain a desired gate threshold value. At the same time as the formation of the P-type region 46, the P-type LDD regions 25 and 27 of the P-channel MOS 30 in the CMOS 40 are also formed.

  Next, as shown in FIG. 4A, an insulating film 5 is formed on the surface of the semiconductor layer 50, a gate electrode material is formed on the insulating film 5, and then the gate electrode material remains at a desired position. Thus, the gate electrode 53 is formed by processing into a desired shape. At the same time, the insulating film 5 and the gate electrodes 18 and 28 in the CMOS 40 are also formed.

  Next, as shown in FIG. 4B, a part of the drain side of the gate electrode 53 on the low concentration P-type well region 42 is covered with a mask 71, and in this state, an N-type impurity is added to the P-type region 46. Implantation is performed by an ion implantation method to form an N-type region 45 to be an LDD region. The boundary (PN junction) between the N-type region 45 and the P-type region 46 is located in the vicinity of the end of the gate electrode 53 on the source side. At the same time, LDD regions 15 and 17 of the N-channel MOS 20 in the CMOS 40 are also formed.

Next, as shown in FIG. 4C, a portion where the N-type region 45 is formed and a portion on the source side of the gate electrode 53 are covered with a mask 72, and in this state, the low-concentration P-type well region 42 is covered. In the surface layer portion, N-type impurities 47 are implanted by an ion implantation method to form an N ⁻ -type region 47 serving as a drift region.

  Next, as shown in FIG. 5A, sidewall insulating films 19 are formed on both side walls of the gate electrode 53 in the gate length direction. At the same time, the sidewall insulating film 19 is also formed on the side walls of the gate electrodes 18 and 28 in the CMOS 40.

Next, as shown in FIG. 5 (b), a portion of the N-type region 45, N in the gate electrode 53 ^- Some -type region 47 side, N ^- -type region 47 of the side wall insulating film 19, and N ^- covering a part of the type region 47 in the mask 73. Then, an N-type impurity is implanted into the N-type region 45 and the N ⁻ -type region 47 that are not covered with the mask 73 by ion implantation to form the source region 44 and the drain region 48 as shown in FIG. To do. At the same time, the source region 14 and the drain region 16 of the N-channel MOS 20 in the CMOS 40 are also formed.

  Thereafter, a necessary portion is covered with a mask (not shown), and then selective ion implantation of a P-type impurity is performed in the source region 44 to form a contact region 43. At the same time, the source region 24 and the drain region 26 of the P-channel MOS 30 in the CMOS 40 are also formed.

  Thereafter, for the LDMOS 10 and the CMOS 40, the source electrodes 51, 21, 31 and the drain electrodes 52, 22, 32 are simultaneously formed to obtain the structure shown in FIG.

[Second Embodiment]
FIG. 7 is a schematic diagram showing a second embodiment of the LDMOS 10. In addition, the same code | symbol is attached | subjected about the same element as the said 1st Embodiment, and the detailed description is abbreviate | omitted.

  In the present embodiment, an N-type layer 80 is provided on the substrate 11 that supports the semiconductor layer 50, and a semiconductor having a high-concentration P-type well region 41 and a low-concentration P-type well region 42 on the N-type layer 80. A layer 50 is provided.

The N-type layer 80 is connected to an arbitrary electrode via an N ⁺ layer (not shown) having a relatively high impurity concentration at the element end. Thus, the element portion above the N-type layer 80 is surrounded by the N-type layer 80 to which an arbitrary potential is applied, and is separated from the substrate 11 side potential.

  8 and 9 show a method for manufacturing the LDMOS of this embodiment.

  First, as shown in FIG. 8A, an N-type impurity is introduced into the substrate 11 by ion implantation, and then heat treatment is performed to form an N-type layer 80 as shown in FIG. 8B. A mask is not used for this ion implantation, and impurities are introduced with a uniform dose in the direction of the surface of the substrate 11.

  Next, a high-concentration P-type well region 41 and a low-concentration P-type well region 42 are formed simultaneously by introducing a P-type impurity into the N-type layer 80 by ion implantation. Specifically, as shown in FIG. 9A, ion implantation is performed using a mask 60 as in the first embodiment.

  By performing ion implantation into the substrate 11 using the mask 60, the high concentration P-type well region 41 having a relatively high impurity concentration and the low concentration P-type well region 42 having a relatively low impurity concentration are formed at a time. They are formed simultaneously in the ion implantation process. At the same time, the P-type well region 12 of the N-channel MOS 20 in the CMOS 40 shown in FIG. 1 is also formed.

  Thereafter, the same steps as those in FIG. 3C and subsequent steps are continued, and the structure shown in FIG. 7 is obtained.

  Further, instead of the methods shown in FIGS. 8 and 9, the methods shown in FIGS. 10 and 11 may be used.

  In this method, first, an N-type impurity is introduced into the substrate 11 by ion implantation to form an N-type layer 80 having a low-concentration N-type region 81 and a high-concentration N-type region 82. Specifically, as shown in FIG. 10A, ion implantation is performed using the mask 60 described above.

  By performing ion implantation into the substrate 11 using the mask 60, a low concentration N-type region 81 having a relatively low impurity concentration and a high concentration N-type region 82 having a relatively high impurity concentration are implanted once. Simultaneously formed in the process.

  Next, as shown in FIG. 11A, a P-type impurity is introduced into the N-type layer 80 with a uniform dose in the surface direction without using a mask by an ion implantation method. When heat treatment is performed thereafter, a high concentration P type well region 41 is formed on the low concentration N type region 81 and a low concentration P type well region 42 is formed on the high concentration N type region 82 as shown in FIG. Is done.

  That is, the dose in the surface direction of the P-type impurity implanted into the N-type layer 80 is uniform, but the portion where the P-type impurity is introduced in the low-concentration N-type region 81 has a relatively high P-type impurity concentration. Thus, the P-type impurity concentration in the portion where the P-type impurity is introduced in the high-concentration N-type region 82 is relatively low.

  Also in the second embodiment described above, a low impurity concentration well region for LDMOS can be formed simultaneously without changing the CMOS well region concentration condition applied by the fine rule. That is, two well regions having relatively different effective impurity concentrations can be formed for LDMOS in accordance with the step of forming the CMOS well region. As a result, a CMOS process can be applied to manufacture a mixed chip of CMOS and LDMOS having a higher withstand voltage than this, and costs can be reduced without additional steps for LDMOS. Moreover, the LDMOS can be designed with a desired high breakdown voltage that does not depend on the set breakdown voltage of the CMOS.

[Third Embodiment]
Next, FIG. 12 shows a schematic cross-sectional view of an LDMOS according to a third embodiment of the present invention.

  In the present embodiment, the low concentration P-type well region 42 further includes two regions (a first region 42a and a second region 42b).

  The first region 42 a is provided on the high concentration P-type well region 41 side, and is in contact with the portion 47 a on the gate electrode 53 side in the drift region 47. The second region 42 b is provided on the opposite side of the high-concentration P-type well region 41 with the first region 42 a interposed therebetween, and is in contact with the drain region 48 side portion 47 b and the drain region 48 in the drift region 47. The second region 42b has a lower P-type impurity concentration than the first region 42a.

  N-type impurity ions are implanted into the surfaces of the first region 42a and the second region 42b, followed by heat treatment, whereby the drift region 47 is formed. The dose amount of the N-type impurity ions is substantially uniform in the plane direction of the first region 42a and the second region 42b, but the P-type impurity concentration in the first region 42a is higher than that in the second region 42b. Since the height is high, two portions 47 a and 47 b having relatively different effective concentrations of the N-type impurity regions are formed in the drift region 47.

  The portion 47a in contact with the first region 42a on the first region 42a has a relatively lower N-type impurity concentration than the portion 47b in contact with the second region 42b on the second region 42b.

  By relatively reducing the impurity concentration of the portion 47a on the gate electrode 53 side in the drift region 47, the portion 47a is completely depleted when the gate electrode 53 is off (when a voltage higher than the threshold is not applied to the gate electrode 53). High off breakdown voltage can be obtained.

  By relatively increasing the impurity concentration of the portion 47b on the drain region 48 side in the drift region 47, depletion of the portion 47b is suppressed and high when a full bias higher than the threshold is applied to the gate electrode 53. ON breakdown voltage can be obtained. The semiconductor device according to this embodiment is suitable, for example, for a system power supply that requires a high on-voltage.

  FIGS. 13A and 13B are schematic views showing a method of forming the high concentration P-type well region 41 and the low concentration P-type well region 42 in the present embodiment.

  As shown in FIG. 13A, a high-concentration P-type well region 41 and a low-concentration P-type well region 42 are formed by ion implantation of P-type impurities into the substrate 11 using a mask 90. The

  The mask 90 has a first opening formation region and a second opening formation region. The first opening formation region is opened over substantially the entire surface, and the high-concentration P-type well region 41 is formed thereunder.

  Similar to the mask described above with reference to FIGS. 6A to 6C, the second opening formation region is formed with, for example, a stripe-shaped, lattice-shaped, or island-shaped shielding portion. The aperture ratio per unit area is lower than that. Further, the second opening formation region has a first region 91 and a second region 92. The first region 91 is adjacent to the first opening formation region. The second region 92 is located on the opposite side of the first opening formation region across the first region 91, and has a lower aperture ratio per unit area than the first region 91.

  For this reason, the first region 42a having a relatively high P-type impurity concentration is formed under the first region 91 of the mask 90 having a relatively high aperture ratio, and the mask 90 having a relatively low aperture ratio. A second region 42b having a relatively low P-type impurity concentration is formed under the second region 92 (FIG. 13B).

  That is, in the present embodiment, the high concentration P-type well region 41, the first region 42a having a lower P-type impurity concentration, and the second region 42b having a lower P-type impurity concentration than this, They can be formed simultaneously in the same ion implantation step.

  Then, by uniformly injecting N-type impurities into the surfaces of the first region 42a and the second region 42b, a drift region 47 having portions 47a and 47b having relatively different N-type effective impurity concentrations is obtained. It is done.

  In simultaneously forming the first region 42a and the second region 42b having relatively different P-type impurity concentrations, masks 93 and 94 having relatively different film thicknesses are used as shown in FIG. May be. The mask 94 is thicker than the mask 93. The acceleration voltage is controlled so that the P-type impurity ions pass through the masks 93 and 94 and enter the substrate 11.

  Then, ions implanted into the substrate 11 through the mask 94 having a relatively large film thickness are relative to ions implanted into the substrate 11 through the mask 93 having a relatively small film thickness. The injection amount is reduced. As a result, a first region 42 a having a relatively high P-type impurity concentration is formed under the mask 93, and a second region 42 b having a relatively low P-type impurity concentration is formed under the mask 94.

  Further, as shown in FIG. 14B, a mask 95 whose film thickness gradually increases from the first region to the second region may be used. In the mask 95, a region having a relatively high P-type impurity concentration is formed under a portion having a relatively thin film thickness, and a region having a relatively low P-type impurity concentration is formed under a portion having a relatively thick film thickness. A region is formed. When this mask 95 is used, it is possible to form a structure in which the P-type impurity concentration gradually decreases from the end of the first region 42a to the end of the second region 42b.

  As shown in FIG. 15, the low concentration P-type well region 42 may be divided into three regions (a first region 42a, a second region 42b, and a third region 42c).

  The first region 42 a is provided on the high concentration P-type well region 41 side, and is in contact with the portion 47 a on the gate electrode 53 side in the drift region 47. The second region 42b is provided on the opposite side of the high concentration P-type well region 41 with the first region 42a interposed therebetween, and is in contact with the portion 47b of the drift region 47 on the drain region 48 side. The third region 42 c is provided below the drain region 48 and is in contact with the drain region 48.

  When the P-type impurity concentration of the first region 42a is Qd1, the P-type impurity concentration of the second region 42b is Qd2, and the P-type impurity concentration of the third region 42c is Qd3, Qd1> Qd2> Qd3 holds.

  N-type impurity ions are implanted into the surfaces of the first region 42a and the second region 42b, followed by heat treatment, whereby the drift region 47 is formed. The dose amount of the N-type impurity ions is substantially uniform in the plane direction of the first region 42a and the second region 42b, but the P-type impurity concentration in the first region 42a is higher than that in the second region 42b. Since the height is high, two portions 47 a and 47 b having relatively different effective concentrations of impurities are formed in the drift region 47.

  That is, the portion 47a in contact with the first region 42a on the first region 42a has a relatively lower N-type impurity concentration than the portion 47b in contact with the second region 42b on the second region 42b.

  By relatively reducing the impurity concentration of the portion 47a on the gate electrode 53 side in the drift region 47, the portion 47a is completely depleted when the gate electrode 53 is off (when a voltage higher than the threshold is not applied to the gate electrode 53). High off breakdown voltage can be obtained.

  By relatively increasing the impurity concentration of the portion 47b on the drain region 48 side in the drift region 47, depletion of the portion 47b is suppressed and high when a full bias higher than the threshold is applied to the gate electrode 53. ON breakdown voltage can be obtained.

  In the present embodiment, the breakdown voltage of the junction between the drain region 48 and the third region 42c is lowered by setting the third region 42c below the drain region 48 to a lower impurity concentration than the second region 42b. Can be further suppressed.

  This embodiment is also applicable to the structure of the second embodiment shown in FIG. The structure is shown in FIG.

  If the impurity concentration in the portion between the drain region 48 and the N-type layer 80 having a relatively high impurity concentration is high, there is a concern that the drain region 48 and the N-type layer 80 may punch through and lower the breakdown voltage.

  In the structure shown in FIG. 16, by providing the third region 42 c having a lower impurity concentration between the drain region 48 and the N-type layer 80, the punch-through can be suppressed and high breakdown voltage can be obtained. Can do.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to them, and various modifications can be made based on the technical idea of the present invention.

  For example, silicon can be used as the semiconductor material, but not limited to this, other semiconductor materials may be used. Further, not only a single element semiconductor but also a compound semiconductor may be used.

  DESCRIPTION OF SYMBOLS 10 ... LDMOS, 11 ... Substrate, 12 ... P type well region, 13 ... N type well region, 20 ... N channel type MOS, 30 ... P channel type MOS, 40 ... CMOS, 41 ... High concentration P type well region, 42 ... Low-concentration P-type well region, 44 ... Source region, 47 ... Drift region, 48 ... Drain region, 51 ... Source electrode, 52 ... Drain electrode, 53 ... Gate electrode

Claims (6)

The semiconductor layer is selectively ion-implanted using a mask, the first semiconductor region of the first conductivity type is formed in the semiconductor layer, and the first conductivity type impurity concentration is lower than that of the first semiconductor region. Simultaneously forming a second semiconductor region of one conductivity type;
Forming a gate electrode on the semiconductor layer via an insulating film;
Forming a second conductivity type source region on the first semiconductor region;
Forming a second conductivity type drain region on the second semiconductor region at a position sandwiching the gate electrode with the source region;
Forming a drift region of a second conductivity type in contact with the drain region and having a lower impurity concentration than the drain region in a surface layer portion between the gate electrode and the drain region in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein a dose amount of the ion implantation is substantially uniform in a surface direction of the semiconductor layer. The mask has a first opening forming region and a second opening forming region having a lower opening ratio per unit area than the first opening forming region,
The first semiconductor region is formed in the semiconductor layer under the first opening formation region, and the second semiconductor region is formed in the semiconductor layer under the second opening formation region. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. The second opening forming region is
A first region adjacent to the first opening forming region;
A second region located on the opposite side of the first opening formation region across the first region and having a lower aperture ratio per unit area than the first region;
The method of manufacturing a semiconductor device according to claim 3, further comprising: The second opening forming region is
A first region adjacent to the first opening forming region;
A second region located on the opposite side of the first opening formation region across the first region and having a thickness greater than that of the first region;
The method of manufacturing a semiconductor device according to claim 3, further comprising: The semiconductor layer is selectively ion-implanted using a mask, and a second conductivity type first semiconductor region and a second conductivity type impurity concentration higher than that of the first semiconductor region are formed in the semiconductor layer. Simultaneously forming a second conductivity type second semiconductor region;
Ion implantation is performed uniformly over the entire surface of the first semiconductor region and the second semiconductor region, a first conductive type third semiconductor region is formed on the first semiconductor region, and the third semiconductor region is formed. Simultaneously forming a first conductivity type fourth semiconductor region having a first conductivity type impurity concentration lower than that of the semiconductor region on the second semiconductor region;
Forming a gate electrode on the semiconductor layer via an insulating film;
Forming a second conductivity type source region on the third semiconductor region;
Forming a second conductivity type drain region on the fourth semiconductor region at a position sandwiching the gate electrode with the source region;
Forming a drift region of a second conductivity type in contact with the drain region and having a lower impurity concentration than the drain region in a surface layer portion between the gate electrode and the drain region in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising:

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