JP2011009382A - Semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element, wherein the external light emission efficiency is improved.SOLUTION: The semiconductor light emitting element includes a substrate 10, processed layers 18 which are arranged on the substrate 10 and subjected to nanosize processing, an n-type semiconductor layer 12 which is arranged on the substrate 10 while being held between the processed layers 18 and on the processed layers 18 and is doped with n-type impurities, an active layer 13 arranged on the n-type semiconductor layer 12, and a p-type semiconductor layer 14 which is arranged on the active layer 13 and doped with p-type impurities.

Description

  The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor light emitting device with improved external light emission efficiency.

A semiconductor light emitting element made of a group III nitride semiconductor is used for a light emitting diode (LED) or the like. Examples of group III nitride semiconductors include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). A typical group III nitride semiconductor is represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

  A semiconductor light emitting device using a group III nitride semiconductor includes, for example, an n-type group III nitride semiconductor layer (n-type semiconductor layer), an active layer (light-emitting layer), and a p-type group III nitride on a substrate. It has a structure in which a series semiconductor layer (p-type semiconductor layer) is laminated in this order. Then, the light generated by the recombination of the holes supplied from the p-type semiconductor layer and the electrons supplied from the n-type semiconductor layer in the active layer is output to the outside.

  As the active layer, a multi-quantum well (MQW) structure in which a plurality of well layers (well layers) are sandwiched between barrier layers (barrier layers) having a larger band gap than the well layers can be employed. .

In the metal organic vapor phase epitaxy (MOVPE) method, the dislocation density of GaN obtained using an AlN or GaN low-temperature buffer layer on a sapphire substrate is about 10 ⁸ to 10 ¹⁰ cm ^−2. . In producing a device such as a semiconductor laser, about 10 ⁶ cm ⁻² or less is required. The dislocations in question are threading dislocations that are inherited with crystal growth from the interface region with the sapphire substrate.

At present, a technique established as an effective method capable of reducing the dislocation density to about 10 ⁶ to 10 ⁷ cm ⁻² is an ELO (Epitaxial Lateral Overgrowth) technique utilizing the characteristics of selective lateral growth.

  Some ELO technologies applied to GaN are based on the HVPE (Hydride Vapor Phase Epitaxy) method and the MOVPE method. The HVPE method is characterized in that the growth rate can be increased to several tens to several hundreds μm / h.

A method based on the HVPE method is called FIELO (Facet-Initiated Epitaxial Lateral Overgrowth). In FIELO, for example, a SiO ₂ striped mask pattern formed by lithography on GaN having a thickness of 1 to 1.5 μm grown on the sapphire (0001) plane (c-plane) by the MOVPE method is used as a base. Used. That is, in the conventional semiconductor light emitting device, an n-type GaN layer is first epitaxially grown on the sapphire substrate by about several μm, and then a SiO ₂ film or SiN _x film is partially formed on the n-type GaN layer. The n-type GaN layer other than the SiO ₂ or SiN _x film is used as a seed crystal for selective lateral epitaxial growth, and the n-type semiconductor layer is formed by selective lateral epitaxial growth.

However, an n-type GaN layer having a refractive index significantly different from the refractive index value of the sapphire substrate is disposed below the SiO ₂ film or SiN _x film having a refractive index close to that of the sapphire substrate. Then, light is reflected at the interface between the sapphire substrate and the n-type GaN layer, so that the light from the semiconductor light emitting device cannot be effectively extracted outside, and the external light emission efficiency is lowered.

  In the conventional structure, when a nitride semiconductor is manufactured by metal organic chemical vapor deposition (MOCVD), for example, a sapphire substrate is used as a growth substrate, and an organic metal compound gas is used as a reaction gas. The GaN epitaxial growth layer was formed on the sapphire substrate at a crystal growth temperature of about 900 ° C. to 1100 ° C. The surface morphology of the GaN semiconductor layer grown directly on the sapphire substrate using the MOCVD method is extremely poor. Therefore, a method of forming an AlN buffer layer on the sapphire substrate before the GaN semiconductor layer is grown is used. However, in the above method, the growth conditions of the buffer layer are strictly limited, and the film thickness must be strictly controlled within a very thin range of 100 to 500 angstroms. In addition, when the GaN layer is grown on the AlN buffer layer, lattice constant mismatch is significant.

Further, when the p-type semiconductor layer is formed in a multilayer structure, it is necessary to grow at a low temperature in order to reduce the thermal damage to the active layer, and at the same time, the forward voltage (V _f ) is lowered and the luminous efficiency is improved. There is a need. Further, when a GaN layer is applied as the p-type semiconductor layer, there is a problem in terms of transparency with respect to the emission wavelength.

  In the conventional structure, 4 to 5 pairs of MQWs are used. In this case, electrons supplied from the n-type semiconductor layer jump over the active layer and flow to the p-type semiconductor layer. At this time, holes supplied from the p-type semiconductor layer recombine with electrons before reaching the active layer, and the hole concentration reaching the active layer is reduced. Thereby, the brightness | luminance of LED will reduce. In order to prevent this, a structure in which a p-type AlGaN layer having a large band gap is inserted in front of the p-type semiconductor layer is used. However, when aluminum (Al) is introduced, it becomes difficult to form p-type, and the resistance value increases. On the other hand, when an InGaN layer is applied to the well layer of the active layer, there is a problem that it is vulnerable to thermal damage associated with a high temperature process in forming the p-type semiconductor layer.

  On the other hand, it is possible to produce a concavo-convex pattern of a dielectric pattern on a sapphire substrate (see, for example, Patent Document 1).

  Moreover, it is possible to produce the uneven | corrugated pattern to a substrate growth surface with resin, a resist, etc. using nanoimprint technology (for example, refer patent documents 2-4).

  A schematic cross-sectional structure for explaining one step of the sapphire substrate processing step of the semiconductor light emitting device according to the conventional example is expressed as shown in FIGS. 31 (a) and 31 (b).

  FIG. 31A shows a schematic cross-sectional structure in which a pattern of the resist layer 6a is formed on the sapphire substrate 10a. In the structure of FIG. 31A, if the surface of the sapphire substrate 10a is to be processed by dry etching such as reactive ion etching (RIE), a resist layer as shown in FIG. The resistance of 6a is not achieved, and the slightly shallow groove 4a is only formed on the surface of the sapphire substrate 10a, and the sapphire substrate 10a cannot be sufficiently processed.

  As described above, when the substrate is a material that is difficult to process, such as sapphire, there is a problem in that the resist layer does not have resistance, and the processing for producing a sufficiently high uneven structure on the substrate cannot be performed.

JP 2009-54898 A JP 2005-136106 A JP 2008-153634 A

  Instead of processing the substrate itself, the present inventors previously formed a layer of a material that can be easily processed on the substrate surface, and by processing this layer, the substrate surface has a sufficiently high unevenness. We found the technology to form the structure.

  An object of the present invention is to provide a semiconductor light emitting device having an improved external light emission efficiency by producing a sufficiently uneven structure on a substrate growth surface using a nanoimprint technique.

  According to an aspect of the present invention for achieving the above object, a substrate, a first processed layer disposed on the substrate and nano-sized, the substrate sandwiched between the first processed layers, and the An n-type semiconductor layer disposed on the first processed layer and doped with an n-type impurity, an active layer disposed on the n-type semiconductor layer, and disposed on the active layer and doped with a p-type impurity And a p-type semiconductor layer.

  According to the present invention, it is possible to provide a semiconductor light emitting device with an improved external light emission efficiency by producing a sufficiently high uneven structure on the substrate growth surface using nanoimprint technology.

1A is a schematic cross-sectional structure diagram of a semiconductor light emitting element according to a first embodiment of the present invention, and FIG. 1B is a schematic plan pattern configuration diagram corresponding to FIG. 2A is a schematic cross-sectional structure diagram showing a structure in which the semiconductor light emitting device according to the first embodiment of the present invention is mounted on a package, FIG. 2B is an enlarged view of a portion A in FIG. (A) Schematic cross-sectional structure diagram for explaining one step of a substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention (Part 1), (b) In the first embodiment of the present invention FIG. 2 is a schematic cross-sectional structure diagram for explaining one step of a semiconductor light emitting device substrate processing step, (c) explaining one step of a semiconductor light emitting device substrate processing step according to the first embodiment of the present invention; Schematic cross-sectional structure diagram (Part 3), (d) Schematic cross-sectional structure diagram (Part 4) explaining one step of the substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention. (A) Schematic cross-sectional structure diagram for explaining one step of a substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention (No. 5), (b) In the first embodiment of the present invention FIG. 6 is a schematic cross-sectional structure diagram for explaining one step of a substrate processing process of the semiconductor light emitting device (No. 6), and FIG. 8C explains one step of the substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention. Schematic cross-sectional structure diagram (Part 7), (d) Schematic of the substrate formed using one step of the substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention and the processed processing layer Sectional structural drawing (Structural Example 1). (A) Schematic cross-sectional structure diagram (Structure Example 2) of a substrate and a processed layer formed using the substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention, (b) the first of the present invention 1 is a schematic cross-sectional structure diagram (Structural Example 3) of a substrate and a processed layer formed by using the substrate processing step of the semiconductor light emitting element according to the first embodiment, and (c) according to the first embodiment of the present invention. The typical cross-section figure of the board | substrate and process layer which were formed using the board | substrate processing process of a semiconductor light-emitting device (structure example 4). (A) Schematic plane pattern configuration diagram (Configuration Example 1) of a processing layer on a substrate formed by using the substrate processing step of the semiconductor light emitting device according to the first embodiment of the present invention, (b) the present invention. FIG. 2 is a schematic plan pattern configuration diagram (configuration example 2) of a processing layer on a substrate formed by using the substrate processing step of the semiconductor light emitting device according to the first embodiment, (c) the first embodiment of the present invention. Schematic plane pattern configuration diagram (configuration example 3) of a processing layer on a substrate formed using the substrate processing step of the semiconductor light emitting element according to the embodiment, (d) the semiconductor according to the first embodiment of the present invention The typical plane pattern block diagram (structure example 4) of the process layer on the board | substrate formed using the board | substrate processing process of a light emitting element. (A) In the semiconductor light emitting element which concerns on the 1st Embodiment of this invention, the typical cross-section figure explaining the process of forming the process layers 18-1 to 18-n in a multilayer structure on a board | substrate, (b). The typical cross-section figure of the board | substrate formed using the board | substrate processing process of the semiconductor light-emitting device concerning the 1st Embodiment of this invention, and the processed processed layer. The schematic diagram explaining the refractive index distribution in the process layer of FIG. In the case of forming a silicon oxynitride (SiON) film as a working layer, it shows the relationship between the refractive index n and N ₂ O flow rate (sccm). In the case of forming a silicon nitride (SiN) film as a working layer, it shows the relationship between the flow rate of NH ₃ and (sccm) and the refractive index n. The figure which shows the dimension of each part of the processing layer 18 used for simulation in the semiconductor light-emitting device concerning the 1st Embodiment of this invention. The figure showing the relationship between the transmittance | permeability T (%) and pitch ratio b / a in the semiconductor light-emitting device concerning the 1st Embodiment of this invention. The figure showing the relationship between the transmittance | permeability T (%) and a (nm) in the semiconductor light-emitting device concerning the 1st Embodiment of this invention. The figure showing the relationship between the transmittance | permeability T (%) which uses a as a parameter, and h (nm) in the semiconductor light-emitting device concerning the 1st Embodiment of this invention. FIG. 2 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention (No. 1). Typical cross-section FIG. (2) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. Typical cross-section FIG. (3) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. Typical cross-section FIG. (4) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. Typical cross-section FIG. (5) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. Typical cross-section FIG. (6) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. Typical cross-section FIG. (7) explaining 1 process of the manufacturing method of the semiconductor light-emitting device concerning the 1st Embodiment of this invention. 1 is a detailed schematic cross-sectional structure example 1 of a semiconductor light-emitting element according to a first embodiment of the present invention, and is an enlarged schematic cross-sectional structure diagram of a semiconductor light-emitting element part and an active layer part. FIG. 3 is an enlarged schematic cross-sectional structure diagram of a semiconductor light-emitting element portion and an active layer portion in a detailed schematic cross-sectional structure example 2 of the semiconductor light-emitting element according to the first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram for demonstrating the crystal plane of the group III nitride semiconductor applied to the semiconductor light-emitting device concerning the 1st Embodiment of this invention, Comprising: (a) Crystal structure c of a group III nitride semiconductor Schematic diagram showing plane, a-plane, m-plane, (b) schematic diagram for explaining semipolar plane {10-11}, (c) schematic diagram for explaining semipolar plane {10-13}, (D) The schematic diagram which shows the coupling | bonding of a group III atom and a nitrogen atom. FIG. 23 is a schematic cross-sectional structure diagram formed up to a p-side electrode and an n-side electrode in the semiconductor light emitting device according to the first embodiment of the present invention shown in FIG. 22. 4 is a detailed schematic cross-sectional structure example 3 of the semiconductor light-emitting element according to the first embodiment of the present invention, and is an enlarged schematic cross-sectional structure diagram of a semiconductor light-emitting element part and an active layer part. FIG. FIG. 27 is a schematic cross-sectional structure diagram formed up to a p-side electrode and an n-side electrode of the semiconductor light emitting device according to the first embodiment of the present invention shown in FIG. 26. 1 is a schematic cross-sectional structure diagram showing a structure in which a semiconductor light emitting element according to a first embodiment of the present invention is mounted on a flip chip package. The typical cross-section figure which shows the structure where the semiconductor light-emitting device which concerns on the modification 1 of the 1st Embodiment of this invention was mounted in the package. The typical cross-section figure which shows the structure where the semiconductor light emitting element which concerns on the modification 2 of the 1st Embodiment of this invention was mounted in the package. (A) Typical cross-sectional structure diagram for explaining one step of a sapphire substrate processing step of a semiconductor light emitting device according to a conventional example (Part 1), (b) One step of a sapphire substrate processing step of a semiconductor light emitting device according to a conventional example. FIG. 2 is a schematic cross-sectional structure diagram (part 2) to explain.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

  In the semiconductor light emitting device according to the following embodiments of the present invention, “transparent” is defined as having a transmittance of about 50% or more. The term “transparent” is used to mean colorless and transparent with respect to visible light in the semiconductor light emitting device according to the embodiment of the present invention. Visible light corresponds to a wavelength of about 360 nm to 830 nm and an energy of about 3.4 eV to 1.5 eV, and is transparent unless absorption, reflection, or scattering occurs in this region.

Transparency is determined by the band gap E _g and the plasma frequency ω _p . When the band gap E _g is about 3.1 eV or more, the transition between electrons in the visible light does not occur, and therefore the visible light is transmitted without being absorbed. On the other hand, light having energy lower than the plasma frequency ω _p cannot enter the plasma and is reflected by carriers that can be regarded as plasma. The plasma frequency ω _p is expressed as ω _p = (nq ² / εm ^* ) ^1/2 where n is the carrier density, q is the charge, ε is the dielectric constant, and m ^* is the effective mass, and is a function of the carrier density. is there.

[First embodiment]
(Element structure)
As shown in FIGS. 1A and 1B, the semiconductor light emitting device according to the first embodiment of the present invention is arranged on a substrate 10 and a nano-sized processed layer disposed on the substrate 10. 18, an n-type semiconductor layer 12 disposed on the substrate 10 and the processed layer 18 sandwiched between the processed layers 18 and doped with an n-type impurity, and an active layer 13 disposed on the n-type semiconductor layer 12. A p-type semiconductor layer 14 disposed on the active layer 13 and doped with a p-type impurity.

  The pattern size of the processed layer 18 is a nanometer scale, and the pattern of the processed layer 18 is formed, for example, by forming a concavo-convex structure having a sufficiently high height on the substrate growth surface using a nanoimprint technique.

  Further, a buffer layer 16 disposed on the substrate 10 sandwiched between the processed layers 18 may be further provided.

  In addition, as shown in FIGS. 1A and 1B, the semiconductor light emitting device according to the first embodiment includes a transparent electrode 15 disposed on the p-type semiconductor layer 14, a transparent electrode 15, An n-side electrode 200 disposed on the surface of the n-type semiconductor layer 12 obtained by removing a part of the p-type semiconductor layer 14, the active layer 13, and the n-type semiconductor layer 12, and a transparent electrode 15. a p-side electrode 100. The details of each part will be described together with the detailed structure shown in FIG.

  A schematic cross-sectional structure in which the semiconductor light-emitting device according to the first embodiment is mounted in a package is expressed as shown in FIG. Moreover, the enlarged schematic cross-sectional structure of A part of Fig.2 (a) is represented as shown in FIG.2 (b).

  As shown in FIG. 2A, the p-side electrode 100 of the semiconductor light emitting device according to the first embodiment has an anode mounted on the bottom of the inner wall of the package 2 by a bonding wire 104 through a bonding contact 102. Similarly, the n-side electrode 200 is connected to the cathode electrode pattern 206 mounted on the bottom of the inner wall of the package 2 through the bonding contact 202 via the bonding contact 202. .

  In addition, the semiconductor light emitting element according to the first embodiment is mounted in the package 2 by, for example, the mold resin 1.

  As shown in FIG. 2A, the light emitted upward from the active layer 13 is partially reflected at the interface between the p-type semiconductor layer 14 and the transparent electrode 15 and propagates downward. Further, the light emitted downward from the active layer 13 is efficiently refracted in the processed layer 18, propagates through the substrate 10, is reflected at the bottom of the inner wall of the package 2, and propagates upward.

  As a result, as shown in FIG. 2A, in the semiconductor light emitting device according to the first embodiment mounted on the package 2, the light emitted upward and downward from the active layer 13 is efficiently obtained. Can be taken out.

(Substrate processing process)
In the process of processing the substrate 10 of the semiconductor light emitting device according to the first embodiment, instead of processing the substrate itself, a layer of a material that can be easily processed is formed on the substrate surface in advance, For example, a concavo-convex structure having a sufficiently high height is formed on the surface of the substrate by processing the nanoimprint technique on the nanometer order.

  The processing steps of the substrate 10 of the semiconductor light emitting device according to the first embodiment will be described below with reference to FIGS. 3 (a) to 3 (d) and FIGS. 4 (a) to (d).

(A) First, as shown in FIG. 3A, for example, a sapphire substrate is prepared as the substrate 10.

(B) Next, as shown in FIG. 3B, a processed layer 18 is formed on the surface of the substrate 10. The processed layer 18 is a layer of a material that can be easily processed. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, an alumina film, or the like can be applied.

(C) Next, as shown in FIG. 3C, a resist layer 6 is formed on the processed layer 18.

(D) Next, as shown in FIG.3 (d), the nanoimprint mold 4 applied to a nanoimprint technique is prepared. As a material of the nanoimprint mold 4, a metal such as copper (Cu), quartz, or the like can be used. The pattern of the nanoimprint mold 4 is formed by an electron beam drawing method and has a nanometer scale. For example, if the emission peak wavelength of the semiconductor light emitting element is λ, the pattern pitch is about λ / 2 and the pattern size is about λ / 4 as shown in FIG.

(E) Next, as shown in FIG. 4A, a nanoimprint technique is applied, and the nanoimprint mold 4 is pressure-bonded to the resist layer 6 to form a recess in the resist layer 6. Here, as the nanoimprint technique, for example, a thermal cycle nanoimprint technique, an optical nanoimprint technique, or the like can be used.

(F) Next, as shown in FIG. 4B, the resist layer 6 is processed using an etching technique such as RIE.

(G) Next, as shown in FIG. 4C, the processed layer 18 is processed using the resist pattern described above and an etching technique such as RIE to expose the sapphire substrate 10.

(H) Next, as shown in FIG. 4D, the resist layer 6 is peeled off to form a pattern of the processed layer 18 on the substrate 10. The pattern of the processed layer 18 also reflects the pattern of the nanoimprint mold 4, and as shown in FIG. 4D, the pattern pitch is about λ / 2 and the pattern size is about λ / 4.

  FIG. 4D corresponds to a schematic cross-sectional structure example 1 of the substrate 10 and the processing layer 18 formed using the substrate processing step of the semiconductor light emitting device according to the first embodiment. This is an example having a rectangular pattern with a pattern pitch λ / 2 and a pattern width λ / 4.

  Other typical cross-sectional structure examples 2 to 4 of the substrate 10 and the processing layer 18 formed using the substrate processing step of the semiconductor light emitting device according to the first embodiment are shown in FIGS. As shown in Fig. 4, a trapezoidal pattern having a pattern pitch λ / 2 and a pattern width λ / 4 on the upper base, a triangular pattern having a pattern pitch λ / 2 and a pattern width λ / 4 on the lower side, and a pattern pitch λ / 2 and a diameter, respectively. A semicircular pattern having a pattern width of λ / 4 may be provided.

  Typical planar pattern configuration examples 1 to 4 of the processing layer on the substrate formed by using the substrate processing step of the semiconductor light emitting device according to the first embodiment are as shown in FIGS. It is expressed in FIG. 6A shows an example in which rectangular processed layers 18 are arranged in a lattice pattern. FIG. 6B shows an example in which rectangular processed layers 18 are arranged in a staggered pattern, and the pattern pitches of adjacent processed layers 18 are all equal to a. FIG. 6C is an example in which circular processed layers 18 are arranged in a staggered pattern, and the pattern pitches of adjacent processed layers 18 are all equal to a. FIG. 6D shows an example in which hexagonal processed layers 18 are arranged in a staggered pattern, and the pattern pitches of adjacent processed layers 18 are all equal to a. Here, in FIGS. 6B to 6D, the value of a is, for example, about λ / 2.

(Formation of processed layer and refractive index distribution)
In the semiconductor light emitting device according to the first embodiment, a schematic cross-sectional structure for explaining the process of forming the processed layers 18-1 to 18-n on the substrate 10 in a multilayer structure is as shown in FIG. A schematic cross-sectional structure of the substrate 10 and the processed processed layer 18 is expressed as shown in FIG. In the processed layers 18-1 to 18-n shown in FIG. 7A, the distribution of the refractive index n is formed so as to gradually increase in the x direction.

  The distribution of the refractive index n in the processed layer 18 of FIG. 7 is formed like a stepped line C, reflecting the multilayer structure of the processed layers 18-1 to 18-n, for example, as shown in FIG. Is done.

  Further, when each layer of the multilayer structure is formed as a fine layer, the refractive index n distribution in the processed layer 18 is easily formed in a curved shape as indicated by a broken line B.

In practice, the distribution of the refractive index n in the processed layer 18 is often formed in a curved line as shown by a broken line B, rather than in a stepped line C. This is because the distribution of the refractive index n can be easily realized as a curved smooth distribution by controlling the gas flow rate ratio. That is, by gradually changing the supply ratio of SiH ₄ , NH ₃ , and N ₂ O gas during film formation, the refractive index n changes smoothly instead of stepwise as shown by the broken line B in FIG. Such a processed layer 18 can also be produced.

In the case of forming a silicon nitride film as the processing layer 18, a film is formed using a plasma chemical vapor deposition (CVD) method using SiH ₄ , NH ₃ , and N ₂ as source gases. . When a silicon oxide film is formed as the processed layer 18, it is formed by using plasma CVD and using SiH ₄ , H ₂ O, and N ₂ as source gases. In the case where a silicon oxynitride film (SiON) is formed as the processing layer 18, plasma CVD is used, SiH ₄ , NH ₃ , N ₂ O, and N ₂ are used as source gases, and these gases are allowed to flow simultaneously. To form a film.

When a silicon oxynitride film (SiON) is formed as the processed layer 18, the relationship between the N ₂ O flow rate (sccm) and the refractive index n is expressed as shown in FIG. By increasing the N ₂ O flow rate and increasing the relative nitrogen content, the refractive index n gradually decreases. For example, by changing the N ₂ O flow rate in the range of 0 to 300 (sccm), the refractive index n in the x direction in the processed layer 18 can be increased from about 1.6 to about 2.1. As described above, an intermediate SiON film between SiN and SiO ₂ can be formed by introducing N ₂ O gas or the like. Thereby, the value of the refractive index n can be freely changed from n = 1.5 which is lower than the refractive index value 1.7 of the sapphire substrate 10 to n = 2.4 which is close to the refractive index value of GaN. Can do.

When a silicon nitride film (SiN) is formed as the processed layer 18, the relationship between the NH ₃ flow rate (sccm) and the refractive index n is expressed as shown in FIG. By fixing the ratio of NH ₃ and N ₂ and increasing the NH ₃ flow rate (sccm) to increase the relative nitrogen content, the refractive index n gradually decreases. For example, by changing the NH ₃ flow rate in the range of 50 to 200 (sccm), the refractive index n in the x direction in the processed layer 18 can be increased from about 1.9 to about 2.3. The composition ratio y of the nitride film SiN _{y has} a width centering on Si ₃ N _4, and a desired refractive index n and SiN _y film can be obtained depending on the value of the composition ratio y. For example, when the SiN film is formed by the CVD method, as shown in FIG. 10, the value of the refractive index n can be freely changed by changing the supply amount of NH _{3 to} SiH ₄ .

(simulation result)
In order to determine the optimum size of the processed layer 18, a simulation was performed. In FIG. 11, the dimension of each part of the process layer 18 used for simulation is shown. As shown in FIG. 11, the height of the processed layer 18 is represented by h (nm), the pattern width is represented by b (nm), and the pattern pitch is represented by a (nm).

  FIG. 12 shows the transmittance T (%) when the emission wavelength λ and the height h of the processed layer 18 are fixed and the pitch ratio b / a is changed. As shown in FIG. 12, at a predetermined pitch ratio b / a, the transmittance T tends to have a peak value.

  Next, FIG. 13 shows the transmittance T (%) when the emission wavelength λ, the height h of the processed layer 18 and the pattern width b are fixed and only the pattern pitch a is changed. As shown in FIG. 13, when the value of the pattern pitch a is changed to λ / 2, λ, and 2λ, the transmittance T (%) is the peak value when the value of the pattern pitch a is between λ and 2λ. The tendency to have

  Next, FIG. 14 shows the transmittance T (%) when the emission wavelength λ, the pattern width b and the pattern pitch a of the processed layer 18 are fixed, and the height h of the processed layer 18 is changed. FIG. 14 shows the results when the pattern pitch a is changed to 1.8λ, 3.2λ, 1.1λ, and λ. In either case, when the value of the height h of the processed layer 18 is between λ and 2λ, the transmittance T (%) tends to have a peak value.

  According to the semiconductor light emitting device according to the first embodiment, the processed layer 18 having the tendency that the refractive index n gradually increases is formed on the substrate 10, and the nanoimprint technique is used for the processed layer 18. Thus, by producing a nanometer-scale concavo-convex structure, it is possible to provide a semiconductor light emitting device with improved light extraction efficiency toward the substrate 10 and improved external light emission efficiency.

(Production method)
In the method for manufacturing a semiconductor light emitting device according to the first embodiment, as shown in FIGS. 15 to 21, a process of preparing a substrate 10 and a nano-sized processed layer 18 are formed on the substrate 10. A step of patterning the processing layer 18 to expose the substrate 10; and the substrate 10 exposed between the processing layer 18 and the n-type semiconductor layer 12 doped with n-type impurities on the processing layer 18 A step of forming by directional epitaxial growth, a step of forming an active layer 13 on the n-type semiconductor layer 12, and a step of forming a p-type semiconductor layer 14 doped with a p-type impurity on the active layer 13.

  The pattern size of the processed layer 18 is a nanometer scale, and the pattern of the processed layer 18 is formed, for example, by forming a concavo-convex structure having a sufficiently high height on the substrate growth surface using a nanoimprint technique.

  Further, after the step of exposing the substrate 10, the method further includes a step of forming the buffer layer 16 on the exposed substrate 10 sandwiched between the processed layers 18.

  Hereinafter, with reference to FIGS. 15 to 21, a method for manufacturing the semiconductor light emitting element according to the first embodiment will be described. The manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including modifications. Here, an example in which a sapphire substrate is applied to the substrate 10 will be described.

(A) First, as shown in FIG. 15, a sapphire substrate 10 is prepared, a processed layer 18 is formed on the sapphire substrate 10, and then nano-sized using a nanoimprint technique to expose the surface of the substrate 10.

  The processed layer 18 may have a pattern shape that does not hinder lateral selective epitaxial growth (ELO), such as a rectangle, a triangle, a diamond, a hexagon, a circle, and a stripe. In particular, in order to perform ELO, the direction of the pattern is selected in consideration of the a-plane and m-plane which are lateral growth planes. When light is extracted from the back surface of the sapphire substrate 10 or the upper surface of the epitaxial growth layer, unevenness is generated at the interface between the processed layer 18 and the epitaxial growth layer, so that the light is scattered or diffracted and totally reflected by the difference in refractive index between the epitaxial growth layer and the heterogeneous substrate interface. The light that has been used is efficiently extracted outside. A processed layer 18 having a refractive index n tends to increase gradually is formed on the sapphire substrate 10, and a nanometer-scale concavo-convex structure is produced on the processed layer 18, particularly using a nanoimprint technique. The light extraction efficiency to the substrate 10 side is improved, and the external light emission efficiency is improved.

(B) Next, as shown in FIG. 16, an AlN buffer layer 16 is grown on the exposed sapphire substrate 10 by MOCVD or the like. For example, by supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier at a high temperature of about 900 ° C. to 950 ° C., the thickness is about 10 to 50 Å. A thin AlN buffer layer 16 is grown in a short time.

(C) Next, as shown in FIG. 17, a GaN layer to be the n-type semiconductor layer 12 is grown on the AlN buffer layer 16 by MOCVD or the like. For example, after the sapphire substrate 10 on which the AlN buffer layer 16 is formed is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 12 doped with n-type impurities is formed on the AlN buffer layer 16. Grow about 1-5 μm. As the n-type semiconductor layer 12, for example, a GaN film doped with Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ can be used. When adding Si as an impurity, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form the n-type semiconductor layer 12. As shown in FIG. 17, threading dislocations 20 are generated in the GaN layer that becomes the n-type semiconductor layer 12.

(D) Next, as shown in FIG. 18, the n-type semiconductor layer 12 is formed by ELO. A lateral selective epitaxial growth layer is formed on the m-plane or the a-plane which is the lateral selective epitaxial growth surface, and the n-type semiconductor layer 12 is selectively epitaxially grown in the lateral direction in the vectors LA and LB in FIG. As a result, the threading dislocations 20 are also bent, and the selective epitaxial growth surfaces from the left and right are merged in the vicinity of the central portion LO of the processed layer 18, and the threading dislocations 20 are also connected at the same time.

  In order to fill the processed layer 18, the epitaxial growth conditions may be changed from the middle to conditions that promote the lateral growth. In order to promote the lateral growth, for example, the pressure of the gas system during crystal growth may be changed. As a first step, for example, after growth of about 1 μm at about 1050 ° C. and about 100 Torr, for example, about 1.5 μm can be grown at about 1050 ° C. and about 200 Torr, for example. By forming the n-type semiconductor layer 12 in this way, lateral growth can be promoted together with the effect of reducing threading dislocation density by ELO.

  Since lateral selective epitaxial growth (ELO) is performed so as to cover the processed layer 18, threading dislocations in the crystal can be bent, and crystallinity is also improved.

  Further, the pressure and growth temperature conditions for forming the n-type semiconductor layer 12 can be changed and divided into several steps. For example, as shown in FIG. 19, an n-type semiconductor layer having a four-layer structure is used. 12 (121, 122, 123, 124) can also be formed. By doing so, the surface morphology of the n-type semiconductor layer 12 is improved, and the crystallinity can be improved.

For example, when the pattern of the processed layer 18 is formed in a stripe shape, the stripe is in the <11-20> or <1-100> direction, the width of the processed layer 18 is about 1 to 4 μm, and the repetition period is, for example, about The thickness is about 7 μm. On top of this, GaN to be the n-type semiconductor layer 12 is grown at 1000 ° C. by HVPE. In the HVPE method, GaCl and NH ₃ are reacted to grow GaN. When the stripe direction is <11-20>, the growth of GaN is first faceted at the opening of the processed layer 18 by the {1-101} plane inclined with respect to the substrate surface by the growth in the first (0001) direction. A triangular cross-sectional shape is generated. Next, with the facets held, lateral growth proceeds on the processed layer 18 until adjacent growth portions merge. After the coalescence, the growth proceeds so that the surface is further flattened, and a completely flat growth layer having a (0001) plane is obtained. In the pattern in which the stripe is in the <1-100> direction, the {11-22} plane is faceted, but a similar growth layer is obtained.

  The above example is an example, and other patterns and pattern directions are also applicable. In addition, in the above example, the example of the polar plane is described as the main plane of crystal growth, but a nonpolar plane or a semipolar plane can also be applied.

(E) Next, as shown in FIG. 20, the active layer 13 is formed on the n-type semiconductor layer 12.

(F) Next, as shown in FIG. 21, the substrate temperature is set to about 800 ° C. to 900 ° C., and the p-type semiconductor layer 14 doped with p-type impurities on the final barrier layer 310 is about 0.05 to 1 μm. Form.

(G) Next, as shown in FIG. 2, a transparent electrode 15 is formed on the p-type semiconductor layer 14 by vapor deposition, sputtering technique, or the like. As the transparent electrode 15, for example, any one of ZnO, ITO, or ZnO containing indium can be used. Further, an n-type impurity such as Ga or Al may be added at a high concentration up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(H) Next, as shown in FIG. 2, after patterning the transparent electrode 15, the middle of the p-type semiconductor layer 14 to the n-type semiconductor layer 12 is removed by using an etching technique such as RIE to form an n-type semiconductor. The surface of layer 12 is exposed.

(I) Next, the n-side electrode 200 is formed on the exposed surface of the n-type semiconductor layer 12 by vapor deposition, sputtering technique, or the like. Also on the transparent electrode 15 on the p-type semiconductor layer 14, the p-side electrode 100 is formed by vapor deposition, sputtering technique, etc. after pattern formation, and the semiconductor light emitting device shown in FIG. 2 is completed.

(Detailed structure example 1)
22 is a detailed schematic cross-sectional structure example 1 of the semiconductor light-emitting device according to the first embodiment, and an enlarged schematic cross-sectional structure diagram of the semiconductor light-emitting device portion and the active layer portion is as shown in FIG. A substrate 10, a nano-sized processed layer 18 disposed on the substrate 10, a buffer layer 16 disposed on the substrate 10 sandwiched between the processed layers 18, and a buffer layer 16 and a processed layer 18. An n-type semiconductor layer 12 doped with an n-type impurity, a block layer 17 disposed on the n-type semiconductor layer 12 and doped with an n-type impurity at a lower concentration than the n-type semiconductor layer 12, and a block The active layer 13 is disposed on the layer 17, the p-type semiconductor layer 14 is disposed on the active layer 13, and the transparent electrode 15 is disposed on the p-type semiconductor layer 14.

In the configuration of FIG. 22, a GaN film doped with Si at a concentration of less than 1 × 10 ¹⁷ cm ⁻³ , for example, about 8 × 10 ¹⁶ cm ^{−3 is used} as the block layer 17 on the n-type semiconductor layer 12. Grow about 200 nm. At this time, the same source gas as in the case where the n-type semiconductor layer 12 is formed can be applied.

  As shown in FIG. 22, the active layer 13 has a stacked structure in which barrier layers 311 to 31 n and 310 and well layers 321 to 32 n having a smaller band gap than the barrier layers 311 to 31 n and 310 are alternately arranged. Hereinafter, the first barrier layer 311 to the n-th barrier layer 31n included in the active layer 13 are collectively referred to as “barrier layer 31”. Also, all well layers included in the active layer 13 are collectively referred to as “well layers 32”.

On the formed laminated structure, as shown in FIG. 22, an active layer 13 is formed by forming a non-doped GaN film of about 10 nm as the final barrier layer 310. The film thickness d ₀ of the final barrier layer 310 is set to such a thickness that the p-type dopant that diffuses from the p-type semiconductor layer 14 to the active layer 13 does not reach the well layer 32 of the active layer 13.

  For example, as shown in FIG. 22, the active layer 13 is formed by alternately laminating barrier layers 31 made of GaN films and well layers 32 made of InGaN films. Specifically, the barrier layer 31 and the well layer 32 are alternately and continuously grown while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 13, and the barrier layer 31 and the well layer 32 are laminated. An active layer 13 is formed. That is, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a stacked structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

In the case of forming the barrier layer 31, for example, TMG gas and NH ₃ gas are supplied to the processing apparatus for film formation as source gases. On the other hand, when forming the well layer 32, for example, TMG gas, trimethylindium (TMI) gas, and NH ₃ gas are supplied to the processing apparatus as source gases. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

For example, as shown in FIG. 22, the p-type semiconductor layer 14 is formed in a four-layer structure in which Mg is added as a p-type impurity. The first nitride-based semiconductor layer 41 disposed on the active layer 13 is formed of a p-type GaN layer having a thickness of about 2 × 10 ²⁰ cm ⁻³ and a thickness of about 50 nm, and the second nitride-based semiconductor layer 42 is formed. Is formed of a p-type GaN layer having a thickness of about 4 × 10 ¹⁹ cm ⁻³ and a thickness of about 100 nm. The third nitride semiconductor layer 43 has a thickness of about 1 × 10 ²⁰ cm ⁻³ and a thickness of about 40 nm, for example. The fourth nitride semiconductor layer 44 is formed of a p-type GaN layer having a thickness of about 8 × 10 ¹⁹ cm ⁻³ and a thickness of about 10 nm.

When Mg is added as an impurity, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are supplied as source gases to form the p-type semiconductor layers 14 (41 to 44). Mg is diffused from the p-type semiconductor layer 14 (41 to 44) to the active layer 13 during the formation of the p-type semiconductor layer 14 (41 to 44), but the final barrier layer 310 causes Mg to enter the well layer 32 of the active layer 13. It is prevented from spreading.

  The film thickness of the final barrier layer 310 in the uppermost layer of the stacked structure is larger than the thicknesses of the other barrier layers (the first barrier layer 311 to the nth barrier layer 31n) included in the stacked structure other than the final barrier layer 310. It may be formed.

  In the semiconductor light emitting device shown in FIG. 22, the concentration of the p-type dopant in the final barrier layer 310 extends from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 along the film thickness direction of the final barrier layer 310. There is no p-type dopant on the second main surface that gradually decreases and faces the first main surface.

  The n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 are each made of a group III nitride semiconductor, and after forming a nano-sized processed layer 18 on the substrate 10, the buffer layer 16, the n-type semiconductor layer 12, the block layer 17, the active layer 13, and the p-type semiconductor layer 14 are sequentially stacked.

(Processed layer)
The processed layer 18 is transparent to the emission wavelength, and the refractive index of the processed layer 18 is substantially equal to the refractive index of the substrate 10. For example, as the processing layer 18, a layer having a refractive index close to the refractive index of the substrate 10 that is sufficiently transparent to the emission wavelength may be used.

When a sapphire substrate (n = 1.7 to 1.8) is used as the substrate 10, if a SiO ₂ film is used as the processed layer 18, the refractive index of the SiO ₂ film is about n = 1.46. The refractive index n of the substrate is about the same as 1.7 to 1.8. When a SiN _x film is used as the processed layer 18, the refractive index of the SiN _x film is about n = 2.05, which is about the same as the refractive index of the sapphire substrate. When a TiO _x film is used as the processing layer 18, the refractive index of the TiO _x film is about n = 1.8, which is about the same as the refractive index of the sapphire substrate. Furthermore, when an Al ₂ O ₃ film is used as the processed layer 18, the refractive index of the Al ₂ O ₃ film is about n = 1.7 to 1.8, which is about the same as the refractive index of the sapphire substrate.

  Therefore, as the processed layer 18, any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, and an alumina film can be applied.

  In addition, as shown in FIGS. 7 to 8, by providing a distribution of the refractive index n inside the processed layer 18, the light extraction efficiency to the substrate 10 side is improved, and the external light emission efficiency is improved. A light-emitting element can be provided.

(AlN buffer layer)
The buffer layer 16 is formed of, for example, an AlN layer having a thickness of about 10 to 50 angstroms. When the AlN buffer layer 16 is crystal-grown, for example, it is grown at a high temperature in the temperature range of about 900 ° C. to 950 ° C.

By supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier, a thin AlN buffer layer 16 having a thickness of about 10 to 50 Å can be grown at a high speed. And can be formed while maintaining good crystallinity.

  According to the semiconductor light emitting device according to the first embodiment, the crystallinity and surface morphology of the group III nitride semiconductor formed on the high temperature AlN buffer layer 16 and the processed layer 18 can be improved.

(Block layer)
The block layer 17 disposed between the n-type semiconductor layer 12 and the active layer 13 is a group III nitride semiconductor having a thickness of about 200 nm, for example, doped with Si as an n-type impurity at less than 1 × 10 ¹⁷ cm ^−3. For example, a GaN layer can be employed.

In the semiconductor light emitting device shown in FIG. 22, for example, when Si is doped with about 3 × 10 ¹⁸ cm ^{−3 in the} n-type semiconductor layer 12, Si is doped with about 8 × 10 ¹⁶ cm ^−3. By disposing the layer 17 between the n-type semiconductor layer 12 and the active layer 13, the diffusion of Si from the n-type semiconductor layer 12 to the active layer 13 in the process of forming the active layer 13 and the manufacturing process after that process can be prevented. .

  That is, Si does not diffuse into the active layer 13, and a decrease in luminance of light generated in the active layer 13 is prevented. Further, when a bias is applied between the n-type semiconductor layer 12 and the p-type semiconductor layer 14 to cause the active layer 13 to emit light, electrons supplied from the n-type semiconductor layer 12 to the active layer 13 cause the active layer 13 to An overflow that passes through and reaches the p-type semiconductor layer 14 can be prevented, and a decrease in luminance of light output from the semiconductor light emitting element can be prevented.

The Si concentration of the block layer 17 is less than 1 × 10 ¹⁷ cm ⁻³ . This is because, when the Si concentration of the block layer 17 is too high, electrons supplied from the n-type semiconductor layer 12 overflow the active layer 13 and reach the p-type semiconductor layer 14. This is because recombination occurs, the recombination rate in the active layer 13 decreases, and the luminance of light generated in the active layer 13 decreases. On the other hand, when the Si concentration of the block layer 17 is too low, the carrier density of electrons injected from the n-type semiconductor layer 12 into the active layer 13 cannot be increased. Therefore, the Si concentration of the block layer 17 is preferably about 5 × 10 ¹⁶ to less than 1 × 10 ¹⁷ cm ⁻³ .

  As described above, in the semiconductor light emitting device according to the first embodiment, the block layer 17 is disposed between the n-type semiconductor layer 12 and the active layer 13, thereby allowing the n-type semiconductor layer 12 during the manufacturing process. Diffusion of Si from the active layer 13 to the active layer 13 and overflow of electrons from the n-type semiconductor layer 12 to the p-type semiconductor layer 14 during light emission can be prevented, and the luminance of light output from the semiconductor light-emitting element can be reduced. Can be prevented. As a result, deterioration of the quality of the semiconductor light emitting element shown in FIG. 22 can be prevented.

(N-type semiconductor layer)
The n-type semiconductor layer 12 supplies electrons to the active layer 13, and the p-type semiconductor layer 14 supplies holes (holes) to the active layer 13. Light is generated by the recombination of the supplied electrons and holes in the active layer 13.

  The n-type semiconductor layer 12 may be a group III nitride semiconductor having a thickness of about 1 to 6 μm doped with an n-type impurity such as silicon (Si), such as a GaN layer.

  The n-type semiconductor layer 12 made of a nitride semiconductor is directly epitaxially grown on the heterogeneous substrate 10 through the processed layer 18. In order to fill the processed layer 18, the condition is changed from the middle to a condition that promotes lateral growth. In order to promote the lateral growth, for example, the pressure of the gas system during crystal growth may be changed. As a first step, for example, after growth of about 1 μm at about 1050 ° C. and about 100 Torr, for example, about 1.5 μm can be grown at about 1050 ° C. and about 200 Torr, for example. By forming the n-type semiconductor layer 12 in this way, lateral growth can be promoted together with the effect of reducing threading dislocation density by lateral growth (ELO).

  Since lateral growth (ELO) is performed so as to cover the processed layer 18, threading dislocations in the crystal can be bent, and crystallinity is also improved.

(P-type semiconductor layer)
The p-type semiconductor layer 14 may be a group III nitride semiconductor having a thickness of about 0.05 to 1 μm doped with p-type impurities, such as a GaN layer. As the p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

  A configuration example of the p-type semiconductor layer 14 is as follows in more detail. That is, as shown in FIG. 22, the p-type semiconductor layer 14 is disposed on the active layer 13 and is formed on the first nitride-based semiconductor layer 41 including the p-type impurity and on the first nitride-based semiconductor layer 41. A second nitride-based semiconductor layer 42 including a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 41; and a second nitride-based semiconductor layer 42 disposed on the second nitride-based semiconductor layer 42; A third nitride-based semiconductor layer 43 containing a p-type impurity at a higher concentration than the p-type impurities of the nitride-based semiconductor layer 42; and a third nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer 43 And a fourth nitride-based semiconductor layer 44 containing a p-type impurity having a lower concentration than the 43 p-type impurities.

  The thickness of the second nitride-based semiconductor layer 42 is formed to be greater than the thickness of the first nitride-based semiconductor layer 41 or the third nitride-based semiconductor layer 43 to the fourth nitride-based semiconductor layer 44.

Here, the material and thickness of each layer will be specifically described. The first nitride semiconductor layer 41 containing p-type impurities disposed on the active layer 13 is, for example, a p-type GaN layer of about 2 × 10 ²⁰ cm ⁻³ and about 50 nm thick doped with Mg. Formed with.

The second nitride semiconductor layer 42 disposed on the first nitride semiconductor layer 41 and containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride semiconductor layer 41 is doped with, for example, Mg. The p-type GaN layer is about 4 × 10 ¹⁹ cm ⁻³ and about 100 nm thick.

The third nitride-based semiconductor layer 43 disposed on the second nitride-based semiconductor layer 42 and containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42 is doped with, for example, Mg. The p-type GaN layer is about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick.

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer 14 formed on the active layer 13 made of a multiple quantum well containing indium has a four-layer structure with different Mg concentrations as described above. It consists of a p-type GaN layer and is doped at the above concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 13.

  The first nitride semiconductor layer 41 closest to the active layer 13 has a higher emission intensity as the Mg concentration is higher. Therefore, the higher the Mg concentration, the better.

The second nitride-based semiconductor layer 42 has a Mg concentration of about 10 ¹⁹ cm ⁻³ because the crystal defects due to Mg increase and the resistance of the film increases when Mg is excessively doped. It is desirable.

  The third nitride-based semiconductor layer 43 is a layer that determines the amount of holes injected into the active layer 13, and is therefore preferably set to a slightly higher Mg concentration than the second nitride-based semiconductor layer 42.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the transparent electrode 15 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Further, the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42 close to the active layer 13 do not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 13 is made of N ₂ carrier gas. The crystal is grown by the extension of the growth. When these p-type GaN layers are grown, a film having a lower resistance can be grown by increasing the V / III ratio as much as possible, and the forward voltage (V _f ) of the light emitting element can be lowered.

According to the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer is formed at a low temperature to reduce the thermal damage to the active layer, to reduce the forward voltage (V _f ), and to improve the luminous efficiency. Can be improved.

(Active layer)
The active layer 13 has a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layers are alternately arranged, and is formed of a multiple quantum well containing indium.

The barrier layer is made of GaN, the well layer is made of In _x Ga _1-x N (0 <x <1), and the number of pairs of multiple quantum wells is about 6 to 11, for example.

  Moreover, the thickness of a well layer is 2-3 nm, for example, and the thickness of a barrier layer is 15-18 nm, for example.

  More specifically, as shown in FIG. 22, the active layer 13 includes first well layers 321 to 32n sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, respectively. It has a multiple quantum well (MQW) structure (n: natural number). That is, the active layer 13 has a quantum well structure in which a well layer 32 is sandwiched between barrier layers 31 having a larger band gap than the well layer 32 in a unit pair structure, and this unit pair structure is stacked n times. Have

  Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer 313. The The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 13 is disposed on the n-type semiconductor layer 12 via the block layer 17, and the p-type semiconductor layer 14 (41 to 44) is disposed on the final barrier layer 310 of the active layer 13. Is done.

The well layers 321 to 32n are formed by, for example, In _x Ga _1-x N (0 <x <1) layers, and the barrier layers 311 to 31n and 310 are formed by, for example, GaN layers. The number of pairs of the multiple quantum well layers is, for example, 6 to 11. The indium (In) ratio {x / (1-x)} of the well layers 321 to 32n is appropriately set according to the wavelength of light to be generated.

  Further, the thickness of the well layers 321 to 32n is, for example, about 2 to 3 nm, preferably about 2.8 nm, and the thickness of the barrier layers 311 to 31n is about 7 to 18 nm, preferably about It is about 16.5 nm.

  In the semiconductor light emitting device according to the first embodiment, the active layer for efficiently recombining the electrons supplied from the n-type semiconductor layer 12 and the holes supplied from the p-type semiconductor layer 14 in the active layer 13. The number of MQW pairs in 13 can be optimized.

(Final barrier layer)
The final barrier layer 310 is formed thicker than the Mg diffusion distance from the p-type semiconductor layer 14 to the active layer 13.

  In the example of the semiconductor light emitting device shown in FIG. 22, the concentration of the p-type impurity in the final barrier layer 310 is from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 in the film thickness direction of the final barrier layer 310. The p-type impurity is substantially absent in the second main surface that gradually decreases along the second main surface and faces the first main surface.

The film thickness d ₀ of the final barrier layer 310 of the semiconductor light emitting device shown in FIG. 22 is such that the p-type impurity diffused from the p-type semiconductor layer 14 to the active layer 13 after the formation process of the p-type semiconductor layer 14 and after that process. It is set so as not to reach the well layer 32 of the active layer 13. That is, the p-type impurity diffused from the p-type semiconductor layer 14 to the final barrier layer 310 is a second main surface (the final barrier layer 310 is a well) facing the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14. The film thickness d ₀ is set to a thickness that does not reach the surface) that contacts the layer 32n.

The Mg concentration on the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 is, for example, about 2 × 10 ²⁰ cm ⁻³ , and the second concentration of the final barrier layer 310 facing the first main surface is about 2 × 10 ²⁰ cm ⁻³ . The Mg concentration gradually decreases toward the main surface, and the Mg concentration does not have an influence of less than about 10 ¹⁶ cm ^{−3 at a} distance of about 7 to 8 nm from the first main surface, and is below the detection lower limit in the analysis. Become.

That is, by setting the film thickness d ₀ of the final barrier layer 310 to about 10 nm, Mg does not diffuse to the second main surface of the final barrier layer 310, and therefore, the first barrier layer 310 in contact with the active layer 13 is not diffused. 2 Mg does not exist on the main surface. That is, Mg does not diffuse into the n-th well layer 32n, and a reduction in the luminance of light generated in the active layer 13 is prevented.

The film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n may be the same. However, the thicknesses d1 to dn are such that holes injected from the n-type semiconductor layer 12 into the active layer 13 reach the n-th well layer 32n, and light is emitted by recombination of electrons and holes in the n-th well layer 32n. It is necessary to set a thickness that can be generated. This is because if the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are too thick, the movement of holes in the active layer 13 is hindered and the light emission efficiency is lowered. For example, the film thickness d ₀ of the final barrier layer 310 is about 10 nm, the film thicknesses d ₁ to dn of the first barrier layer 311 to the n-th barrier layer 31 n are about 7 to 18 nm, and the first well layers 321 to 321 The film thickness of the n-th well layer 32n is about 2 to 3 nm.

As described above, in the semiconductor light emitting device according to the first embodiment, the film thickness d ₀ of the final barrier layer 310 in contact with the p-type semiconductor layer 14 diffuses from the p-type semiconductor layer 14 to the active layer 13. The thickness is set such that the p-type impurity does not reach the well layer 32 of the active layer 13. That is, according to the semiconductor light emitting device shown in FIG. 15, by setting the film thickness d ₀ of the final barrier layer 310 to be larger than the Mg diffusion distance, the increase in the film thickness of the entire active layer 13 is suppressed, and p The diffusion of p-type impurities from the type semiconductor layer 14 to the well layer 32 of the active layer 13 can be prevented. As a result, it is possible to manufacture a semiconductor light emitting device in which the light luminance is not lowered due to the diffusion of the p-type impurity into the well layer 32 and the deterioration of the quality of the semiconductor light emitting device is suppressed.

(Transparent electrode)
The transparent electrode 15 may be any one of ZnO, ITO, or ZnO containing indium. Alternatively, the transparent electrode 15 may be any one of ZnO, ITO, or ZnO containing Ga or Al doped with an impurity concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(Detailed structure example 2)
23 is a detailed schematic cross-sectional structure example 2 of the semiconductor light-emitting device according to the first embodiment. An enlarged schematic cross-sectional structure of the semiconductor light-emitting device portion and the active layer portion is shown in FIG. A nano-sized processed layer 18 disposed on the substrate 10, a buffer layer 16 disposed on the substrate 10 sandwiched between the processed layers 18, a buffer layer 16 and a processed layer 18. An n-type semiconductor layer 12 doped with an n-type impurity, a block layer 17 disposed on the n-type semiconductor layer 12 and doped with an n-type impurity at a lower concentration than the n-type semiconductor layer 12, and a block layer 17 An active layer 13 disposed above, a p-type semiconductor layer 14 disposed on the active layer 13, and a transparent electrode 15 disposed on the p-type semiconductor layer 14 are provided.

  The detailed schematic cross-sectional structure example 2 of the semiconductor light emitting device according to the first embodiment includes a third nitride-based semiconductor layer 43 including a p-type impurity disposed on the active layer 13, and a third nitride. A fourth nitride-based semiconductor layer that is disposed on the semiconductor layer and includes a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer; and a fourth nitride-based semiconductor layer, And a transparent electrode 15.

  In the detailed schematic cross-sectional structure example 2 of the semiconductor light emitting device according to the first embodiment, the third nitride semiconductor in which the p-type semiconductor layer 14 is directly disposed on the active layer 13 due to its structure. 2 comprising a layer 43 and a fourth nitride-based semiconductor layer 44 disposed on the third nitride-based semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride-based semiconductor layer 43. It is formed in a layer structure.

The third nitride semiconductor layer 43 disposed directly on the active layer 13 is formed of, for example, a p-type GaN layer of about 1 × 10 ²⁰ cm ⁻³ doped with Mg and having a thickness of about 40 nm. .

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the detailed schematic cross-sectional structure example 2 of the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer 14 formed on the active layer 13 made of a multiple quantum well containing indium is as described above. The p-type GaN layer has a two-layer structure with different Mg concentrations, and is doped at the above concentrations. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 13.

  Since the third nitride semiconductor layer 43 closest to the active layer 13 is a layer that determines the amount of holes injected into the active layer 13, the higher the Mg concentration, the higher the emission intensity. For this reason, the higher the Mg concentration, the better.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the transparent electrode 15 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When growing two p-type GaN layers, the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Alternatively, the third nitride-based semiconductor layer 43 close to the active layer 13 does not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 13 is grown by the N ₂ carrier gas, so that the third nitride semiconductor layer 43 is crystallized. It may be grown.

  Also in the detailed schematic cross-sectional structure example 2 of the semiconductor light emitting element according to the first embodiment, the processed layer 18 disposed on the substrate 10 and the buffer layer disposed on the substrate 10 sandwiched between the processed layers 18 16, the n-type semiconductor layer 12, the block layer 17, the active layer 13, the p-type semiconductor layer 14, the final barrier layer 310, and the electrode structure, which are disposed on the buffer layer 16 and the processed layer 18 and doped with n-type impurities. Since this is the same as the detailed structure example 1 of the semiconductor light emitting device according to the first embodiment of the present invention, the description thereof is omitted.

  In the detailed schematic cross-sectional structure example 1 and structure example 2 of the semiconductor light emitting device according to the first embodiment, the crystallinity of the group III nitride semiconductor formed on the high-temperature AlN buffer layer 16 and the processed layer 18 is described. And the surface morphology can be improved.

In addition, the p-type semiconductor layer 14 can be formed at a low temperature to reduce thermal damage to the active layer 13 and to reduce the forward voltage V _f to improve the light emission efficiency.

  Further, the number of MQW pairs in the active layer 13 for efficiently recombining the electrons supplied from the n-type semiconductor layer 12 and the holes supplied from the p-type semiconductor layer 14 in the active layer 13 is optimized, and the light emission efficiency is improved. Can be improved.

  Further, the diffusion of p-type impurities from the p-type semiconductor layer 14 to the well layer can be suppressed, and the light emission efficiency can be improved. The overflow of electrons from the n-type semiconductor layer 12 to the p-type semiconductor layer 14 and the n-type The diffusion of n-type impurities from the semiconductor layer 12 to the active layer 13 can be suppressed, and the light emission efficiency can be improved.

(Crystal growth plane orientation)
A crystal plane of a group III nitride semiconductor applied to the semiconductor light emitting device according to the first embodiment will be described. The c-plane, a-plane, and m-plane of the crystal structure of the group III nitride semiconductor are schematically represented as shown in FIG. 24A, and the semipolar plane {10-11} is schematically shown in FIG. b), the semipolar plane {10-13} is schematically represented as shown in FIG. 24 (c), and the bond shape between the group III atom and the nitrogen atom is schematically illustrated in FIG. 24 (d).

  The crystal structure of the group III nitride semiconductor can be approximated by a hexagonal system as shown in FIGS. 24 (a) to 24 (d), and there are four nitrogen atoms for one group III atom. Are connected. Four nitrogen atoms are located at four vertices of a regular tetrahedron having a group III atom arranged at the center. Of these four nitrogen atoms, one nitrogen atom is positioned in the + c axis direction with respect to the group III atom, and the other three nitrogen atoms are positioned on the −c axis side with respect to the group III atom. Because of such a structure, the polarization direction is along the c-axis in the group III nitride semiconductor.

  The c-axis is along the axial direction of the hexagonal column, and the plane (the top surface of the hexagonal column) having the c-axis as a normal is the c-plane {0001}. When the group III nitride semiconductor crystal is cleaved by two planes parallel to the c plane, the + c axis side plane (+ c plane) becomes a crystal plane in which group III atoms are arranged, and the −c axis side plane (−c plane) ) Is a crystal plane with nitrogen atoms. For this reason, the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the −c-axis side.

  Since the + c plane and the −c plane are different crystal planes, different physical properties are exhibited accordingly. Specifically, it is known that the + c surface has high durability against chemical reactions such as resistance to alkali, and conversely, the −c surface is chemically weak and is soluble in alkali, for example.

  On the other hand, the side surfaces of the hexagonal columns are m-planes {10-10}, respectively, and the planes passing through a pair of ridge lines that are not adjacent to each other are a-planes {11-20}. Since these are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, they are nonpolar planes, that is, nonpolar planes. Furthermore, as shown in FIGS. 24B and 24C, crystal planes {10-11} and {10-13} that are inclined with respect to the c-plane (not parallel nor perpendicular) are Since it crosses diagonally with respect to the polarization direction, it is a plane with some polarity, that is, a semipolar plane. Specific examples of other semipolar planes are planes such as {10-1-1} plane, {10-1-3} plane, {11-22} plane.

  For example, a GaN single crystal substrate having an m-plane as a main surface can be produced by cutting from a GaN single crystal having a c-plane as a main surface. The m-plane of the cut substrate is polished by, for example, a chemical mechanical polishing process, and the orientation error in both the [0001] direction and the [11-20] direction is within ± 1 ° (preferably ± 0.3 °). Within). In this way, a GaN single crystal substrate having an m-plane as a main surface is obtained.

  The semiconductor light emitting device according to the first embodiment can use each surface of the hexagonal crystal structure as a crystal main surface, and can form a semiconductor light emitting device by MOCVD or the like.

  In the semiconductor light emitting device according to the first embodiment and its modification, for example, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a non-polar plane with a hexagonal crystal structure as the main crystal growth. The pattern shape of the processed layer 18 may be selected so that the lateral growth surface of the n-type semiconductor layer 12 is a nonpolar surface perpendicular to the nonpolar surface.

  Alternatively, in the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14, the m-plane of the hexagonal crystal structure is a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 is the above m-plane. The pattern shape of the processed layer 18 may be selected so as to be an a-plane perpendicular to the plane.

  Alternatively, in the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14, the a-plane of the hexagonal crystal structure is a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 is the above-described a The pattern shape of the processed layer 18 may be selected so that the m plane is perpendicular to the plane.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexapolar structure semipolar plane as the main plane for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 is The pattern shape of the processed layer 18 may be selected so as to be an a-plane or m-plane perpendicular to the semipolar plane.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexagonal crystal polar surface as a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 has an m-plane or The pattern shape of the processed layer 18 may be selected so as to be the a-plane.

  In the detailed schematic cross-sectional structure example 1 of the semiconductor light emitting device according to the first embodiment shown in FIG. 22, the schematic cross-sectional structure formed up to the p-side electrode and the n-side electrode is as shown in FIG. An n-side electrode 200 that applies a voltage to the n-type semiconductor layer 12 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 14 are further provided. As shown in FIG. 25, an n-side electrode is formed on the surface of the n-type semiconductor layer 12 exposed by etching a partial region of the p-type semiconductor layer 14, the active layer 13, the block layer 17, and the n-type semiconductor layer 12. 200 is arranged.

  The p-side electrode 100 is disposed on the p-type semiconductor layer 14 via the transparent electrode 15. Alternatively, the p-side electrode 100 may be disposed directly on the p-type semiconductor layer 14. The transparent electrode 15 disposed on the fourth nitride-based semiconductor layer 44 includes, for example, any of ZnO, ITO, or ZnO containing indium.

  The n-side electrode 200 is, for example, an aluminum (Al) film, a multilayer film of Ti / Ni / Au or Al / Ti / Au, Al / Ni / Au, Al / Ti / Ni / Au, or Au—Sn / Ti from the upper layer. The p-side electrode 100 is made of, for example, an Al film, a palladium (Pd) -gold (Au) alloy film, a Ni / Ti / Au multilayer film, or an Au—Sn / It consists of a multilayer film of Ti / Au. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 12, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 14 via the transparent electrode 15.

(Detailed structure example 3)
26 is a detailed schematic cross-sectional structure example 3 of the semiconductor light-emitting device according to the first embodiment, and an enlarged schematic cross-sectional structure of the semiconductor light-emitting device portion and the active layer portion is formed on a substrate as shown in FIG. 10, a processing layer 18 disposed on the substrate 10 and nano-sized, an AlN buffer layer 16 disposed on the substrate 10 sandwiched between the processing layers 18, an AlN buffer layer 16, and a processing layer 18. disposed, and n-type semiconductor layer 25 n-type impurity is made of Al _x Ga _1-x n layer doped impurity (0 <x <1), is disposed on the n-type semiconductor layer 25, Al _x Ga _{1 -x} N layer (0 <x <1) and Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1) having a smaller band gap than the barrier layer Active layer 6 composed of multiple quantum wells having a stacked structure in which well layers are alternately arranged 0 and a p-type semiconductor layer 80 made of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity and disposed on the active layer 60. The n-type semiconductor layer 25 is disposed on the n-type semiconductor layer 12 and the n-type semiconductor layer 12 composed of an Al _x Ga _1-x N layer (0 <x <1) doped with an n-type impurity. And an n-type contact layer 19 made of an Al _x Ga _1-x N layer (0 <x <1) doped with a type impurity.

As shown in FIG. 26, the active layer 60 includes barrier layers 611 to 61n and 610 made of Al _x Ga _1-x N layers (0 <x <1) and Al having a smaller band gap than the barrier layers 611 to 61n and 610. having _x in _y Ga _1-xy N layer (0 <x ≦ y <1 , 0 <x + y <1) stacked structure well layer 621~62n are arranged alternately consisting of.

  In the detailed schematic cross-sectional structure example 3 of the semiconductor light emitting device according to the first embodiment shown in FIG. 26, the schematic cross-sectional structure formed up to the p-side electrode and the n-side electrode is as shown in FIG. An n-side electrode 200 that applies a voltage to the n-type semiconductor layer 25 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 80 are further provided. As shown in FIG. 27, the n-side electrode 200 is disposed on the surface of the n-type contact layer 19 that is exposed by etching a partial region of the p-type semiconductor layer 80, the active layer 60, and the n-type contact layer 19. The

(Flip chip structure)
A schematic cross-sectional structure showing a structure in which the semiconductor light-emitting device according to the first embodiment is mounted on a flip-chip package is expressed as shown in FIG.

  The p-side electrode 100 of the semiconductor light emitting device according to the first embodiment is connected to an anode electrode pattern (not shown) mounted on the inner wall bottom of the package 2 by die bonding. Reference numeral 200 denotes a cathode electrode pattern (not shown) mounted on the bottom of the inner wall of the package 2 by die bonding.

  In addition, the semiconductor light emitting element according to the first embodiment is mounted in the package 2 by, for example, the mold resin 1.

  In the semiconductor light emitting device according to the first embodiment mounted in the flip chip structure, the light emitted downward from the active layer 13 is partially reflected at the interface between the p-type semiconductor layer 14 and the transparent electrode 15. And propagates upward. The light emitted upward from the active layer 13 is efficiently refracted in the processed layer 18, propagates in the substrate 10, and propagates upward.

  As a result, as shown in FIG. 28, in the semiconductor light emitting device according to the first embodiment mounted on the package 2 having the flip chip structure, the light emitted upward and downward from the active layer 13 is efficient. It can be taken out well.

  A flip chip structure that is a path for extracting light from the GaN layer side to the outside through the sapphire substrate 10 is particularly effective in that the external light emission efficiency can be improved.

  A substrate in which a processed layer 18 having a partially different refractive index is formed on a different substrate 10 is prepared, and a nitride-based semiconductor is directly epitaxially grown on the substrate to form a light emitting device. Unevenness can be formed on the substrate interface, light scattering and diffraction occur, and light extraction efficiency is improved.

  In addition, as shown in FIGS. 7 to 8, by providing a distribution of the refractive index n inside the processed layer 18, the light extraction efficiency to the substrate 10 side is improved, and the external light emission efficiency is improved. A light-emitting element can be provided.

(Modification 1)
A schematic cross-sectional structure showing a structure in which the semiconductor light emitting device according to the first modification of the first embodiment is mounted on a package is expressed as shown in FIG.

  The semiconductor light emitting device according to the first modification of the first embodiment of the present invention is characterized in that a processed layer 19 a is also provided on the transparent electrode 15. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  The pattern size of the processed layer 19a is a nanometer scale, and the pattern of the processed layer 19a is formed by, for example, producing a concavo-convex structure having a sufficiently high height on the transparent electrode 15 using the nanoimprint technique. Further, the processed layer 19a is a layer of a material that can be processed easily, and, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, an alumina film, or the like is applied as in the processed layer 18. Can do.

  The light radiated upward from the active layer 13 is partially reflected at the interface between the p-type semiconductor layer 14 and the transparent electrode 15 and propagates downward, but part of the light is generated by the uneven surface of the processed layer 19a. It is irregularly reflected and propagates upward due to the refractive index distribution inside the processed layer 19a.

  Further, the light emitted downward from the active layer 13 is efficiently refracted in the processed layer 18, propagates through the substrate 10, is reflected at the bottom of the inner wall of the package 2, and propagates upward.

  As a result, in the semiconductor light emitting device according to the first modification of the first embodiment mounted on the package 2, the light emitted upward and downward from the active layer 13 can be efficiently extracted to the outside. .

(Modification 2)
A schematic cross-sectional structure showing a structure in which the semiconductor light emitting device according to the second modification of the first embodiment is mounted on a package is expressed as shown in FIG.

  In the semiconductor light emitting device according to the second modification of the first embodiment of the present invention, in addition to the processed layer 19a on the transparent electrode 15, the processed layer 19b is also formed on the surface of the n-type semiconductor layer 12 exposed by etching. It is characterized by providing. The other configuration is the same as that of the first modification of the first embodiment, and a duplicate description is omitted.

  The pattern size of the processed layer 19b is on the nanometer scale. For example, the pattern of the processed layer 19b is formed by forming a sufficiently uneven structure on the n-type semiconductor layer 12 using nanoimprint technology. The processed layer 19b is a layer of a material that can be easily processed. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, an alumina film, or the like is applied as in the processed layer 18. Can do.

  The light emitted upward from the active layer 13 is partially reflected at the interface between the p-type semiconductor layer 14 and the transparent electrode 15 and propagates downward, but part of it is on the uneven surface of the processed layer 19a. It is irregularly reflected and propagates upward due to the refractive index distribution inside the processed layer 19a.

  Further, the light emitted downward from the active layer 13 is efficiently refracted in the processed layer 18, propagates in the substrate 10, is reflected on the bottom of the inner wall of the package 2, is propagated upward, and a part thereof Then, it is irregularly reflected by the uneven surface of the processed layer 19b, and is propagated upward by the refractive index distribution inside the processed layer 19b.

  As a result, in the semiconductor light emitting device according to the second modification of the first embodiment mounted on the package 2, the light emitted upward and downward from the active layer 13 can be efficiently extracted to the outside. .

  According to the first embodiment of the present invention and its modification, a semiconductor light emitting device with improved external light emission efficiency is produced by producing a concavo-convex structure with a sufficiently high height on the substrate growth surface, particularly using nanoimprint technology. be able to.

[Other embodiments]
As described above, the present invention has been described with reference to the first embodiment and its modifications. However, the discussion and the drawings that form a part of this disclosure are illustrative and are intended to limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the description of the embodiment already described, the barrier layer 31 composed of the Al _x Ga _1-x N layer (0 <x <1) and the Al _x In _y Ga _1-xy N having a smaller band gap than the barrier layer 31. Although an example of the active layer 30 composed of multiple quantum wells having a stacked structure in which the well layers 32 composed of layers (0 <x ≦ y <1, 0 <x + y <1) are alternately arranged is shown, One well layer 32 composed of an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1) is included, and is disposed between the well layer 32 and the p-type semiconductor layer 40. The final barrier layer 310 may have a structure in which the film thickness d ₀ is thicker than the Mg diffusion distance.

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor light emitting device of the present invention can be used for all nitride semiconductor devices such as LED devices and LD devices having a quantum well structure.

DESCRIPTION OF SYMBOLS 1 ... Mold resin 2 ... Package 4 ... Nanoimprint mold 6 ... Resist layer 10 ... Substrate (sapphire substrate)
12, 25, 121, 122, 123, 124 ... n-type semiconductor layers 13, 30, 60 ... active layer 14 ... p-type semiconductor layer 15 ... transparent electrode 16 ... buffer layer 17 ... block layers 18, 18-1 to 18- n, 19a, 19b ... processed layer 19 ... n-type contact layer 20 ... threading dislocation 21 ... electron barrier layer 22 ... cap layers 31, 311 to 31n ... barrier layer (GaN layer)
32, 321-32n ... well layer (InGaN layer)
61,611-61n ... barrier layer (AlGaN layer)
62,621-62n ... well layer (AlInGaN layer)
40, 80 ... p-type semiconductor layers 41, 81 ... first nitride semiconductor layers 42, 82 ... second nitride semiconductor layers 43, 83 ... third nitride semiconductor layers 44, 84 ... fourth nitride systems Semiconductor layer (p-type contact layer)
100 ... p-side electrode 102, 202 ... bonding contact 104,204 ... bonding wire 106,206 ... electrode pattern 200 ... n-side electrode 310,610 ... final barrier layer LO ... center part LA, LB of processed layer 18 ... horizontal selection Growth direction vector

Claims (8)

A substrate,
A first processing layer disposed on the substrate and nano-sized;
An n-type semiconductor layer disposed on the substrate and the first processed layer sandwiched between the first processed layers and doped with an n-type impurity;
An active layer disposed on the n-type semiconductor layer;
A semiconductor light emitting device comprising: a p-type semiconductor layer disposed on the active layer and doped with a p-type impurity.   The semiconductor light emitting device according to claim 1, further comprising a buffer layer disposed on the substrate sandwiched between the first processed layers. A transparent electrode disposed on the p-type semiconductor layer;
An n-side electrode disposed on the n-type semiconductor layer surface obtained by removing a part of the transparent electrode, the p-type semiconductor layer, the active layer and the n-type semiconductor layer;
The semiconductor light-emitting element according to claim 1, further comprising: a p-side electrode disposed on the transparent electrode.   The semiconductor light emitting device according to claim 3, further comprising a second processed layer that is nano-sized on the transparent electrode.   5. The semiconductor light-emitting element according to claim 3, further comprising a third processed layer nano-sized processed on the surface of the n-type semiconductor layer obtained by removing a part of the n-type semiconductor layer.   2. The semiconductor light emitting device according to claim 1, wherein the first processed layer has a refractive index distribution in which a value of a refractive index increases as the first processed layer is separated from the substrate.   The semiconductor according to claim 1, wherein the first processed layer is any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, and an alumina film. Light emitting element.   The semiconductor light-emitting element according to claim 1, wherein the semiconductor light-emitting element has a flip chip structure, and light is extracted from the substrate side.

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