JP2011009640A - Semiconductor integrated circuit device - Google Patents

Abstract

In a nonvolatile memory, a technique capable of improving operation reliability when the number of data rewrites is increased is provided.
A gate electrode 9A is formed on a substrate 1 via a laminated insulating film composed of a bottom oxide film 7A, a charge storage layer 8A and a top oxide film 9A. The thickness of the bottom oxide film 7A is the top oxide film. It is formed thicker than the film thickness of 9A. In the memory cell configured as described above, charge exchange to the charge storage layer 8A for writing and erasing is performed between the gate electrode 10A and the charge storage layer 8A.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a nonvolatile memory element.

  Japanese Patent Laying-Open No. 2008-4913 (Patent Document 1) discloses a multilayer tunneling dielectric structure in a nonvolatile memory cell structure in which an insulating layer, a charge storage layer, a multilayer tunneling dielectric structure, and a gate are sequentially stacked on a semiconductor substrate. Discloses a structure in which a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is used. Further, an operation method is described in which data writing and data erasing are performed from the gate electrode side.

  Japanese Patent Laying-Open No. 2008-277530 (Patent Document 2) discloses a nonvolatile memory having a structure in which a silicon nitride film as a charge storage portion is sandwiched between silicon oxide films and a memory gate electrode is disposed on an upper silicon oxide film. A cell is disclosed.

  Japanese Laid-Open Patent Publication No. 10-247694 (Patent Document 3) discloses a tunnel substrate made of a silicon oxide film or an oxynitride film, an insulating film made of a silicon nitride film, a silicon oxide film, or the like on a semiconductor substrate, and a gate electrode. In the MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory cell having a structure in which layers are stacked in order, a structure in which an upper insulating film is thinner than a lower tunnel film is disclosed.

  Japanese Patent Laid-Open No. 7-58313 (Patent Document 4) discloses a structure of a nonvolatile memory cell in which a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a gate electrode are sequentially stacked from a lower layer on a semiconductor substrate. A structure is disclosed in which silicon oxynitride is thinner than the underlying silicon oxide film.

  Japanese Patent Laying-Open No. 2004-349680 (Patent Document 5) discloses a structure of a nonvolatile memory cell in which a silicon oxide film, a silicon nitride film, a silicon oxide film, a gate electrode, and a cap insulating film are sequentially stacked from a lower layer on a semiconductor substrate. Discloses a structure in which the lower silicon oxide film is thinner than the upper silicon oxide film. Further, an operation method for writing data and erasing data from the substrate side is also described.

JP 2008-4913 A JP 2008-277530 A JP-A-10-247694 Japanese Patent Laid-Open No. 7-58313 JP 2004-349680 A

  As a nonvolatile storage device that can electrically write and erase data, an EEPROM (Electrical Erasable and Programmable Read Only Memory) and a flash memory are widely used. These non-volatile semiconductor memory devices (non-volatile memories) represented by EEPROM and flash memory, which are widely used at present, are sandwiched between a silicon oxide film or the like under the gate electrode of a MOS (Metal Oxide Semiconductor) transistor. A conductive floating gate electrode or trapping insulating film is used, and the floating gate electrode or trapping insulating film is used as a charge storage layer. The threshold value of the transistor depends on the charge storage state of the floating gate electrode or trapping insulating film. The information is memorized by using the difference.

  This trapping insulating film refers to an insulating film having a trap level in which charges can be accumulated, and examples thereof include a silicon nitride film. In a non-volatile semiconductor memory device having a trapping insulating film, the threshold value of the MOS transistor is shifted by charge injection / release to / from the trapping insulating film to operate as a memory element. Such a non-volatile semiconductor memory device using a trapping insulating film as a charge storage film is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor, compared to the case where a conductive floating gate electrode is used for the charge storage film. In addition, since charges are accumulated in discrete trap levels, the reliability of data retention is excellent. In addition, since the data retention reliability is excellent, the thickness of the silicon oxide film above and below the trapping insulating film can be reduced, and the voltage of the write / erase operation can be reduced.

  In a MONOS transistor, for example, in a nonvolatile memory cell disclosed in Japanese Patent Application Laid-Open No. 2004-349680 (Patent Document 5), charge is exchanged over the entire channel formed in a semiconductor substrate during data writing and erasing. A non-volatile semiconductor memory device to perform is disclosed. However, as the number of data rewrites increases, the interface state between the silicon oxide film below the trapping insulating film and the underlying semiconductor substrate increases, and the current (read current) during the data read operation increases. There was a problem that it decreased. Therefore, there is a problem that a read current in a state where data is erased cannot be secured, resulting in a retention failure.

  As a countermeasure for such a problem, a method is conceivable in which charge exchange during writing and erasing is not performed between the semiconductor substrate and the trapping insulating film but between the gate electrode and the trapping insulating film. At this time, for example, in order to improve the retention characteristics of electrons injected into the trap insulating film as in the nonvolatile memory cell disclosed in Japanese Patent Application Laid-Open No. 2008-4913 (Patent Document 1), the trapping property is improved. There is a means for forming a three-layered film of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the insulating film. However, the use of the laminated film increases the physical and electrical film thickness and makes it necessary to set a high voltage (for example, about 16 V or more) for data writing and data erasing. For this reason, problems such as the need to increase the area of the booster circuit and the strict guarantee of the reliability of peripheral devices arise.

  An object of the present invention is to provide a technique capable of improving the operation reliability when the number of data rewrites is increased in a MONOS type nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having memory cells,
The memory cell is
A semiconductor substrate;
An n-type source region and an n-type drain region formed in the semiconductor substrate;
A first insulating layer formed on a main surface of the semiconductor substrate;
An insulating charge storage layer formed on the first insulating layer;
A second insulating layer formed on the charge storage layer;
A gate electrode formed on the second insulating layer;
Have
The second insulating layer is formed of a single layer;
The second insulating layer is thinner than the first insulating layer,
The memory cell performs data writing and erasing by injecting charge from the gate electrode to the charge storage layer through the second insulating layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the MONOS type nonvolatile memory, the operation reliability when the number of data rewrites is increased can be improved.

It is principal part sectional drawing explaining the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7; It is explanatory drawing which shows the voltage conditions applied at the time of write-in operation | movement in the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. 6 is a circuit diagram in a write operation of a nonvolatile memory cell included in the semiconductor integrated circuit device according to one embodiment of the present invention; FIG. It is explanatory drawing which shows the relationship between the gate voltage at the time of write-in operation | movement of the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. It is explanatory drawing which shows the voltage conditions applied at the time of the erase operation in the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. FIG. 6 is a circuit diagram in an erase operation of a nonvolatile memory cell included in a semiconductor integrated circuit device according to an embodiment of the present invention. It is explanatory drawing which shows the relationship between the gate voltage at the time of erasure | elimination operation | movement of the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. It is explanatory drawing which shows the voltage conditions applied at the time of read-out operation in the memory cell of the flash memory which the semiconductor integrated circuit device which is one embodiment of this invention has. 4 is a circuit diagram in a read operation of a nonvolatile memory cell included in the semiconductor integrated circuit device according to one embodiment of the present invention; FIG. It is explanatory drawing which shows formation of the interface state in the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. It is explanatory drawing which shows formation of the interface state in the memory cell of the non-volatile memory which the present inventors examined. It is explanatory drawing which shows the relationship between the gate voltage and the read current accompanying the change of the data rewrite frequency in the memory cell of the non-volatile memory which the semiconductor integrated circuit device which is one embodiment of this invention has. It is explanatory drawing which shows the relationship of the change of the number of times of data rewriting in the memory cell of the non-volatile memory which the present inventors examined, gate voltage, and read-out current. 1 is an energy band diagram under a low electric field (thermal equilibrium state) in an n-channel nonvolatile memory cell included in a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 5 is an energy band diagram at the time of data erasing operation in an n-channel nonvolatile memory cell included in the semiconductor integrated circuit device according to one embodiment of the present invention. FIG. 6 is an energy band diagram under a low electric field (thermal equilibrium state) in a p-channel nonvolatile memory cell. FIG. 6 is an energy band diagram at the time of data erasing operation in a p-channel nonvolatile memory cell. FIG. 6 is an energy band diagram at the time of data erasing operation in a p-channel nonvolatile memory cell.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, when referring to the constituent elements in the embodiments, etc., “consisting of A” and “consisting of A” do not exclude other elements unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (for example, SiGe) having silicon as a main element.

  In addition, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The semiconductor integrated circuit device of this embodiment has a MONOS type nonvolatile memory as a nonvolatile memory. Further, the semiconductor integrated circuit device of the present embodiment is mounted with a logic circuit composed of an input / output circuit and a processor such as a CPU, a RAM, and the like, for example. The semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS.

  1 to 8 are cross-sectional views during a manufacturing process of a portion corresponding to the memory cell portion of the MONOS type nonvolatile memory of the present embodiment.

  First, as shown in FIG. 1, a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of single crystal silicon is heat-treated to form a thin silicon oxide film (pad oxide film) on its main surface. Next, after depositing a silicon nitride film on the silicon oxide film by a CVD (Chemical Vapor Deposition) method, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using a photoresist film as a mask. The silicon oxide film is formed for the purpose of alleviating stress applied to the substrate when the silicon oxide film buried in the element isolation trench is densified (baked) in a later step. In addition, since the silicon nitride film is difficult to oxidize, the silicon nitride film is used as a mask for preventing oxidation of the lower surface (active region) of the substrate surface.

  Subsequently, a trench having a depth of about 350 nm is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film as a mask. Next, in order to remove the damage layer generated on the inner wall of the groove by etching, the substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film having a thickness of about 10 nm on the inner wall of the groove. Subsequently, after depositing a silicon oxide film on the substrate 1 by the CVD method, in order to improve the film quality of the silicon oxide film, the substrate 1 is heat treated to densify the silicon oxide film.

  Next, the silicon oxide film on the substrate 1 is polished by the chemical mechanical polishing (CMP) method using the above-described silicon nitride film as a stopper and left inside the groove on the main surface of the substrate 1. Then, the element isolation trench 2 having a planarized surface is formed.

  Next, as shown in FIG. 2, the substrate 1 is subjected to heat treatment to form a silicon oxide film 3 on the main surface of the substrate 1. This silicon oxide film 3 has a function of preventing damage to the substrate 1 when impurity ions are implanted into the main surface of the substrate 1 in a later step, and that the main surface of the substrate 1 is contaminated. It has a function to prevent.

  Subsequently, impurity ions (for example, phosphorus or arsenic) having n-type conductivity are introduced into the main surface of the substrate 1 through the silicon oxide film 3 and formed on the main surface of the substrate 1 in a later step. An n-type isolation region 4 for electrically separating the well and the substrate 1 is formed. Next, impurity ions (for example, boron) having p-type conductivity are introduced into the main surface of the substrate 1 to form the p-type well 5. Next, impurity ions having an n-type conductivity type (for example, arsenic) or p-type conductivity type (for example, boron) for adjusting the threshold voltage of the transistor are introduced into the main surface of the substrate 1, so that the n-type or p-type conductivity is obtained. A mold channel region 6 is formed.

  Next, as shown in FIG. 3, the silicon oxide film 3 is removed by wet etching by cleaning the substrate 1. Subsequently, by subjecting the substrate 1 to heat treatment, a silicon oxide film 7 having a thickness of, for example, about 5 nm to 9 nm, preferably about 7 nm or more is formed on the main surface of the substrate 1 as an insulating film. The relationship between the reason for designing the thickness of the silicon oxide film 7 and the characteristics of the nonvolatile memory according to the present embodiment will be described later when the characteristics of the nonvolatile memory according to the present embodiment are described.

  Subsequently, a silicon nitride film 8 of, eg, about 14 nm to 20 nm is deposited as an insulating film having a trap level on the silicon oxide film 7 by low pressure CVD. This silicon nitride film 8 becomes a charge storage layer in the nonvolatile memory of the present embodiment. The silicon nitride film 8 can be formed by an ALD (Atomic-Layer-Deposition) method or the like other than the exemplified low-pressure CVD method. When the ALD method is used, since the silicon nitride film 8 can be a silicon-rich silicon nitride film, when it becomes a charge storage layer, it can be a charge storage layer with a higher charge trap density. Thus, the retention characteristics can be improved.

  In this embodiment, a silicon nitride film is used as the charge storage layer. However, the charge storage layer is not limited to a silicon nitride film, and is more than a silicon nitride film such as an aluminum oxide film (alumina), a hafnium oxide film, or a tantalum oxide film. A high dielectric constant film having a high dielectric constant may be used. In the case where an insulating film having a trap level is used as the charge storage layer, charges are trapped in the trap level formed in the insulating film. Thus, charges are accumulated in the insulating film by trapping the charges at the trap level.

  Subsequently, a silicon oxide film 9 having a thickness of, for example, about 2 nm or less is formed on the silicon nitride film 8 as an insulating film. Examples of a method for forming the silicon oxide film 9 include a steam oxidation method or an ISSG (In-Situ Steam Generation) oxidation method. The relationship between the reason for designing the thickness of the silicon oxide film 9 and the characteristics of the nonvolatile memory of the present embodiment will be described later when the characteristics of the nonvolatile memory of the present embodiment are described.

  Subsequently, a polycrystalline silicon film 10 of about 200 nm, for example, is formed on the silicon oxide film 9 by low pressure CVD, and an n-type impurity (for example, phosphorus) is introduced into this polycrystalline silicon film. Thereafter, for example, a silicon oxide film 11 of about 70 nm is deposited as an insulating film. The polycrystalline silicon film 10 is processed in a later step to be a gate electrode, and the silicon oxide film 11 is to be a cap insulating film used as a hard mask when the polycrystalline silicon film 10 is processed (etched).

  Next, as shown in FIG. 4, the silicon oxide film 11 is patterned by dry etching using a photoresist film (not shown) patterned by the photolithography technique as a mask. Thereafter, the polycrystalline silicon film 10, the silicon oxide film 9, the silicon nitride film 8 and the silicon oxide film 7 are dry-etched using the patterned silicon oxide film 11 as a hard mask. Thereby, the gate electrode 10A, the top oxide film (second insulating layer) 9A, the charge storage layer 8A, and the bottom oxide film (first insulating layer) 7A, which are the memory cells of the nonvolatile memory according to the present embodiment, are formed. In this embodiment mode, etching in the step illustrated in FIG. 4 is performed by using a hard mask. However, this step may be performed by using a resist.

  Next, as shown in FIG. 5, the substrate 1 is subjected to heat treatment, and the surface of the substrate 1 (n-type or p-type channel region 6), the bottom oxide film 7A, the charge storage layer 8A, the top oxide film 9A, and the gate. A protective film 12 made of silicon oxide is formed on the side wall of the electrode 10A. This protective film 12 protects the sidewalls of the bottom oxide film 7A, the charge storage layer 8A, the top oxide film 9A, and the gate electrode 10A when introducing impurity ions into the main surface of the substrate 1 in the next step. It has a function to prevent damage and contamination to the main surface of the.

Subsequently, on the main surface of the substrate 1 on both sides of the laminated film composed of the bottom oxide film 7A, the charge storage layer 8A, the top oxide film 9A, the gate electrode 10A and the silicon oxide film 11, a low level of about 1 × 10 ¹⁸ / cm ³ is provided. Impurities (for example, phosphorus) having n-type conductivity at a concentration are introduced to form n ⁻ -type extension regions 13.

  Next, as shown in FIG. 6, for example, a silicon oxide film is deposited as an insulating film on the main surface of the substrate 1 by low-pressure CVD, and then the silicon oxide film and the silicon oxide film 11 used as a hard mask are formed. By anisotropically etching (etching back), sidewall spacers 14 made of a silicon oxide film are formed on the sidewalls of bottom oxide film 7A, charge storage layer 8A, top oxide film 9A, and gate electrode 10A. Here, in this embodiment, a silicon oxide film is used as an insulating film for forming the sidewall spacer. However, the insulating film is not limited to a silicon oxide film, and is formed of a silicon nitride film, or a silicon oxide film and a silicon nitride film. You may form as a laminated film. The thickness of the sidewall spacer 14 in the direction horizontal to the main surface of the substrate 1 can be adjusted by the thickness of the insulating film that is anisotropically etched.

Subsequently, the main surface of the substrate 1 on both sides of the laminated film including the bottom oxide film 7A, the charge storage layer 8A, the top oxide film 9A, and the gate electrode 10A having the side wall spacers 14 formed on the side walls is 1 × 10 ²⁰ / Impurities (for example, arsenic) having an n-type conductivity of about cm ³ are introduced. Next, the introduced impurity is activated by performing heat treatment on the substrate 1 at about 800 ° C. to 900 ° C., and the n ⁺ type semiconductor region 15 is formed. Thereby, an n ⁻ type extension region 13 and an n ⁺ type LDD (Lightly-Doped-Drain) structure source region and drain region composed of an n ⁺ type semiconductor region 15 can be formed.

Next, the silicide process will be described. On the main surface of the substrate 1, for example, a cobalt film is formed as a metal film. At this time, the cobalt film is in contact with the exposed gate electrode 10 ^</ b ^{> A} and the exposed n ⁺ -type semiconductor region 15. Thereafter, a heat treatment is performed on the substrate 1 to form a cobalt silicide film 16 in the gate electrode 10 < ^/ b> A and the n ⁺ type semiconductor region 15. As a result, the gate electrode 10A has a laminated structure of the polycrystalline silicon film and the cobalt silicide film. The cobalt silicide film 16 is formed to reduce the resistance of the gate electrode 10A. Similarly, by the above-described heat treatment, the silicon silicide film 16 reacts with the surface of the n ⁺ type semiconductor region 15 to form the cobalt silicide film 16. For this reason, the resistance can be reduced also in the n ⁺ type semiconductor region 15. In the first embodiment, the cobalt silicide film 16 is formed. However, for example, a nickel silicide film, a titanium silicide film, or a platinum silicide film is formed instead of the cobalt silicide film 16. Also good.

  Through the steps so far, the memory cell of the nonvolatile memory of this embodiment can be formed.

Next, as shown in FIG. 7, a silicon nitride film 17 and a silicon oxide film 18 are sequentially deposited on the main surface of the substrate 1 by a CVD method. The silicon nitride film 17 has a protective function for preventing a problem that hydrogen, heavy metal, and the like enter from the outside to each device including the memory cell of the nonvolatile memory according to the present embodiment. When a contact hole reaching the cobalt silicide film 16 formed on the n ⁺ type semiconductor region 15 is formed in the silicon oxide film 18 and the silicon nitride film 17, etching for SAC (Self-Align-Contact) is performed. Functions as a stopper film.

Next, as shown in FIG. 8, the silicon oxide film 18 and the silicon nitride film 17 are dry-etched using a photoresist film (not shown) patterned by the photolithography technique as a mask, so that the n ⁺ type semiconductor region 15 Contact holes reaching the cobalt silicide film 16 formed above and the cobalt silicide film 16 formed on the gate electrode 10A are formed. Next, after forming a barrier metal film (a titanium nitride film, a titanium film, or a laminated film thereof) on the silicon oxide film 18 including the inside of the contact hole, a tungsten film is further deposited, and the contact hole is made of the tungsten film. Embed. Thereafter, the barrier metal film and the tungsten film on the silicon oxide film 18 other than the contact holes are removed by, for example, the CMP method, and the plug 19 is formed.

  Next, the wiring 20 connected to the plug 19 is formed, and the semiconductor integrated circuit device of this embodiment is manufactured. In order to form the wiring 20, for example, a titanium film, an aluminum alloy film serving as a main conductive layer, and a titanium nitride film are sequentially deposited on the silicon oxide film 18 by a sputtering method, and then by dry etching using a photoresist film as a mask. The titanium film, aluminum alloy film and titanium nitride film are patterned.

  Thereafter, the wiring layer may be formed in multiple layers by repeating the process of forming the silicon oxide film 18, the plug 19 and the wiring 20.

  Note that the nonvolatile memory of this embodiment forms a NOR type memory circuit. By using a NOR type memory circuit, the data rewrite unit is small, but it is effective in a field such as an IC card that can exchange data at high speed.

  Next, the operation of the nonvolatile memory cell will be described with reference to the drawings. The voltage shown below is an example of application conditions, and is not limited to this, and can be variously changed as necessary. In the present embodiment, the injection of electrons into the charge storage layer 8A is defined as “writing”, and the injection of holes is defined as “erasing”.

FIG. 9 is a diagram showing voltage conditions applied during a write operation in the memory cell of the present embodiment. As shown in FIG. 9, a negative voltage of about -12V to -13V is applied to the p-type well 5 and 0V to the gate electrode 10A. Then, 0 V is applied to the source region and the drain region (n ⁺ type semiconductor region 15 and n ⁻ type extension region 13). In this memory cell, a tunnel current is generated by a potential difference between the gate electrode 10A (-12V to -13V), the source region (0V), the drain region (0V) and the p-type well 5 (0V), and the gate electrode 10A Then, electrons 21 are injected into the charge storage layer 8A. That is, electrons are injected from the gate electrode 10A to the charge storage layer 8A using the FN tunnel phenomenon. The injected electrons 21 are trapped in the trap level of the charge storage layer 8A. As a result, the electrons 21 are stored in the charge storage layer 8A, and the threshold value of the memory cell is increased as shown in FIG. Information is written into the memory cell.

  FIG. 10 is a circuit diagram showing a selected memory cell and a non-selected memory cell during a write operation. In this case, the case where the target of writing is the selected memory cell MC1 is illustrated. A negative voltage of about −12V to −13V is applied to the gate electrode 10A through the selected word line WL1. At this time, 0 V is applied to the selected bit line BL1. Of the memory cells connected to the selected bit line BL1, 0 V is applied to the unselected word line WL2. The unselected bit line BL2 is applied with a potential of -12V to -13V equivalent to that of the selected word line WL1.

  At this time, in the non-selected memory cell MC2, since the potential of the selected word line WL1 and the potential of the non-selected bit line BL2 are equal, electrons are not injected into the charge storage layer 8A.

  However, in the non-selected memory cell MC3, the potential of the non-selected bit line BL2 is large, and a large electric field is generated on the bottom oxide film 7A side, so that electrons may be accidentally injected into the charge storage layer 8A. In the present embodiment, the bottom oxide film 7A is made thicker than the top oxide film 9A, so that the electric field is relaxed even at the same potential as the bottom oxide film 7A. For this reason, it is possible to solve the problem that electrons are erroneously injected into the charge storage layer 8A. That is, disturbance in the non-selected bit line BL2 can be prevented.

Next, the erase operation will be described. FIG. 12 is a diagram showing voltage conditions applied during the erase operation in the memory cell of the present embodiment. As shown in FIG. 12, 0V is applied to the p-type well 5, and a positive voltage of about + 12V to + 13V is applied to the gate electrode 10A. Then, 0 V is applied to the source region and the drain region (n ⁺ type semiconductor region 15 and n ⁻ type extension region 13). In this memory cell, a tunnel current is generated due to a potential difference between the gate electrode 10A (+ 12V to + 13V), the source region (0V), the drain region (0V) and the p-type well 5 (0V), and a charge is generated from the gate electrode 10A. Holes 22 are injected into the storage layer 8A. That is, holes are injected from the gate electrode 10A into the charge storage layer 8A using the FN tunnel phenomenon. The injected holes 22 are captured by the trap level of the charge storage layer 8A, and the threshold value of the memory cell is lowered as shown in FIG. In this way, the erase operation is performed.

  FIG. 13 is a circuit diagram showing the selected memory cell MC4 during the erase operation. In the erasing operation, a positive voltage of about +12 V to +13 V is applied to each gate electrode 10A electrically connected to the selected word line WL1, and batch erasing is performed. At this time, a positive voltage of about + 12V to + 13V is applied to a non-selected well (not shown), thereby relaxing the electric field.

  Next, the reading operation will be described. FIG. 15 is a diagram showing voltage conditions applied during a read operation in the memory cell of the present embodiment. As shown in FIG. 15, -2V is applied to the p-type well 5, + 1.5V is applied to the gate electrode 10A, and + 0.8V is applied to the drain region. Further, 0 V is applied to the source region. At this time, when the memory cell is in a write state and the threshold voltage is high, no current flows through the memory cell. On the other hand, when the memory cell is in the erased state and the threshold voltage is low, a current flows through the memory cell. As described above, whether the memory cell is in a writing state or an erasing state can be determined by detecting the presence or absence of a current flowing through the memory cell.

  FIG. 16 is a circuit diagram showing the selected memory cell MC5 during the read operation. As described above, except for the selected memory cell MC5, the operating voltage is such that no current flows between the source and the drain, and only the selected memory cell MC5 can be read.

  As described above, in the write operation and erase operation of the memory cell in the present embodiment, charges are exchanged by the tunnel current between the gate electrode 10A and the charge storage layer 8A. Therefore, as shown in FIG. 17, when the number of operations for rewriting memory cell data increases, an interface state 23 is formed at the interface between the gate electrode 10A and the top oxide film 9A. “X” in FIG. 17 indicates an interface state. On the other hand, for example, in the technique described in the background art (Patent Document 5), charge exchange in the write operation and the erase operation is performed by a tunnel current between the semiconductor substrate and the charge storage layer. Therefore, as shown in FIG. 18, when the number of operations for rewriting memory cell data increases, an interface state 23 is formed at the interface between the semiconductor substrate and the lower oxide film.

  Here, the relationship between the gate voltage and the read current in the erased state accompanying the increase in the number of data rewrites shown in FIGS. 19 and 20 will be compared. FIG. 19 shows a case where the rewriting operation according to the present embodiment is performed, and FIG. 20 shows a case where the rewriting operation described in the background art is performed. As shown in FIG. 19, in the memory cell in the present embodiment, an interface state is formed at the interface between the gate electrode 10A and the top oxide film 9A. Does not affect. On the other hand, as shown in FIG. 20, when charges are exchanged in writing and erasing operations by a tunnel current between the semiconductor substrate and the charge storage layer, if the number of rewrites increases, the semiconductor substrate and the underlying oxide film are exchanged. Since interface states are formed at the interface, there is a concern that the read current is reduced and a retention failure occurs.

  Therefore, in order to reduce the probability of occurrence of the above defects and improve the operation reliability even when the number of data rewrites is increased, writing in which no interface state is formed at the interface between the semiconductor substrate and the lower oxide film And an erase operation is required. In the data writing and erasing operations of the memory cell in the present embodiment, charges are exchanged by a tunnel current between the gate electrode 10A and the charge storage layer 8A. By performing such write and erase operations, it is possible to avoid the formation of interface states at the interface between the semiconductor substrate and the lower oxide film.

  In this embodiment, in order to perform writing and erasing operations by the tunnel current between the gate electrode 10A and the charge storage layer 8A, the silicon oxide film 7 to be the bottom oxide film 7A and the silicon oxide to be the top oxide film 9A The film 9 is formed with a film thickness as in the process shown in FIG. Specifically, the bottom oxide film 7A is formed so that the thickness (about 5 nm to 9 nm, preferably about 7 nm or more) is larger than the top oxide film 9A (about 2 nm or less). By increasing the thickness of the bottom oxide film 7A, the charge 21 escapes from the charge storage layer 8A to the bottom oxide film 7A side (channel region 6 side) and the charge from the bottom oxide film 7A side (channel region 6 side). The injection of the charge 21 into the storage layer 8A can be suppressed. Further, by forming the top oxide film 9A as thin as about 2 nm or less, charges can be exchanged by the tunnel current between the gate electrode 10A and the charge storage layer 8A.

  Further, since the top oxide film 9A has a single layer structure, the physical thickness of the top oxide film 9A and the equivalent oxide thickness can be reduced. Thereby, the voltage (gate voltage) used for the write operation and the erase operation can be set low. As a result, the area of the booster circuit can be reduced, and the reliability of peripheral devices can be guaranteed.

  The memory cell of the nonvolatile memory according to this embodiment has an n-channel configuration. Hereinafter, advantages obtained when the memory cell of this embodiment is an n-channel type will be described with reference to FIGS.

  21 and 22 are energy band diagrams in a low electric field (thermal equilibrium state) and data erasing operation in an n-channel memory cell, respectively. FIGS. 23, 24, and 25 are p-channel memory, respectively. It is an energy band figure under the low electric field (thermal equilibrium state) and the data erasing operation in the cell. The numerical values in the figure are the band gap width and work function difference of each material, “−” indicates a charge trap site, and “h” indicates a hole. Comparing the n-channel memory cell and the p-channel memory cell, as shown in FIGS. 21 and 23, in a silicon nitride film in the p-channel memory cell under a low electric field (thermal equilibrium state). There is an advantage that the position where the hole is trapped becomes deeper than that of the n-channel type memory cell, and the hole is difficult to escape to the gate electrode side. However, on the other hand, as shown in FIGS. 22 and 24, in the data erasing operation, the n-channel memory cell has an energy band configuration close to direct tunneling in which holes do not pass through the silicon nitride film, and the erasing operation has a high speed. However, since the p-channel memory cell has an energy band structure in which holes pass through the silicon nitride film, the speed of the erase operation cannot be increased as in the n-channel memory cell. However, as shown in FIG. 25, even in a p-channel type memory cell, if the gate voltage at the time of erasing operation is increased, the energy band configuration at the time of erasing operation of the n-channel type memory cell becomes close. However, in that case, it is necessary to make the peripheral circuit have a high breakdown voltage structure, and there is a concern that a problem of increasing the area in which the circuit is formed may occur. That is, it is preferable to use an n-channel nonvolatile memory cell as in this embodiment.

  In the memory cell according to the present embodiment, a film formed between the charge storage layer 8A and the gate electrode 10A and through which a tunnel current flows during writing and erasing operations is a single layer of silicon oxide as the top oxide film 9A. Since it is formed, the writing and erasing speed can be increased as compared with the case where it is formed by lamination.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The configuration of the semiconductor integrated circuit device of the present invention can be applied to a semiconductor device having a nonvolatile memory.

1 substrate 2 element isolation trench 3 silicon oxide film 4 n-type isolation region 5 p-type well 6 channel region 7 silicon oxide film 7A bottom oxide film (first insulating layer)
8 Silicon nitride film 8A Charge storage layer 9 Silicon oxide film 9A Top oxide film (second insulating layer)
DESCRIPTION OF SYMBOLS 10 Polycrystalline silicon film 10A Gate electrode 11 Silicon oxide film 12 Protective film 13 n ⁻ type extension region 14 Side wall spacer 15 n ⁺ type semiconductor region 16 Cobalt silicide film 17 Silicon nitride film 18 Silicon oxide film 19 Plug 20 Wiring 21 Electron 22 Hole 23 Interface states BL1, BL2 Bit lines MC1, MC2, MC3, MC4, MC5 Memory cells WL1, WL2 Word line

Claims (8)

A semiconductor integrated circuit device having a memory cell, wherein the memory cell is
A semiconductor substrate;
An n-type source region and an n-type drain region formed in the semiconductor substrate;
A first insulating layer formed on a main surface of the semiconductor substrate;
An insulating charge storage layer formed on the first insulating layer;
A second insulating layer formed on the charge storage layer;
A gate electrode formed on the second insulating layer;
Have
The second insulating layer is formed of a single layer;
The second insulating layer is thinner than the first insulating layer,
2. The semiconductor integrated circuit device according to claim 1, wherein the memory cell performs data writing and erasing by injecting charges from the gate electrode to the charge storage layer through the second insulating layer. The semiconductor integrated circuit device according to claim 1.
The semiconductor integrated circuit device, wherein the charge storage layer is formed of a film containing silicon nitride as a main component. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device, wherein the charge storage layer is formed of silicon-rich silicon nitride. The semiconductor integrated circuit device according to claim 2.
The semiconductor integrated circuit device, wherein the first insulating layer and the second insulating layer are formed of a silicon oxide film. The semiconductor integrated circuit device according to claim 4.
The thickness of the first insulating layer is 5 nm to 9 nm,
The charge storage layer has a thickness of 14 nm to 20 nm,
The semiconductor integrated circuit device, wherein the second insulating layer has a thickness of 2 nm or less. The semiconductor integrated circuit device according to claim 1.
A semiconductor integrated circuit device, wherein the memory cell forms a NOR type memory circuit. The semiconductor integrated circuit device according to claim 1.
The data writing and erasing are performed by using an FN tunnel phenomenon. The semiconductor integrated circuit device according to claim 1.
A plurality of the memory cells;
The plurality of memory cells include a first memory cell connected to a selected word line and a selected bit line during the data write operation, and a first memory cell connected to a non-selected word line and a non-selected bit line during the data write operation. 2 memory cells,
In the data write operation, the potential of the selected word line and the potential of the non-selected bit line are the same, and the potential of the non-selected word line and the potential of the selected bit line are the same Integrated circuit device.

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