JP2011014851A - Semiconductor element, and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the semiconductor device that can reduce the on-resistance of the semiconductor device and reduce the total number of manufacturing steps.
In ion implantation for forming a source / drain region, in a low breakdown voltage lateral trench MOSFET, an opening for drain formation is separated from a trench sidewall, and an opening for source formation reaches the trench sidewall. In the power MOSFET, a mask having a pattern in which the opening for forming the source is separated from the side wall of the trench and the opening for forming the drain reaches the side wall of the trench is used. Using this mask, ion implantation performed at a high dose amount and a low acceleration voltage and ion implantation performed at a low dose amount and a high acceleration voltage are continuously performed, so that the LDD region of the low breakdown voltage lateral trench MOSFET and the trench lateral type can be obtained. The LDD region of the power MOSFET is formed at the same time.
[Selection] Figure 9

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art In recent years, in the IC field centered on power supply ICs (Integrated Circuits), development for reducing the size of semiconductor elements (shrinking), reducing costs, and increasing the efficiency of circuits on which semiconductor elements are mounted has been progressing. For example, as a technique for reducing the on-resistance (RonA) of a semiconductor element used in the output stage, a trench gate structure is provided, and the channel length is extended from the trench side wall to the length along the bottom surface, whereby the on-resistance per unit area is increased. 2. Description of the Related Art A lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the above is reduced is known (for example, see Non-Patent Document 1 below).

  For example, in a lateral MOSFET having a trench gate structure (hereinafter referred to as a low breakdown voltage lateral trench MOSFET), channel resistance, which is one of on-resistance components, is a major factor that increases on-resistance. For this reason, a technique that focuses on reducing channel resistance has been proposed.

  In general, in a miniaturization process with a design rule of 0.6 μm or less, a low breakdown voltage lateral trench MOSFET has an LDD (Lightly Doped Drain) structure that reduces the electric field in the vicinity of the drain region in order to improve hot carrier resistance. Yes. For example, a low breakdown voltage lateral trench MOSFET having an LDD structure is a low concentration region (LDD region) having the same conductivity type as a source region and a drain region between a source region and a channel region and between a drain region and a channel region. Are provided.

FIG. 13 is a cross-sectional view showing a lateral MOSFET having a conventional trench gate structure. In the low breakdown voltage lateral trench MOSFET shown in FIG. 13, a p well region 202 is provided in the surface layer of the p ⁻ semiconductor substrate 201. A trench 203 is provided in a part of the p well region 202 so as not to penetrate the p well region 202. A gate electrode 204 is provided inside the trench 203 through a gate insulating film 212. A part of the surface layer of the p-well region 202 is provided with a source region 205 and a drain region 206 that are deeper than the trench 203 and in contact with a part of the side wall of the trench 203 with the trench 203 interposed therebetween.

  A high concentration source region 207 is provided on the surface layer of the source region 205. The high concentration source region 207 has a higher impurity concentration than the source region 205. A high concentration drain region 208 is provided in the surface layer of the drain region 206. The high concentration drain region 208 has a higher impurity concentration than the drain region 206. The source electrode 209 is in contact with the high concentration source region 207. The drain electrode 210 is in contact with the high concentration drain region 208. The low breakdown voltage lateral trench MOSFET is separated from an adjacent semiconductor element (not shown) by a local insulating film 211 such as LOCOS (Local Oxidation of Silicon). In such a low breakdown voltage lateral trench MOSFET, the source region 205 and the drain region 206 are configured as LDD regions.

  Further, as another semiconductor element having an LDD structure, the following apparatus has been proposed. A pore or a narrow groove is provided in the main surface portion of the first semiconductor region of the first conductivity type, and the first conductive region is electrically conductive through an insulating film on the main surface of the first semiconductor region along the pore or narrow groove. A second semiconductor region of a second conductivity type is provided on the main surface portion of the first semiconductor region on both sides of the conductive layer, and the second semiconductor region is provided on both sides of the conductive layer below the second semiconductor region. The main surface portion of the first semiconductor region is a region having the same conductivity type as that of the second semiconductor region and having an impurity concentration lower than that of the second semiconductor region, and is in the second semiconductor region and the first semiconductor region. The third semiconductor region electrically connected to the region where the channel is formed in FIG. 4 constitutes an insulated gate field effect transistor. The second semiconductor region and the third semiconductor region are used as a source region or a drain region, and the conductive layer is used as a gate electrode (see, for example, Patent Document 1 below).

  As another device, the following device has been proposed. A side wall is provided on the side wall of the groove formed in the semiconductor substrate, and a gate electrode is provided in the bottom of the groove exposed from the side wall, and a gate electrode is embedded in the groove. The surface layer of the semiconductor substrate is provided with a source / drain disposed opposite to the gate electrode through the sidewall, and further, between the source / drain and the channel formation portion below the gate insulating film, the sidewall is provided. A low concentration diffusion layer formed by impurity diffusion from the semiconductor substrate to the semiconductor substrate is provided (for example, see Patent Document 2 below).

  In addition, as a method of manufacturing a semiconductor element having an LDD structure, a step of forming a groove in the element region of the first conductivity type semiconductor substrate, a step of implanting an impurity for threshold control at the bottom of the groove, A step of depositing a conductive film, a step of leaving a conductive film only in the trench, and forming a gate electrode, and ion-implanting and activating a second conductivity type impurity over the entire surface to extend the impurity profile to the bottom of the trench. A method including a step of forming source and drain regions has been proposed (see, for example, Patent Document 3 below).

JP-A-61-125084 JP 2005-019584 A Japanese Patent Laid-Open No. 61-042958

M. Zitouni, 1 other, A New Concept for Lateral DMOS Transistor for Smart Power IC's (A New Concept for the Lateral DMOS Transistor for Smart Power IC's, Onc Power Semiconductor Device and IC's 1999 (International Symposium on Power Semiconductor Devices & IC's 1999: ISPSD 1999), May 26-28, 1999, p. 73-76

  However, in the low breakdown voltage lateral trench MOSFET as described above, a process for forming a trench gate structure or an LDD structure is required. Further, in the miniaturization process, the following steps are also required. When the semiconductor element is miniaturized, the distance from the contact formation portion to the active region or the distance from the contact formation portion to the LOCOS insulating film is shortened. For example, when the contact of the drain electrode 210 (see FIG. 13) is formed, if the etching for forming the contact penetrates the drain region 206, the portion or the drain region 206 under the local insulating film 211 is formed. There is a possibility that the drain electrode 210 is short-circuited to the p-well region 202 at a portion that is not formed. Therefore, a step of forming a diffusion layer (hereinafter referred to as a plug layer) for preventing a short circuit in the contact formation is performed. Therefore, the number of processes increases in the production of the low breakdown voltage lateral trench MOSFET.

  On the other hand, in a lateral power MOSFET having a trench gate structure proposed by the inventors (hereinafter referred to as a trench lateral power MOSFET), a technique for reducing on-resistance has been developed separately from the above-described low breakdown voltage lateral trench MOSFET. ing. For example, the on-resistance is reduced by reducing the channel resistance and the drain resistance. For example, in order to reduce the drain resistance, in the trench lateral power MOSFET, a drain region is provided so as to occupy a part of the bottom of the trench and to be in contact with the trench sidewall. The trench lateral power MOSFET is assumed to have a breakdown voltage of 15 to 30 V, for example. In such a trench lateral power MOSFET, the on-resistance is greatly reduced as compared with a planar high-breakdown-voltage vertical MOSFET (DMOS: Double Diffused MOSFET). However, since the number of steps for forming the trench gate structure increases, the number of steps increases.

  Therefore, it was examined whether or not the number of processes could be reduced by simultaneously fabricating a low breakdown voltage lateral trench MOSFET and a trench lateral power MOSFET on the same substrate. For example, it can be estimated that the number of processes is reduced by simultaneously forming the LDD region of the low breakdown voltage lateral trench MOSFET and the source region and drain region of the trench lateral power MOSFET. However, in that case, it has been found that there are the following problems.

  In the technique of Patent Document 1 described above, the LDD region of the low breakdown voltage lateral trench MOSFET is formed so as to be in contact with the entire surface of the trench side wall by a plurality of ion implantations with different ion implantation conditions. Therefore, when forming the LDD region of the low breakdown voltage lateral trench MOSFET and the drain region of the trench lateral power MOSFET simultaneously, for example, if ion implantation is performed according to the configuration of the trench lateral power MOSFET, the LDD region of the low breakdown voltage lateral trench MOSFET is It will be formed to occupy the bottom of the trench. In that case, in the low breakdown voltage lateral trench MOSFET, a short channel effect and punch-through occur, and it becomes impossible to reduce the on-resistance. On the other hand, if ion implantation is performed in accordance with the configuration of the low breakdown voltage lateral trench MOSFET, the trench lateral power MOSFET has a drain region formed shallower than the bottom surface of the trench, so that the on-resistance cannot be reduced.

  Further, when the drain region of the low breakdown voltage lateral trench MOSFET is formed so as to occupy the bottom surface of the trench, the distance between the drain region contacting the gate electrode through the gate insulating film increases, and thus the gate-drain capacitance ( The feedback capacity increases. In this case, the gate-drain capacitance of the semiconductor element (hereinafter referred to as the gate-drain capacitance independent of the size of the semiconductor element is referred to as the product of on-resistance and gate charge (RonQg)) increases, and delay and switching loss There is a risk of causing.

  An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance in order to eliminate the above-described problems caused by the prior art. It is another object of the present invention to provide a semiconductor element that can reduce the product of on-resistance and gate charge. It is another object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the number of manufacturing steps as a whole.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to claim 1 includes a well region provided in a surface layer of a semiconductor substrate and a well region provided in the well region. The shallow first trench and the surface layer of the well region are provided deeper than the first trench so as to be in contact with one side wall of the first trench and occupy the corner portion of the bottom surface of the first trench. A first source region; a first drain region provided deeper than the first trench in contact with a part of the other side wall of the first trench on a surface layer of the well region; and the first source region A first high concentration source region having an impurity concentration higher than that of the first source region and a surface layer of the first drain region provided apart from a sidewall of the first trench. A first high-concentration drain region having an impurity concentration higher than that of the first drain region; and a first gate electrode provided in the first trench through a first gate insulating film. And

The semiconductor device according to the invention of claim 2 is the invention according to claim 1, in the depth direction of the well region, the first distance X _s of the first source region and the first trench is in contact Is the depth D _t1 of the first trench, the width L _t1 of the bottom surface of the first trench, and the second distance X _n1 where the first high-concentration source region and the first trench are in contact with each other. _s <D _t1 + L _t1 −X _n1 is satisfied.

According to a third aspect of the present invention, there is provided the semiconductor element according to the first or second aspect, wherein the first drain region and the first trench are in contact with each other in the depth direction of the well region. X _d is the depth of the first trench D _t1, when the first drain region is said depth from the surface of the well region to a surface of the first gate electrode D _p1 before provided, D _p1 < X _d <D _t1 is satisfied.

  According to a fourth aspect of the present invention, there is provided a semiconductor element including a well region provided in a surface layer of a semiconductor substrate, a second trench provided in the well region and shallower than the well region, and a surface of the well region. A second source region provided in contact with a part of one side wall of the second trench and deeper than the second trench; and a surface layer of the well region on the other side wall of the second trench. A second drain region deeper than the second trench so as to occupy a corner portion of the bottom surface of the second trench, and a surface layer of the well region at the bottom surface of the second trench, A low-concentration semiconductor region provided in contact with the second drain region, having the same conductivity type as the second drain region, and having an impurity concentration lower than that of the second drain region; and A second high concentration source region having an impurity concentration higher than that of the second source region, which is provided apart from a side wall of the second trench, and a surface layer of the second drain region; A second high-concentration drain region having an impurity concentration higher than that of the second drain region, and a second gate insulating film interposed between the second source region and the low-concentration semiconductor region inside the second trench. And a second gate electrode provided as described above.

The semiconductor device according to the invention of claim 5 is the invention according to claim 4, in the depth direction of the well region, the fourth distance X _sp which said second source region and the second trench is in contact Is the depth D _t2 of the second trench and the depth D _p2 from the surface of the well region before the second source region is provided to the surface of the second gate electrode, D _p2 <X _sp <D _t2 is satisfied.

According to a sixth aspect of the present invention, there is provided a semiconductor device according to the fourth or fifth aspect, wherein the second drain region and the second trench are in contact with each other in the depth direction of the well region. X _dp is a depth D _t2 of the second trench, a width L _t2 of the bottom surface of the second trench, and a sixth distance X _{n2 at} which the second high-concentration drain region and the second trench are in contact with each other. And X _dp <D _t2 + (1/2) L _t2 −X _n2 is satisfied.

  According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor element, wherein the first semiconductor element and the second semiconductor element are formed on the same semiconductor substrate, the surface of the semiconductor substrate being formed. A first trench of the first semiconductor element is formed shallower than the well region in a well region of the first conductivity type formed in the layer, and has a width wider than the first trench away from the first trench. A trench forming step of forming a second trench of the second semiconductor element shallower than the well region; a first gate insulating film is formed on the side wall and bottom surface of the first trench; and the side wall and bottom surface of the second trench An insulating film forming step of forming a second gate insulating film on the surface, and after the insulating film forming step, a surface of the well region is embedded so as to be embedded in the first trench and the second trench. Forming a conductive film on the conductive film; and etching the conductive film to form a first gate electrode in the first trench, and a second gate electrode in the second trench. After the first ion implantation step of ion-implanting a second conductivity type impurity into the bottom surface of the second trench using the second gate electrode as a mask, and after the first ion implantation step, After the first trench and the second trench are filled with an insulating film, a first opening that opens to one side wall of the first trench and an opening that does not reach the other side wall of the first trench Forming a mask having a second opening that opens, a third opening that opens so as not to reach one side wall of the second trench, and a fourth opening that opens to the other side wall of the second trench. Mask worker A second ion implantation step of ion-implanting a second conductivity type impurity using the mask formed in the mask step, and a second conductivity type using the mask formed in the mask step. And a third ion implantation step of ion-implanting impurities.

  Here, the first ion implantation step is a step for implanting first ions into the bottom surface of the second trench and forming a low concentration semiconductor region in the surface layer of the well region at the bottom surface of the second trench. Also good.

  In the second ion implantation step, a first source region of the first semiconductor element is formed in a surface layer of the well region exposed to the first opening by second ion implantation, and the second opening is formed in the second opening. A first drain region of the first semiconductor element is formed in a surface layer of the well region exposed, and a second source region of the second semiconductor element is formed in a surface layer of the well region exposed in the third opening. And forming a second drain region of the second semiconductor element having a higher impurity concentration than the low-concentration semiconductor region formed in the first ion implantation step on the surface layer of the well region exposed in the fourth opening. It may be a process for

  In the third ion implantation step, a first high-concentration source having a higher impurity concentration than the first source region is formed in the surface layer of the first source region exposed to the first opening by the third ion implantation. Forming a region, forming a first high-concentration drain region having an impurity concentration higher than that of the first drain region in a surface layer of the first drain region exposed to the second opening, and the third opening Forming a second high-concentration source region having an impurity concentration higher than that of the second source region in a surface layer of the second source region exposed to the second source region, and exposing the surface of the second drain region exposed to the fourth opening; The step may be a step for forming a second high-concentration drain region having an impurity concentration higher than that of the second drain region in the layer.

  According to an eighth aspect of the present invention, in the semiconductor device manufacturing method according to the seventh aspect of the present invention, the second ion implantation is performed at a higher acceleration voltage than the third ion implantation.

  According to a ninth aspect of the present invention, in the semiconductor device manufacturing method according to the seventh or eighth aspect of the invention, the second ion implantation is performed with a dose amount lower than that of the third ion implantation. To do.

  According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the seventh to ninth aspects, wherein the second ion implantation step and the third ion implantation step are performed continuously. It is characterized by performing.

  A method of manufacturing a semiconductor device according to an invention of claim 11 is the invention according to any one of claims 7 to 9, wherein a thermal diffusion process is performed after the second ion implantation process, and then the mask is passed through the mask. The third ion implantation step is continuously performed.

  According to the first to third aspects of the present invention, the channel resistance can be reduced by providing the first source region so as to occupy the corner portion of the bottom surface of the first trench. Thereby, the on-resistance can be reduced. Moreover, the overlap capacitance between the gate and the drain can be reduced by shortening the distance between the first drain region and the first trench. As a result, the gate-drain capacitance can be reduced, and the product of on-resistance and gate charge (RonQg) can be reduced.

  According to the fourth to sixth aspects of the present invention, the drain resistance is reduced by providing the second drain region so as to occupy the corner portion of the bottom surface of the second trench and to be in contact with the low concentration semiconductor region. Can do. Thereby, the on-resistance can be reduced. Moreover, the overlap capacitance between the gate and the source can be reduced by shortening the distance between the second source region and the second trench. As a result, the gate-source capacitance can be reduced, and the product of on-resistance and gate charge can be reduced.

  According to the seventh to eleventh aspects of the invention described above, the LDD region (the first source region and the first drain region) of the first semiconductor element and the LDD region (the second source region and the first source region) of the second semiconductor element. 2 drain regions and the like are formed at the same time, the number of manufacturing steps of the entire semiconductor device can be reduced. Further, the second ion implantation performed at a high dose and a low acceleration voltage and the third ion implantation performed at a low dose and a high acceleration voltage are continuously performed, so that the impurity concentration is increased in the depth direction of the well region. A source region and a drain region can be provided to be low. Further, by subsequent heat treatment, the source region and the drain region can be formed deeper than the trench. Accordingly, the semiconductor element can have an LDD structure, and the on-resistance of the semiconductor element can be reduced. Further, the drain region can function as a plug layer. This eliminates the step of forming the plug layer, thereby further reducing the number of manufacturing steps.

  Further, by performing second ion implantation using the mask formed in the mask process as a mask, the first source region can be formed to occupy the corner portion of the bottom surface of the first trench in the first semiconductor element. . Thereby, the channel resistance of the first semiconductor element can be reduced, and the on-resistance can be reduced. Further, the distance between the first drain region and the first trench can be shortened. As a result, the gate-drain capacitance can be reduced, and the product of on-resistance and gate charge can be reduced. On the other hand, in the second semiconductor element, the second drain region can be formed to occupy the corner portion of the bottom surface of the second trench and to be in contact with the low concentration semiconductor region. Thereby, the drain resistance of the second semiconductor element can be reduced, and the on-resistance can be reduced. Further, the distance between the second source region and the second trench can be shortened. As a result, the gate-source capacitance can be reduced, and the product of on-resistance and gate charge (RonQg) can be reduced.

  According to the semiconductor element and the manufacturing method thereof according to the present invention, there is an effect that the on-resistance of the semiconductor element can be reduced. In addition, the product of on-resistance and gate charge can be reduced. Moreover, there exists an effect that the number of the whole manufacturing processes can be reduced.

1 is a cross-sectional view showing a semiconductor element according to a first embodiment. FIG. 6 is a cross-sectional view showing a semiconductor element according to a second embodiment. It is a top view which shows the mask pattern concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. It is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. FIG. 6 is a characteristic diagram illustrating a relationship between drain current and drain voltage when the semiconductor element according to the first embodiment is on. FIG. 6 is a characteristic diagram illustrating a relationship between drain current and drain voltage when the semiconductor element according to the first embodiment is off. FIG. 6 is a characteristic diagram showing a gate-drain capacitance of the semiconductor element according to the first embodiment; It is sectional drawing which shows the horizontal type MOSFET which has the conventional trench gate structure.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor element shown in FIG. 1 is a lateral MOSFET (low withstand voltage lateral trench MOSFET) having a trench gate structure. As shown in FIG. 1, in a low breakdown voltage lateral trench MOSFET, a p ^- type well region 2 is provided in a surface layer of a p ⁻ -type semiconductor substrate 1. A first trench 3 is provided in a part of the well region 2 so as not to penetrate the well region 2. A first gate electrode 4 is provided inside the first trench 3 via a first gate insulating film 12. A part of the surface layer of the well region 2 is in contact with one side wall of the first trench 3, for example, a corner portion having a curved shape on the bottom surface of the first trench 3 (hereinafter, referred to as a first trench curvature portion 51). N-type first source region 5 is provided so as to occupy. The first source region 5 is deeper than the first trench 3. An n-type first drain region 6 is provided in contact with a part of the other side wall of the first trench 3. The first drain region 6 is deeper than the first trench 3.

On the surface layer of the first source region 5, an n ⁺ -type first high concentration source region 7 is provided. The first high-concentration source region 7 is provided so as not to contact the first gate electrode 4 through the first gate insulating film 12. The first high concentration source region 7 has a higher impurity concentration than the first source region 5. A part of the surface layer of the first drain region 6 is provided with an n ⁺ -type first high-concentration drain region 8 away from the side wall of the first trench 3. The first high concentration drain region 8 has a higher impurity concentration than the first drain region 6.

  The first source electrode 9 is in contact with the first high concentration source region 7. The first drain electrode 10 is in contact with the first high concentration drain region 8. The low breakdown voltage lateral trench MOSFET is separated from an adjacent semiconductor element (not shown) by a local insulating film 11 such as LOCOS.

The first source region 5 is preferably provided so as to satisfy the following expression (1). Equation (1) is a preferable range of the first distance X _s in which the first source region 5 and the first trench 3 are in contact with each other in the depth direction of the well region 2. The depth D _t1 of the first trench 3, the width L _t1 of the bottom surface of the first trench 3, and the second distance X _n1 where the first high-concentration source region 7 and the first trench 3 are in contact with each other.

X _s <D _t1 + L _t1 −X _n1 (1)

(1) The reason for providing the first source region 5 so as to satisfy the formula, if the value of the first distance X _s is greater than the upper limit, because the punch-through occurs between the source and the drain.

The first drain region 6 is preferably provided so as to satisfy the following expression (2). Expression (2) is a preferable range of the third distance X _d in which the first drain region 6 and the first trench 3 are in contact with each other in the depth direction of the well region 2. It is assumed that the depth D _t1 of the first trench 3 is the depth D _p1 from the surface of the well region 2 before the first drain region 6 is provided to the surface of the first gate electrode 4.

D _p1 <X _d <D _t1 (2)

The reason why the first drain region 6 is provided so as to satisfy the expression (2) is as follows. When the value of the third distance _Xd is smaller than the lower limit value, the first drain region 6 does not contact the first gate electrode 4 via the first gate insulating film 12, so that the low breakdown voltage lateral trench MOSFET is It is because it does not become a composition. Further, when the value of the third distance _Xd is larger than the upper limit value, the channel resistance of the low breakdown voltage lateral trench MOSFET cannot be reduced.

  In such a low breakdown voltage lateral trench MOSFET, the channel resistance can be reduced by providing the first source region 5 so as to occupy the first trench curvature portion 51 on the bottom surface of the first trench 3. The reason will be described later. Further, by shortening the distance that the first drain region 6 is in contact with the first gate electrode 4 through the first gate insulating film 12, the overlap capacitance between the gate and the drain can be reduced. Thereby, the gate-drain capacitance (feedback capacitance) can be reduced. The reason will be described later.

  In addition, by providing the first high-concentration source region 7 in the surface layer of the first source region 5, the source region can be provided so that the impurity concentration decreases in the depth direction of the well region 2. Further, by providing the first high-concentration drain region 8 in the surface layer of the first drain region 6, the drain region can be provided so that the impurity concentration decreases in the depth direction of the well region 2. As a result, the low breakdown voltage lateral trench MOSFET can have an LDD structure. Further, by providing the first drain region 6 deeply, the first drain region 6 can function as a diffusion layer (plug layer) for preventing a short circuit in contact formation.

  Further, by providing the first high-concentration drain region 8 away from the side wall of the first trench 3, impurities in the first high-concentration drain region 8 are diffused in the portion where the electric field is concentrated in the low breakdown voltage lateral trench MOSFET. Can be prevented.

  As described above, according to the first embodiment, the channel resistance can be reduced by providing the first source region 5 so as to occupy the first trench curvature portion 51 on the bottom surface of the first trench 3. it can. Thereby, the on-resistance can be reduced. Moreover, the overlap capacitance between the gate and the drain can be reduced by shortening the distance that the first drain region 6 and the first trench 3 are in contact with each other. As a result, the gate-drain capacitance can be reduced, and the product of on-resistance and gate charge (RonQg) can be reduced. A region extending from the bottom surface of the first trench 3 to the side wall of the first trench 3 on the first drain region 6 side can be a channel region. Therefore, even if the first trench 3 is formed shallow and the trench width is narrowed, the low breakdown voltage lateral trench MOSFET can have a structure capable of suppressing the short channel effect and punch-through.

(Embodiment 2)
FIG. 2 is a cross-sectional view of the semiconductor element according to the second embodiment. The semiconductor element shown in FIG. 2 is a lateral power MOSFET (trench lateral power MOSFET) having a trench gate structure. As shown in FIG. 2, in the trench lateral power MOSFET, a second trench 21 is provided in a part of the well region 2 so as not to penetrate the well region 2. The second trench 21 has a width wider than that of the first trench of the low breakdown voltage lateral trench MOSFET of the first embodiment, for example. An n-type second source region 24 is provided in a part of the surface layer of the well region 2 in contact with a part of one side wall of the second trench 21. The second source region 24 is deeper than the second trench 21. In addition, the n-type second so as to be in contact with the other side wall of the second trench 21 and occupy, for example, a corner portion having a curved shape (hereinafter, referred to as a second trench curvature portion 52) on the bottom surface of the second trench 21. A drain region 25 is provided. The second drain region 25 is deeper than the second trench 21.

On the bottom surface of the second trench 21, an n ⁻ low concentration semiconductor region 23 is provided in the surface layer of the well region 2 so as to be in contact with the second drain region 25. The n ⁻ low concentration semiconductor region 23 has the same conductivity type as the second drain region 25. The n ⁻ low concentration semiconductor region 23 has a lower impurity concentration than the second drain region 25. A part of the surface layer of the second source region 24 is provided with an n ⁺ -type second high-concentration source region 26 apart from the side wall of the second trench 21. The second high concentration source region 26 has a higher impurity concentration than the second source region 24. In the surface layer of the second drain region 25, an n ⁺ -type second high concentration drain region 27 is provided. The second high concentration drain region 27 has a higher impurity concentration than the second drain region 25.

The second gate electrode 22 is provided in the second trench 21 so as to extend from the second source region 24 to the n ⁻ low concentration semiconductor region 23 with the second gate insulating film 30 interposed therebetween. The second source electrode 28 is in contact with the second high concentration source region 26. The second drain electrode 29 is in contact with the second high concentration drain region 27. Further, the second drain electrode 29 is short-circuited with an electrode provided on the side wall of the second trench 21 on the second drain region 25 side through the second gate insulating film 30. Other configurations are the same as those of the low breakdown voltage lateral trench MOSFET of the first embodiment.

The second source region 24 is preferably provided so as to satisfy the following expression (3). Expression (3) is a preferable range of the fourth distance _Xsp where the second source region 24 and the second trench 21 are in contact with each other in the depth direction of the well region 2. It is assumed that the depth D _t2 of the second trench 21 is the depth D _p2 from the surface of the well region 2 before the second source region 24 is provided to the surface of the second gate electrode 22.

D _p2 <X _sp <D _t2 (3)

The reason why the second source region 24 is provided so as to satisfy the expression (3) is as follows. When the value of the fourth distance _Xsp is smaller than the lower limit value, the second source region 24 does not contact the second gate electrode 22 through the second gate insulating film 30, so that the trench lateral power MOSFET is configured as a MOSFET. It is because it does not become. Further, when the value of the fourth distance X _sp is larger than the upper limit value, the second source region 24 is short-circuited to the second drain electrode 29 through the n ⁻ low concentration semiconductor region 23.

The second drain region 25 is preferably provided so as to satisfy the following expression (4). Expression (4) is a preferable range of the fifth distance X _dp where the second drain region 25 and the second trench 21 are in contact with each other in the depth direction of the well region 2. The depth D _t2 of the second trench 21, the width L _t2 of the bottom surface of the second trench 21, and the sixth distance X _{n2 at} which the second high concentration drain region 27 and the second trench 21 are in contact with each other.

X _dp <D _t2 + (1/2) L _t2 −X _n2 (4)

The reason why the second drain region 25 is provided so as to satisfy the expression (4) is as follows. Value larger than the value is an upper limit value of the fifth distance X _dp, in order to increase the breakdown voltage between the source and drain for example, n ^- to form a second drain region 25 so as to cover the whole of the low concentration semiconductor region 23 As a result, the n ⁻ low-concentration semiconductor region 23 becomes the potential of the second drain region 25, and the well region 2 becomes difficult to be depleted. Therefore, it is necessary to maintain the potential near the bottom surface of the second drain region 25 at the potential of the n ⁻ low concentration semiconductor region 23.

  In such a trench lateral power MOSFET, the well region 2 near the bottom surface of the second source region 24 functions as a channel region. Further, by shortening the distance that the second source region 24 is in contact with the second gate electrode 22 through the second gate insulating film 30, the overlap capacitance between the gate and the drain can be reduced. Thereby, the gate-drain capacitance can be reduced.

  Further, by providing the second high-concentration source region 26 in the surface layer of the second source region 24, the source region can be provided so that the impurity concentration decreases in the depth direction of the well region 2. Further, by providing the second high-concentration drain region 27 in the surface layer of the second drain region 25, the drain region can be provided so that the impurity concentration decreases in the depth direction of the well region 2. As a result, the trench lateral power MOSFET can have an LDD structure. Further, by providing the second drain region 25 deeply, the second drain region 25 can function as a plug layer.

As described above, according to the second embodiment, the second drain region 25 is provided so as to occupy the second trench curvature portion 52 on the bottom surface of the second trench 21 and to be in contact with the n ⁻ low concentration semiconductor region 23. As a result, the drain resistance can be reduced. Thereby, the on-resistance can be reduced. Further, by shortening the distance between the second source region 24 and the second trench 21 in contact, the gate-source overlap capacitance can be reduced. As a result, the gate-source capacitance can be reduced, and the product of on-resistance and gate charge can be reduced.

(Embodiment 3)
FIG. 3 is a plan view showing a mask pattern according to the present invention. FIG. 3 shows a mask pattern at the time of ion implantation when forming the source region and the drain region of the low breakdown voltage lateral trench MOSFET according to the first embodiment. As shown in FIG. 3, for example, a third trench 33 is provided in the semiconductor region 34. The first mask opening 31 in the drain region is formed away from the third trench 33. For example, the first interval A between the first mask opening 31 and the third trench 33 is formed, for example, at a distance of about 0.10 to 0.2 μm. This is because the drain region is formed by ion implantation with a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² when the angle (taper angle) formed between the bottom surface and the side surface of the third trench 33 is 86 to 89 degrees. When formed, this is an approximate range for obtaining the desired third distance _Xd . That is, the range of the first interval A varies depending on the dose amount and acceleration voltage of ion implantation for forming the drain region, the heat treatment after ion implantation, the aspect ratio of the third trench 33, and the taper angle of the third trench 33. Also good. The second mask opening 32 in the source region is formed in contact with the third trench 33. That is, the second interval B between the second mask opening 32 and the third trench 33 is zero. With such a mask pattern, the first source region, the first drain region, the first high concentration source region, and the first high concentration drain region of the low breakdown voltage lateral trench MOSFET according to the first embodiment are formed.

  In the mask pattern for forming the source region and the drain region of the trench lateral power MOSFET according to the second embodiment, the first mask opening 31 in the drain region is formed in contact with the third trench 33. . The second mask opening 32 in the source region is formed away from the third trench 33. That is, the mask pattern shown in FIG. 3 is a mask pattern in which the first interval A and the second interval B are reversed.

  4-9 is sectional drawing which shows the manufacturing method of the semiconductor element concerning this invention. A process of forming the low breakdown voltage lateral trench MOSFET according to the first embodiment and the trench lateral power MOSFET according to the second embodiment on the same semiconductor substrate 1 will be described. The low breakdown voltage lateral trench MOSFET corresponds to the first semiconductor element. The trench lateral power MOSFET corresponds to a second semiconductor element.

  First, as shown in FIG. 4, an impurity such as boron (B) is ion-implanted into the surface layer of the semiconductor substrate 1 from the mask oxide film (not shown) formed on the surface of the semiconductor substrate 1. Next, heat treatment is performed to diffuse impurities implanted in the surface layer of the semiconductor substrate 1, thereby forming the well region 2 on the surface of the semiconductor substrate 1. In the semiconductor substrate 1 thus formed, a region for forming a low breakdown voltage lateral trench MOSFET (hereinafter referred to as a first semiconductor element forming region) 100 and a region for forming a trench lateral power MOSFET (hereinafter referred to as a second semiconductor). 110 as an element formation region).

Next, the first trench 3 is formed in the first semiconductor element formation region 100 by photolithography. In addition, the second trench 21 is formed in the second semiconductor element formation region 110. The width L _t2 of the bottom surface of the second trench 21 is preferably formed wider than the width L _t1 of the bottom surface of the first trench 3 (L _t1 <L _t2 ). The reason will be described later. The depth D _t1 and the bottom width L _t1 of the first trench 3 may be, for example, 0.7 μm and 0.5 μm, respectively. For example, the depth D _t2 and the bottom width L _t2 of the second trench 21 may be 0.7 μm and 1.0 μm, respectively.

  Next, a first resist pattern (not shown) that covers the first semiconductor element formation region 100 and the second semiconductor element formation region 110 is formed by photolithography. Next, using the first resist pattern as a mask, the surface of the well region 2 is locally thermally oxidized (LOCOS) to form a local insulating film 11. Thereby, the low breakdown voltage lateral trench MOSFET and the trench lateral power MOSFET are separated by the local insulating film 11. Next, the mask of the first resist pattern is removed, and an oxide film 40 is formed on the surface of the well region 2. At this time, the oxide film 40 is also formed on the sidewalls and bottom surfaces of the first trench 3 and the second trench 21. The oxide film 40 formed on the side wall and the bottom surface of the first trench 3 is the first gate insulating film 12. The oxide film 40 formed on the side wall and the bottom surface of the second trench 21 is the second gate insulating film 30. The thickness of the oxide film 40 may be, for example, 100 to 200 mm.

Next, the inside of the first trench 3 and the second trench 21 is embedded in the entire surface of the semiconductor substrate 1 where the oxide film 40 is formed over the entire first semiconductor element formation region 100 and the second semiconductor element formation region 110. Then, polysilicon doped with impurities (doped poly-silicon) is deposited. This polysilicon film corresponds to a conductive film. Next, etch back is performed to remove the polysilicon on the surface of the oxide film 40. In the first semiconductor element formation region 100, the polysilicon near the opening of the first trench 3 is also removed. Thereby, the first gate electrode 4 is formed inside the first trench 3. Further, since the width L _t2 of the bottom surface of the second trench 21 is wider than the width L _t1 of the bottom surface of the first trench 3, in the second semiconductor element formation region 110, together with polysilicon near the opening of the second trench 21, Polysilicon near the center of the second trench 21 is also removed. As a result, the polysilicon remains only on the side wall of the second trench 21 and the second gate electrode 22 is formed. The polysilicon remaining on the side wall on the side where the second source region 24 is formed is the second gate electrode 22.

Next, as shown in FIG. 5, a second resist pattern 41 having an opening in the formation region of the second trench 21 and the vicinity thereof is formed by photolithography. Next, phosphorus (P), for example, is ion-implanted from above the oxide film 40 into the surface layer of the well region 2 using the second resist pattern 41 as a mask. The ion implantation conditions may be, for example, an acceleration voltage of 50 KeV and a dose amount of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² . This ion implantation corresponds to the first ion implantation. By diffusing in a later heat treatment step, an n ⁻ low concentration semiconductor region 23 is formed in the surface layer of the well region 2 on the bottom surface of the second trench 21 as shown in FIG. The n ⁻ low concentration semiconductor region 23 is formed in a self-aligned manner by the polysilicon remaining on the side wall of the second trench 21 and the second gate electrode 22. Also, regions that will become the second source region 24 and the second drain region 25 are formed in the surface layer of the well region 2 in the upper portion of the side wall of the second trench 21 in a later step. Next, the second resist pattern 41 is removed. When the phosphorus (P) dose is as low as about 1 × 10 ¹² cm ⁻² , the second resist pattern 41 is not necessary. In this case, the surface layer of the well region 2 is formed on the oxide film 40. Ion implantation may be performed on the entire surface.

  Next, after filling the inside of the trench with an insulating film, as shown in FIG. 7, the formation region of the first source region 5, the first drain region 6, the second source region 24, and the second drain region 25 is formed by photolithography. A third resist pattern 42 having an opening is formed. The opening in the formation region of the first source region 5 opens to one side wall of the first trench 3 (see FIG. 3). This opening corresponds to the first opening. The opening in the formation region of the first drain region 6 opens so as not to reach the other side wall of the first trench 3. The distance from the sidewall of the opening to the sidewall of the first trench 3 may be, for example, about 0.10 to 0.20 μm. This opening corresponds to the second opening. The opening in the formation region of the second source region 24 opens so as not to reach one side wall of the second trench 21. The distance from the sidewall of the opening to the sidewall of the second trench 21 may be, for example, about 0.10 to 0.20 μm. This opening corresponds to the third opening. The opening in the formation region of the second drain region 25 opens to the other side wall of the second trench 21. This opening corresponds to the fourth opening. That is, the shape of the opening in the first semiconductor element formation region 100 and the shape of the opening in the second semiconductor element formation region 110 are symmetrical.

Next, using the third resist pattern 42 as a mask, for example, phosphorus is ion-implanted from above the oxide film 40 into the surface layer of the well region 2 at a tilt of 7 ° with respect to the depth direction of the well region 2 . This ion implantation is preferably performed with a low dose and a high acceleration voltage, compared to the next continuous ion implantation. The ion implantation conditions may be, for example, an acceleration voltage of 150 KeV to 1 MeV and a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . This ion implantation corresponds to the second ion implantation. For example, when phosphorus is ion-implanted at 150 KeV, for example, by performing a thermal diffusion process in a nitrogen atmosphere, the phosphor is driven so as to be deeper than the bottom of the trench, so that in the first semiconductor element formation region 100, A first source region 5 and a first drain region 6 are formed in the surface layer. In the second semiconductor element formation region 110, the second source region 24 and the second drain region 25 are formed in the surface layer of the well region 2.

  In addition, when phosphorus is ion-implanted at 1 MeV, the range reaches about 1 μm, so that the above-described thermal diffusion process is not necessary, and it is activated by a subsequent heat treatment process. The first source region 5 and the first drain region 6 are formed in the surface layer of the well region 2. In the second semiconductor element formation region 110, the second source region 24 and the second drain region 25 are formed in the surface layer of the well region 2.

Next, as shown in FIG. 8, for example, arsenic (As) is perpendicular to the surface layer of the well region 2 from the top of the oxide film 40 using the third resist pattern 42 as a mask, or in the depth direction of the well region 2. The ions are implanted at an inclination of 7 ° with respect to the angle. The ion implantation conditions may be, for example, an acceleration voltage of 40 KeV and a dose amount of about 3 × 10 ¹⁵ cm ⁻² . This ion implantation corresponds to the third ion implantation.

  When the thermal diffusion process is not required after the second ion implantation, the second ion implantation and the third ion implantation can be continuously performed using the same mask. Also, in the case where the third ion implantation is performed after the thermal diffusion process is performed after the second ion implantation, the thermal diffusion process is performed in a reducing atmosphere, so that the second ion implantation is performed using the mask for performing the second ion implantation. Three ion implantations can be performed.

  In the third ion implantation, for example, a first high-concentration source region 7 is formed in the surface layer of the first source region 5 in a region where arsenic is implanted, by a subsequent heat treatment process. Further, the first high concentration drain region 8 is formed in the surface layer of the first drain region 6. A second high concentration source region 26 is formed in the surface layer of the second source region 24. A second high concentration drain region 27 is formed in the surface layer of the second drain region 25.

Next, deposition of a protective oxide film such as HTO (High Temperature Oxide), reflow of an interlayer insulating film such as BPSG (Boro-Phospho Silicate Glass), and annealing of the source region and the drain region are performed. By such heat treatment, as shown in FIG. 9, impurities in the diffusion region formed by ion implantation are diffused to a desired size in the depth direction and the horizontal direction of the well region 2. For example, the LDD regions such as the source region and the drain region are deeper than the depth of the trench (for example, 0.7 μm), for example, about 1.0 μm. In the first semiconductor element formation region 100, the first source region 5 diffuses so as to occupy the first trench curvature portion 51 on the bottom surface of the first trench 3. Further, the first drain region 6 diffuses in the direction away from the first trench 3 in the same direction as the diffusion direction of the first source region 5. In the second semiconductor element formation region 110, the second drain region 25 diffuses so as to occupy the second trench curvature portion 52 on the bottom surface of the second trench 21. Further, the second source region 24 diffuses in the direction away from the second trench 21 in the same direction as the diffusion direction of the second drain region 25. Further, the n ⁻ low concentration semiconductor region 23 is also diffused.

  Next, a first source electrode 9 in contact with the first high concentration source region 7 is formed. Further, the first drain electrode 10 in contact with the first high concentration drain region 8 is formed. Further, a second source electrode 28 in contact with the second high concentration source region 26 is formed. Further, a second drain electrode 29 in contact with the second high concentration drain region 27 is formed. For the polysilicon remaining on the side wall of the second trench 21 on the second drain region 25 side and the second drain electrode 29, for example, aluminum or the like is used for the polysilicon drawn at the edge portion in the gate depth direction. Short-circuit by electrical connection. Thereby, the semiconductor device in which the low breakdown voltage lateral trench MOSFET according to the first embodiment and the trench lateral power MOSFET according to the second embodiment are formed on the same semiconductor substrate 1 is completed.

  As described above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained. In addition, by simultaneously forming the LDD region of the low breakdown voltage lateral trench MOSFET and the LDD region of the trench lateral power MOSFET, the number of manufacturing steps of the entire semiconductor device can be reduced. Further, the ion concentration performed at a high dose and a low acceleration voltage and the ion implantation performed at a low dose and a high acceleration voltage are continuously performed so that the impurity concentration decreases in the depth direction of the well region 2. In addition, a source region and a drain region can be provided. Further, by subsequent heat treatment, the source region and the drain region can be formed deeper than the trench. Accordingly, the semiconductor element can have an LDD structure, and the on-resistance of the semiconductor element can be reduced. Further, the drain region can function as a plug layer. This eliminates the step of forming the plug layer, thereby further reducing the number of manufacturing steps.

Further, by performing ion implantation using the third resist pattern 42 as a mask, in the low breakdown voltage lateral trench MOSFET, the first source region 5 is formed so as to occupy the first trench curvature portion 51 on the bottom surface of the first trench 3. can do. Thereby, the channel resistance of the low breakdown voltage lateral trench MOSFET can be reduced, and the on-resistance can be reduced. Moreover, the distance which the 1st drain region 6 and the 1st trench 3 contact can be formed short. As a result, the gate-drain capacitance can be reduced, and the product of on-resistance and gate charge can be reduced. On the other hand, in the trench lateral power MOSFET, the second drain region 25 can be formed so as to occupy the second trench curvature portion 52 on the bottom surface of the second trench 21 and to be in contact with the n ⁻ low concentration semiconductor region 23. As a result, the drain resistance of the trench lateral power MOSFET can be reduced, and the on-resistance can be reduced. Further, the distance between the second source region 24 and the second trench 21 can be shortened. As a result, the gate-source capacitance can be reduced, and the product of on-resistance and gate charge can be reduced.

Next, the on-resistance of the semiconductor element according to each embodiment described above and the product of the on-resistance and the gate charge (RonQg) were verified. The semiconductor device according to the first embodiment will be described as an example. FIG. 10 is a characteristic diagram illustrating a relationship between drain current and drain voltage when the semiconductor element according to the first embodiment is on. FIG. 11 is a characteristic diagram showing the relationship between the drain current and the drain voltage when the semiconductor device according to the first embodiment is off. FIG. 12 is a characteristic diagram showing the gate-drain capacitance of the semiconductor element according to the first embodiment. First, according to the first embodiment described above, a low breakdown voltage lateral trench MOSFET was formed (hereinafter referred to as an example). For comparison, a conventional low breakdown voltage lateral trench MOSFET as shown in FIG. 13 was prepared (hereinafter referred to as a conventional example). In both the example and the conventional example, the depth D _t1 and the bottom width L _t1 of the first trench 3 were set to 0.7 μm and 0.5 μm, respectively. The length of the channel region in the direction perpendicular to the channel length was 25 μm. The gate voltage was 5.0V.

  From the results shown in FIG. 10, it was found that the on-resistance was reduced in the example as compared with the conventional example. It can be assumed that the channel resistance can be greatly reduced. As shown in FIG. 10, it can be seen that the on-resistance can be reduced by about 30% in the embodiment.

  Moreover, from the results shown in FIG. 11, the off-breakdown voltages of the example and the conventional example are substantially the same value. This is because the off breakdown voltage of the lateral MOSFET having the gate trench structure is determined by the impurity concentration of the first drain region 6 in the upper portion of the sidewall on the drain region side of the trench. As shown in FIG. 11, it can be seen that when the drain-source leakage current is 1.0 μA, the off-breakdown voltage of the example and the conventional example is 14V.

  From the results shown in FIG. 12, it was found that the product of the on-resistance and the gate charge was reduced in the example as compared with the conventional example. This is because the gate-drain capacitance (feedback capacitance) can be reduced in the example as described in the first embodiment. Further, as shown in FIG. 10, the on-resistance can be reduced.

  In addition, the trench lateral power MOSFET includes an LDD region, like the low breakdown voltage lateral trench MOSFET. Therefore, it can be seen that the on-resistance can also be reduced in the trench lateral power MOSFET. In the trench lateral power MOSFET, the structure between the second gate electrode 22 and the second source region 24 is the same as the structure between the first gate electrode 4 and the first drain region 6 of the low breakdown voltage lateral trench MOSFET. Therefore, it can be estimated that the drain-source capacitance can be reduced. Accordingly, it can be estimated that the product of the on-resistance and the gate charge can be reduced also in the trench lateral power MOSFET.

In the above description, the present invention has been described by taking an n-type MOSFET as an example. In that case, boron (B ₁₁ ) and boron fluoride (BF ₂ ), for example, are ion-implanted into the surface layer of the n-type well region 2, and a p-type source region, a high-concentration source region, a p-type drain region, and It is preferable to provide a high concentration drain region.

  Even when the low breakdown voltage lateral trench MOSFET and the semiconductor element having the diffusion region having the same configuration as the LDD region of the low breakdown voltage lateral trench MOSFET are formed on the same substrate, the diffusion region of the semiconductor element and the low breakdown voltage lateral trench are formed. The present invention can be applied by simultaneously forming the LDD region of the MOSFET. The present invention can also be applied to a trench lateral power MOSFET when the trench lateral power MOSFET and a semiconductor element having a diffusion region having the same configuration as the LDD region of the trench lateral power MOSFET are formed on the same substrate.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device including a lateral MOSFET having a gate electrode in a trench, and are particularly suitable for a semiconductor device used in a power supply IC. Yes.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Well region 3 1st trench 4 1st gate electrode 5 1st source region 6 1st drain region 7 1st high concentration source region 8 1st high concentration drain region 9 1st source electrode 10 1st drain electrode 11 local insulating film 12 first gate insulating film 21 and the second trench 22 second gate electrode 23 n ^- low concentration semiconductor region 24 and the second source region 25 and the second drain region 26 second heavily-doped source region 27 second heavily doped drain region 28 Second source electrode 29 Second drain electrode 30 Second gate insulating film 33 Third trench 100 Semiconductor element formation region (first)
110 Semiconductor element formation region (second)

Claims (11)

A well region provided in a surface layer of a semiconductor substrate;
A first trench provided in the well region and shallower than the well region;
A first source region provided deeper than the first trench so as to be in contact with one side wall of the first trench and occupy a corner portion of the bottom surface of the first trench on a surface layer of the well region;
A first drain region provided deeper than the first trench in contact with a part of the other side wall of the first trench on a surface layer of the well region;
A first high concentration source region provided in a surface layer of the first source region and having an impurity concentration higher than that of the first source region;
A first high-concentration drain region having an impurity concentration higher than that of the first drain region, provided in a surface layer of the first drain region, apart from a sidewall of the first trench;
A first gate electrode provided in the first trench through a first gate insulating film;
A semiconductor device comprising: In the depth direction of the well region, the first distance X _s where the first source region and the first trench are in contact is the depth D _t1 of the first trench and the width L _t1 of the bottom surface of the first trench. And the second distance X _n1 where the first high-concentration source region and the first trench are in contact with each other,
X _s <D _t1 + L _t1 −X _n1
The semiconductor device according to claim 1, wherein: In the depth direction of the well region, the third distance _{Xd at which} the first drain region and the first trench are in contact is the depth D _t1 of the first trench, before the first drain region is provided. When the depth D _p1 from the surface of the well region to the surface of the first gate electrode is set,
D _p1 <X _d <D _t1
The semiconductor element according to claim 1, wherein: A well region provided in a surface layer of a semiconductor substrate;
A second trench provided in the well region and shallower than the well region;
A second source region provided deeper than the second trench in contact with a part of one side wall of the second trench on a surface layer of the well region;
A second drain region provided deeper than the second trench so as to occupy a corner of the bottom surface of the second trench in contact with the other side wall of the second trench on the surface layer of the well region;
The surface layer of the well region at the bottom surface of the second trench is provided in contact with the second drain region, has the same conductivity type as the second drain region, and has an impurity concentration lower than that of the second drain region. A low concentration semiconductor region,
A second high-concentration source region having an impurity concentration higher than that of the second source region, provided on the surface layer of the second source region, apart from the sidewall of the second trench;
A second high-concentration drain region provided in a surface layer of the second drain region and having an impurity concentration higher than that of the second drain region;
A second gate electrode provided in the second trench so as to straddle the low-concentration semiconductor region from the second source region via a second gate insulating film;
A semiconductor device comprising: In the depth direction of the well region, the fourth distance X _{sp at which} the second source region and the second trench are in contact is the depth D _t2 of the second trench, before the second source region is provided. When the depth D _p2 from the surface of the well region to the surface of the second gate electrode is set,
D _p2 <X _sp <D _t2
The semiconductor device according to claim 4, wherein: In the depth direction of the well region, the fifth distance X _dp where the second drain region and the second trench are in contact with each other is the depth D _t2 of the second trench and the width L _t2 of the bottom surface of the second trench. And a sixth distance X _n2 where the second high-concentration drain region and the second trench are in contact with each other,
X _dp <D _t2 + (1/2) L _t2 −X _n2
The semiconductor element according to claim 4, wherein: A method of manufacturing a semiconductor element, wherein a first semiconductor element and a second semiconductor element are formed on the same semiconductor substrate,
A first trench of the first semiconductor element is formed shallower than the well region in a first conductivity type well region formed in a surface layer of the semiconductor substrate, and the first trench is separated from the first trench. A trench forming step of forming a second trench of the second semiconductor element having a wider width shallower than the well region;
Forming an insulating film on the sidewall and bottom surface of the first trench, and forming a second gate insulating film on the sidewall and bottom surface of the second trench;
A conductive film forming step of forming a conductive film on a surface of the well region so as to be embedded in the first trench and the second trench after the insulating film forming step;
Etching the conductive film to form a first gate electrode inside the first trench and forming a second gate electrode inside the second trench; and
A first ion implantation step of ion-implanting a second conductivity type impurity into the bottom surface of the second trench using the second gate electrode as a mask;
After the first ion implantation step, the first trench and the second trench are filled with an insulating film and then opened to one side wall of the first trench, and the first trench A second opening that opens so as not to reach the other side wall; a third opening that opens so as not to reach one side wall of the second trench; and a fourth opening that opens to the other side wall of the second trench. A mask process for forming a mask having an opening;
A second ion implantation step of ion-implanting a second conductivity type impurity using the mask formed in the mask step;
A third ion implantation step of ion implanting a second conductivity type impurity using the mask formed in the mask step;
The manufacturing method of the semiconductor element characterized by the above-mentioned.   The method of manufacturing a semiconductor device according to claim 7, wherein the second ion implantation is performed at a higher acceleration voltage than the third ion implantation.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the second ion implantation is performed with a dose amount lower than that of the third ion implantation.   The method for manufacturing a semiconductor device according to claim 7, wherein the second ion implantation step and the third ion implantation step are continuously performed.   10. The semiconductor device according to claim 7, wherein a thermal diffusion process is performed after the second ion implantation process, and then the third ion implantation process is continuously performed through the mask. 11. Manufacturing method.

Images